ccs-pll.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * drivers/media/i2c/ccs-pll.h
  4 *
  5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
  6 *
  7 * Copyright (C) 2020 Intel Corporation
  8 * Copyright (C) 2012 Nokia Corporation
  9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
 10 */
 11
 12#ifndef CCS_PLL_H
 13#define CCS_PLL_H
 14
 15#include <linux/bits.h>
 16
 17/* CSI-2 or CCP-2 */
 18#define CCS_PLL_BUS_TYPE_CSI2_DPHY				0x00
 19#define CCS_PLL_BUS_TYPE_CSI2_CPHY				0x01
 20
 21/* Old SMIA and implementation specific flags. */
 22/* OP PIX clock is for all lanes in total normally. */
 23#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			BIT(0)
 24/* If set, the PLL multipliers are required to be even. */
 25#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER			BIT(3)
 26
 27/* CCS PLL flags */
 28
 29/* The sensor doesn't have OP clocks at all. */
 30#define CCS_PLL_FLAG_NO_OP_CLOCKS				BIT(1)
 31/* System speed model if this flag is unset. */
 32#define CCS_PLL_FLAG_LANE_SPEED_MODEL				BIT(2)
 33/* If set, the pre-PLL divider may have odd values, too. */
 34#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER				BIT(4)
 35/*
 36 * If set, the OP PIX clock doesn't have to exactly match with data rate, it may
 37 * be higher. See "OP Domain Formulas" in MIPI CCS 1.1 spec.
 38 */
 39#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV			BIT(5)
 40/* If set, the VT domain may run faster than the OP domain. */
 41#define CCS_PLL_FLAG_FIFO_DERATING				BIT(6)
 42/* If set, the VT domain may run slower than the OP domain. */
 43#define CCS_PLL_FLAG_FIFO_OVERRATING				BIT(7)
 44/* If set, the PLL tree has two PLLs instead of one. */
 45#define CCS_PLL_FLAG_DUAL_PLL					BIT(8)
 46/*
 47 * If set, the OP SYS clock is a dual data rate clock, transferring two bits per
 48 * cycle instead of one.
 49 */
 50#define CCS_PLL_FLAG_OP_SYS_DDR					BIT(9)
 51/*
 52 * If set, the OP PIX clock is a dual data rate clock, transferring two pixels
 53 * per cycle instead of one.
 54 */
 55#define CCS_PLL_FLAG_OP_PIX_DDR					BIT(10)
 56
 57/**
 58 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
 59 *
 60 * A single branch front-end of the CCS PLL tree.
 61 *
 62 * @pre_pll_clk_div: Pre-PLL clock divisor
 63 * @pll_multiplier: PLL multiplier
 64 * @pll_ip_clk_freq_hz: PLL input clock frequency
 65 * @pll_op_clk_freq_hz: PLL output clock frequency
 66 */
 67struct ccs_pll_branch_fr {
 68	u16 pre_pll_clk_div;
 69	u16 pll_multiplier;
 70	u32 pll_ip_clk_freq_hz;
 71	u32 pll_op_clk_freq_hz;
 72};
 73
 74/**
 75 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
 76 *
 77 * A single branch back-end of the CCS PLL tree.
 78 *
 79 * @sys_clk_div: System clock divider
 80 * @pix_clk_div: Pixel clock divider
 81 * @sys_clk_freq_hz: System clock frequency
 82 * @pix_clk_freq_hz: Pixel clock frequency
 83 */
 84struct ccs_pll_branch_bk {
 85	u16 sys_clk_div;
 86	u16 pix_clk_div;
 87	u32 sys_clk_freq_hz;
 88	u32 pix_clk_freq_hz;
 89};
 90
 91/**
 92 * struct ccs_pll - Full CCS PLL configuration
 93 *
 94 * All information required to calculate CCS PLL configuration.
 95 *
 96 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
 97 * @op_lanes: Number of operational lanes (input)
 98 * @vt_lanes: Number of video timing lanes (input)
 99 * @csi2: CSI-2 related parameters
100 * @csi2.lanes: The number of the CSI-2 data lanes (input)
101 * @binning_vertical: Vertical binning factor (input)
102 * @binning_horizontal: Horizontal binning factor (input)
103 * @scale_m: Downscaling factor, M component, [16, max] (input)
104 * @scale_n: Downscaling factor, N component, typically 16 (input)
105 * @bits_per_pixel: Bits per pixel on the output data bus (input)
106 * @op_bits_per_lane: Number of bits per OP lane (input)
107 * @flags: CCS_PLL_FLAG_* (input)
108 * @link_freq: Chosen link frequency (input)
109 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
110 *		     (input)
111 * @vt_fr: Video timing front-end configuration (output)
112 * @vt_bk: Video timing back-end configuration (output)
113 * @op_fr: Operational timing front-end configuration (output)
114 * @op_bk: Operational timing back-end configuration (output)
115 * @pixel_rate_csi: Pixel rate on the output data bus (output)
116 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
117 *			    (output)
118 */
119struct ccs_pll {
120	/* input values */
121	u8 bus_type;
122	u8 op_lanes;
123	u8 vt_lanes;
124	struct {
125		u8 lanes;
126	} csi2;
127	u8 binning_horizontal;
128	u8 binning_vertical;
129	u8 scale_m;
130	u8 scale_n;
131	u8 bits_per_pixel;
132	u8 op_bits_per_lane;
133	u16 flags;
134	u32 link_freq;
135	u32 ext_clk_freq_hz;
136
137	/* output values */
138	struct ccs_pll_branch_fr vt_fr;
139	struct ccs_pll_branch_bk vt_bk;
140	struct ccs_pll_branch_fr op_fr;
141	struct ccs_pll_branch_bk op_bk;
142
143	u32 pixel_rate_csi;
144	u32 pixel_rate_pixel_array;
145};
146
147/**
148 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
149 *
150 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
151 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
152 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
153 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
154 * @min_pll_multiplier: Minimum PLL multiplier
155 * @max_pll_multiplier: Maximum PLL multiplier
156 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
157 * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
158 */
159struct ccs_pll_branch_limits_fr {
160	u16 min_pre_pll_clk_div;
161	u16 max_pre_pll_clk_div;
162	u32 min_pll_ip_clk_freq_hz;
163	u32 max_pll_ip_clk_freq_hz;
164	u16 min_pll_multiplier;
165	u16 max_pll_multiplier;
166	u32 min_pll_op_clk_freq_hz;
167	u32 max_pll_op_clk_freq_hz;
168};
169
170/**
171 * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
172 *
173 * @min_sys_clk_div: Minimum system clock divider
174 * @max_sys_clk_div: Maximum system clock divider
175 * @min_sys_clk_freq_hz: Minimum system clock frequency
176 * @max_sys_clk_freq_hz: Maximum system clock frequency
177 * @min_pix_clk_div: Minimum pixel clock divider
178 * @max_pix_clk_div: Maximum pixel clock divider
179 * @min_pix_clk_freq_hz: Minimum pixel clock frequency
180 * @max_pix_clk_freq_hz: Maximum pixel clock frequency
181 */
182struct ccs_pll_branch_limits_bk {
183	u16 min_sys_clk_div;
184	u16 max_sys_clk_div;
185	u32 min_sys_clk_freq_hz;
186	u32 max_sys_clk_freq_hz;
187	u16 min_pix_clk_div;
188	u16 max_pix_clk_div;
189	u32 min_pix_clk_freq_hz;
190	u32 max_pix_clk_freq_hz;
191};
192
193/**
194 * struct ccs_pll_limits - CCS PLL limits
195 *
196 * @min_ext_clk_freq_hz: Minimum external clock frequency
197 * @max_ext_clk_freq_hz: Maximum external clock frequency
198 * @vt_fr: Video timing front-end limits
199 * @vt_bk: Video timing back-end limits
200 * @op_fr: Operational timing front-end limits
201 * @op_bk: Operational timing back-end limits
202 * @min_line_length_pck_bin: Minimum line length in pixels, with binning
203 * @min_line_length_pck: Minimum line length in pixels without binning
204 */
205struct ccs_pll_limits {
206	/* Strict PLL limits */
207	u32 min_ext_clk_freq_hz;
208	u32 max_ext_clk_freq_hz;
209
210	struct ccs_pll_branch_limits_fr vt_fr;
211	struct ccs_pll_branch_limits_bk vt_bk;
212	struct ccs_pll_branch_limits_fr op_fr;
213	struct ccs_pll_branch_limits_bk op_bk;
214
215	/* Other relevant limits */
216	u32 min_line_length_pck_bin;
217	u32 min_line_length_pck;
218};
219
220struct device;
221
222/**
223 * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
224 *
225 * @dev: Device pointer, used for printing messages
226 * @limits: Limits specific to the sensor
227 * @pll: Given PLL configuration
228 *
229 * Calculate the CCS PLL configuration based on the limits as well as given
230 * device specific, system specific or user configured input data.
231 */
232int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
233		      struct ccs_pll *pll);
234
235#endif /* CCS_PLL_H */