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ccs-pll.c
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linux-6.19.14/drivers/media/i2c/ccs-pll.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12#include <linux/device.h> 13#include <linux/gcd.h> 14#include <linux/lcm.h> 15#include <linux/module.h> 16 17#include "ccs-pll.h" 18 19/* Return an even number or one. */ 20static inline u32 clk_div_even(u32 a) 21{ 22 return max_t(u32, 1, a & ~1); 23} 24 25/* Return an even number or one. */ 26static inline u32 clk_div_even_up(u32 a) 27{ 28 if (a == 1) 29 return 1; 30 return (a + 1) & ~1; 31} 32 33static inline u32 is_one_or_even(u32 a) 34{ 35 if (a == 1) 36 return 1; 37 if (a & 1) 38 return 0; 39 40 return 1; 41} 42 43static inline u32 one_or_more(u32 a) 44{ 45 return a ?: 1; 46} 47 48static int bounds_check(struct device *dev, u32 val, 49 u32 min, u32 max, const char *prefix, 50 char *str) 51{ 52 if (val >= min && val <= max) 53 return 0; 54 55 dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix, 56 str, val, min, max); 57 58 return -EINVAL; 59} 60 61#define PLL_OP 1 62#define PLL_VT 2 63 64static const char *pll_string(unsigned int which) 65{ 66 switch (which) { 67 case PLL_OP: 68 return "op"; 69 case PLL_VT: 70 return "vt"; 71 } 72 73 return NULL; 74} 75 76#define PLL_FL(f) CCS_PLL_FLAG_##f 77 78static void print_pll(struct device *dev, const struct ccs_pll *pll) 79{ 80 const struct { 81 const struct ccs_pll_branch_fr *fr; 82 const struct ccs_pll_branch_bk *bk; 83 unsigned int which; 84 } branches[] = { 85 { &pll->vt_fr, &pll->vt_bk, PLL_VT }, 86 { &pll->op_fr, &pll->op_bk, PLL_OP } 87 }, *br; 88 unsigned int i; 89 90 dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz); 91 92 for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) { 93 const char *s = pll_string(br->which); 94 95 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL || 96 br->which == PLL_VT) { 97 dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s, 98 br->fr->pre_pll_clk_div); 99 dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s, 100 br->fr->pll_multiplier); 101 102 dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s, 103 br->fr->pll_ip_clk_freq_hz); 104 dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s, 105 br->fr->pll_op_clk_freq_hz); 106 } 107 108 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) || 109 br->which == PLL_VT) { 110 dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s, 111 br->bk->sys_clk_div); 112 dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s, 113 br->bk->pix_clk_div); 114 115 dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s, 116 br->bk->sys_clk_freq_hz); 117 dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s, 118 br->bk->pix_clk_freq_hz); 119 } 120 } 121 122 dev_dbg(dev, "pixel rate in pixel array:\t%u\n", 123 pll->pixel_rate_pixel_array); 124 dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n", 125 pll->pixel_rate_csi); 126} 127 128static void print_pll_flags(struct device *dev, struct ccs_pll *pll) 129{ 130 dev_dbg(dev, "PLL flags%s%s%s%s%s%s%s%s%s%s%s\n", 131 pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "", 132 pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "", 133 pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "", 134 pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", 135 pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ? 136 " ext-ip-pll-divider" : "", 137 pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ? 138 " flexible-op-pix-div" : "", 139 pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "", 140 pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "", 141 pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "", 142 pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "", 143 pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : ""); 144} 145 146static u32 op_sys_ddr(u32 flags) 147{ 148 return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0; 149} 150 151static u32 op_pix_ddr(u32 flags) 152{ 153 return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0; 154} 155 156static int check_fr_bounds(struct device *dev, 157 const struct ccs_pll_limits *lim, 158 const struct ccs_pll *pll, unsigned int which) 159{ 160 const struct ccs_pll_branch_limits_fr *lim_fr; 161 const struct ccs_pll_branch_fr *pll_fr; 162 const char *s = pll_string(which); 163 int rval; 164 165 if (which == PLL_OP) { 166 lim_fr = &lim->op_fr; 167 pll_fr = &pll->op_fr; 168 } else { 169 lim_fr = &lim->vt_fr; 170 pll_fr = &pll->vt_fr; 171 } 172 173 rval = bounds_check(dev, pll_fr->pre_pll_clk_div, 174 lim_fr->min_pre_pll_clk_div, 175 lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div"); 176 177 if (!rval) 178 rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz, 179 lim_fr->min_pll_ip_clk_freq_hz, 180 lim_fr->max_pll_ip_clk_freq_hz, 181 s, "pll_ip_clk_freq_hz"); 182 if (!rval) 183 rval = bounds_check(dev, pll_fr->pll_multiplier, 184 lim_fr->min_pll_multiplier, 185 lim_fr->max_pll_multiplier, 186 s, "pll_multiplier"); 187 if (!rval) 188 rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz, 189 lim_fr->min_pll_op_clk_freq_hz, 190 lim_fr->max_pll_op_clk_freq_hz, 191 s, "pll_op_clk_freq_hz"); 192 193 return rval; 194} 195 196static int check_bk_bounds(struct device *dev, 197 const struct ccs_pll_limits *lim, 198 const struct ccs_pll *pll, unsigned int which) 199{ 200 const struct ccs_pll_branch_limits_bk *lim_bk; 201 const struct ccs_pll_branch_bk *pll_bk; 202 const char *s = pll_string(which); 203 int rval; 204 205 if (which == PLL_OP) { 206 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 207 return 0; 208 209 lim_bk = &lim->op_bk; 210 pll_bk = &pll->op_bk; 211 } else { 212 lim_bk = &lim->vt_bk; 213 pll_bk = &pll->vt_bk; 214 } 215 216 rval = bounds_check(dev, pll_bk->sys_clk_div, 217 lim_bk->min_sys_clk_div, 218 lim_bk->max_sys_clk_div, s, "op_sys_clk_div"); 219 if (!rval) 220 rval = bounds_check(dev, pll_bk->sys_clk_freq_hz, 221 lim_bk->min_sys_clk_freq_hz, 222 lim_bk->max_sys_clk_freq_hz, 223 s, "sys_clk_freq_hz"); 224 if (!rval) 225 rval = bounds_check(dev, pll_bk->sys_clk_div, 226 lim_bk->min_sys_clk_div, 227 lim_bk->max_sys_clk_div, 228 s, "sys_clk_div"); 229 if (!rval) 230 rval = bounds_check(dev, pll_bk->pix_clk_freq_hz, 231 lim_bk->min_pix_clk_freq_hz, 232 lim_bk->max_pix_clk_freq_hz, 233 s, "pix_clk_freq_hz"); 234 235 return rval; 236} 237 238static int check_ext_bounds(struct device *dev, const struct ccs_pll *pll) 239{ 240 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) && 241 pll->pixel_rate_pixel_array > pll->pixel_rate_csi) { 242 dev_dbg(dev, "device does not support derating\n"); 243 return -EINVAL; 244 } 245 246 if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) && 247 pll->pixel_rate_pixel_array < pll->pixel_rate_csi) { 248 dev_dbg(dev, "device does not support overrating\n"); 249 return -EINVAL; 250 } 251 252 return 0; 253} 254 255static void 256ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, 257 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, 258 u16 min_vt_div, u16 max_vt_div, 259 u16 *min_sys_div, u16 *max_sys_div) 260{ 261 /* 262 * Find limits for sys_clk_div. Not all values are possible with all 263 * values of pix_clk_div. 264 */ 265 *min_sys_div = lim->vt_bk.min_sys_clk_div; 266 dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div); 267 *min_sys_div = max_t(u16, *min_sys_div, 268 DIV_ROUND_UP(min_vt_div, 269 lim->vt_bk.max_pix_clk_div)); 270 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div); 271 *min_sys_div = max_t(u16, *min_sys_div, 272 pll_fr->pll_op_clk_freq_hz 273 / lim->vt_bk.max_sys_clk_freq_hz); 274 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div); 275 *min_sys_div = clk_div_even_up(*min_sys_div); 276 dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div); 277 278 *max_sys_div = lim->vt_bk.max_sys_clk_div; 279 dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div); 280 *max_sys_div = min_t(u16, *max_sys_div, 281 DIV_ROUND_UP(max_vt_div, 282 lim->vt_bk.min_pix_clk_div)); 283 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div); 284 *max_sys_div = min_t(u16, *max_sys_div, 285 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 286 lim->vt_bk.min_pix_clk_freq_hz)); 287 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div); 288} 289 290#define CPHY_CONST 7 291#define DPHY_CONST 16 292#define PHY_CONST_DIV 16 293 294static inline int 295__ccs_pll_calculate_vt_tree(struct device *dev, 296 const struct ccs_pll_limits *lim, 297 struct ccs_pll *pll, u32 mul, u32 div) 298{ 299 const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; 300 const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk; 301 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; 302 struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk; 303 u32 more_mul; 304 u16 best_pix_div = SHRT_MAX >> 1, best_div = lim_bk->max_sys_clk_div; 305 u16 vt_div, min_sys_div, max_sys_div, sys_div; 306 307 pll_fr->pll_ip_clk_freq_hz = 308 pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div; 309 310 dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz); 311 312 more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz, 313 pll_fr->pll_ip_clk_freq_hz * mul)); 314 315 dev_dbg(dev, "more_mul: %u\n", more_mul); 316 more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul); 317 dev_dbg(dev, "more_mul2: %u\n", more_mul); 318 319 if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER && 320 (mul & 1) && (more_mul & 1)) 321 more_mul <<= 1; 322 323 pll_fr->pll_multiplier = mul * more_mul; 324 if (pll_fr->pll_multiplier > lim_fr->max_pll_multiplier) { 325 dev_dbg(dev, "pll multiplier %u too high\n", 326 pll_fr->pll_multiplier); 327 return -EINVAL; 328 } 329 330 pll_fr->pll_op_clk_freq_hz = 331 pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier; 332 if (pll_fr->pll_op_clk_freq_hz > lim_fr->max_pll_op_clk_freq_hz) { 333 dev_dbg(dev, "too high OP clock %u\n", 334 pll_fr->pll_op_clk_freq_hz); 335 return -EINVAL; 336 } 337 338 vt_div = div * more_mul; 339 340 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div, 341 &min_sys_div, &max_sys_div); 342 343 max_sys_div = (vt_div & 1) ? 1 : max_sys_div; 344 345 dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div); 346 347 for (sys_div = min_sys_div; sys_div <= max_sys_div; 348 sys_div += 2 - (sys_div & 1)) { 349 u16 pix_div; 350 351 if (vt_div % sys_div) 352 continue; 353 354 pix_div = vt_div / sys_div; 355 356 if (pix_div < lim_bk->min_pix_clk_div || 357 pix_div > lim_bk->max_pix_clk_div) { 358 dev_dbg(dev, 359 "pix_div %u too small or too big (%u--%u)\n", 360 pix_div, 361 lim_bk->min_pix_clk_div, 362 lim_bk->max_pix_clk_div); 363 continue; 364 } 365 366 dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div, 367 best_pix_div); 368 369 if (pix_div * sys_div <= best_pix_div) { 370 best_pix_div = pix_div; 371 best_div = pix_div * sys_div; 372 } 373 } 374 if (best_pix_div == SHRT_MAX >> 1) 375 return -EINVAL; 376 377 pll_bk->sys_clk_div = best_div / best_pix_div; 378 pll_bk->pix_clk_div = best_pix_div; 379 380 pll_bk->sys_clk_freq_hz = 381 pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div; 382 pll_bk->pix_clk_freq_hz = 383 pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div; 384 385 pll->pixel_rate_pixel_array = 386 pll_bk->pix_clk_freq_hz * pll->vt_lanes; 387 388 return 0; 389} 390 391static int ccs_pll_calculate_vt_tree(struct device *dev, 392 const struct ccs_pll_limits *lim, 393 struct ccs_pll *pll) 394{ 395 const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; 396 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; 397 u16 min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div; 398 u16 max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div; 399 u32 pre_mul, pre_div; 400 401 pre_div = gcd(pll->pixel_rate_csi, 402 pll->ext_clk_freq_hz * pll->vt_lanes); 403 pre_mul = pll->pixel_rate_csi / pre_div; 404 pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div; 405 406 /* Make sure PLL input frequency is within limits */ 407 max_pre_pll_clk_div = 408 min_t(u16, max_pre_pll_clk_div, 409 DIV_ROUND_UP(pll->ext_clk_freq_hz, 410 lim_fr->min_pll_ip_clk_freq_hz)); 411 412 min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div, 413 pll->ext_clk_freq_hz / 414 lim_fr->max_pll_ip_clk_freq_hz); 415 if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER)) 416 min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div); 417 418 dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n", 419 min_pre_pll_clk_div, max_pre_pll_clk_div); 420 421 for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div; 422 pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div; 423 pll_fr->pre_pll_clk_div += 424 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 425 2 - (pll_fr->pre_pll_clk_div & 1)) { 426 u32 mul, div; 427 int rval; 428 429 div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div); 430 mul = pre_mul * pll_fr->pre_pll_clk_div / div; 431 div = pre_div / div; 432 433 dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n", 434 pll_fr->pre_pll_clk_div, mul, div); 435 436 rval = __ccs_pll_calculate_vt_tree(dev, lim, pll, 437 mul, div); 438 if (rval) 439 continue; 440 441 rval = check_fr_bounds(dev, lim, pll, PLL_VT); 442 if (rval) 443 continue; 444 445 rval = check_bk_bounds(dev, lim, pll, PLL_VT); 446 if (rval) 447 continue; 448 449 return 0; 450 } 451 452 dev_dbg(dev, "unable to compute VT pre_pll divisor\n"); 453 return -EINVAL; 454} 455 456static int 457ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 458 const struct ccs_pll_branch_limits_bk *op_lim_bk, 459 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, 460 struct ccs_pll_branch_bk *op_pll_bk, bool cphy, 461 u32 phy_const) 462{ 463 u16 sys_div; 464 u16 best_pix_div = SHRT_MAX >> 1; 465 u16 vt_op_binning_div; 466 u16 min_vt_div, max_vt_div, vt_div; 467 u16 min_sys_div, max_sys_div; 468 469 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 470 goto out_calc_pixel_rate; 471 472 /* 473 * Find out whether a sensor supports derating. If it does not, VT and 474 * OP domains are required to run at the same pixel rate. 475 */ 476 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) { 477 min_vt_div = 478 op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div 479 * pll->vt_lanes * phy_const / pll->op_lanes 480 / (PHY_CONST_DIV << op_pix_ddr(pll->flags)); 481 } else { 482 /* 483 * Some sensors perform analogue binning and some do this 484 * digitally. The ones doing this digitally can be roughly be 485 * found out using this formula. The ones doing this digitally 486 * should run at higher clock rate, so smaller divisor is used 487 * on video timing side. 488 */ 489 if (lim->min_line_length_pck_bin > lim->min_line_length_pck 490 / pll->binning_horizontal) 491 vt_op_binning_div = pll->binning_horizontal; 492 else 493 vt_op_binning_div = 1; 494 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); 495 496 /* 497 * Profile 2 supports vt_pix_clk_div E [4, 10] 498 * 499 * Horizontal binning can be used as a base for difference in 500 * divisors. One must make sure that horizontal blanking is 501 * enough to accommodate the CSI-2 sync codes. 502 * 503 * Take scaling factor and number of VT lanes into account as well. 504 * 505 * Find absolute limits for the factor of vt divider. 506 */ 507 dev_dbg(dev, "scale_m: %u\n", pll->scale_m); 508 min_vt_div = 509 DIV_ROUND_UP(pll->bits_per_pixel 510 * op_pll_bk->sys_clk_div * pll->scale_n 511 * pll->vt_lanes * phy_const, 512 (pll->flags & 513 CCS_PLL_FLAG_LANE_SPEED_MODEL ? 514 pll->csi2.lanes : 1) 515 * vt_op_binning_div * pll->scale_m 516 * PHY_CONST_DIV << op_pix_ddr(pll->flags)); 517 } 518 519 /* Find smallest and biggest allowed vt divisor. */ 520 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); 521 min_vt_div = max_t(u16, min_vt_div, 522 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 523 lim->vt_bk.max_pix_clk_freq_hz)); 524 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", 525 min_vt_div); 526 min_vt_div = max_t(u16, min_vt_div, lim->vt_bk.min_pix_clk_div 527 * lim->vt_bk.min_sys_clk_div); 528 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); 529 530 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; 531 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); 532 max_vt_div = min_t(u16, max_vt_div, 533 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 534 lim->vt_bk.min_pix_clk_freq_hz)); 535 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", 536 max_vt_div); 537 538 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div, 539 max_vt_div, &min_sys_div, &max_sys_div); 540 541 /* 542 * Find pix_div such that a legal pix_div * sys_div results 543 * into a value which is not smaller than div, the desired 544 * divisor. 545 */ 546 for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) { 547 u16 __max_sys_div = vt_div & 1 ? 1 : max_sys_div; 548 549 for (sys_div = min_sys_div; sys_div <= __max_sys_div; 550 sys_div += 2 - (sys_div & 1)) { 551 u16 pix_div; 552 u16 rounded_div; 553 554 pix_div = DIV_ROUND_UP(vt_div, sys_div); 555 556 if (pix_div < lim->vt_bk.min_pix_clk_div 557 || pix_div > lim->vt_bk.max_pix_clk_div) { 558 dev_dbg(dev, 559 "pix_div %u too small or too big (%u--%u)\n", 560 pix_div, 561 lim->vt_bk.min_pix_clk_div, 562 lim->vt_bk.max_pix_clk_div); 563 continue; 564 } 565 566 rounded_div = roundup(vt_div, best_pix_div); 567 568 /* Check if this one is better. */ 569 if (pix_div * sys_div <= rounded_div) 570 best_pix_div = pix_div; 571 572 /* Bail out if we've already found the best value. */ 573 if (vt_div == rounded_div) 574 break; 575 } 576 if (best_pix_div < SHRT_MAX >> 1) 577 break; 578 } 579 if (best_pix_div == SHRT_MAX >> 1) 580 return -EINVAL; 581 582 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div); 583 pll->vt_bk.pix_clk_div = best_pix_div; 584 585 pll->vt_bk.sys_clk_freq_hz = 586 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; 587 pll->vt_bk.pix_clk_freq_hz = 588 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; 589 590out_calc_pixel_rate: 591 pll->pixel_rate_pixel_array = 592 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; 593 594 return 0; 595} 596 597/* 598 * Heuristically guess the PLL tree for a given common multiplier and 599 * divisor. Begin with the operational timing and continue to video 600 * timing once operational timing has been verified. 601 * 602 * @mul is the PLL multiplier and @div is the common divisor 603 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL 604 * multiplier will be a multiple of @mul. 605 * 606 * @return Zero on success, error code on error. 607 */ 608static int 609ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, 610 const struct ccs_pll_branch_limits_fr *op_lim_fr, 611 const struct ccs_pll_branch_limits_bk *op_lim_bk, 612 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, 613 struct ccs_pll_branch_bk *op_pll_bk, u32 mul, 614 u32 div, u32 op_sys_clk_freq_hz_sdr, u32 l, 615 bool cphy, u32 phy_const) 616{ 617 /* 618 * Higher multipliers (and divisors) are often required than 619 * necessitated by the external clock and the output clocks. 620 * There are limits for all values in the clock tree. These 621 * are the minimum and maximum multiplier for mul. 622 */ 623 u32 more_mul_min, more_mul_max; 624 u32 more_mul_factor; 625 u32 i; 626 627 /* 628 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be 629 * too high. 630 */ 631 dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); 632 633 /* Don't go above max pll multiplier. */ 634 more_mul_max = op_lim_fr->max_pll_multiplier / mul; 635 dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", 636 more_mul_max); 637 /* Don't go above max pll op frequency. */ 638 more_mul_max = 639 min_t(u32, 640 more_mul_max, 641 op_lim_fr->max_pll_op_clk_freq_hz 642 / (pll->ext_clk_freq_hz / 643 op_pll_fr->pre_pll_clk_div * mul)); 644 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 645 more_mul_max); 646 /* Don't go above the division capability of op sys clock divider. */ 647 more_mul_max = min(more_mul_max, 648 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 649 / div); 650 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 651 more_mul_max); 652 /* Ensure we won't go above max_pll_multiplier. */ 653 more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); 654 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 655 more_mul_max); 656 657 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 658 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 659 pll->ext_clk_freq_hz / 660 op_pll_fr->pre_pll_clk_div * mul); 661 dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", 662 more_mul_min); 663 /* Ensure we won't go below min_pll_multiplier. */ 664 more_mul_min = max(more_mul_min, 665 DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); 666 dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", 667 more_mul_min); 668 669 if (more_mul_min > more_mul_max) { 670 dev_dbg(dev, 671 "unable to compute more_mul_min and more_mul_max\n"); 672 return -EINVAL; 673 } 674 675 more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; 676 dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); 677 more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); 678 dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", 679 more_mul_factor); 680 i = roundup(more_mul_min, more_mul_factor); 681 if (!is_one_or_even(i)) 682 i <<= 1; 683 684 if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER && 685 mul & 1 && i & 1) 686 i <<= 1; 687 688 dev_dbg(dev, "final more_mul: %u\n", i); 689 if (i > more_mul_max) { 690 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); 691 return -EINVAL; 692 } 693 694 op_pll_fr->pll_multiplier = mul * i; 695 op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; 696 dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); 697 698 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz 699 / op_pll_fr->pre_pll_clk_div; 700 701 op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz 702 * op_pll_fr->pll_multiplier; 703 704 if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) 705 op_pll_bk->pix_clk_div = 706 (pll->bits_per_pixel 707 * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags)) 708 / PHY_CONST_DIV / pll->csi2.lanes / l) 709 >> op_pix_ddr(pll->flags); 710 else 711 op_pll_bk->pix_clk_div = 712 (pll->bits_per_pixel 713 * (phy_const << op_sys_ddr(pll->flags)) 714 / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags); 715 716 op_pll_bk->pix_clk_freq_hz = 717 (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags)) 718 / op_pll_bk->pix_clk_div; 719 op_pll_bk->sys_clk_freq_hz = 720 op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags); 721 722 dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); 723 724 return 0; 725} 726 727int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 728 struct ccs_pll *pll) 729{ 730 const struct ccs_pll_branch_limits_fr *op_lim_fr; 731 const struct ccs_pll_branch_limits_bk *op_lim_bk; 732 struct ccs_pll_branch_fr *op_pll_fr; 733 struct ccs_pll_branch_bk *op_pll_bk; 734 bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; 735 u32 phy_const = cphy ? CPHY_CONST : DPHY_CONST; 736 u32 op_sys_clk_freq_hz_sdr; 737 u16 min_op_pre_pll_clk_div; 738 u16 max_op_pre_pll_clk_div; 739 u32 mul, div; 740 u32 l = (!pll->op_bits_per_lane || 741 pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; 742 u32 i; 743 int rval = -EINVAL; 744 745 print_pll_flags(dev, pll); 746 747 if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) { 748 pll->op_lanes = 1; 749 pll->vt_lanes = 1; 750 } 751 752 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) { 753 op_lim_fr = &lim->op_fr; 754 op_lim_bk = &lim->op_bk; 755 op_pll_fr = &pll->op_fr; 756 op_pll_bk = &pll->op_bk; 757 } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 758 /* 759 * If there's no OP PLL at all, use the VT values 760 * instead. The OP values are ignored for the rest of 761 * the PLL calculation. 762 */ 763 op_lim_fr = &lim->vt_fr; 764 op_lim_bk = &lim->vt_bk; 765 op_pll_fr = &pll->vt_fr; 766 op_pll_bk = &pll->vt_bk; 767 } else { 768 op_lim_fr = &lim->vt_fr; 769 op_lim_bk = &lim->op_bk; 770 op_pll_fr = &pll->vt_fr; 771 op_pll_bk = &pll->op_bk; 772 } 773 774 if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel || 775 !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m || 776 !op_lim_fr->min_pll_ip_clk_freq_hz || 777 !op_lim_fr->max_pll_ip_clk_freq_hz || 778 !op_lim_fr->min_pll_op_clk_freq_hz || 779 !op_lim_fr->max_pll_op_clk_freq_hz || 780 !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier) 781 return -EINVAL; 782 783 /* 784 * Make sure op_pix_clk_div will be integer --- unless flexible 785 * op_pix_clk_div is supported 786 */ 787 if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) && 788 (pll->bits_per_pixel * pll->op_lanes) % 789 (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) { 790 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n", 791 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l); 792 return -EINVAL; 793 } 794 795 dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); 796 dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); 797 798 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, 799 pll->binning_vertical); 800 801 switch (pll->bus_type) { 802 case CCS_PLL_BUS_TYPE_CSI2_DPHY: 803 case CCS_PLL_BUS_TYPE_CSI2_CPHY: 804 op_sys_clk_freq_hz_sdr = pll->link_freq * 2 805 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 806 1 : pll->csi2.lanes); 807 break; 808 default: 809 return -EINVAL; 810 } 811 812 pll->pixel_rate_csi = 813 div_u64((uint64_t)op_sys_clk_freq_hz_sdr 814 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 815 pll->csi2.lanes : 1) * PHY_CONST_DIV, 816 phy_const * pll->bits_per_pixel * l); 817 818 /* Figure out limits for OP pre-pll divider based on extclk */ 819 dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", 820 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); 821 max_op_pre_pll_clk_div = 822 min_t(u16, op_lim_fr->max_pre_pll_clk_div, 823 DIV_ROUND_UP(pll->ext_clk_freq_hz, 824 op_lim_fr->min_pll_ip_clk_freq_hz)); 825 min_op_pre_pll_clk_div = 826 max_t(u16, op_lim_fr->min_pre_pll_clk_div, 827 clk_div_even_up( 828 DIV_ROUND_UP(pll->ext_clk_freq_hz, 829 op_lim_fr->max_pll_ip_clk_freq_hz))); 830 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", 831 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 832 833 i = gcd(op_sys_clk_freq_hz_sdr, 834 pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)); 835 mul = op_sys_clk_freq_hz_sdr / i; 836 div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i; 837 dev_dbg(dev, "mul %u / div %u\n", mul, div); 838 839 min_op_pre_pll_clk_div = 840 max_t(u16, min_op_pre_pll_clk_div, 841 clk_div_even_up( 842 mul / 843 one_or_more( 844 DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz, 845 pll->ext_clk_freq_hz)))); 846 if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER)) 847 min_op_pre_pll_clk_div = clk_div_even(min_op_pre_pll_clk_div); 848 dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", 849 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 850 851 for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; 852 op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; 853 op_pll_fr->pre_pll_clk_div += 854 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 855 2 - (op_pll_fr->pre_pll_clk_div & 1)) { 856 rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll, 857 op_pll_fr, op_pll_bk, mul, div, 858 op_sys_clk_freq_hz_sdr, l, cphy, 859 phy_const); 860 if (rval) 861 continue; 862 863 rval = check_fr_bounds(dev, lim, pll, 864 pll->flags & CCS_PLL_FLAG_DUAL_PLL ? 865 PLL_OP : PLL_VT); 866 if (rval) 867 continue; 868 869 rval = check_bk_bounds(dev, lim, pll, PLL_OP); 870 if (rval) 871 continue; 872 873 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) 874 break; 875 876 rval = ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, 877 op_pll_bk, cphy, phy_const); 878 if (rval) 879 continue; 880 881 rval = check_bk_bounds(dev, lim, pll, PLL_VT); 882 if (rval) 883 continue; 884 rval = check_ext_bounds(dev, pll); 885 if (rval) 886 continue; 887 888 break; 889 } 890 891 if (rval) { 892 dev_dbg(dev, "unable to compute OP pre_pll divisor\n"); 893 return rval; 894 } 895 896 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) { 897 rval = ccs_pll_calculate_vt_tree(dev, lim, pll); 898 899 if (rval) 900 return rval; 901 } 902 903 print_pll(dev, pll); 904 905 return 0; 906} 907EXPORT_SYMBOL_GPL(ccs_pll_calculate); 908 909MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>"); 910MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); 911MODULE_LICENSE("GPL");
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