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adv7842.c
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linux-6.19.14/drivers/media/i2c/adv7842.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * adv7842 - Analog Devices ADV7842 video decoder driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8/* 9 * References (c = chapter, p = page): 10 * REF_01 - Analog devices, ADV7842, 11 * Register Settings Recommendations, Rev. 1.9, April 2011 12 * REF_02 - Analog devices, Software User Guide, UG-206, 13 * ADV7842 I2C Register Maps, Rev. 0, November 2010 14 * REF_03 - Analog devices, Hardware User Guide, UG-214, 15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 16 * Decoder and Digitizer , Rev. 0, January 2011 17 */ 18 19 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/slab.h> 23#include <linux/i2c.h> 24#include <linux/delay.h> 25#include <linux/videodev2.h> 26#include <linux/workqueue.h> 27#include <linux/v4l2-dv-timings.h> 28#include <linux/hdmi.h> 29#include <media/cec.h> 30#include <media/v4l2-device.h> 31#include <media/v4l2-event.h> 32#include <media/v4l2-ctrls.h> 33#include <media/v4l2-dv-timings.h> 34#include <media/i2c/adv7842.h> 35 36static int debug; 37module_param(debug, int, 0644); 38MODULE_PARM_DESC(debug, "debug level (0-2)"); 39 40MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 41MODULE_AUTHOR("Hans Verkuil <hverkuil@kernel.org>"); 42MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 43MODULE_LICENSE("GPL"); 44 45/* ADV7842 system clock frequency */ 46#define ADV7842_fsc (28636360) 47 48#define ADV7842_RGB_OUT (1 << 1) 49 50#define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) 51#define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) 52#define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) 53 54#define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) 55#define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) 56#define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) 57#define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) 58#define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) 59#define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) 60 61#define ADV7842_OP_CH_SEL_GBR (0 << 5) 62#define ADV7842_OP_CH_SEL_GRB (1 << 5) 63#define ADV7842_OP_CH_SEL_BGR (2 << 5) 64#define ADV7842_OP_CH_SEL_RGB (3 << 5) 65#define ADV7842_OP_CH_SEL_BRG (4 << 5) 66#define ADV7842_OP_CH_SEL_RBG (5 << 5) 67 68#define ADV7842_OP_SWAP_CB_CR (1 << 0) 69 70#define ADV7842_MAX_ADDRS (3) 71 72/* 73********************************************************************** 74* 75* Arrays with configuration parameters for the ADV7842 76* 77********************************************************************** 78*/ 79 80struct adv7842_format_info { 81 u32 code; 82 u8 op_ch_sel; 83 bool rgb_out; 84 bool swap_cb_cr; 85 u8 op_format_sel; 86}; 87 88struct adv7842_state { 89 struct adv7842_platform_data pdata; 90 struct v4l2_subdev sd; 91 struct media_pad pads[ADV7842_PAD_SOURCE + 1]; 92 struct v4l2_ctrl_handler hdl; 93 enum adv7842_mode mode; 94 struct v4l2_dv_timings timings; 95 enum adv7842_vid_std_select vid_std_select; 96 97 const struct adv7842_format_info *format; 98 99 v4l2_std_id norm; 100 struct { 101 u8 edid[512]; 102 u32 blocks; 103 u32 present; 104 } hdmi_edid; 105 struct { 106 u8 edid[128]; 107 u32 blocks; 108 u32 present; 109 } vga_edid; 110 struct v4l2_fract aspect_ratio; 111 u32 rgb_quantization_range; 112 bool is_cea_format; 113 struct delayed_work delayed_work_enable_hotplug; 114 bool restart_stdi_once; 115 bool hdmi_port_a; 116 117 struct dentry *debugfs_dir; 118 struct v4l2_debugfs_if *infoframes; 119 120 /* i2c clients */ 121 struct i2c_client *i2c_sdp_io; 122 struct i2c_client *i2c_sdp; 123 struct i2c_client *i2c_cp; 124 struct i2c_client *i2c_vdp; 125 struct i2c_client *i2c_afe; 126 struct i2c_client *i2c_hdmi; 127 struct i2c_client *i2c_repeater; 128 struct i2c_client *i2c_edid; 129 struct i2c_client *i2c_infoframe; 130 struct i2c_client *i2c_cec; 131 struct i2c_client *i2c_avlink; 132 133 /* controls */ 134 struct v4l2_ctrl *detect_tx_5v_ctrl; 135 struct v4l2_ctrl *analog_sampling_phase_ctrl; 136 struct v4l2_ctrl *free_run_color_ctrl_manual; 137 struct v4l2_ctrl *free_run_color_ctrl; 138 struct v4l2_ctrl *rgb_quantization_range_ctrl; 139 140 struct cec_adapter *cec_adap; 141 u8 cec_addr[ADV7842_MAX_ADDRS]; 142 u8 cec_valid_addrs; 143 bool cec_enabled_adap; 144}; 145 146/* Unsupported timings. This device cannot support 720p30. */ 147static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 148 V4L2_DV_BT_CEA_1280X720P30, 149 { } 150}; 151 152static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 153{ 154 int i; 155 156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 157 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) 158 return false; 159 return true; 160} 161 162struct adv7842_video_standards { 163 struct v4l2_dv_timings timings; 164 u8 vid_std; 165 u8 v_freq; 166}; 167 168/* sorted by number of lines */ 169static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 170 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 171 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 172 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 173 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 174 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 175 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 176 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 177 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 178 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 179 /* TODO add 1920x1080P60_RB (CVT timing) */ 180 { }, 181}; 182 183/* sorted by number of lines */ 184static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 185 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 186 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 187 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 188 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 189 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 190 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 191 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 192 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 193 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 194 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 195 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 196 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 197 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 198 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 199 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 200 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 201 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 202 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 203 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 204 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 205 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 206 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 207 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 208 { }, 209}; 210 211/* sorted by number of lines */ 212static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 213 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 214 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 215 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 216 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 217 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 218 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 219 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 220 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 221 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 222 { }, 223}; 224 225/* sorted by number of lines */ 226static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 227 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 228 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 229 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 230 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 231 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 232 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 233 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 234 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 235 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 236 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 237 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 238 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 239 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 240 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 241 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 242 { }, 243}; 244 245static const struct v4l2_event adv7842_ev_fmt = { 246 .type = V4L2_EVENT_SOURCE_CHANGE, 247 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 248}; 249 250/* ----------------------------------------------------------------------- */ 251 252static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 253{ 254 return container_of(sd, struct adv7842_state, sd); 255} 256 257static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 258{ 259 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 260} 261 262static inline unsigned htotal(const struct v4l2_bt_timings *t) 263{ 264 return V4L2_DV_BT_FRAME_WIDTH(t); 265} 266 267static inline unsigned vtotal(const struct v4l2_bt_timings *t) 268{ 269 return V4L2_DV_BT_FRAME_HEIGHT(t); 270} 271 272 273/* ----------------------------------------------------------------------- */ 274 275static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 276 u8 command, bool check) 277{ 278 union i2c_smbus_data data; 279 280 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 281 I2C_SMBUS_READ, command, 282 I2C_SMBUS_BYTE_DATA, &data)) 283 return data.byte; 284 if (check) 285 v4l_err(client, "error reading %02x, %02x\n", 286 client->addr, command); 287 return -EIO; 288} 289 290static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 291{ 292 int i; 293 294 for (i = 0; i < 3; i++) { 295 int ret = adv_smbus_read_byte_data_check(client, command, true); 296 297 if (ret >= 0) { 298 if (i) 299 v4l_err(client, "read ok after %d retries\n", i); 300 return ret; 301 } 302 } 303 v4l_err(client, "read failed\n"); 304 return -EIO; 305} 306 307static s32 adv_smbus_write_byte_data(struct i2c_client *client, 308 u8 command, u8 value) 309{ 310 union i2c_smbus_data data; 311 int err; 312 int i; 313 314 data.byte = value; 315 for (i = 0; i < 3; i++) { 316 err = i2c_smbus_xfer(client->adapter, client->addr, 317 client->flags, 318 I2C_SMBUS_WRITE, command, 319 I2C_SMBUS_BYTE_DATA, &data); 320 if (!err) 321 break; 322 } 323 if (err < 0) 324 v4l_err(client, "error writing %02x, %02x, %02x\n", 325 client->addr, command, value); 326 return err; 327} 328 329static void adv_smbus_write_byte_no_check(struct i2c_client *client, 330 u8 command, u8 value) 331{ 332 union i2c_smbus_data data; 333 data.byte = value; 334 335 i2c_smbus_xfer(client->adapter, client->addr, 336 client->flags, 337 I2C_SMBUS_WRITE, command, 338 I2C_SMBUS_BYTE_DATA, &data); 339} 340 341/* ----------------------------------------------------------------------- */ 342 343static inline int io_read(struct v4l2_subdev *sd, u8 reg) 344{ 345 struct i2c_client *client = v4l2_get_subdevdata(sd); 346 347 return adv_smbus_read_byte_data(client, reg); 348} 349 350static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 351{ 352 struct i2c_client *client = v4l2_get_subdevdata(sd); 353 354 return adv_smbus_write_byte_data(client, reg, val); 355} 356 357static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 358{ 359 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 360} 361 362static inline int io_write_clr_set(struct v4l2_subdev *sd, 363 u8 reg, u8 mask, u8 val) 364{ 365 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 366} 367 368static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 369{ 370 struct adv7842_state *state = to_state(sd); 371 372 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 373} 374 375static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 376{ 377 struct adv7842_state *state = to_state(sd); 378 379 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 380} 381 382static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 383{ 384 struct adv7842_state *state = to_state(sd); 385 386 return adv_smbus_read_byte_data(state->i2c_cec, reg); 387} 388 389static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 390{ 391 struct adv7842_state *state = to_state(sd); 392 393 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 394} 395 396static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 397{ 398 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 399} 400 401static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 402{ 403 struct adv7842_state *state = to_state(sd); 404 405 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 406} 407 408static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 409{ 410 struct adv7842_state *state = to_state(sd); 411 412 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 413} 414 415static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 416{ 417 struct adv7842_state *state = to_state(sd); 418 419 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 420} 421 422static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 423{ 424 struct adv7842_state *state = to_state(sd); 425 426 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 427} 428 429static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 430{ 431 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 432} 433 434static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 435{ 436 struct adv7842_state *state = to_state(sd); 437 438 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 439} 440 441static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 442{ 443 struct adv7842_state *state = to_state(sd); 444 445 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 446} 447 448static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 449{ 450 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 451} 452 453static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 454{ 455 struct adv7842_state *state = to_state(sd); 456 457 return adv_smbus_read_byte_data(state->i2c_afe, reg); 458} 459 460static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 461{ 462 struct adv7842_state *state = to_state(sd); 463 464 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 465} 466 467static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 468{ 469 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 470} 471 472static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 473{ 474 struct adv7842_state *state = to_state(sd); 475 476 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 477} 478 479static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 480{ 481 struct adv7842_state *state = to_state(sd); 482 483 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 484} 485 486static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 487{ 488 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 489} 490 491static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 492{ 493 struct adv7842_state *state = to_state(sd); 494 495 return adv_smbus_read_byte_data(state->i2c_edid, reg); 496} 497 498static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 499{ 500 struct adv7842_state *state = to_state(sd); 501 502 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 503} 504 505static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 506{ 507 struct adv7842_state *state = to_state(sd); 508 509 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 510} 511 512static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 513{ 514 struct adv7842_state *state = to_state(sd); 515 516 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 517} 518 519static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 520{ 521 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 522} 523 524static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 525{ 526 struct adv7842_state *state = to_state(sd); 527 528 return adv_smbus_read_byte_data(state->i2c_cp, reg); 529} 530 531static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 532{ 533 struct adv7842_state *state = to_state(sd); 534 535 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 536} 537 538static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 539{ 540 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 541} 542 543static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 544{ 545 struct adv7842_state *state = to_state(sd); 546 547 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 548} 549 550static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 551{ 552 struct adv7842_state *state = to_state(sd); 553 554 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 555} 556 557static void main_reset(struct v4l2_subdev *sd) 558{ 559 struct i2c_client *client = v4l2_get_subdevdata(sd); 560 561 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 562 563 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 564 565 mdelay(5); 566} 567 568/* ----------------------------------------------------------------------------- 569 * Format helpers 570 */ 571 572static const struct adv7842_format_info adv7842_formats[] = { 573 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, 574 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, 575 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, 576 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 577 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, 578 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 579 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, 580 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 581 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, 582 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 583 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, 584 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 585 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, 586 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 587 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, 588 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 589 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, 590 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 591 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, 592 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 593 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, 594 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 595 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, 596 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 597 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, 598 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 599 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, 600 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 601 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, 602 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 603 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, 604 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 605 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, 606 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 607 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, 608 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 609 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, 610 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 611}; 612 613static const struct adv7842_format_info * 614adv7842_format_info(struct adv7842_state *state, u32 code) 615{ 616 unsigned int i; 617 618 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { 619 if (adv7842_formats[i].code == code) 620 return &adv7842_formats[i]; 621 } 622 623 return NULL; 624} 625 626/* ----------------------------------------------------------------------- */ 627 628static inline bool is_analog_input(struct v4l2_subdev *sd) 629{ 630 struct adv7842_state *state = to_state(sd); 631 632 return ((state->mode == ADV7842_MODE_RGB) || 633 (state->mode == ADV7842_MODE_COMP)); 634} 635 636static inline bool is_digital_input(struct v4l2_subdev *sd) 637{ 638 struct adv7842_state *state = to_state(sd); 639 640 return state->mode == ADV7842_MODE_HDMI; 641} 642 643static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 644 .type = V4L2_DV_BT_656_1120, 645 /* keep this initialization for compatibility with GCC < 4.4.6 */ 646 .reserved = { 0 }, 647 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 648 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 649 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 650 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 651 V4L2_DV_BT_CAP_CUSTOM) 652}; 653 654static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 655 .type = V4L2_DV_BT_656_1120, 656 /* keep this initialization for compatibility with GCC < 4.4.6 */ 657 .reserved = { 0 }, 658 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 659 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 660 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 661 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 662 V4L2_DV_BT_CAP_CUSTOM) 663}; 664 665static inline const struct v4l2_dv_timings_cap * 666adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 667{ 668 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 669 &adv7842_timings_cap_analog; 670} 671 672/* ----------------------------------------------------------------------- */ 673 674static u16 adv7842_read_cable_det(struct v4l2_subdev *sd) 675{ 676 u8 reg = io_read(sd, 0x6f); 677 u16 val = 0; 678 679 if (reg & 0x02) 680 val |= 1; /* port A */ 681 if (reg & 0x01) 682 val |= 2; /* port B */ 683 return val; 684} 685 686static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 687{ 688 struct delayed_work *dwork = to_delayed_work(work); 689 struct adv7842_state *state = container_of(dwork, 690 struct adv7842_state, delayed_work_enable_hotplug); 691 struct v4l2_subdev *sd = &state->sd; 692 int present = state->hdmi_edid.present; 693 u8 mask = 0; 694 695 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 696 __func__, present); 697 698 if (present & (0x04 << ADV7842_EDID_PORT_A)) 699 mask |= 0x20; 700 if (present & (0x04 << ADV7842_EDID_PORT_B)) 701 mask |= 0x10; 702 io_write_and_or(sd, 0x20, 0xcf, mask); 703} 704 705static int edid_write_vga_segment(struct v4l2_subdev *sd) 706{ 707 struct i2c_client *client = v4l2_get_subdevdata(sd); 708 struct adv7842_state *state = to_state(sd); 709 const u8 *edid = state->vga_edid.edid; 710 u32 blocks = state->vga_edid.blocks; 711 int err = 0; 712 int i; 713 714 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 715 716 if (!state->vga_edid.present) 717 return 0; 718 719 /* HPA disable on port A and B */ 720 io_write_and_or(sd, 0x20, 0xcf, 0x00); 721 722 /* Disable I2C access to internal EDID ram from VGA DDC port */ 723 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 724 725 /* edid segment pointer '1' for VGA port */ 726 rep_write_and_or(sd, 0x77, 0xef, 0x10); 727 728 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) 729 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 730 I2C_SMBUS_BLOCK_MAX, 731 edid + i); 732 if (err) 733 return err; 734 735 /* Calculates the checksums and enables I2C access 736 * to internal EDID ram from VGA DDC port. 737 */ 738 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 739 740 for (i = 0; i < 1000; i++) { 741 if (rep_read(sd, 0x79) & 0x20) 742 break; 743 mdelay(1); 744 } 745 if (i == 1000) { 746 v4l_err(client, "error enabling edid on VGA port\n"); 747 return -EIO; 748 } 749 750 /* enable hotplug after 200 ms */ 751 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 752 753 return 0; 754} 755 756static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 757{ 758 struct i2c_client *client = v4l2_get_subdevdata(sd); 759 struct adv7842_state *state = to_state(sd); 760 const u8 *edid = state->hdmi_edid.edid; 761 u32 blocks = state->hdmi_edid.blocks; 762 unsigned int spa_loc; 763 u16 pa, parent_pa; 764 int err = 0; 765 int i; 766 767 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n", 768 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 769 770 /* HPA disable on port A and B */ 771 io_write_and_or(sd, 0x20, 0xcf, 0x00); 772 773 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 774 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 775 776 if (!state->hdmi_edid.present) { 777 cec_phys_addr_invalidate(state->cec_adap); 778 return 0; 779 } 780 781 pa = v4l2_get_edid_phys_addr(edid, blocks * 128, &spa_loc); 782 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 783 if (err) 784 return err; 785 786 if (!spa_loc) { 787 /* 788 * There is no SPA, so just set spa_loc to 128 and pa to whatever 789 * data is there. 790 */ 791 spa_loc = 128; 792 pa = (edid[spa_loc] << 8) | edid[spa_loc + 1]; 793 } 794 795 796 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) { 797 /* set edid segment pointer for HDMI ports */ 798 if (i % 256 == 0) 799 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00); 800 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 801 I2C_SMBUS_BLOCK_MAX, edid + i); 802 } 803 if (err) 804 return err; 805 806 if (port == ADV7842_EDID_PORT_A) { 807 rep_write(sd, 0x72, pa >> 8); 808 rep_write(sd, 0x73, pa & 0xff); 809 } else { 810 rep_write(sd, 0x74, pa >> 8); 811 rep_write(sd, 0x75, pa & 0xff); 812 } 813 rep_write(sd, 0x76, spa_loc & 0xff); 814 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 815 816 /* Calculates the checksums and enables I2C access to internal 817 * EDID ram from HDMI DDC ports 818 */ 819 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 820 821 for (i = 0; i < 1000; i++) { 822 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 823 break; 824 mdelay(1); 825 } 826 if (i == 1000) { 827 v4l_err(client, "error enabling edid on port %c\n", 828 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 829 return -EIO; 830 } 831 cec_s_phys_addr(state->cec_adap, parent_pa, false); 832 833 /* enable hotplug after 200 ms */ 834 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 835 836 return 0; 837} 838 839/* ----------------------------------------------------------------------- */ 840 841#ifdef CONFIG_VIDEO_ADV_DEBUG 842static void adv7842_inv_register(struct v4l2_subdev *sd) 843{ 844 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 845 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 846 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 847 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 848 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 849 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 850 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 851 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 852 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 853 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 854 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 855 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 856} 857 858static int adv7842_g_register(struct v4l2_subdev *sd, 859 struct v4l2_dbg_register *reg) 860{ 861 reg->size = 1; 862 switch (reg->reg >> 8) { 863 case 0: 864 reg->val = io_read(sd, reg->reg & 0xff); 865 break; 866 case 1: 867 reg->val = avlink_read(sd, reg->reg & 0xff); 868 break; 869 case 2: 870 reg->val = cec_read(sd, reg->reg & 0xff); 871 break; 872 case 3: 873 reg->val = infoframe_read(sd, reg->reg & 0xff); 874 break; 875 case 4: 876 reg->val = sdp_io_read(sd, reg->reg & 0xff); 877 break; 878 case 5: 879 reg->val = sdp_read(sd, reg->reg & 0xff); 880 break; 881 case 6: 882 reg->val = afe_read(sd, reg->reg & 0xff); 883 break; 884 case 7: 885 reg->val = rep_read(sd, reg->reg & 0xff); 886 break; 887 case 8: 888 reg->val = edid_read(sd, reg->reg & 0xff); 889 break; 890 case 9: 891 reg->val = hdmi_read(sd, reg->reg & 0xff); 892 break; 893 case 0xa: 894 reg->val = cp_read(sd, reg->reg & 0xff); 895 break; 896 case 0xb: 897 reg->val = vdp_read(sd, reg->reg & 0xff); 898 break; 899 default: 900 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 901 adv7842_inv_register(sd); 902 break; 903 } 904 return 0; 905} 906 907static int adv7842_s_register(struct v4l2_subdev *sd, 908 const struct v4l2_dbg_register *reg) 909{ 910 u8 val = reg->val & 0xff; 911 912 switch (reg->reg >> 8) { 913 case 0: 914 io_write(sd, reg->reg & 0xff, val); 915 break; 916 case 1: 917 avlink_write(sd, reg->reg & 0xff, val); 918 break; 919 case 2: 920 cec_write(sd, reg->reg & 0xff, val); 921 break; 922 case 3: 923 infoframe_write(sd, reg->reg & 0xff, val); 924 break; 925 case 4: 926 sdp_io_write(sd, reg->reg & 0xff, val); 927 break; 928 case 5: 929 sdp_write(sd, reg->reg & 0xff, val); 930 break; 931 case 6: 932 afe_write(sd, reg->reg & 0xff, val); 933 break; 934 case 7: 935 rep_write(sd, reg->reg & 0xff, val); 936 break; 937 case 8: 938 edid_write(sd, reg->reg & 0xff, val); 939 break; 940 case 9: 941 hdmi_write(sd, reg->reg & 0xff, val); 942 break; 943 case 0xa: 944 cp_write(sd, reg->reg & 0xff, val); 945 break; 946 case 0xb: 947 vdp_write(sd, reg->reg & 0xff, val); 948 break; 949 default: 950 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 951 adv7842_inv_register(sd); 952 break; 953 } 954 return 0; 955} 956#endif 957 958static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 959{ 960 struct adv7842_state *state = to_state(sd); 961 u16 cable_det = adv7842_read_cable_det(sd); 962 963 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det); 964 965 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 966} 967 968static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 969 u8 prim_mode, 970 const struct adv7842_video_standards *predef_vid_timings, 971 const struct v4l2_dv_timings *timings) 972{ 973 int i; 974 975 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 976 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 977 is_digital_input(sd) ? 250000 : 1000000, false)) 978 continue; 979 /* video std */ 980 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 981 /* v_freq and prim mode */ 982 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 983 return 0; 984 } 985 986 return -1; 987} 988 989static int configure_predefined_video_timings(struct v4l2_subdev *sd, 990 struct v4l2_dv_timings *timings) 991{ 992 struct adv7842_state *state = to_state(sd); 993 int err; 994 995 v4l2_dbg(1, debug, sd, "%s\n", __func__); 996 997 /* reset to default values */ 998 io_write(sd, 0x16, 0x43); 999 io_write(sd, 0x17, 0x5a); 1000 /* disable embedded syncs for auto graphics mode */ 1001 cp_write_and_or(sd, 0x81, 0xef, 0x00); 1002 cp_write(sd, 0x26, 0x00); 1003 cp_write(sd, 0x27, 0x00); 1004 cp_write(sd, 0x28, 0x00); 1005 cp_write(sd, 0x29, 0x00); 1006 cp_write(sd, 0x8f, 0x40); 1007 cp_write(sd, 0x90, 0x00); 1008 cp_write(sd, 0xa5, 0x00); 1009 cp_write(sd, 0xa6, 0x00); 1010 cp_write(sd, 0xa7, 0x00); 1011 cp_write(sd, 0xab, 0x00); 1012 cp_write(sd, 0xac, 0x00); 1013 1014 switch (state->mode) { 1015 case ADV7842_MODE_COMP: 1016 case ADV7842_MODE_RGB: 1017 err = find_and_set_predefined_video_timings(sd, 1018 0x01, adv7842_prim_mode_comp, timings); 1019 if (err) 1020 err = find_and_set_predefined_video_timings(sd, 1021 0x02, adv7842_prim_mode_gr, timings); 1022 break; 1023 case ADV7842_MODE_HDMI: 1024 err = find_and_set_predefined_video_timings(sd, 1025 0x05, adv7842_prim_mode_hdmi_comp, timings); 1026 if (err) 1027 err = find_and_set_predefined_video_timings(sd, 1028 0x06, adv7842_prim_mode_hdmi_gr, timings); 1029 break; 1030 default: 1031 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1032 __func__, state->mode); 1033 err = -1; 1034 break; 1035 } 1036 1037 1038 return err; 1039} 1040 1041static void configure_custom_video_timings(struct v4l2_subdev *sd, 1042 const struct v4l2_bt_timings *bt) 1043{ 1044 struct adv7842_state *state = to_state(sd); 1045 struct i2c_client *client = v4l2_get_subdevdata(sd); 1046 u32 width = htotal(bt); 1047 u32 height = vtotal(bt); 1048 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1049 u16 cp_start_eav = width - bt->hfrontporch; 1050 u16 cp_start_vbi = height - bt->vfrontporch + 1; 1051 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 1052 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1053 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1054 const u8 pll[2] = { 1055 0xc0 | ((width >> 8) & 0x1f), 1056 width & 0xff 1057 }; 1058 1059 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1060 1061 switch (state->mode) { 1062 case ADV7842_MODE_COMP: 1063 case ADV7842_MODE_RGB: 1064 /* auto graphics */ 1065 io_write(sd, 0x00, 0x07); /* video std */ 1066 io_write(sd, 0x01, 0x02); /* prim mode */ 1067 /* enable embedded syncs for auto graphics mode */ 1068 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1069 1070 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1071 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1072 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1073 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 1074 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1075 break; 1076 } 1077 1078 /* active video - horizontal timing */ 1079 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1080 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1081 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1082 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1083 1084 /* active video - vertical timing */ 1085 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1086 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1087 ((cp_end_vbi >> 8) & 0xf)); 1088 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1089 break; 1090 case ADV7842_MODE_HDMI: 1091 /* set default prim_mode/vid_std for HDMI 1092 according to [REF_03, c. 4.2] */ 1093 io_write(sd, 0x00, 0x02); /* video std */ 1094 io_write(sd, 0x01, 0x06); /* prim mode */ 1095 break; 1096 default: 1097 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1098 __func__, state->mode); 1099 break; 1100 } 1101 1102 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1103 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1104 cp_write(sd, 0xab, (height >> 4) & 0xff); 1105 cp_write(sd, 0xac, (height & 0x0f) << 4); 1106} 1107 1108static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1109{ 1110 struct adv7842_state *state = to_state(sd); 1111 u8 offset_buf[4]; 1112 1113 if (auto_offset) { 1114 offset_a = 0x3ff; 1115 offset_b = 0x3ff; 1116 offset_c = 0x3ff; 1117 } 1118 1119 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1120 __func__, auto_offset ? "Auto" : "Manual", 1121 offset_a, offset_b, offset_c); 1122 1123 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1124 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1125 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1126 offset_buf[3] = offset_c & 0x0ff; 1127 1128 /* Registers must be written in this order with no i2c access in between */ 1129 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1130 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1131} 1132 1133static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1134{ 1135 struct adv7842_state *state = to_state(sd); 1136 u8 gain_buf[4]; 1137 u8 gain_man = 1; 1138 u8 agc_mode_man = 1; 1139 1140 if (auto_gain) { 1141 gain_man = 0; 1142 agc_mode_man = 0; 1143 gain_a = 0x100; 1144 gain_b = 0x100; 1145 gain_c = 0x100; 1146 } 1147 1148 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1149 __func__, auto_gain ? "Auto" : "Manual", 1150 gain_a, gain_b, gain_c); 1151 1152 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1153 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1154 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1155 gain_buf[3] = ((gain_c & 0x0ff)); 1156 1157 /* Registers must be written in this order with no i2c access in between */ 1158 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1159 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1160} 1161 1162static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1163{ 1164 struct adv7842_state *state = to_state(sd); 1165 bool rgb_output = io_read(sd, 0x02) & 0x02; 1166 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1167 u8 y = HDMI_COLORSPACE_RGB; 1168 1169 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1170 y = infoframe_read(sd, 0x01) >> 5; 1171 1172 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1173 __func__, state->rgb_quantization_range, 1174 rgb_output, hdmi_signal); 1175 1176 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1177 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1178 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1179 1180 switch (state->rgb_quantization_range) { 1181 case V4L2_DV_RGB_RANGE_AUTO: 1182 if (state->mode == ADV7842_MODE_RGB) { 1183 /* Receiving analog RGB signal 1184 * Set RGB full range (0-255) */ 1185 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1186 break; 1187 } 1188 1189 if (state->mode == ADV7842_MODE_COMP) { 1190 /* Receiving analog YPbPr signal 1191 * Set automode */ 1192 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1193 break; 1194 } 1195 1196 if (hdmi_signal) { 1197 /* Receiving HDMI signal 1198 * Set automode */ 1199 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1200 break; 1201 } 1202 1203 /* Receiving DVI-D signal 1204 * ADV7842 selects RGB limited range regardless of 1205 * input format (CE/IT) in automatic mode */ 1206 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1207 /* RGB limited range (16-235) */ 1208 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1209 } else { 1210 /* RGB full range (0-255) */ 1211 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1212 1213 if (is_digital_input(sd) && rgb_output) { 1214 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1215 } else { 1216 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1217 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1218 } 1219 } 1220 break; 1221 case V4L2_DV_RGB_RANGE_LIMITED: 1222 if (state->mode == ADV7842_MODE_COMP) { 1223 /* YCrCb limited range (16-235) */ 1224 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1225 break; 1226 } 1227 1228 if (y != HDMI_COLORSPACE_RGB) 1229 break; 1230 1231 /* RGB limited range (16-235) */ 1232 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1233 1234 break; 1235 case V4L2_DV_RGB_RANGE_FULL: 1236 if (state->mode == ADV7842_MODE_COMP) { 1237 /* YCrCb full range (0-255) */ 1238 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1239 break; 1240 } 1241 1242 if (y != HDMI_COLORSPACE_RGB) 1243 break; 1244 1245 /* RGB full range (0-255) */ 1246 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1247 1248 if (is_analog_input(sd) || hdmi_signal) 1249 break; 1250 1251 /* Adjust gain/offset for DVI-D signals only */ 1252 if (rgb_output) { 1253 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1254 } else { 1255 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1256 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1257 } 1258 break; 1259 } 1260} 1261 1262static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1263{ 1264 struct v4l2_subdev *sd = to_sd(ctrl); 1265 struct adv7842_state *state = to_state(sd); 1266 1267 /* TODO SDP ctrls 1268 contrast/brightness/hue/free run is acting a bit strange, 1269 not sure if sdp csc is correct. 1270 */ 1271 switch (ctrl->id) { 1272 /* standard ctrls */ 1273 case V4L2_CID_BRIGHTNESS: 1274 cp_write(sd, 0x3c, ctrl->val); 1275 sdp_write(sd, 0x14, ctrl->val); 1276 /* ignore lsb sdp 0x17[3:2] */ 1277 return 0; 1278 case V4L2_CID_CONTRAST: 1279 cp_write(sd, 0x3a, ctrl->val); 1280 sdp_write(sd, 0x13, ctrl->val); 1281 /* ignore lsb sdp 0x17[1:0] */ 1282 return 0; 1283 case V4L2_CID_SATURATION: 1284 cp_write(sd, 0x3b, ctrl->val); 1285 sdp_write(sd, 0x15, ctrl->val); 1286 /* ignore lsb sdp 0x17[5:4] */ 1287 return 0; 1288 case V4L2_CID_HUE: 1289 cp_write(sd, 0x3d, ctrl->val); 1290 sdp_write(sd, 0x16, ctrl->val); 1291 /* ignore lsb sdp 0x17[7:6] */ 1292 return 0; 1293 /* custom ctrls */ 1294 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1295 afe_write(sd, 0xc8, ctrl->val); 1296 return 0; 1297 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1298 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1299 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1300 return 0; 1301 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1302 u8 R = (ctrl->val & 0xff0000) >> 16; 1303 u8 G = (ctrl->val & 0x00ff00) >> 8; 1304 u8 B = (ctrl->val & 0x0000ff); 1305 /* RGB -> YUV, numerical approximation */ 1306 int Y = 66 * R + 129 * G + 25 * B; 1307 int U = -38 * R - 74 * G + 112 * B; 1308 int V = 112 * R - 94 * G - 18 * B; 1309 1310 /* Scale down to 8 bits with rounding */ 1311 Y = (Y + 128) >> 8; 1312 U = (U + 128) >> 8; 1313 V = (V + 128) >> 8; 1314 /* make U,V positive */ 1315 Y += 16; 1316 U += 128; 1317 V += 128; 1318 1319 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1320 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1321 1322 /* CP */ 1323 cp_write(sd, 0xc1, R); 1324 cp_write(sd, 0xc0, G); 1325 cp_write(sd, 0xc2, B); 1326 /* SDP */ 1327 sdp_write(sd, 0xde, Y); 1328 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1329 return 0; 1330 } 1331 case V4L2_CID_DV_RX_RGB_RANGE: 1332 state->rgb_quantization_range = ctrl->val; 1333 set_rgb_quantization_range(sd); 1334 return 0; 1335 } 1336 return -EINVAL; 1337} 1338 1339static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1340{ 1341 struct v4l2_subdev *sd = to_sd(ctrl); 1342 1343 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1344 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1345 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1346 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1347 return 0; 1348 } 1349 return -EINVAL; 1350} 1351 1352static inline bool no_power(struct v4l2_subdev *sd) 1353{ 1354 return io_read(sd, 0x0c) & 0x24; 1355} 1356 1357static inline bool no_cp_signal(struct v4l2_subdev *sd) 1358{ 1359 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1360} 1361 1362static inline bool is_hdmi(struct v4l2_subdev *sd) 1363{ 1364 return hdmi_read(sd, 0x05) & 0x80; 1365} 1366 1367static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1368{ 1369 struct adv7842_state *state = to_state(sd); 1370 1371 *status = 0; 1372 1373 if (io_read(sd, 0x0c) & 0x24) 1374 *status |= V4L2_IN_ST_NO_POWER; 1375 1376 if (state->mode == ADV7842_MODE_SDP) { 1377 /* status from SDP block */ 1378 if (!(sdp_read(sd, 0x5A) & 0x01)) 1379 *status |= V4L2_IN_ST_NO_SIGNAL; 1380 1381 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1382 __func__, *status); 1383 return 0; 1384 } 1385 /* status from CP block */ 1386 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1387 !(cp_read(sd, 0xb1) & 0x80)) 1388 /* TODO channel 2 */ 1389 *status |= V4L2_IN_ST_NO_SIGNAL; 1390 1391 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1392 *status |= V4L2_IN_ST_NO_SIGNAL; 1393 1394 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1395 __func__, *status); 1396 1397 return 0; 1398} 1399 1400struct stdi_readback { 1401 u16 bl, lcf, lcvs; 1402 u8 hs_pol, vs_pol; 1403 bool interlaced; 1404}; 1405 1406static int stdi2dv_timings(struct v4l2_subdev *sd, 1407 struct stdi_readback *stdi, 1408 struct v4l2_dv_timings *timings) 1409{ 1410 struct adv7842_state *state = to_state(sd); 1411 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1412 u32 pix_clk; 1413 int i; 1414 1415 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1416 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1417 1418 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1419 adv7842_get_dv_timings_cap(sd), 1420 adv7842_check_dv_timings, NULL)) 1421 continue; 1422 if (vtotal(bt) != stdi->lcf + 1) 1423 continue; 1424 if (bt->vsync != stdi->lcvs) 1425 continue; 1426 1427 pix_clk = hfreq * htotal(bt); 1428 1429 if ((pix_clk < bt->pixelclock + 1000000) && 1430 (pix_clk > bt->pixelclock - 1000000)) { 1431 *timings = v4l2_dv_timings_presets[i]; 1432 return 0; 1433 } 1434 } 1435 1436 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1437 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1438 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1439 false, adv7842_get_dv_timings_cap(sd), timings)) 1440 return 0; 1441 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1442 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1443 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1444 false, state->aspect_ratio, 1445 adv7842_get_dv_timings_cap(sd), timings)) 1446 return 0; 1447 1448 v4l2_dbg(2, debug, sd, 1449 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1450 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1451 stdi->hs_pol, stdi->vs_pol); 1452 return -1; 1453} 1454 1455static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1456{ 1457 u32 status; 1458 1459 adv7842_g_input_status(sd, &status); 1460 if (status & V4L2_IN_ST_NO_SIGNAL) { 1461 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1462 return -ENOLINK; 1463 } 1464 1465 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1466 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1467 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1468 1469 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1470 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1471 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1472 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1473 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1474 } else { 1475 stdi->hs_pol = 'x'; 1476 stdi->vs_pol = 'x'; 1477 } 1478 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1479 1480 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1481 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1482 return -ENOLINK; 1483 } 1484 1485 v4l2_dbg(2, debug, sd, 1486 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1487 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1488 stdi->hs_pol, stdi->vs_pol, 1489 stdi->interlaced ? "interlaced" : "progressive"); 1490 1491 return 0; 1492} 1493 1494static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1495 struct v4l2_enum_dv_timings *timings) 1496{ 1497 if (timings->pad != 0) 1498 return -EINVAL; 1499 1500 return v4l2_enum_dv_timings_cap(timings, 1501 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1502} 1503 1504static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1505 struct v4l2_dv_timings_cap *cap) 1506{ 1507 if (cap->pad != 0) 1508 return -EINVAL; 1509 1510 *cap = *adv7842_get_dv_timings_cap(sd); 1511 return 0; 1512} 1513 1514/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1515 if the format is listed in adv7842_timings[] */ 1516static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1517 struct v4l2_dv_timings *timings) 1518{ 1519 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1520 is_digital_input(sd) ? 250000 : 1000000, 1521 adv7842_check_dv_timings, NULL); 1522 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; 1523} 1524 1525static int adv7842_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1526 struct v4l2_dv_timings *timings) 1527{ 1528 struct adv7842_state *state = to_state(sd); 1529 struct v4l2_bt_timings *bt = &timings->bt; 1530 struct stdi_readback stdi = { 0 }; 1531 1532 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1533 1534 if (pad != 0) 1535 return -EINVAL; 1536 1537 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1538 1539 /* SDP block */ 1540 if (state->mode == ADV7842_MODE_SDP) 1541 return -ENODATA; 1542 1543 /* read STDI */ 1544 if (read_stdi(sd, &stdi)) { 1545 state->restart_stdi_once = true; 1546 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1547 return -ENOLINK; 1548 } 1549 bt->interlaced = stdi.interlaced ? 1550 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1551 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1552 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1553 1554 if (is_digital_input(sd)) { 1555 u32 freq; 1556 1557 timings->type = V4L2_DV_BT_656_1120; 1558 1559 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1560 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1561 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1562 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1563 if (is_hdmi(sd)) { 1564 /* adjust for deep color mode */ 1565 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1566 } 1567 bt->pixelclock = freq; 1568 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1569 hdmi_read(sd, 0x21); 1570 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1571 hdmi_read(sd, 0x23); 1572 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1573 hdmi_read(sd, 0x25); 1574 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1575 hdmi_read(sd, 0x2b)) / 2; 1576 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1577 hdmi_read(sd, 0x2f)) / 2; 1578 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1579 hdmi_read(sd, 0x33)) / 2; 1580 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1581 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1582 if (bt->interlaced == V4L2_DV_INTERLACED) { 1583 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1584 hdmi_read(sd, 0x0c); 1585 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1586 hdmi_read(sd, 0x2d)) / 2; 1587 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1588 hdmi_read(sd, 0x31)) / 2; 1589 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1590 hdmi_read(sd, 0x35)) / 2; 1591 } else { 1592 bt->il_vfrontporch = 0; 1593 bt->il_vsync = 0; 1594 bt->il_vbackporch = 0; 1595 } 1596 adv7842_fill_optional_dv_timings_fields(sd, timings); 1597 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && 1598 freq < bt->pixelclock) { 1599 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; 1600 u32 delta_freq = abs(freq - reduced_freq); 1601 1602 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) 1603 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; 1604 } 1605 } else { 1606 /* find format 1607 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1608 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1609 */ 1610 if (!stdi2dv_timings(sd, &stdi, timings)) 1611 goto found; 1612 stdi.lcvs += 1; 1613 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1614 if (!stdi2dv_timings(sd, &stdi, timings)) 1615 goto found; 1616 stdi.lcvs -= 2; 1617 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1618 if (stdi2dv_timings(sd, &stdi, timings)) { 1619 /* 1620 * The STDI block may measure wrong values, especially 1621 * for lcvs and lcf. If the driver can not find any 1622 * valid timing, the STDI block is restarted to measure 1623 * the video timings again. The function will return an 1624 * error, but the restart of STDI will generate a new 1625 * STDI interrupt and the format detection process will 1626 * restart. 1627 */ 1628 if (state->restart_stdi_once) { 1629 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1630 /* TODO restart STDI for Sync Channel 2 */ 1631 /* enter one-shot mode */ 1632 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1633 /* trigger STDI restart */ 1634 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1635 /* reset to continuous mode */ 1636 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1637 state->restart_stdi_once = false; 1638 return -ENOLINK; 1639 } 1640 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1641 return -ERANGE; 1642 } 1643 state->restart_stdi_once = true; 1644 } 1645found: 1646 1647 if (debug > 1) 1648 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1649 timings, true); 1650 return 0; 1651} 1652 1653static int adv7842_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1654 struct v4l2_dv_timings *timings) 1655{ 1656 struct adv7842_state *state = to_state(sd); 1657 struct v4l2_bt_timings *bt; 1658 int err; 1659 1660 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1661 1662 if (pad != 0) 1663 return -EINVAL; 1664 1665 if (state->mode == ADV7842_MODE_SDP) 1666 return -ENODATA; 1667 1668 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1669 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1670 return 0; 1671 } 1672 1673 bt = &timings->bt; 1674 1675 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1676 adv7842_check_dv_timings, NULL)) 1677 return -ERANGE; 1678 1679 adv7842_fill_optional_dv_timings_fields(sd, timings); 1680 1681 state->timings = *timings; 1682 1683 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1684 1685 /* Use prim_mode and vid_std when available */ 1686 err = configure_predefined_video_timings(sd, timings); 1687 if (err) { 1688 /* custom settings when the video format 1689 does not have prim_mode/vid_std */ 1690 configure_custom_video_timings(sd, bt); 1691 } 1692 1693 set_rgb_quantization_range(sd); 1694 1695 1696 if (debug > 1) 1697 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1698 timings, true); 1699 return 0; 1700} 1701 1702static int adv7842_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1703 struct v4l2_dv_timings *timings) 1704{ 1705 struct adv7842_state *state = to_state(sd); 1706 1707 if (pad != 0) 1708 return -EINVAL; 1709 1710 if (state->mode == ADV7842_MODE_SDP) 1711 return -ENODATA; 1712 *timings = state->timings; 1713 return 0; 1714} 1715 1716static void enable_input(struct v4l2_subdev *sd) 1717{ 1718 struct adv7842_state *state = to_state(sd); 1719 1720 set_rgb_quantization_range(sd); 1721 switch (state->mode) { 1722 case ADV7842_MODE_SDP: 1723 case ADV7842_MODE_COMP: 1724 case ADV7842_MODE_RGB: 1725 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1726 break; 1727 case ADV7842_MODE_HDMI: 1728 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1729 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1730 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1731 break; 1732 default: 1733 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1734 __func__, state->mode); 1735 break; 1736 } 1737} 1738 1739static void disable_input(struct v4l2_subdev *sd) 1740{ 1741 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1742 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1743 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1744 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1745} 1746 1747static void sdp_csc_coeff(struct v4l2_subdev *sd, 1748 const struct adv7842_sdp_csc_coeff *c) 1749{ 1750 /* csc auto/manual */ 1751 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1752 1753 if (!c->manual) 1754 return; 1755 1756 /* csc scaling */ 1757 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1758 1759 /* A coeff */ 1760 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1761 sdp_io_write(sd, 0xe1, c->A1); 1762 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1763 sdp_io_write(sd, 0xe3, c->A2); 1764 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1765 sdp_io_write(sd, 0xe5, c->A3); 1766 1767 /* A scale */ 1768 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1769 sdp_io_write(sd, 0xe7, c->A4); 1770 1771 /* B coeff */ 1772 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1773 sdp_io_write(sd, 0xe9, c->B1); 1774 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1775 sdp_io_write(sd, 0xeb, c->B2); 1776 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1777 sdp_io_write(sd, 0xed, c->B3); 1778 1779 /* B scale */ 1780 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1781 sdp_io_write(sd, 0xef, c->B4); 1782 1783 /* C coeff */ 1784 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1785 sdp_io_write(sd, 0xf1, c->C1); 1786 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1787 sdp_io_write(sd, 0xf3, c->C2); 1788 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1789 sdp_io_write(sd, 0xf5, c->C3); 1790 1791 /* C scale */ 1792 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1793 sdp_io_write(sd, 0xf7, c->C4); 1794} 1795 1796static void select_input(struct v4l2_subdev *sd, 1797 enum adv7842_vid_std_select vid_std_select) 1798{ 1799 struct adv7842_state *state = to_state(sd); 1800 1801 switch (state->mode) { 1802 case ADV7842_MODE_SDP: 1803 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1804 io_write(sd, 0x01, 0); /* prim mode */ 1805 /* enable embedded syncs for auto graphics mode */ 1806 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1807 1808 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1809 afe_write(sd, 0xc8, 0x00); /* phase control */ 1810 1811 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1812 /* script says register 0xde, which don't exist in manual */ 1813 1814 /* Manual analog input muxing mode, CVBS (6.4)*/ 1815 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1816 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1817 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1818 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1819 } else { 1820 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1821 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1822 } 1823 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1824 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1825 1826 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1827 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1828 1829 /* SDP recommended settings */ 1830 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1831 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1832 1833 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1834 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1835 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1836 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1837 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1838 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1839 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1840 1841 /* deinterlacer enabled and 3D comb */ 1842 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1843 1844 break; 1845 1846 case ADV7842_MODE_COMP: 1847 case ADV7842_MODE_RGB: 1848 /* Automatic analog input muxing mode */ 1849 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1850 /* set mode and select free run resolution */ 1851 io_write(sd, 0x00, vid_std_select); /* video std */ 1852 io_write(sd, 0x01, 0x02); /* prim mode */ 1853 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1854 for auto graphics mode */ 1855 1856 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1857 afe_write(sd, 0xc8, 0x00); /* phase control */ 1858 if (state->mode == ADV7842_MODE_COMP) { 1859 /* force to YCrCb */ 1860 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1861 } else { 1862 /* force to RGB */ 1863 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1864 } 1865 1866 /* set ADI recommended settings for digitizer */ 1867 /* "ADV7842 Register Settings Recommendations 1868 * (rev. 1.8, November 2010)" p. 9. */ 1869 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1870 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1871 1872 /* set to default gain for RGB */ 1873 cp_write(sd, 0x73, 0x10); 1874 cp_write(sd, 0x74, 0x04); 1875 cp_write(sd, 0x75, 0x01); 1876 cp_write(sd, 0x76, 0x00); 1877 1878 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1879 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1880 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1881 break; 1882 1883 case ADV7842_MODE_HDMI: 1884 /* Automatic analog input muxing mode */ 1885 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1886 /* set mode and select free run resolution */ 1887 if (state->hdmi_port_a) 1888 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1889 else 1890 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1891 io_write(sd, 0x00, vid_std_select); /* video std */ 1892 io_write(sd, 0x01, 5); /* prim mode */ 1893 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1894 for auto graphics mode */ 1895 1896 /* set ADI recommended settings for HDMI: */ 1897 /* "ADV7842 Register Settings Recommendations 1898 * (rev. 1.8, November 2010)" p. 3. */ 1899 hdmi_write(sd, 0xc0, 0x00); 1900 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1901 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1902 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1903 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1904 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1905 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1906 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1907 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1908 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1909 Improve robustness */ 1910 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1911 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1912 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1913 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1914 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1915 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1916 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1917 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1918 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1919 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1920 1921 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1922 afe_write(sd, 0xc8, 0x40); /* phase control */ 1923 1924 /* set to default gain for HDMI */ 1925 cp_write(sd, 0x73, 0x10); 1926 cp_write(sd, 0x74, 0x04); 1927 cp_write(sd, 0x75, 0x01); 1928 cp_write(sd, 0x76, 0x00); 1929 1930 /* reset ADI recommended settings for digitizer */ 1931 /* "ADV7842 Register Settings Recommendations 1932 * (rev. 2.5, June 2010)" p. 17. */ 1933 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1934 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1935 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1936 1937 /* CP coast control */ 1938 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1939 1940 /* color space conversion, autodetect color space */ 1941 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1942 break; 1943 1944 default: 1945 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1946 __func__, state->mode); 1947 break; 1948 } 1949} 1950 1951static int adv7842_s_routing(struct v4l2_subdev *sd, 1952 u32 input, u32 output, u32 config) 1953{ 1954 struct adv7842_state *state = to_state(sd); 1955 1956 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1957 1958 switch (input) { 1959 case ADV7842_SELECT_HDMI_PORT_A: 1960 state->mode = ADV7842_MODE_HDMI; 1961 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1962 state->hdmi_port_a = true; 1963 break; 1964 case ADV7842_SELECT_HDMI_PORT_B: 1965 state->mode = ADV7842_MODE_HDMI; 1966 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1967 state->hdmi_port_a = false; 1968 break; 1969 case ADV7842_SELECT_VGA_COMP: 1970 state->mode = ADV7842_MODE_COMP; 1971 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1972 break; 1973 case ADV7842_SELECT_VGA_RGB: 1974 state->mode = ADV7842_MODE_RGB; 1975 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1976 break; 1977 case ADV7842_SELECT_SDP_CVBS: 1978 state->mode = ADV7842_MODE_SDP; 1979 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1980 break; 1981 case ADV7842_SELECT_SDP_YC: 1982 state->mode = ADV7842_MODE_SDP; 1983 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1984 break; 1985 default: 1986 return -EINVAL; 1987 } 1988 1989 disable_input(sd); 1990 select_input(sd, state->vid_std_select); 1991 enable_input(sd); 1992 1993 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 1994 1995 return 0; 1996} 1997 1998static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, 1999 struct v4l2_subdev_state *sd_state, 2000 struct v4l2_subdev_mbus_code_enum *code) 2001{ 2002 if (code->index >= ARRAY_SIZE(adv7842_formats)) 2003 return -EINVAL; 2004 code->code = adv7842_formats[code->index].code; 2005 return 0; 2006} 2007 2008static void adv7842_fill_format(struct adv7842_state *state, 2009 struct v4l2_mbus_framefmt *format) 2010{ 2011 memset(format, 0, sizeof(*format)); 2012 2013 format->width = state->timings.bt.width; 2014 format->height = state->timings.bt.height; 2015 format->field = V4L2_FIELD_NONE; 2016 format->colorspace = V4L2_COLORSPACE_SRGB; 2017 2018 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 2019 format->colorspace = (state->timings.bt.height <= 576) ? 2020 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 2021} 2022 2023/* 2024 * Compute the op_ch_sel value required to obtain on the bus the component order 2025 * corresponding to the selected format taking into account bus reordering 2026 * applied by the board at the output of the device. 2027 * 2028 * The following table gives the op_ch_value from the format component order 2029 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 2030 * adv7842_bus_order value in row). 2031 * 2032 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 2033 * ----------+------------------------------------------------- 2034 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 2035 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 2036 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 2037 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 2038 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 2039 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 2040 */ 2041static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) 2042{ 2043#define _SEL(a, b, c, d, e, f) { \ 2044 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ 2045 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } 2046#define _BUS(x) [ADV7842_BUS_ORDER_##x] 2047 2048 static const unsigned int op_ch_sel[6][6] = { 2049 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 2050 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 2051 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 2052 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 2053 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 2054 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 2055 }; 2056 2057 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 2058} 2059 2060static void adv7842_setup_format(struct adv7842_state *state) 2061{ 2062 struct v4l2_subdev *sd = &state->sd; 2063 2064 io_write_clr_set(sd, 0x02, 0x02, 2065 state->format->rgb_out ? ADV7842_RGB_OUT : 0); 2066 io_write(sd, 0x03, state->format->op_format_sel | 2067 state->pdata.op_format_mode_sel); 2068 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); 2069 io_write_clr_set(sd, 0x05, 0x01, 2070 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); 2071 set_rgb_quantization_range(sd); 2072} 2073 2074static int adv7842_get_format(struct v4l2_subdev *sd, 2075 struct v4l2_subdev_state *sd_state, 2076 struct v4l2_subdev_format *format) 2077{ 2078 struct adv7842_state *state = to_state(sd); 2079 2080 if (format->pad != ADV7842_PAD_SOURCE) 2081 return -EINVAL; 2082 2083 if (state->mode == ADV7842_MODE_SDP) { 2084 /* SPD block */ 2085 if (!(sdp_read(sd, 0x5a) & 0x01)) 2086 return -EINVAL; 2087 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; 2088 format->format.width = 720; 2089 /* valid signal */ 2090 if (state->norm & V4L2_STD_525_60) 2091 format->format.height = 480; 2092 else 2093 format->format.height = 576; 2094 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 2095 return 0; 2096 } 2097 2098 adv7842_fill_format(state, &format->format); 2099 2100 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2101 struct v4l2_mbus_framefmt *fmt; 2102 2103 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 2104 format->format.code = fmt->code; 2105 } else { 2106 format->format.code = state->format->code; 2107 } 2108 2109 return 0; 2110} 2111 2112static int adv7842_set_format(struct v4l2_subdev *sd, 2113 struct v4l2_subdev_state *sd_state, 2114 struct v4l2_subdev_format *format) 2115{ 2116 struct adv7842_state *state = to_state(sd); 2117 const struct adv7842_format_info *info; 2118 2119 if (format->pad != ADV7842_PAD_SOURCE) 2120 return -EINVAL; 2121 2122 if (state->mode == ADV7842_MODE_SDP) 2123 return adv7842_get_format(sd, sd_state, format); 2124 2125 info = adv7842_format_info(state, format->format.code); 2126 if (info == NULL) 2127 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2128 2129 adv7842_fill_format(state, &format->format); 2130 format->format.code = info->code; 2131 2132 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2133 struct v4l2_mbus_framefmt *fmt; 2134 2135 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 2136 fmt->code = format->format.code; 2137 } else { 2138 state->format = info; 2139 adv7842_setup_format(state); 2140 } 2141 2142 return 0; 2143} 2144 2145static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 2146{ 2147 if (enable) { 2148 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 2149 io_write(sd, 0x46, 0x9c); 2150 /* ESDP_50HZ_DET interrupt */ 2151 io_write(sd, 0x5a, 0x10); 2152 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 2153 io_write(sd, 0x73, 0x03); 2154 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2155 io_write(sd, 0x78, 0x03); 2156 /* Enable SDP Standard Detection Change and SDP Video Detected */ 2157 io_write(sd, 0xa0, 0x09); 2158 /* Enable HDMI_MODE interrupt */ 2159 io_write(sd, 0x69, 0x08); 2160 } else { 2161 io_write(sd, 0x46, 0x0); 2162 io_write(sd, 0x5a, 0x0); 2163 io_write(sd, 0x73, 0x0); 2164 io_write(sd, 0x78, 0x0); 2165 io_write(sd, 0xa0, 0x0); 2166 io_write(sd, 0x69, 0x0); 2167 } 2168} 2169 2170#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2171static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 2172{ 2173 struct adv7842_state *state = to_state(sd); 2174 2175 if ((cec_read(sd, 0x11) & 0x01) == 0) { 2176 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 2177 return; 2178 } 2179 2180 if (tx_raw_status & 0x02) { 2181 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2182 __func__); 2183 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2184 1, 0, 0, 0); 2185 return; 2186 } 2187 if (tx_raw_status & 0x04) { 2188 u8 status; 2189 u8 nack_cnt; 2190 u8 low_drive_cnt; 2191 2192 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2193 /* 2194 * We set this status bit since this hardware performs 2195 * retransmissions. 2196 */ 2197 status = CEC_TX_STATUS_MAX_RETRIES; 2198 nack_cnt = cec_read(sd, 0x14) & 0xf; 2199 if (nack_cnt) 2200 status |= CEC_TX_STATUS_NACK; 2201 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2202 if (low_drive_cnt) 2203 status |= CEC_TX_STATUS_LOW_DRIVE; 2204 cec_transmit_done(state->cec_adap, status, 2205 0, nack_cnt, low_drive_cnt, 0); 2206 return; 2207 } 2208 if (tx_raw_status & 0x01) { 2209 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2210 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2211 return; 2212 } 2213} 2214 2215static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled) 2216{ 2217 u8 cec_irq; 2218 2219 /* cec controller */ 2220 cec_irq = io_read(sd, 0x93) & 0x0f; 2221 if (!cec_irq) 2222 return; 2223 2224 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2225 adv7842_cec_tx_raw_status(sd, cec_irq); 2226 if (cec_irq & 0x08) { 2227 struct adv7842_state *state = to_state(sd); 2228 struct cec_msg msg; 2229 2230 msg.len = cec_read(sd, 0x25) & 0x1f; 2231 if (msg.len > CEC_MAX_MSG_SIZE) 2232 msg.len = CEC_MAX_MSG_SIZE; 2233 2234 if (msg.len) { 2235 u8 i; 2236 2237 for (i = 0; i < msg.len; i++) 2238 msg.msg[i] = cec_read(sd, i + 0x15); 2239 cec_write(sd, 0x26, 0x01); /* re-enable rx */ 2240 cec_received_msg(state->cec_adap, &msg); 2241 } 2242 } 2243 2244 io_write(sd, 0x94, cec_irq); 2245 2246 if (handled) 2247 *handled = true; 2248} 2249 2250static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable) 2251{ 2252 struct adv7842_state *state = cec_get_drvdata(adap); 2253 struct v4l2_subdev *sd = &state->sd; 2254 2255 if (!state->cec_enabled_adap && enable) { 2256 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2257 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2258 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2259 /* enabled irqs: */ 2260 /* tx: ready */ 2261 /* tx: arbitration lost */ 2262 /* tx: retry timeout */ 2263 /* rx: ready */ 2264 io_write_clr_set(sd, 0x96, 0x0f, 0x0f); 2265 cec_write(sd, 0x26, 0x01); /* enable rx */ 2266 } else if (state->cec_enabled_adap && !enable) { 2267 /* disable cec interrupts */ 2268 io_write_clr_set(sd, 0x96, 0x0f, 0x00); 2269 /* disable address mask 1-3 */ 2270 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2271 /* power down cec section */ 2272 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2273 state->cec_valid_addrs = 0; 2274 } 2275 state->cec_enabled_adap = enable; 2276 return 0; 2277} 2278 2279static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2280{ 2281 struct adv7842_state *state = cec_get_drvdata(adap); 2282 struct v4l2_subdev *sd = &state->sd; 2283 unsigned int i, free_idx = ADV7842_MAX_ADDRS; 2284 2285 if (!state->cec_enabled_adap) 2286 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2287 2288 if (addr == CEC_LOG_ADDR_INVALID) { 2289 cec_write_clr_set(sd, 0x27, 0x70, 0); 2290 state->cec_valid_addrs = 0; 2291 return 0; 2292 } 2293 2294 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2295 bool is_valid = state->cec_valid_addrs & (1 << i); 2296 2297 if (free_idx == ADV7842_MAX_ADDRS && !is_valid) 2298 free_idx = i; 2299 if (is_valid && state->cec_addr[i] == addr) 2300 return 0; 2301 } 2302 if (i == ADV7842_MAX_ADDRS) { 2303 i = free_idx; 2304 if (i == ADV7842_MAX_ADDRS) 2305 return -ENXIO; 2306 } 2307 state->cec_addr[i] = addr; 2308 state->cec_valid_addrs |= 1 << i; 2309 2310 switch (i) { 2311 case 0: 2312 /* enable address mask 0 */ 2313 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2314 /* set address for mask 0 */ 2315 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2316 break; 2317 case 1: 2318 /* enable address mask 1 */ 2319 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2320 /* set address for mask 1 */ 2321 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2322 break; 2323 case 2: 2324 /* enable address mask 2 */ 2325 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2326 /* set address for mask 1 */ 2327 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2328 break; 2329 } 2330 return 0; 2331} 2332 2333static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2334 u32 signal_free_time, struct cec_msg *msg) 2335{ 2336 struct adv7842_state *state = cec_get_drvdata(adap); 2337 struct v4l2_subdev *sd = &state->sd; 2338 u8 len = msg->len; 2339 unsigned int i; 2340 2341 /* 2342 * The number of retries is the number of attempts - 1, but retry 2343 * at least once. It's not clear if a value of 0 is allowed, so 2344 * let's do at least one retry. 2345 */ 2346 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2347 2348 if (len > 16) { 2349 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2350 return -EINVAL; 2351 } 2352 2353 /* write data */ 2354 for (i = 0; i < len; i++) 2355 cec_write(sd, i, msg->msg[i]); 2356 2357 /* set length (data + header) */ 2358 cec_write(sd, 0x10, len); 2359 /* start transmit, enable tx */ 2360 cec_write(sd, 0x11, 0x01); 2361 return 0; 2362} 2363 2364static const struct cec_adap_ops adv7842_cec_adap_ops = { 2365 .adap_enable = adv7842_cec_adap_enable, 2366 .adap_log_addr = adv7842_cec_adap_log_addr, 2367 .adap_transmit = adv7842_cec_adap_transmit, 2368}; 2369#endif 2370 2371static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2372{ 2373 struct adv7842_state *state = to_state(sd); 2374 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 2375 u8 irq_status[6]; 2376 2377 adv7842_irq_enable(sd, false); 2378 2379 /* read status */ 2380 irq_status[0] = io_read(sd, 0x43); 2381 irq_status[1] = io_read(sd, 0x57); 2382 irq_status[2] = io_read(sd, 0x70); 2383 irq_status[3] = io_read(sd, 0x75); 2384 irq_status[4] = io_read(sd, 0x9d); 2385 irq_status[5] = io_read(sd, 0x66); 2386 2387 /* and clear */ 2388 if (irq_status[0]) 2389 io_write(sd, 0x44, irq_status[0]); 2390 if (irq_status[1]) 2391 io_write(sd, 0x58, irq_status[1]); 2392 if (irq_status[2]) 2393 io_write(sd, 0x71, irq_status[2]); 2394 if (irq_status[3]) 2395 io_write(sd, 0x76, irq_status[3]); 2396 if (irq_status[4]) 2397 io_write(sd, 0x9e, irq_status[4]); 2398 if (irq_status[5]) 2399 io_write(sd, 0x67, irq_status[5]); 2400 2401 adv7842_irq_enable(sd, true); 2402 2403 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 2404 irq_status[0], irq_status[1], irq_status[2], 2405 irq_status[3], irq_status[4], irq_status[5]); 2406 2407 /* format change CP */ 2408 fmt_change_cp = irq_status[0] & 0x9c; 2409 2410 /* format change SDP */ 2411 if (state->mode == ADV7842_MODE_SDP) 2412 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 2413 else 2414 fmt_change_sdp = 0; 2415 2416 /* digital format CP */ 2417 if (is_digital_input(sd)) 2418 fmt_change_digital = irq_status[3] & 0x03; 2419 else 2420 fmt_change_digital = 0; 2421 2422 /* format change */ 2423 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 2424 v4l2_dbg(1, debug, sd, 2425 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 2426 __func__, fmt_change_cp, fmt_change_digital, 2427 fmt_change_sdp); 2428 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 2429 if (handled) 2430 *handled = true; 2431 } 2432 2433 /* HDMI/DVI mode */ 2434 if (irq_status[5] & 0x08) { 2435 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2436 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2437 set_rgb_quantization_range(sd); 2438 if (handled) 2439 *handled = true; 2440 } 2441 2442#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2443 /* cec */ 2444 adv7842_cec_isr(sd, handled); 2445#endif 2446 2447 /* tx 5v detect */ 2448 if (irq_status[2] & 0x3) { 2449 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2450 adv7842_s_detect_tx_5v_ctrl(sd); 2451 if (handled) 2452 *handled = true; 2453 } 2454 return 0; 2455} 2456 2457static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2458{ 2459 struct adv7842_state *state = to_state(sd); 2460 u32 blocks = 0; 2461 u8 *data = NULL; 2462 2463 memset(edid->reserved, 0, sizeof(edid->reserved)); 2464 2465 switch (edid->pad) { 2466 case ADV7842_EDID_PORT_A: 2467 case ADV7842_EDID_PORT_B: 2468 if (state->hdmi_edid.present & (0x04 << edid->pad)) { 2469 data = state->hdmi_edid.edid; 2470 blocks = state->hdmi_edid.blocks; 2471 } 2472 break; 2473 case ADV7842_EDID_PORT_VGA: 2474 if (state->vga_edid.present) { 2475 data = state->vga_edid.edid; 2476 blocks = state->vga_edid.blocks; 2477 } 2478 break; 2479 default: 2480 return -EINVAL; 2481 } 2482 2483 if (edid->start_block == 0 && edid->blocks == 0) { 2484 edid->blocks = blocks; 2485 return 0; 2486 } 2487 2488 if (!data) 2489 return -ENODATA; 2490 2491 if (edid->start_block >= blocks) 2492 return -EINVAL; 2493 2494 if (edid->start_block + edid->blocks > blocks) 2495 edid->blocks = blocks - edid->start_block; 2496 2497 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2498 2499 return 0; 2500} 2501 2502/* 2503 * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then 2504 * the first two blocks of the EDID are for the HDMI, and the first block 2505 * of segment 1 (i.e. the third block of the EDID) is for VGA. 2506 * So if a VGA EDID is installed, then the maximum size of the HDMI EDID 2507 * is 2 blocks. 2508 */ 2509static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2510{ 2511 struct adv7842_state *state = to_state(sd); 2512 unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4; 2513 int err = 0; 2514 2515 memset(e->reserved, 0, sizeof(e->reserved)); 2516 2517 if (e->pad > ADV7842_EDID_PORT_VGA) 2518 return -EINVAL; 2519 if (e->start_block != 0) 2520 return -EINVAL; 2521 if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks) 2522 max_blocks = 2; 2523 if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2) 2524 return -EBUSY; 2525 if (e->blocks > max_blocks) { 2526 e->blocks = max_blocks; 2527 return -E2BIG; 2528 } 2529 2530 /* todo, per edid */ 2531 if (e->blocks) 2532 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2533 e->edid[0x16]); 2534 2535 switch (e->pad) { 2536 case ADV7842_EDID_PORT_VGA: 2537 memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid)); 2538 state->vga_edid.blocks = e->blocks; 2539 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2540 if (e->blocks) 2541 memcpy(state->vga_edid.edid, e->edid, 128); 2542 err = edid_write_vga_segment(sd); 2543 break; 2544 case ADV7842_EDID_PORT_A: 2545 case ADV7842_EDID_PORT_B: 2546 memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid)); 2547 state->hdmi_edid.blocks = e->blocks; 2548 if (e->blocks) { 2549 state->hdmi_edid.present |= 0x04 << e->pad; 2550 memcpy(state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2551 } else { 2552 state->hdmi_edid.present &= ~(0x04 << e->pad); 2553 adv7842_s_detect_tx_5v_ctrl(sd); 2554 } 2555 err = edid_write_hdmi_segment(sd, e->pad); 2556 break; 2557 default: 2558 return -EINVAL; 2559 } 2560 if (err < 0) 2561 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2562 return err; 2563} 2564 2565struct adv7842_cfg_read_infoframe { 2566 const char *desc; 2567 u8 present_mask; 2568 u8 head_addr; 2569 u8 payload_addr; 2570}; 2571 2572static const struct adv7842_cfg_read_infoframe adv7842_cri[] = { 2573 { "AVI", 0x01, 0xe0, 0x00 }, 2574 { "Audio", 0x02, 0xe3, 0x1c }, 2575 { "SDP", 0x04, 0xe6, 0x2a }, 2576 { "Vendor", 0x10, 0xec, 0x54 } 2577}; 2578 2579static int adv7842_read_infoframe_buf(struct v4l2_subdev *sd, int index, 2580 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN]) 2581{ 2582 const struct adv7842_cfg_read_infoframe *cri = &adv7842_cri[index]; 2583 int len, i; 2584 2585 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2586 v4l2_dbg(1, debug, sd, 2587 "%s infoframe not received\n", cri->desc); 2588 return -ENOENT; 2589 } 2590 2591 for (i = 0; i < 3; i++) 2592 buf[i] = infoframe_read(sd, cri->head_addr + i); 2593 2594 len = buf[2] + 1; 2595 2596 if (len + 3 > V4L2_DEBUGFS_IF_MAX_LEN) { 2597 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", 2598 __func__, cri->desc, len); 2599 return -ENOENT; 2600 } 2601 2602 for (i = 0; i < len; i++) 2603 buf[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2604 return len + 3; 2605} 2606 2607static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2608{ 2609 struct i2c_client *client = v4l2_get_subdevdata(sd); 2610 struct device *dev = &client->dev; 2611 union hdmi_infoframe frame; 2612 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 2613 int len, i; 2614 2615 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2616 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2617 return; 2618 } 2619 2620 for (i = 0; i < ARRAY_SIZE(adv7842_cri); i++) { 2621 len = adv7842_read_infoframe_buf(sd, i, buffer); 2622 if (len < 0) 2623 continue; 2624 2625 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0) 2626 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", 2627 __func__, adv7842_cri[i].desc); 2628 else 2629 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2630 } 2631} 2632 2633#if 0 2634/* Let's keep it here for now, as it could be useful for debug */ 2635static const char * const prim_mode_txt[] = { 2636 "SDP", 2637 "Component", 2638 "Graphics", 2639 "Reserved", 2640 "CVBS & HDMI AUDIO", 2641 "HDMI-Comp", 2642 "HDMI-GR", 2643 "Reserved", 2644 "Reserved", 2645 "Reserved", 2646 "Reserved", 2647 "Reserved", 2648 "Reserved", 2649 "Reserved", 2650 "Reserved", 2651 "Reserved", 2652}; 2653#endif 2654 2655static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2656{ 2657 /* SDP (Standard definition processor) block */ 2658 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2659 2660 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2661 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2662 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2663 2664 v4l2_info(sd, "SDP: free run: %s\n", 2665 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2666 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2667 "valid SD/PR signal detected" : "invalid/no signal"); 2668 if (sdp_signal_detected) { 2669 static const char * const sdp_std_txt[] = { 2670 "NTSC-M/J", 2671 "1?", 2672 "NTSC-443", 2673 "60HzSECAM", 2674 "PAL-M", 2675 "5?", 2676 "PAL-60", 2677 "7?", "8?", "9?", "a?", "b?", 2678 "PAL-CombN", 2679 "d?", 2680 "PAL-BGHID", 2681 "SECAM" 2682 }; 2683 v4l2_info(sd, "SDP: standard %s\n", 2684 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2685 v4l2_info(sd, "SDP: %s\n", 2686 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2687 v4l2_info(sd, "SDP: %s\n", 2688 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2689 v4l2_info(sd, "SDP: deinterlacer %s\n", 2690 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2691 v4l2_info(sd, "SDP: csc %s mode\n", 2692 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2693 } 2694 return 0; 2695} 2696 2697static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2698{ 2699 /* CP block */ 2700 struct adv7842_state *state = to_state(sd); 2701 struct v4l2_dv_timings timings; 2702 int temp; 2703 u8 reg_io_0x02 = io_read(sd, 0x02); 2704 u8 reg_io_0x21 = io_read(sd, 0x21); 2705 u8 reg_rep_0x77 = rep_read(sd, 0x77); 2706 u8 reg_rep_0x7d = rep_read(sd, 0x7d); 2707 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2708 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2709 bool audio_mute = io_read(sd, 0x65) & 0x40; 2710 2711 static const char * const csc_coeff_sel_rb[16] = { 2712 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2713 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2714 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2715 "reserved", "reserved", "reserved", "reserved", "manual" 2716 }; 2717 static const char * const input_color_space_txt[16] = { 2718 "RGB limited range (16-235)", "RGB full range (0-255)", 2719 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2720 "xvYCC Bt.601", "xvYCC Bt.709", 2721 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2722 "invalid", "invalid", "invalid", "invalid", "invalid", 2723 "invalid", "invalid", "automatic" 2724 }; 2725 static const char * const rgb_quantization_range_txt[] = { 2726 "Automatic", 2727 "RGB limited range (16-235)", 2728 "RGB full range (0-255)", 2729 }; 2730 static const char * const deep_color_mode_txt[4] = { 2731 "8-bits per channel", 2732 "10-bits per channel", 2733 "12-bits per channel", 2734 "16-bits per channel (not supported)" 2735 }; 2736 2737 v4l2_info(sd, "-----Chip status-----\n"); 2738 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2739 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2740 state->hdmi_port_a ? "A" : "B"); 2741 v4l2_info(sd, "EDID A %s, B %s\n", 2742 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2743 "enabled" : "disabled", 2744 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2745 "enabled" : "disabled"); 2746 v4l2_info(sd, "HPD A %s, B %s\n", 2747 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2748 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2749 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2750 "enabled" : "disabled"); 2751 if (state->cec_enabled_adap) { 2752 int i; 2753 2754 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2755 bool is_valid = state->cec_valid_addrs & (1 << i); 2756 2757 if (is_valid) 2758 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2759 state->cec_addr[i]); 2760 } 2761 } 2762 2763 v4l2_info(sd, "-----Signal status-----\n"); 2764 if (state->hdmi_port_a) { 2765 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2766 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2767 v4l2_info(sd, "TMDS signal detected: %s\n", 2768 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2769 v4l2_info(sd, "TMDS signal locked: %s\n", 2770 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2771 } else { 2772 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2773 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2774 v4l2_info(sd, "TMDS signal detected: %s\n", 2775 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2776 v4l2_info(sd, "TMDS signal locked: %s\n", 2777 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2778 } 2779 v4l2_info(sd, "CP free run: %s\n", 2780 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2781 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2782 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2783 (io_read(sd, 0x01) & 0x70) >> 4); 2784 2785 v4l2_info(sd, "-----Video Timings-----\n"); 2786 if (no_cp_signal(sd)) { 2787 v4l2_info(sd, "STDI: not locked\n"); 2788 } else { 2789 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2790 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2791 u32 lcvs = cp_read(sd, 0xb3) >> 3; 2792 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2793 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2794 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2795 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2796 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2797 v4l2_info(sd, 2798 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2799 lcf, bl, lcvs, fcl, 2800 (cp_read(sd, 0xb1) & 0x40) ? 2801 "interlaced" : "progressive", 2802 hs_pol, vs_pol); 2803 } 2804 if (adv7842_query_dv_timings(sd, 0, &timings)) 2805 v4l2_info(sd, "No video detected\n"); 2806 else 2807 v4l2_print_dv_timings(sd->name, "Detected format: ", 2808 &timings, true); 2809 v4l2_print_dv_timings(sd->name, "Configured format: ", 2810 &state->timings, true); 2811 2812 if (no_cp_signal(sd)) 2813 return 0; 2814 2815 v4l2_info(sd, "-----Color space-----\n"); 2816 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2817 rgb_quantization_range_txt[state->rgb_quantization_range]); 2818 v4l2_info(sd, "Input color space: %s\n", 2819 input_color_space_txt[reg_io_0x02 >> 4]); 2820 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2821 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2822 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2823 "(16-235)" : "(0-255)", 2824 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2825 temp = cp_read(sd, 0xf4) >> 4; 2826 v4l2_info(sd, "Color space conversion: %s\n", 2827 temp < 0 ? "" : csc_coeff_sel_rb[temp]); 2828 2829 if (!is_digital_input(sd)) 2830 return 0; 2831 2832 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2833 v4l2_info(sd, "HDCP encrypted content: %s\n", 2834 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2835 v4l2_info(sd, "HDCP keys read: %s%s\n", 2836 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2837 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2838 if (!is_hdmi(sd)) 2839 return 0; 2840 2841 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2842 audio_pll_locked ? "locked" : "not locked", 2843 audio_sample_packet_detect ? "detected" : "not detected", 2844 audio_mute ? "muted" : "enabled"); 2845 if (audio_pll_locked && audio_sample_packet_detect) { 2846 v4l2_info(sd, "Audio format: %s\n", 2847 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2848 } 2849 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2850 (hdmi_read(sd, 0x5c) << 8) + 2851 (hdmi_read(sd, 0x5d) & 0xf0)); 2852 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2853 (hdmi_read(sd, 0x5e) << 8) + 2854 hdmi_read(sd, 0x5f)); 2855 v4l2_info(sd, "AV Mute: %s\n", 2856 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2857 temp = hdmi_read(sd, 0x0b) >> 6; 2858 v4l2_info(sd, "Deep color mode: %s\n", 2859 temp < 0 ? "" : deep_color_mode_txt[temp]); 2860 2861 adv7842_log_infoframes(sd); 2862 2863 return 0; 2864} 2865 2866static int adv7842_log_status(struct v4l2_subdev *sd) 2867{ 2868 struct adv7842_state *state = to_state(sd); 2869 2870 if (state->mode == ADV7842_MODE_SDP) 2871 return adv7842_sdp_log_status(sd); 2872 return adv7842_cp_log_status(sd); 2873} 2874 2875static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2876{ 2877 struct adv7842_state *state = to_state(sd); 2878 2879 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2880 2881 if (state->mode != ADV7842_MODE_SDP) 2882 return -ENODATA; 2883 2884 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2885 *std = 0; 2886 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2887 return 0; 2888 } 2889 2890 switch (sdp_read(sd, 0x52) & 0x0f) { 2891 case 0: 2892 /* NTSC-M/J */ 2893 *std &= V4L2_STD_NTSC; 2894 break; 2895 case 2: 2896 /* NTSC-443 */ 2897 *std &= V4L2_STD_NTSC_443; 2898 break; 2899 case 3: 2900 /* 60HzSECAM */ 2901 *std &= V4L2_STD_SECAM; 2902 break; 2903 case 4: 2904 /* PAL-M */ 2905 *std &= V4L2_STD_PAL_M; 2906 break; 2907 case 6: 2908 /* PAL-60 */ 2909 *std &= V4L2_STD_PAL_60; 2910 break; 2911 case 0xc: 2912 /* PAL-CombN */ 2913 *std &= V4L2_STD_PAL_Nc; 2914 break; 2915 case 0xe: 2916 /* PAL-BGHID */ 2917 *std &= V4L2_STD_PAL; 2918 break; 2919 case 0xf: 2920 /* SECAM */ 2921 *std &= V4L2_STD_SECAM; 2922 break; 2923 default: 2924 *std &= V4L2_STD_ALL; 2925 break; 2926 } 2927 return 0; 2928} 2929 2930static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2931{ 2932 if (s && s->adjust) { 2933 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2934 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2935 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2936 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2937 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2938 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2939 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2940 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2941 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2942 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2943 sdp_io_write(sd, 0xaa, s->vs_end_o); 2944 sdp_io_write(sd, 0xab, s->vs_end_e); 2945 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2946 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2947 sdp_io_write(sd, 0xae, s->de_v_end_o); 2948 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2949 } else { 2950 /* set to default */ 2951 sdp_io_write(sd, 0x94, 0x00); 2952 sdp_io_write(sd, 0x95, 0x00); 2953 sdp_io_write(sd, 0x96, 0x00); 2954 sdp_io_write(sd, 0x97, 0x20); 2955 sdp_io_write(sd, 0x98, 0x00); 2956 sdp_io_write(sd, 0x99, 0x00); 2957 sdp_io_write(sd, 0x9a, 0x00); 2958 sdp_io_write(sd, 0x9b, 0x00); 2959 sdp_io_write(sd, 0xa8, 0x04); 2960 sdp_io_write(sd, 0xa9, 0x04); 2961 sdp_io_write(sd, 0xaa, 0x04); 2962 sdp_io_write(sd, 0xab, 0x04); 2963 sdp_io_write(sd, 0xac, 0x04); 2964 sdp_io_write(sd, 0xad, 0x04); 2965 sdp_io_write(sd, 0xae, 0x04); 2966 sdp_io_write(sd, 0xaf, 0x04); 2967 } 2968} 2969 2970static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2971{ 2972 struct adv7842_state *state = to_state(sd); 2973 struct adv7842_platform_data *pdata = &state->pdata; 2974 2975 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2976 2977 if (state->mode != ADV7842_MODE_SDP) 2978 return -ENODATA; 2979 2980 if (norm & V4L2_STD_625_50) 2981 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2982 else if (norm & V4L2_STD_525_60) 2983 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2984 else 2985 adv7842_s_sdp_io(sd, NULL); 2986 2987 if (norm & V4L2_STD_ALL) { 2988 state->norm = norm; 2989 return 0; 2990 } 2991 return -EINVAL; 2992} 2993 2994static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2995{ 2996 struct adv7842_state *state = to_state(sd); 2997 2998 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2999 3000 if (state->mode != ADV7842_MODE_SDP) 3001 return -ENODATA; 3002 3003 *norm = state->norm; 3004 return 0; 3005} 3006 3007/* ----------------------------------------------------------------------- */ 3008 3009static int adv7842_core_init(struct v4l2_subdev *sd) 3010{ 3011 struct adv7842_state *state = to_state(sd); 3012 struct adv7842_platform_data *pdata = &state->pdata; 3013 hdmi_write(sd, 0x48, 3014 (pdata->disable_pwrdnb ? 0x80 : 0) | 3015 (pdata->disable_cable_det_rst ? 0x40 : 0)); 3016 3017 disable_input(sd); 3018 3019 /* 3020 * Disable I2C access to internal EDID ram from HDMI DDC ports 3021 * Disable auto edid enable when leaving powerdown mode 3022 */ 3023 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 3024 3025 /* power */ 3026 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 3027 io_write(sd, 0x15, 0x80); /* Power up pads */ 3028 3029 /* video format */ 3030 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); 3031 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 3032 pdata->insert_av_codes << 2 | 3033 pdata->replicate_av_codes << 1); 3034 adv7842_setup_format(state); 3035 3036 /* HDMI audio */ 3037 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 3038 3039 /* Drive strength */ 3040 io_write_and_or(sd, 0x14, 0xc0, 3041 pdata->dr_str_data << 4 | 3042 pdata->dr_str_clk << 2 | 3043 pdata->dr_str_sync); 3044 3045 /* HDMI free run */ 3046 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 3047 (pdata->hdmi_free_run_mode << 1)); 3048 3049 /* SPD free run */ 3050 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 3051 (pdata->sdp_free_run_cbar_en << 1) | 3052 (pdata->sdp_free_run_man_col_en << 2) | 3053 (pdata->sdp_free_run_auto << 3)); 3054 3055 /* TODO from platform data */ 3056 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 3057 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 3058 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 3059 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 3060 3061 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 3062 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 3063 3064 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 3065 3066 /* todo, improve settings for sdram */ 3067 if (pdata->sd_ram_size >= 128) { 3068 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 3069 if (pdata->sd_ram_ddr) { 3070 /* SDP setup for the AD eval board */ 3071 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 3072 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 3073 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3074 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3075 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3076 } else { 3077 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 3078 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 3079 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 3080 depends on memory */ 3081 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 3082 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3083 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3084 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3085 } 3086 } else { 3087 /* 3088 * Manual UG-214, rev 0 is bit confusing on this bit 3089 * but a '1' disables any signal if the Ram is active. 3090 */ 3091 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 3092 } 3093 3094 select_input(sd, pdata->vid_std_select); 3095 3096 enable_input(sd); 3097 3098 if (pdata->hpa_auto) { 3099 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 3100 hdmi_write(sd, 0x69, 0x5c); 3101 } else { 3102 /* HPA manual */ 3103 hdmi_write(sd, 0x69, 0xa3); 3104 /* HPA disable on port A and B */ 3105 io_write_and_or(sd, 0x20, 0xcf, 0x00); 3106 } 3107 3108 /* LLC */ 3109 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 3110 io_write(sd, 0x33, 0x40); 3111 3112 /* interrupts */ 3113 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 3114 3115 adv7842_irq_enable(sd, true); 3116 3117 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 3118} 3119 3120/* ----------------------------------------------------------------------- */ 3121 3122static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 3123{ 3124 /* 3125 * From ADV784x external Memory test.pdf 3126 * 3127 * Reset must just been performed before running test. 3128 * Recommended to reset after test. 3129 */ 3130 int i; 3131 int pass = 0; 3132 int fail = 0; 3133 int complete = 0; 3134 3135 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 3136 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 3137 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */ 3138 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */ 3139 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */ 3140 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */ 3141 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */ 3142 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 3143 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 3144 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 3145 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 3146 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 3147 3148 usleep_range(5000, 6000); 3149 3150 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 3151 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 3152 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 3153 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 3154 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 3155 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 3156 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 3157 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 3158 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 3159 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 3160 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 3161 3162 usleep_range(5000, 6000); 3163 3164 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 3165 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 3166 3167 msleep(20); 3168 3169 for (i = 0; i < 10; i++) { 3170 u8 result = sdp_io_read(sd, 0xdb); 3171 if (result & 0x10) { 3172 complete++; 3173 if (result & 0x20) 3174 fail++; 3175 else 3176 pass++; 3177 } 3178 msleep(20); 3179 } 3180 3181 v4l2_dbg(1, debug, sd, 3182 "Ram Test: completed %d of %d: pass %d, fail %d\n", 3183 complete, i, pass, fail); 3184 3185 if (!complete || fail) 3186 return -EIO; 3187 return 0; 3188} 3189 3190static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 3191 struct adv7842_platform_data *pdata) 3192{ 3193 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 3194 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 3195 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 3196 io_write(sd, 0xf4, pdata->i2c_cec << 1); 3197 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 3198 3199 io_write(sd, 0xf8, pdata->i2c_afe << 1); 3200 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 3201 io_write(sd, 0xfa, pdata->i2c_edid << 1); 3202 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 3203 3204 io_write(sd, 0xfd, pdata->i2c_cp << 1); 3205 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 3206} 3207 3208static int adv7842_command_ram_test(struct v4l2_subdev *sd) 3209{ 3210 struct i2c_client *client = v4l2_get_subdevdata(sd); 3211 struct adv7842_state *state = to_state(sd); 3212 struct adv7842_platform_data *pdata = client->dev.platform_data; 3213 struct v4l2_dv_timings timings; 3214 int ret = 0; 3215 3216 if (!pdata) 3217 return -ENODEV; 3218 3219 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 3220 v4l2_info(sd, "no sdram or no ddr sdram\n"); 3221 return -EINVAL; 3222 } 3223 3224 main_reset(sd); 3225 3226 adv7842_rewrite_i2c_addresses(sd, pdata); 3227 3228 /* run ram test */ 3229 ret = adv7842_ddr_ram_test(sd); 3230 3231 main_reset(sd); 3232 3233 adv7842_rewrite_i2c_addresses(sd, pdata); 3234 3235 /* and re-init chip and state */ 3236 adv7842_core_init(sd); 3237 3238 disable_input(sd); 3239 3240 select_input(sd, state->vid_std_select); 3241 3242 enable_input(sd); 3243 3244 edid_write_vga_segment(sd); 3245 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 3246 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 3247 3248 timings = state->timings; 3249 3250 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 3251 3252 adv7842_s_dv_timings(sd, 0, &timings); 3253 3254 return ret; 3255} 3256 3257static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 3258{ 3259 switch (cmd) { 3260 case ADV7842_CMD_RAM_TEST: 3261 return adv7842_command_ram_test(sd); 3262 } 3263 return -ENOTTY; 3264} 3265 3266static int adv7842_subscribe_event(struct v4l2_subdev *sd, 3267 struct v4l2_fh *fh, 3268 struct v4l2_event_subscription *sub) 3269{ 3270 switch (sub->type) { 3271 case V4L2_EVENT_SOURCE_CHANGE: 3272 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 3273 case V4L2_EVENT_CTRL: 3274 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 3275 default: 3276 return -EINVAL; 3277 } 3278} 3279 3280static ssize_t 3281adv7842_debugfs_if_read(u32 type, void *priv, struct file *filp, 3282 char __user *ubuf, size_t count, loff_t *ppos) 3283{ 3284 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 3285 struct v4l2_subdev *sd = priv; 3286 int index; 3287 int len; 3288 3289 if (!is_hdmi(sd)) 3290 return 0; 3291 3292 switch (type) { 3293 case V4L2_DEBUGFS_IF_AVI: 3294 index = 0; 3295 break; 3296 case V4L2_DEBUGFS_IF_AUDIO: 3297 index = 1; 3298 break; 3299 case V4L2_DEBUGFS_IF_SPD: 3300 index = 2; 3301 break; 3302 case V4L2_DEBUGFS_IF_HDMI: 3303 index = 3; 3304 break; 3305 default: 3306 return 0; 3307 } 3308 3309 len = adv7842_read_infoframe_buf(sd, index, buf); 3310 if (len > 0) 3311 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 3312 return len < 0 ? 0 : len; 3313} 3314 3315static int adv7842_registered(struct v4l2_subdev *sd) 3316{ 3317 struct adv7842_state *state = to_state(sd); 3318 struct i2c_client *client = v4l2_get_subdevdata(sd); 3319 int err; 3320 3321 err = cec_register_adapter(state->cec_adap, &client->dev); 3322 if (err) { 3323 cec_delete_adapter(state->cec_adap); 3324 } else { 3325 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 3326 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 3327 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO | 3328 V4L2_DEBUGFS_IF_SPD | V4L2_DEBUGFS_IF_HDMI, sd, 3329 adv7842_debugfs_if_read); 3330 } 3331 return err; 3332} 3333 3334static void adv7842_unregistered(struct v4l2_subdev *sd) 3335{ 3336 struct adv7842_state *state = to_state(sd); 3337 3338 cec_unregister_adapter(state->cec_adap); 3339 v4l2_debugfs_if_free(state->infoframes); 3340 state->infoframes = NULL; 3341 debugfs_remove_recursive(state->debugfs_dir); 3342 state->debugfs_dir = NULL; 3343} 3344 3345/* ----------------------------------------------------------------------- */ 3346 3347static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 3348 .s_ctrl = adv7842_s_ctrl, 3349 .g_volatile_ctrl = adv7842_g_volatile_ctrl, 3350}; 3351 3352static const struct v4l2_subdev_core_ops adv7842_core_ops = { 3353 .log_status = adv7842_log_status, 3354 .ioctl = adv7842_ioctl, 3355 .interrupt_service_routine = adv7842_isr, 3356 .subscribe_event = adv7842_subscribe_event, 3357 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3358#ifdef CONFIG_VIDEO_ADV_DEBUG 3359 .g_register = adv7842_g_register, 3360 .s_register = adv7842_s_register, 3361#endif 3362}; 3363 3364static const struct v4l2_subdev_video_ops adv7842_video_ops = { 3365 .g_std = adv7842_g_std, 3366 .s_std = adv7842_s_std, 3367 .s_routing = adv7842_s_routing, 3368 .querystd = adv7842_querystd, 3369 .g_input_status = adv7842_g_input_status, 3370}; 3371 3372static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 3373 .enum_mbus_code = adv7842_enum_mbus_code, 3374 .get_fmt = adv7842_get_format, 3375 .set_fmt = adv7842_set_format, 3376 .get_edid = adv7842_get_edid, 3377 .set_edid = adv7842_set_edid, 3378 .s_dv_timings = adv7842_s_dv_timings, 3379 .g_dv_timings = adv7842_g_dv_timings, 3380 .query_dv_timings = adv7842_query_dv_timings, 3381 .enum_dv_timings = adv7842_enum_dv_timings, 3382 .dv_timings_cap = adv7842_dv_timings_cap, 3383}; 3384 3385static const struct v4l2_subdev_ops adv7842_ops = { 3386 .core = &adv7842_core_ops, 3387 .video = &adv7842_video_ops, 3388 .pad = &adv7842_pad_ops, 3389}; 3390 3391static const struct v4l2_subdev_internal_ops adv7842_int_ops = { 3392 .registered = adv7842_registered, 3393 .unregistered = adv7842_unregistered, 3394}; 3395 3396/* -------------------------- custom ctrls ---------------------------------- */ 3397 3398static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 3399 .ops = &adv7842_ctrl_ops, 3400 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 3401 .name = "Analog Sampling Phase", 3402 .type = V4L2_CTRL_TYPE_INTEGER, 3403 .min = 0, 3404 .max = 0x1f, 3405 .step = 1, 3406 .def = 0, 3407}; 3408 3409static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 3410 .ops = &adv7842_ctrl_ops, 3411 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 3412 .name = "Free Running Color, Manual", 3413 .type = V4L2_CTRL_TYPE_BOOLEAN, 3414 .max = 1, 3415 .step = 1, 3416 .def = 1, 3417}; 3418 3419static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 3420 .ops = &adv7842_ctrl_ops, 3421 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 3422 .name = "Free Running Color", 3423 .type = V4L2_CTRL_TYPE_INTEGER, 3424 .max = 0xffffff, 3425 .step = 0x1, 3426}; 3427 3428 3429static void adv7842_unregister_clients(struct v4l2_subdev *sd) 3430{ 3431 struct adv7842_state *state = to_state(sd); 3432 i2c_unregister_device(state->i2c_avlink); 3433 i2c_unregister_device(state->i2c_cec); 3434 i2c_unregister_device(state->i2c_infoframe); 3435 i2c_unregister_device(state->i2c_sdp_io); 3436 i2c_unregister_device(state->i2c_sdp); 3437 i2c_unregister_device(state->i2c_afe); 3438 i2c_unregister_device(state->i2c_repeater); 3439 i2c_unregister_device(state->i2c_edid); 3440 i2c_unregister_device(state->i2c_hdmi); 3441 i2c_unregister_device(state->i2c_cp); 3442 i2c_unregister_device(state->i2c_vdp); 3443 3444 state->i2c_avlink = NULL; 3445 state->i2c_cec = NULL; 3446 state->i2c_infoframe = NULL; 3447 state->i2c_sdp_io = NULL; 3448 state->i2c_sdp = NULL; 3449 state->i2c_afe = NULL; 3450 state->i2c_repeater = NULL; 3451 state->i2c_edid = NULL; 3452 state->i2c_hdmi = NULL; 3453 state->i2c_cp = NULL; 3454 state->i2c_vdp = NULL; 3455} 3456 3457static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 3458 u8 addr, u8 io_reg) 3459{ 3460 struct i2c_client *client = v4l2_get_subdevdata(sd); 3461 struct i2c_client *cp; 3462 3463 io_write(sd, io_reg, addr << 1); 3464 3465 if (addr == 0) { 3466 v4l2_err(sd, "no %s i2c addr configured\n", desc); 3467 return NULL; 3468 } 3469 3470 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1); 3471 if (IS_ERR(cp)) { 3472 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %pe\n", 3473 desc, addr, cp); 3474 cp = NULL; 3475 } 3476 3477 return cp; 3478} 3479 3480static int adv7842_register_clients(struct v4l2_subdev *sd) 3481{ 3482 struct adv7842_state *state = to_state(sd); 3483 struct adv7842_platform_data *pdata = &state->pdata; 3484 3485 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 3486 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 3487 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 3488 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 3489 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 3490 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 3491 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 3492 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 3493 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 3494 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 3495 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 3496 3497 if (!state->i2c_avlink || 3498 !state->i2c_cec || 3499 !state->i2c_infoframe || 3500 !state->i2c_sdp_io || 3501 !state->i2c_sdp || 3502 !state->i2c_afe || 3503 !state->i2c_repeater || 3504 !state->i2c_edid || 3505 !state->i2c_hdmi || 3506 !state->i2c_cp || 3507 !state->i2c_vdp) 3508 return -1; 3509 3510 return 0; 3511} 3512 3513static int adv7842_probe(struct i2c_client *client) 3514{ 3515 struct adv7842_state *state; 3516 static const struct v4l2_dv_timings cea640x480 = 3517 V4L2_DV_BT_CEA_640X480P59_94; 3518 struct adv7842_platform_data *pdata = client->dev.platform_data; 3519 struct v4l2_ctrl_handler *hdl; 3520 struct v4l2_ctrl *ctrl; 3521 struct v4l2_subdev *sd; 3522 unsigned int i; 3523 u16 rev; 3524 int err; 3525 3526 /* Check if the adapter supports the needed features */ 3527 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3528 return -EIO; 3529 3530 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 3531 client->addr << 1); 3532 3533 if (!pdata) { 3534 v4l_err(client, "No platform data!\n"); 3535 return -ENODEV; 3536 } 3537 3538 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3539 if (!state) 3540 return -ENOMEM; 3541 3542 /* platform data */ 3543 state->pdata = *pdata; 3544 state->timings = cea640x480; 3545 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3546 3547 sd = &state->sd; 3548 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 3549 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3550 sd->internal_ops = &adv7842_int_ops; 3551 state->mode = pdata->mode; 3552 3553 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 3554 state->restart_stdi_once = true; 3555 3556 /* i2c access to adv7842? */ 3557 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3558 adv_smbus_read_byte_data_check(client, 0xeb, false); 3559 if (rev != 0x2012) { 3560 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3561 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3562 adv_smbus_read_byte_data_check(client, 0xeb, false); 3563 } 3564 if (rev != 0x2012) { 3565 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3566 client->addr << 1, rev); 3567 return -ENODEV; 3568 } 3569 3570 if (pdata->chip_reset) 3571 main_reset(sd); 3572 3573 /* control handlers */ 3574 hdl = &state->hdl; 3575 v4l2_ctrl_handler_init(hdl, 6); 3576 3577 /* add in ascending ID order */ 3578 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3579 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3580 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3581 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3582 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3583 V4L2_CID_SATURATION, 0, 255, 1, 128); 3584 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3585 V4L2_CID_HUE, 0, 128, 1, 0); 3586 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3587 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3588 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3589 if (ctrl) 3590 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3591 3592 /* custom controls */ 3593 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3594 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3595 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3596 &adv7842_ctrl_analog_sampling_phase, NULL); 3597 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3598 &adv7842_ctrl_free_run_color_manual, NULL); 3599 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3600 &adv7842_ctrl_free_run_color, NULL); 3601 state->rgb_quantization_range_ctrl = 3602 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3603 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3604 0, V4L2_DV_RGB_RANGE_AUTO); 3605 sd->ctrl_handler = hdl; 3606 if (hdl->error) { 3607 err = hdl->error; 3608 goto err_hdl; 3609 } 3610 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3611 err = -ENODEV; 3612 goto err_hdl; 3613 } 3614 3615 if (adv7842_register_clients(sd) < 0) { 3616 err = -ENOMEM; 3617 v4l2_err(sd, "failed to create all i2c clients\n"); 3618 goto err_i2c; 3619 } 3620 3621 3622 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3623 adv7842_delayed_work_enable_hotplug); 3624 3625 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3626 for (i = 0; i < ADV7842_PAD_SOURCE; ++i) 3627 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3628 state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 3629 err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1, 3630 state->pads); 3631 if (err) 3632 goto err_i2c; 3633 3634 err = adv7842_core_init(sd); 3635 if (err) 3636 goto err_entity; 3637 3638#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 3639 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops, 3640 state, dev_name(&client->dev), 3641 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS); 3642 err = PTR_ERR_OR_ZERO(state->cec_adap); 3643 if (err) 3644 goto err_entity; 3645#endif 3646 3647 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3648 client->addr << 1, client->adapter->name); 3649 return 0; 3650 3651err_entity: 3652 media_entity_cleanup(&sd->entity); 3653err_i2c: 3654 adv7842_unregister_clients(sd); 3655err_hdl: 3656 v4l2_ctrl_handler_free(hdl); 3657 return err; 3658} 3659 3660/* ----------------------------------------------------------------------- */ 3661 3662static void adv7842_remove(struct i2c_client *client) 3663{ 3664 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3665 struct adv7842_state *state = to_state(sd); 3666 3667 adv7842_irq_enable(sd, false); 3668 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 3669 v4l2_device_unregister_subdev(sd); 3670 media_entity_cleanup(&sd->entity); 3671 adv7842_unregister_clients(sd); 3672 v4l2_ctrl_handler_free(sd->ctrl_handler); 3673} 3674 3675/* ----------------------------------------------------------------------- */ 3676 3677static const struct i2c_device_id adv7842_id[] = { 3678 { "adv7842" }, 3679 { } 3680}; 3681MODULE_DEVICE_TABLE(i2c, adv7842_id); 3682 3683/* ----------------------------------------------------------------------- */ 3684 3685static struct i2c_driver adv7842_driver = { 3686 .driver = { 3687 .name = "adv7842", 3688 }, 3689 .probe = adv7842_probe, 3690 .remove = adv7842_remove, 3691 .id_table = adv7842_id, 3692}; 3693 3694module_i2c_driver(adv7842_driver);
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