adv748x.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * Driver for Analog Devices ADV748X video decoder and HDMI receiver
  4 *
  5 * Copyright (C) 2017 Renesas Electronics Corp.
  6 *
  7 * Authors:
  8 *	Koji Matsuoka <koji.matsuoka.xm@renesas.com>
  9 *	Niklas Söderlund <niklas.soderlund@ragnatech.se>
 10 *	Kieran Bingham <kieran.bingham@ideasonboard.com>
 11 *
 12 * The ADV748x range of receivers have the following configurations:
 13 *
 14 *                  Analog   HDMI  MHL  4-Lane  1-Lane
 15 *                    In      In         CSI     CSI
 16 *       ADV7480               X    X     X
 17 *       ADV7481      X        X    X     X       X
 18 *       ADV7482      X        X          X       X
 19 */
 20
 21#include <linux/i2c.h>
 22
 23#ifndef _ADV748X_H_
 24#define _ADV748X_H_
 25
 26enum adv748x_page {
 27	ADV748X_PAGE_IO,
 28	ADV748X_PAGE_DPLL,
 29	ADV748X_PAGE_CP,
 30	ADV748X_PAGE_HDMI,
 31	ADV748X_PAGE_EDID,
 32	ADV748X_PAGE_REPEATER,
 33	ADV748X_PAGE_INFOFRAME,
 34	ADV748X_PAGE_CBUS,
 35	ADV748X_PAGE_CEC,
 36	ADV748X_PAGE_SDP,
 37	ADV748X_PAGE_TXB,
 38	ADV748X_PAGE_TXA,
 39	ADV748X_PAGE_MAX,
 40
 41	/* Fake pages for register sequences */
 42	ADV748X_PAGE_EOR,		/* End Mark */
 43};
 44
 45/*
 46 * Device tree port number definitions
 47 *
 48 * The ADV748X ports define the mapping between subdevices
 49 * and the device tree specification
 50 */
 51enum adv748x_ports {
 52	ADV748X_PORT_AIN0 = 0,
 53	ADV748X_PORT_AIN1 = 1,
 54	ADV748X_PORT_AIN2 = 2,
 55	ADV748X_PORT_AIN3 = 3,
 56	ADV748X_PORT_AIN4 = 4,
 57	ADV748X_PORT_AIN5 = 5,
 58	ADV748X_PORT_AIN6 = 6,
 59	ADV748X_PORT_AIN7 = 7,
 60	ADV748X_PORT_HDMI = 8,
 61	ADV748X_PORT_TTL = 9,
 62	ADV748X_PORT_TXA = 10,
 63	ADV748X_PORT_TXB = 11,
 64	ADV748X_PORT_MAX = 12,
 65};
 66
 67enum adv748x_csi2_pads {
 68	ADV748X_CSI2_SINK,
 69	ADV748X_CSI2_SOURCE,
 70	ADV748X_CSI2_NR_PADS,
 71};
 72
 73/* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
 74#define ADV748X_CSI2_MAX_SUBDEVS 2
 75
 76struct adv748x_csi2 {
 77	struct adv748x_state *state;
 78	unsigned int page;
 79	unsigned int port;
 80	unsigned int num_lanes;
 81	unsigned int active_lanes;
 82
 83	struct media_pad pads[ADV748X_CSI2_NR_PADS];
 84	struct v4l2_ctrl_handler ctrl_hdl;
 85	struct v4l2_ctrl *pixel_rate;
 86	struct v4l2_subdev *src;
 87	struct v4l2_subdev sd;
 88};
 89
 90#define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
 91#define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
 92
 93#define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
 94#define is_txa(_tx) ((_tx) == &(_tx)->state->txa)
 95#define is_txb(_tx) ((_tx) == &(_tx)->state->txb)
 96#define is_tx(_tx) (is_txa(_tx) || is_txb(_tx))
 97
 98#define is_afe_enabled(_state)					\
 99	((_state)->endpoints[ADV748X_PORT_AIN0] != NULL ||	\
100	 (_state)->endpoints[ADV748X_PORT_AIN1] != NULL ||	\
101	 (_state)->endpoints[ADV748X_PORT_AIN2] != NULL ||	\
102	 (_state)->endpoints[ADV748X_PORT_AIN3] != NULL ||	\
103	 (_state)->endpoints[ADV748X_PORT_AIN4] != NULL ||	\
104	 (_state)->endpoints[ADV748X_PORT_AIN5] != NULL ||	\
105	 (_state)->endpoints[ADV748X_PORT_AIN6] != NULL ||	\
106	 (_state)->endpoints[ADV748X_PORT_AIN7] != NULL)
107#define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL)
108
109enum adv748x_hdmi_pads {
110	ADV748X_HDMI_SINK,
111	ADV748X_HDMI_SOURCE,
112	ADV748X_HDMI_NR_PADS,
113};
114
115struct adv748x_hdmi {
116	struct media_pad pads[ADV748X_HDMI_NR_PADS];
117	struct v4l2_ctrl_handler ctrl_hdl;
118	struct v4l2_subdev sd;
119	struct v4l2_mbus_framefmt format;
120
121	struct v4l2_dv_timings timings;
122	struct v4l2_fract aspect_ratio;
123
124	struct adv748x_csi2 *tx;
125
126	struct {
127		u8 edid[512];
128		u32 present;
129		unsigned int blocks;
130	} edid;
131};
132
133#define adv748x_ctrl_to_hdmi(ctrl) \
134	container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
135#define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
136
137enum adv748x_afe_pads {
138	ADV748X_AFE_SINK_AIN0,
139	ADV748X_AFE_SINK_AIN1,
140	ADV748X_AFE_SINK_AIN2,
141	ADV748X_AFE_SINK_AIN3,
142	ADV748X_AFE_SINK_AIN4,
143	ADV748X_AFE_SINK_AIN5,
144	ADV748X_AFE_SINK_AIN6,
145	ADV748X_AFE_SINK_AIN7,
146	ADV748X_AFE_SOURCE,
147	ADV748X_AFE_NR_PADS,
148};
149
150struct adv748x_afe {
151	struct media_pad pads[ADV748X_AFE_NR_PADS];
152	struct v4l2_ctrl_handler ctrl_hdl;
153	struct v4l2_subdev sd;
154	struct v4l2_mbus_framefmt format;
155
156	struct adv748x_csi2 *tx;
157
158	bool streaming;
159	v4l2_std_id curr_norm;
160	unsigned int input;
161};
162
163#define adv748x_ctrl_to_afe(ctrl) \
164	container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
165#define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
166
167/**
168 * struct adv748x_state - State of ADV748X
169 * @dev:		(OF) device
170 * @client:		I2C client
171 * @mutex:		protect global state
172 *
173 * @endpoints:		parsed device node endpoints for each port
174 *
175 * @i2c_clients:	I2C clients for the page accesses
176 * @regmap:		regmap configuration pages.
177 *
178 * @hdmi:		state of HDMI receiver context
179 * @afe:		state of AFE receiver context
180 * @txa:		state of TXA transmitter context
181 * @txb:		state of TXB transmitter context
182 */
183struct adv748x_state {
184	struct device *dev;
185	struct i2c_client *client;
186	struct mutex mutex;
187
188	struct device_node *endpoints[ADV748X_PORT_MAX];
189
190	struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
191	struct regmap *regmap[ADV748X_PAGE_MAX];
192
193	struct adv748x_hdmi hdmi;
194	struct adv748x_afe afe;
195	struct adv748x_csi2 txa;
196	struct adv748x_csi2 txb;
197};
198
199#define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
200#define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
201
202#define adv_err(a, fmt, arg...)	dev_err(a->dev, fmt, ##arg)
203#define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
204#define adv_dbg(a, fmt, arg...)	dev_dbg(a->dev, fmt, ##arg)
205
206/* Register Mappings */
207
208/* IO Map */
209#define ADV748X_IO_PD			0x00	/* power down controls */
210#define ADV748X_IO_PD_RX_EN		BIT(6)
211
212#define ADV748X_IO_REG_01		0x01	/* pwrdn{2}b, prog_xtal_freq */
213#define ADV748X_IO_REG_01_PWRDN_MASK	(BIT(7) | BIT(6))
214#define ADV748X_IO_REG_01_PWRDN2B	BIT(7)	/* CEC Wakeup Support */
215#define ADV748X_IO_REG_01_PWRDNB	BIT(6)	/* CEC Wakeup Support */
216
217#define ADV748X_IO_REG_04		0x04
218#define ADV748X_IO_REG_04_FORCE_FR	BIT(0)	/* Force CP free-run */
219
220#define ADV748X_IO_DATAPATH		0x03	/* datapath cntrl */
221#define ADV748X_IO_DATAPATH_VFREQ_M	0x70
222#define ADV748X_IO_DATAPATH_VFREQ_SHIFT	4
223
224#define ADV748X_IO_VID_STD		0x05
225
226#define ADV748X_IO_10			0x10	/* io_reg_10 */
227#define ADV748X_IO_10_CSI4_EN		BIT(7)
228#define ADV748X_IO_10_CSI1_EN		BIT(6)
229#define ADV748X_IO_10_PIX_OUT_EN	BIT(5)
230#define ADV748X_IO_10_CSI4_IN_SEL_AFE	BIT(3)
231
232#define ADV748X_IO_CHIP_REV_ID_1	0xdf
233#define ADV748X_IO_CHIP_REV_ID_2	0xe0
234
235#define ADV748X_IO_REG_F2		0xf2
236#define ADV748X_IO_REG_F2_READ_AUTO_INC	BIT(0)
237
238/* For PAGE slave address offsets */
239#define ADV748X_IO_SLAVE_ADDR_BASE	0xf2
240
241/*
242 * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and
243 * 0xff as examples for performing a software reset.
244 */
245#define ADV748X_IO_REG_FF		0xff
246#define ADV748X_IO_REG_FF_MAIN_RESET	0xff
247
248/* HDMI RX Map */
249#define ADV748X_HDMI_LW1		0x07	/* line width_1 */
250#define ADV748X_HDMI_LW1_VERT_FILTER	BIT(7)
251#define ADV748X_HDMI_LW1_DE_REGEN	BIT(5)
252#define ADV748X_HDMI_LW1_WIDTH_MASK	0x1fff
253
254#define ADV748X_HDMI_F0H1		0x09	/* field0 height_1 */
255#define ADV748X_HDMI_F0H1_HEIGHT_MASK	0x1fff
256
257#define ADV748X_HDMI_F1H1		0x0b	/* field1 height_1 */
258#define ADV748X_HDMI_F1H1_INTERLACED	BIT(5)
259
260#define ADV748X_HDMI_HFRONT_PORCH	0x20	/* hsync_front_porch_1 */
261#define ADV748X_HDMI_HFRONT_PORCH_MASK	0x1fff
262
263#define ADV748X_HDMI_HSYNC_WIDTH	0x22	/* hsync_pulse_width_1 */
264#define ADV748X_HDMI_HSYNC_WIDTH_MASK	0x1fff
265
266#define ADV748X_HDMI_HBACK_PORCH	0x24	/* hsync_back_porch_1 */
267#define ADV748X_HDMI_HBACK_PORCH_MASK	0x1fff
268
269#define ADV748X_HDMI_VFRONT_PORCH	0x2a	/* field0_vs_front_porch_1 */
270#define ADV748X_HDMI_VFRONT_PORCH_MASK	0x3fff
271
272#define ADV748X_HDMI_VSYNC_WIDTH	0x2e	/* field0_vs_pulse_width_1 */
273#define ADV748X_HDMI_VSYNC_WIDTH_MASK	0x3fff
274
275#define ADV748X_HDMI_VBACK_PORCH	0x32	/* field0_vs_back_porch_1 */
276#define ADV748X_HDMI_VBACK_PORCH_MASK	0x3fff
277
278#define ADV748X_HDMI_TMDS_1		0x51	/* hdmi_reg_51 */
279#define ADV748X_HDMI_TMDS_2		0x52	/* hdmi_reg_52 */
280
281/* HDMI RX Repeater Map */
282#define ADV748X_REPEATER_EDID_SZ	0x70	/* primary_edid_size */
283#define ADV748X_REPEATER_EDID_SZ_SHIFT	4
284
285#define ADV748X_REPEATER_EDID_CTL	0x74	/* hdcp edid controls */
286#define ADV748X_REPEATER_EDID_CTL_EN	BIT(0)	/* man_edid_a_enable */
287
288/* SDP Main Map */
289#define ADV748X_SDP_INSEL		0x00	/* user_map_rw_reg_00 */
290
291#define ADV748X_SDP_VID_SEL		0x02	/* user_map_rw_reg_02 */
292#define ADV748X_SDP_VID_SEL_MASK	0xf0
293#define ADV748X_SDP_VID_SEL_SHIFT	4
294
295/* Contrast - Unsigned*/
296#define ADV748X_SDP_CON			0x08	/* user_map_rw_reg_08 */
297#define ADV748X_SDP_CON_MIN		0
298#define ADV748X_SDP_CON_DEF		128
299#define ADV748X_SDP_CON_MAX		255
300
301/* Brightness - Signed */
302#define ADV748X_SDP_BRI			0x0a	/* user_map_rw_reg_0a */
303#define ADV748X_SDP_BRI_MIN		-128
304#define ADV748X_SDP_BRI_DEF		0
305#define ADV748X_SDP_BRI_MAX		127
306
307/* Hue - Signed, inverted*/
308#define ADV748X_SDP_HUE			0x0b	/* user_map_rw_reg_0b */
309#define ADV748X_SDP_HUE_MIN		-127
310#define ADV748X_SDP_HUE_DEF		0
311#define ADV748X_SDP_HUE_MAX		128
312
313/* Test Patterns / Default Values */
314#define ADV748X_SDP_DEF			0x0c	/* user_map_rw_reg_0c */
315#define ADV748X_SDP_DEF_VAL_EN		BIT(0)	/* Force free run mode */
316#define ADV748X_SDP_DEF_VAL_AUTO_EN	BIT(1)	/* Free run when no signal */
317
318#define ADV748X_SDP_MAP_SEL		0x0e	/* user_map_rw_reg_0e */
319#define ADV748X_SDP_MAP_SEL_RO_MAIN	1
320
321/* Free run pattern select */
322#define ADV748X_SDP_FRP			0x14
323#define ADV748X_SDP_FRP_MASK		GENMASK(2, 0)
324
325/* Saturation */
326#define ADV748X_SDP_SD_SAT_U		0xe3	/* user_map_rw_reg_e3 */
327#define ADV748X_SDP_SD_SAT_V		0xe4	/* user_map_rw_reg_e4 */
328#define ADV748X_SDP_SAT_MIN		0
329#define ADV748X_SDP_SAT_DEF		128
330#define ADV748X_SDP_SAT_MAX		255
331
332/* SDP RO Main Map */
333#define ADV748X_SDP_RO_10		0x10
334#define ADV748X_SDP_RO_10_IN_LOCK	BIT(0)
335
336/* CP Map */
337#define ADV748X_CP_PAT_GEN		0x37	/* int_pat_gen_1 */
338#define ADV748X_CP_PAT_GEN_EN		BIT(7)
339
340/* Contrast Control - Unsigned */
341#define ADV748X_CP_CON			0x3a	/* contrast_cntrl */
342#define ADV748X_CP_CON_MIN		0	/* Minimum contrast */
343#define ADV748X_CP_CON_DEF		128	/* Default */
344#define ADV748X_CP_CON_MAX		255	/* Maximum contrast */
345
346/* Saturation Control - Unsigned */
347#define ADV748X_CP_SAT			0x3b	/* saturation_cntrl */
348#define ADV748X_CP_SAT_MIN		0	/* Minimum saturation */
349#define ADV748X_CP_SAT_DEF		128	/* Default */
350#define ADV748X_CP_SAT_MAX		255	/* Maximum saturation */
351
352/* Brightness Control - Signed */
353#define ADV748X_CP_BRI			0x3c	/* brightness_cntrl */
354#define ADV748X_CP_BRI_MIN		-128	/* Luma is -512d */
355#define ADV748X_CP_BRI_DEF		0	/* Luma is 0 */
356#define ADV748X_CP_BRI_MAX		127	/* Luma is 508d */
357
358/* Hue Control */
359#define ADV748X_CP_HUE			0x3d	/* hue_cntrl */
360#define ADV748X_CP_HUE_MIN		0	/* -90 degree */
361#define ADV748X_CP_HUE_DEF		0	/* -90 degree */
362#define ADV748X_CP_HUE_MAX		255	/* +90 degree */
363
364#define ADV748X_CP_VID_ADJ		0x3e	/* vid_adj_0 */
365#define ADV748X_CP_VID_ADJ_ENABLE	BIT(7)	/* Enable colour controls */
366
367#define ADV748X_CP_DE_POS_HIGH		0x8b	/* de_pos_adj_6 */
368#define ADV748X_CP_DE_POS_HIGH_SET	BIT(6)
369#define ADV748X_CP_DE_POS_END_LOW	0x8c	/* de_pos_adj_7 */
370#define ADV748X_CP_DE_POS_START_LOW	0x8d	/* de_pos_adj_8 */
371
372#define ADV748X_CP_VID_ADJ_2			0x91
373#define ADV748X_CP_VID_ADJ_2_INTERLACED		BIT(6)
374#define ADV748X_CP_VID_ADJ_2_INTERLACED_3D	BIT(4)
375
376#define ADV748X_CP_CLMP_POS		0xc9	/* clmp_pos_cntrl_4 */
377#define ADV748X_CP_CLMP_POS_DIS_AUTO	BIT(0)	/* dis_auto_param_buff */
378
379/* CSI : TXA/TXB Maps */
380#define ADV748X_CSI_VC_REF		0x0d	/* csi_tx_top_reg_0d */
381#define ADV748X_CSI_VC_REF_SHIFT	6
382
383#define ADV748X_CSI_FS_AS_LS		0x1e	/* csi_tx_top_reg_1e */
384#define ADV748X_CSI_FS_AS_LS_UNKNOWN	BIT(6)	/* Undocumented bit */
385
386/* Register handling */
387
388int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
389int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
390int adv748x_write_block(struct adv748x_state *state, int client_page,
391			unsigned int init_reg, const void *val,
392			size_t val_len);
393
394#define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
395#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
396#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
397
398#define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
399#define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m))
400#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
401
402#define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
403#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
404
405#define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
406#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
407#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))
408
409#define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
410#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
411#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))
412
413#define tx_read(t, r) adv748x_read(t->state, t->page, r)
414#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
415
416static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
417{
418	pad = media_pad_remote_pad_first(pad);
419	if (!pad)
420		return NULL;
421
422	return media_entity_to_v4l2_subdev(pad->entity);
423}
424
425void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
426			 const struct v4l2_subdev_ops *ops, u32 function,
427			 const char *ident);
428
429int adv748x_tx_power(struct adv748x_csi2 *tx, bool on);
430
431int adv748x_afe_init(struct adv748x_afe *afe);
432void adv748x_afe_cleanup(struct adv748x_afe *afe);
433int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input);
434
435int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
436void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
437int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc);
438int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
439
440int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
441void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
442
443#endif /* _ADV748X_H_ */