adv7343_regs.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * ADV7343 encoder related structure and register definitions
  4 *
  5 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  6 */
  7
  8#ifndef ADV7343_REGS_H
  9#define ADV7343_REGS_H
 10
 11struct adv7343_std_info {
 12	u32 standard_val3;
 13	u32 fsc_val;
 14	v4l2_std_id stdid;
 15};
 16
 17/* Register offset macros */
 18#define ADV7343_POWER_MODE_REG		(0x00)
 19#define ADV7343_MODE_SELECT_REG		(0x01)
 20#define ADV7343_MODE_REG0		(0x02)
 21
 22#define ADV7343_DAC2_OUTPUT_LEVEL	(0x0b)
 23
 24#define ADV7343_SOFT_RESET		(0x17)
 25
 26#define ADV7343_HD_MODE_REG1		(0x30)
 27#define ADV7343_HD_MODE_REG2		(0x31)
 28#define ADV7343_HD_MODE_REG3		(0x32)
 29#define ADV7343_HD_MODE_REG4		(0x33)
 30#define ADV7343_HD_MODE_REG5		(0x34)
 31#define ADV7343_HD_MODE_REG6		(0x35)
 32
 33#define ADV7343_HD_MODE_REG7		(0x39)
 34
 35#define ADV7343_SD_MODE_REG1		(0x80)
 36#define ADV7343_SD_MODE_REG2		(0x82)
 37#define ADV7343_SD_MODE_REG3		(0x83)
 38#define ADV7343_SD_MODE_REG4		(0x84)
 39#define ADV7343_SD_MODE_REG5		(0x86)
 40#define ADV7343_SD_MODE_REG6		(0x87)
 41#define ADV7343_SD_MODE_REG7		(0x88)
 42#define ADV7343_SD_MODE_REG8		(0x89)
 43
 44#define ADV7343_FSC_REG0		(0x8C)
 45#define ADV7343_FSC_REG1		(0x8D)
 46#define ADV7343_FSC_REG2		(0x8E)
 47#define ADV7343_FSC_REG3		(0x8F)
 48
 49#define ADV7343_SD_CGMS_WSS0		(0x99)
 50
 51#define ADV7343_SD_HUE_REG		(0xA0)
 52#define ADV7343_SD_BRIGHTNESS_WSS	(0xA1)
 53
 54/* Default values for the registers */
 55#define ADV7343_POWER_MODE_REG_DEFAULT		(0x10)
 56#define ADV7343_HD_MODE_REG1_DEFAULT		(0x3C)	/* Changed Default
 57							   720p EAVSAV code*/
 58#define ADV7343_HD_MODE_REG2_DEFAULT		(0x01)	/* Changed Pixel data
 59							   valid */
 60#define ADV7343_HD_MODE_REG3_DEFAULT		(0x00)	/* Color delay 0 clks */
 61#define ADV7343_HD_MODE_REG4_DEFAULT		(0xE8)	/* Changed */
 62#define ADV7343_HD_MODE_REG5_DEFAULT		(0x08)
 63#define ADV7343_HD_MODE_REG6_DEFAULT		(0x00)
 64#define ADV7343_HD_MODE_REG7_DEFAULT		(0x00)
 65#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)
 66#define ADV7343_SOFT_RESET_DEFAULT		(0x02)
 67#define ADV7343_COMPOSITE_POWER_VALUE		(0x80)
 68#define ADV7343_COMPONENT_POWER_VALUE		(0x1C)
 69#define ADV7343_SVIDEO_POWER_VALUE		(0x60)
 70#define ADV7343_SD_HUE_REG_DEFAULT		(127)
 71#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT	(0x03)
 72
 73#define ADV7343_SD_CGMS_WSS0_DEFAULT		(0x10)
 74
 75#define ADV7343_SD_MODE_REG1_DEFAULT		(0x00)
 76#define ADV7343_SD_MODE_REG2_DEFAULT		(0xC9)
 77#define ADV7343_SD_MODE_REG3_DEFAULT		(0x10)
 78#define ADV7343_SD_MODE_REG4_DEFAULT		(0x01)
 79#define ADV7343_SD_MODE_REG5_DEFAULT		(0x02)
 80#define ADV7343_SD_MODE_REG6_DEFAULT		(0x0C)
 81#define ADV7343_SD_MODE_REG7_DEFAULT		(0x04)
 82#define ADV7343_SD_MODE_REG8_DEFAULT		(0x00)
 83
 84/* Bit masks for Mode Select Register */
 85#define INPUT_MODE_MASK			(0x70)
 86#define SD_INPUT_MODE			(0x00)
 87#define HD_720P_INPUT_MODE		(0x10)
 88#define HD_1080I_INPUT_MODE		(0x10)
 89
 90/* Bit masks for Mode Register 0 */
 91#define TEST_PATTERN_BLACK_BAR_EN	(0x04)
 92#define YUV_OUTPUT_SELECT		(0x20)
 93#define RGB_OUTPUT_SELECT		(0xDF)
 94
 95/* Bit masks for DAC output levels */
 96#define DAC_OUTPUT_LEVEL_MASK		(0xFF)
 97
 98/* Bit masks for soft reset register */
 99#define SOFT_RESET			(0x02)
100
101/* Bit masks for HD Mode Register 1 */
102#define OUTPUT_STD_MASK		(0x03)
103#define OUTPUT_STD_SHIFT	(0)
104#define OUTPUT_STD_EIA0_2	(0x00)
105#define OUTPUT_STD_EIA0_1	(0x01)
106#define OUTPUT_STD_FULL		(0x02)
107#define EMBEDDED_SYNC		(0x04)
108#define EXTERNAL_SYNC		(0xFB)
109#define STD_MODE_SHIFT		(3)
110#define STD_MODE_MASK		(0x1F)
111#define STD_MODE_720P		(0x05)
112#define STD_MODE_720P_25	(0x08)
113#define STD_MODE_720P_30	(0x07)
114#define STD_MODE_720P_50	(0x06)
115#define STD_MODE_1080I		(0x0D)
116#define STD_MODE_1080I_25fps	(0x0E)
117#define STD_MODE_1080P_24	(0x12)
118#define STD_MODE_1080P_25	(0x10)
119#define STD_MODE_1080P_30	(0x0F)
120#define STD_MODE_525P		(0x00)
121#define STD_MODE_625P		(0x03)
122
123/* Bit masks for SD Mode Register 1 */
124#define SD_STD_MASK		(0x03)
125#define SD_STD_NTSC		(0x00)
126#define SD_STD_PAL_BDGHI	(0x01)
127#define SD_STD_PAL_M		(0x02)
128#define SD_STD_PAL_N		(0x03)
129#define SD_LUMA_FLTR_MASK	(0x7)
130#define SD_LUMA_FLTR_SHIFT	(0x2)
131#define SD_CHROMA_FLTR_MASK	(0x7)
132#define SD_CHROMA_FLTR_SHIFT	(0x5)
133
134/* Bit masks for SD Mode Register 2 */
135#define SD_PBPR_SSAF_EN		(0x01)
136#define SD_PBPR_SSAF_DI		(0xFE)
137#define SD_DAC_1_DI		(0xFD)
138#define SD_DAC_2_DI		(0xFB)
139#define SD_PEDESTAL_EN		(0x08)
140#define SD_PEDESTAL_DI		(0xF7)
141#define SD_SQUARE_PIXEL_EN	(0x10)
142#define SD_SQUARE_PIXEL_DI	(0xEF)
143#define SD_PIXEL_DATA_VALID	(0x40)
144#define SD_ACTIVE_EDGE_EN	(0x80)
145#define SD_ACTIVE_EDGE_DI	(0x7F)
146
147/* Bit masks for HD Mode Register 6 */
148#define HD_RGB_INPUT_EN		(0x02)
149#define HD_RGB_INPUT_DI		(0xFD)
150#define HD_PBPR_SYNC_EN		(0x04)
151#define HD_PBPR_SYNC_DI		(0xFB)
152#define HD_DAC_SWAP_EN		(0x08)
153#define HD_DAC_SWAP_DI		(0xF7)
154#define HD_GAMMA_CURVE_A	(0xEF)
155#define HD_GAMMA_CURVE_B	(0x10)
156#define HD_GAMMA_EN		(0x20)
157#define HD_GAMMA_DI		(0xDF)
158#define HD_ADPT_FLTR_MODEB	(0x40)
159#define HD_ADPT_FLTR_MODEA	(0xBF)
160#define HD_ADPT_FLTR_EN		(0x80)
161#define HD_ADPT_FLTR_DI		(0x7F)
162
163#define ADV7343_BRIGHTNESS_MAX	(127)
164#define ADV7343_BRIGHTNESS_MIN	(0)
165#define ADV7343_BRIGHTNESS_DEF	(3)
166#define ADV7343_HUE_MAX		(255)
167#define ADV7343_HUE_MIN		(0)
168#define ADV7343_HUE_DEF		(127)
169#define ADV7343_GAIN_MAX	(64)
170#define ADV7343_GAIN_MIN	(-64)
171#define ADV7343_GAIN_DEF	(0)
172
173#endif