adv7180.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * adv7180.c Analog Devices ADV7180 video decoder driver
   4 * Copyright (c) 2009 Intel Corporation
   5 * Copyright (C) 2013 Cogent Embedded, Inc.
   6 * Copyright (C) 2013 Renesas Solutions Corp.
   7 */
   8#include <linux/mod_devicetable.h>
   9#include <linux/module.h>
  10#include <linux/init.h>
  11#include <linux/errno.h>
  12#include <linux/kernel.h>
  13#include <linux/interrupt.h>
  14#include <linux/i2c.h>
  15#include <linux/slab.h>
  16#include <linux/of.h>
  17#include <linux/gpio/consumer.h>
  18#include <linux/videodev2.h>
  19#include <media/v4l2-ioctl.h>
  20#include <media/v4l2-event.h>
  21#include <media/v4l2-device.h>
  22#include <media/v4l2-ctrls.h>
  23#include <linux/mutex.h>
  24#include <linux/delay.h>
  25
  26#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM		0x0
  27#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED		0x1
  28#define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM		0x2
  29#define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM		0x3
  30#define ADV7180_STD_NTSC_J				0x4
  31#define ADV7180_STD_NTSC_M				0x5
  32#define ADV7180_STD_PAL60				0x6
  33#define ADV7180_STD_NTSC_443				0x7
  34#define ADV7180_STD_PAL_BG				0x8
  35#define ADV7180_STD_PAL_N				0x9
  36#define ADV7180_STD_PAL_M				0xa
  37#define ADV7180_STD_PAL_M_PED				0xb
  38#define ADV7180_STD_PAL_COMB_N				0xc
  39#define ADV7180_STD_PAL_COMB_N_PED			0xd
  40#define ADV7180_STD_PAL_SECAM				0xe
  41#define ADV7180_STD_PAL_SECAM_PED			0xf
  42
  43#define ADV7180_REG_INPUT_CONTROL			0x0000
  44#define ADV7180_INPUT_CONTROL_INSEL_MASK		0x0f
  45
  46#define ADV7182_REG_INPUT_VIDSEL			0x0002
  47#define ADV7182_REG_INPUT_RESERVED			BIT(2)
  48
  49#define ADV7180_REG_OUTPUT_CONTROL			0x0003
  50#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL		0x0004
  51#define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS		0xC5
  52
  53#define ADV7180_REG_AUTODETECT_ENABLE			0x0007
  54#define ADV7180_AUTODETECT_DEFAULT			0x7f
  55/* Contrast */
  56#define ADV7180_REG_CON		0x0008	/*Unsigned */
  57#define ADV7180_CON_MIN		0
  58#define ADV7180_CON_DEF		128
  59#define ADV7180_CON_MAX		255
  60/* Brightness*/
  61#define ADV7180_REG_BRI		0x000a	/*Signed */
  62#define ADV7180_BRI_MIN		-128
  63#define ADV7180_BRI_DEF		0
  64#define ADV7180_BRI_MAX		127
  65/* Hue */
  66#define ADV7180_REG_HUE		0x000b	/*Signed, inverted */
  67#define ADV7180_HUE_MIN		-127
  68#define ADV7180_HUE_DEF		0
  69#define ADV7180_HUE_MAX		128
  70
  71#define ADV7180_REG_DEF_VALUE_Y	0x000c
  72#define ADV7180_DEF_VAL_EN		0x1
  73#define ADV7180_DEF_VAL_AUTO_EN	0x2
  74#define ADV7180_REG_CTRL		0x000e
  75#define ADV7180_CTRL_IRQ_SPACE		0x20
  76
  77#define ADV7180_REG_PWR_MAN		0x0f
  78#define ADV7180_PWR_MAN_ON		0x04
  79#define ADV7180_PWR_MAN_OFF		0x24
  80#define ADV7180_PWR_MAN_RES		0x80
  81
  82#define ADV7180_REG_STATUS1		0x0010
  83#define ADV7180_STATUS1_IN_LOCK		0x01
  84#define ADV7180_STATUS1_AUTOD_MASK	0x70
  85#define ADV7180_STATUS1_AUTOD_NTSM_M_J	0x00
  86#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  87#define ADV7180_STATUS1_AUTOD_PAL_M	0x20
  88#define ADV7180_STATUS1_AUTOD_PAL_60	0x30
  89#define ADV7180_STATUS1_AUTOD_PAL_B_G	0x40
  90#define ADV7180_STATUS1_AUTOD_SECAM	0x50
  91#define ADV7180_STATUS1_AUTOD_PAL_COMB	0x60
  92#define ADV7180_STATUS1_AUTOD_SECAM_525	0x70
  93
  94#define ADV7180_REG_IDENT 0x0011
  95#define ADV7180_ID_7180 0x18
  96
  97#define ADV7180_REG_STATUS3		0x0013
  98#define ADV7180_REG_ANALOG_CLAMP_CTL	0x0014
  99#define ADV7180_REG_SHAP_FILTER_CTL_1	0x0017
 100#define ADV7180_REG_CTRL_2		0x001d
 101#define ADV7180_REG_VSYNC_FIELD_CTL_1	0x0031
 102#define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
 103#define ADV7180_REG_MANUAL_WIN_CTL_1	0x003d
 104#define ADV7180_REG_MANUAL_WIN_CTL_2	0x003e
 105#define ADV7180_REG_MANUAL_WIN_CTL_3	0x003f
 106#define ADV7180_REG_LOCK_CNT		0x0051
 107#define ADV7180_REG_CVBS_TRIM		0x0052
 108#define ADV7180_REG_CLAMP_ADJ		0x005a
 109#define ADV7180_REG_RES_CIR		0x005f
 110#define ADV7180_REG_DIFF_MODE		0x0060
 111
 112#define ADV7180_REG_ICONF1		0x2040
 113#define ADV7180_ICONF1_ACTIVE_LOW	0x01
 114#define ADV7180_ICONF1_PSYNC_ONLY	0x10
 115#define ADV7180_ICONF1_ACTIVE_TO_CLR	0xC0
 116/* Saturation */
 117#define ADV7180_REG_SD_SAT_CB	0x00e3	/*Unsigned */
 118#define ADV7180_REG_SD_SAT_CR	0x00e4	/*Unsigned */
 119#define ADV7180_SAT_MIN		0
 120#define ADV7180_SAT_DEF		128
 121#define ADV7180_SAT_MAX		255
 122
 123#define ADV7180_IRQ1_LOCK	0x01
 124#define ADV7180_IRQ1_UNLOCK	0x02
 125#define ADV7180_REG_ISR1	0x2042
 126#define ADV7180_REG_ICR1	0x2043
 127#define ADV7180_REG_IMR1	0x2044
 128#define ADV7180_REG_IMR2	0x2048
 129#define ADV7180_IRQ3_AD_CHANGE	0x08
 130#define ADV7180_REG_ISR3	0x204A
 131#define ADV7180_REG_ICR3	0x204B
 132#define ADV7180_REG_IMR3	0x204C
 133#define ADV7180_REG_IMR4	0x2050
 134
 135#define ADV7180_REG_NTSC_V_BIT_END	0x00E6
 136#define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND	0x4F
 137
 138#define ADV7180_REG_VPP_SLAVE_ADDR	0xFD
 139#define ADV7180_REG_CSI_SLAVE_ADDR	0xFE
 140
 141#define ADV7180_REG_ACE_CTRL1		0x4080
 142#define ADV7180_REG_ACE_CTRL5		0x4084
 143#define ADV7180_REG_FLCONTROL		0x40e0
 144#define ADV7180_FLCONTROL_FL_ENABLE 0x1
 145
 146#define ADV7180_REG_RST_CLAMP	0x809c
 147#define ADV7180_REG_AGC_ADJ1	0x80b6
 148#define ADV7180_REG_AGC_ADJ2	0x80c0
 149
 150#define ADV7180_CSI_REG_PWRDN	0x00
 151#define ADV7180_CSI_PWRDN	0x80
 152
 153#define ADV7180_INPUT_CVBS_AIN1 0x00
 154#define ADV7180_INPUT_CVBS_AIN2 0x01
 155#define ADV7180_INPUT_CVBS_AIN3 0x02
 156#define ADV7180_INPUT_CVBS_AIN4 0x03
 157#define ADV7180_INPUT_CVBS_AIN5 0x04
 158#define ADV7180_INPUT_CVBS_AIN6 0x05
 159#define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
 160#define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
 161#define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
 162#define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
 163#define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
 164
 165#define ADV7182_INPUT_CVBS_AIN1 0x00
 166#define ADV7182_INPUT_CVBS_AIN2 0x01
 167#define ADV7182_INPUT_CVBS_AIN3 0x02
 168#define ADV7182_INPUT_CVBS_AIN4 0x03
 169#define ADV7182_INPUT_CVBS_AIN5 0x04
 170#define ADV7182_INPUT_CVBS_AIN6 0x05
 171#define ADV7182_INPUT_CVBS_AIN7 0x06
 172#define ADV7182_INPUT_CVBS_AIN8 0x07
 173#define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
 174#define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
 175#define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
 176#define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
 177#define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
 178#define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
 179#define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
 180#define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
 181#define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
 182#define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
 183
 184#define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
 185#define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
 186
 187#define V4L2_CID_ADV_FAST_SWITCH	(V4L2_CID_USER_ADV7180_BASE + 0x00)
 188
 189/* Initial number of frames to skip to avoid possible garbage */
 190#define ADV7180_NUM_OF_SKIP_FRAMES       2
 191
 192struct adv7180_state;
 193
 194#define ADV7180_FLAG_RESET_POWERED	BIT(0)
 195#define ADV7180_FLAG_V2			BIT(1)
 196#define ADV7180_FLAG_MIPI_CSI2		BIT(2)
 197#define ADV7180_FLAG_I2P		BIT(3)
 198#define ADV7180_FLAG_TEST_PATTERN	BIT(4)
 199
 200struct adv7180_chip_info {
 201	unsigned int flags;
 202	unsigned int valid_input_mask;
 203	int (*set_std)(struct adv7180_state *st, unsigned int std);
 204	int (*select_input)(struct adv7180_state *st, unsigned int input);
 205	int (*init)(struct adv7180_state *state);
 206};
 207
 208struct adv7180_state {
 209	struct v4l2_ctrl_handler ctrl_hdl;
 210	struct v4l2_subdev	sd;
 211	struct media_pad	pad;
 212	struct mutex		mutex; /* mutual excl. when accessing chip */
 213	int			irq;
 214	struct gpio_desc	*pwdn_gpio;
 215	struct gpio_desc	*rst_gpio;
 216	v4l2_std_id		curr_norm;
 217	bool			streaming;
 218	u8			input;
 219
 220	struct i2c_client	*client;
 221	unsigned int		register_page;
 222	struct i2c_client	*csi_client;
 223	struct i2c_client	*vpp_client;
 224	const struct adv7180_chip_info *chip_info;
 225	enum v4l2_field		field;
 226	bool			force_bt656_4;
 227};
 228#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler,		\
 229					    struct adv7180_state,	\
 230					    ctrl_hdl)->sd)
 231
 232static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
 233{
 234	if (state->register_page != page) {
 235		i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
 236			page);
 237		state->register_page = page;
 238	}
 239
 240	return 0;
 241}
 242
 243static int adv7180_write(struct adv7180_state *state, unsigned int reg,
 244	unsigned int value)
 245{
 246	lockdep_assert_held(&state->mutex);
 247	adv7180_select_page(state, reg >> 8);
 248	return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
 249}
 250
 251static int adv7180_read(struct adv7180_state *state, unsigned int reg)
 252{
 253	lockdep_assert_held(&state->mutex);
 254	adv7180_select_page(state, reg >> 8);
 255	return i2c_smbus_read_byte_data(state->client, reg & 0xff);
 256}
 257
 258static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
 259	unsigned int value)
 260{
 261	return i2c_smbus_write_byte_data(state->csi_client, reg, value);
 262}
 263
 264static int adv7180_set_video_standard(struct adv7180_state *state,
 265	unsigned int std)
 266{
 267	return state->chip_info->set_std(state, std);
 268}
 269
 270static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
 271	unsigned int value)
 272{
 273	return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
 274}
 275
 276static int adv7180_set_power(struct adv7180_state *state, bool on)
 277{
 278	u8 val;
 279	int ret;
 280
 281	if (on)
 282		val = ADV7180_PWR_MAN_ON;
 283	else
 284		val = ADV7180_PWR_MAN_OFF;
 285
 286	ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
 287	if (ret)
 288		return ret;
 289
 290	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 291		if (on) {
 292			adv7180_csi_write(state, 0xDE, 0x02);
 293			adv7180_csi_write(state, 0xD2, 0xF7);
 294			adv7180_csi_write(state, 0xD8, 0x65);
 295			adv7180_csi_write(state, 0xE0, 0x09);
 296			adv7180_csi_write(state, 0x2C, 0x00);
 297			if (state->field == V4L2_FIELD_NONE)
 298				adv7180_csi_write(state, 0x1D, 0x80);
 299			adv7180_csi_write(state, 0x00, 0x00);
 300		} else {
 301			adv7180_csi_write(state, 0x00, 0x80);
 302		}
 303	}
 304
 305	return 0;
 306}
 307
 308static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
 309{
 310	/* in case V4L2_IN_ST_NO_SIGNAL */
 311	if (!(status1 & ADV7180_STATUS1_IN_LOCK))
 312		return V4L2_STD_UNKNOWN;
 313
 314	switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
 315	case ADV7180_STATUS1_AUTOD_NTSM_M_J:
 316		return V4L2_STD_NTSC;
 317	case ADV7180_STATUS1_AUTOD_NTSC_4_43:
 318		return V4L2_STD_NTSC_443;
 319	case ADV7180_STATUS1_AUTOD_PAL_M:
 320		return V4L2_STD_PAL_M;
 321	case ADV7180_STATUS1_AUTOD_PAL_60:
 322		return V4L2_STD_PAL_60;
 323	case ADV7180_STATUS1_AUTOD_PAL_B_G:
 324		return V4L2_STD_PAL;
 325	case ADV7180_STATUS1_AUTOD_SECAM:
 326		return V4L2_STD_SECAM;
 327	case ADV7180_STATUS1_AUTOD_PAL_COMB:
 328		return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
 329	case ADV7180_STATUS1_AUTOD_SECAM_525:
 330		return V4L2_STD_SECAM;
 331	default:
 332		return V4L2_STD_UNKNOWN;
 333	}
 334}
 335
 336static int v4l2_std_to_adv7180(v4l2_std_id std)
 337{
 338	if (std == V4L2_STD_PAL_60)
 339		return ADV7180_STD_PAL60;
 340	if (std == V4L2_STD_NTSC_443)
 341		return ADV7180_STD_NTSC_443;
 342	if (std == V4L2_STD_PAL_N)
 343		return ADV7180_STD_PAL_N;
 344	if (std == V4L2_STD_PAL_M)
 345		return ADV7180_STD_PAL_M;
 346	if (std == V4L2_STD_PAL_Nc)
 347		return ADV7180_STD_PAL_COMB_N;
 348
 349	if (std & V4L2_STD_PAL)
 350		return ADV7180_STD_PAL_BG;
 351	if (std & V4L2_STD_NTSC)
 352		return ADV7180_STD_NTSC_M;
 353	if (std & V4L2_STD_SECAM)
 354		return ADV7180_STD_PAL_SECAM;
 355
 356	return -EINVAL;
 357}
 358
 359static u32 adv7180_status_to_v4l2(u8 status1)
 360{
 361	if (!(status1 & ADV7180_STATUS1_IN_LOCK))
 362		return V4L2_IN_ST_NO_SIGNAL;
 363
 364	return 0;
 365}
 366
 367static int __adv7180_status(struct adv7180_state *state, u32 *status,
 368			    v4l2_std_id *std)
 369{
 370	int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
 371
 372	if (status1 < 0)
 373		return status1;
 374
 375	if (status)
 376		*status = adv7180_status_to_v4l2(status1);
 377	if (std)
 378		*std = adv7180_std_to_v4l2(status1);
 379
 380	return 0;
 381}
 382
 383static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
 384{
 385	return container_of(sd, struct adv7180_state, sd);
 386}
 387
 388static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
 389{
 390	struct adv7180_state *state = to_state(sd);
 391	int ret;
 392
 393	guard(mutex)(&state->mutex);
 394
 395	/*
 396	 * We can't sample the standard if the device is streaming as that would
 397	 * interfere with the capture session as the VID_SEL reg is touched.
 398	 */
 399	if (state->streaming)
 400		return -EBUSY;
 401
 402	/* Set the standard to autodetect PAL B/G/H/I/D, NTSC J or SECAM */
 403	ret = adv7180_set_video_standard(state,
 404					 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
 405	if (ret)
 406		return ret;
 407
 408	/* Allow some time for the autodetection to run. */
 409	msleep(100);
 410
 411	return __adv7180_status(state, NULL, std);
 412}
 413
 414static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
 415			     u32 output, u32 config)
 416{
 417	struct adv7180_state *state = to_state(sd);
 418	int ret = mutex_lock_interruptible(&state->mutex);
 419
 420	if (ret)
 421		return ret;
 422
 423	if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
 424		ret = -EINVAL;
 425		goto out;
 426	}
 427
 428	ret = state->chip_info->select_input(state, input);
 429
 430	if (ret == 0)
 431		state->input = input;
 432out:
 433	mutex_unlock(&state->mutex);
 434	return ret;
 435}
 436
 437static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
 438{
 439	struct adv7180_state *state = to_state(sd);
 440	int ret = mutex_lock_interruptible(&state->mutex);
 441	if (ret)
 442		return ret;
 443
 444	ret = __adv7180_status(state, status, NULL);
 445	mutex_unlock(&state->mutex);
 446	return ret;
 447}
 448
 449static int adv7180_program_std(struct adv7180_state *state)
 450{
 451	int ret;
 452
 453	ret = v4l2_std_to_adv7180(state->curr_norm);
 454	if (ret < 0)
 455		return ret;
 456
 457	ret = adv7180_set_video_standard(state, ret);
 458	if (ret < 0)
 459		return ret;
 460	return 0;
 461}
 462
 463static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
 464{
 465	struct adv7180_state *state = to_state(sd);
 466	int ret;
 467
 468	guard(mutex)(&state->mutex);
 469
 470	/* Make sure we can support this std */
 471	ret = v4l2_std_to_adv7180(std);
 472	if (ret < 0)
 473		return ret;
 474
 475	state->curr_norm = std;
 476
 477	return 0;
 478}
 479
 480static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
 481{
 482	struct adv7180_state *state = to_state(sd);
 483
 484	*norm = state->curr_norm;
 485
 486	return 0;
 487}
 488
 489static int adv7180_get_frame_interval(struct v4l2_subdev *sd,
 490				      struct v4l2_subdev_state *sd_state,
 491				      struct v4l2_subdev_frame_interval *fi)
 492{
 493	struct adv7180_state *state = to_state(sd);
 494
 495	/*
 496	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
 497	 * subdev active state API.
 498	 */
 499	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 500		return -EINVAL;
 501
 502	if (state->curr_norm & V4L2_STD_525_60) {
 503		fi->interval.numerator = 1001;
 504		fi->interval.denominator = 30000;
 505	} else {
 506		fi->interval.numerator = 1;
 507		fi->interval.denominator = 25;
 508	}
 509
 510	/*
 511	 * If the de-interlacer is active, the chip produces full video frames
 512	 * at the field rate.
 513	 */
 514	if (state->field == V4L2_FIELD_NONE)
 515		fi->interval.denominator *= 2;
 516
 517	return 0;
 518}
 519
 520static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
 521{
 522	if (!state->pwdn_gpio)
 523		return;
 524
 525	if (on) {
 526		gpiod_set_value_cansleep(state->pwdn_gpio, 0);
 527		usleep_range(5000, 10000);
 528	} else {
 529		gpiod_set_value_cansleep(state->pwdn_gpio, 1);
 530	}
 531}
 532
 533static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
 534{
 535	if (!state->rst_gpio)
 536		return;
 537
 538	if (on) {
 539		gpiod_set_value_cansleep(state->rst_gpio, 1);
 540	} else {
 541		gpiod_set_value_cansleep(state->rst_gpio, 0);
 542		usleep_range(5000, 10000);
 543	}
 544}
 545
 546static const char * const test_pattern_menu[] = {
 547	"Single color",
 548	"Color bars",
 549	"Luma ramp",
 550	"Boundary box",
 551	"Disable",
 552};
 553
 554static int adv7180_test_pattern(struct adv7180_state *state, int value)
 555{
 556	unsigned int reg = 0;
 557
 558	/* Map menu value into register value */
 559	if (value < 3)
 560		reg = value;
 561	if (value == 3)
 562		reg = 5;
 563
 564	adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
 565
 566	if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
 567		reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
 568		reg &= ~ADV7180_DEF_VAL_EN;
 569		adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
 570		return 0;
 571	}
 572
 573	reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
 574	reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
 575	adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
 576
 577	return 0;
 578}
 579
 580static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
 581{
 582	struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
 583	struct adv7180_state *state = to_state(sd);
 584	int ret = 0;
 585	int val;
 586
 587	lockdep_assert_held(&state->mutex);
 588
 589	val = ctrl->val;
 590	switch (ctrl->id) {
 591	case V4L2_CID_BRIGHTNESS:
 592		ret = adv7180_write(state, ADV7180_REG_BRI, val);
 593		break;
 594	case V4L2_CID_HUE:
 595		/*Hue is inverted according to HSL chart */
 596		ret = adv7180_write(state, ADV7180_REG_HUE, -val);
 597		break;
 598	case V4L2_CID_CONTRAST:
 599		ret = adv7180_write(state, ADV7180_REG_CON, val);
 600		break;
 601	case V4L2_CID_SATURATION:
 602		/*
 603		 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
 604		 *Let's not confuse the user, everybody understands saturation
 605		 */
 606		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
 607		if (ret < 0)
 608			break;
 609		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
 610		break;
 611	case V4L2_CID_ADV_FAST_SWITCH:
 612		if (ctrl->val) {
 613			/* ADI required write */
 614			adv7180_write(state, 0x80d9, 0x44);
 615			adv7180_write(state, ADV7180_REG_FLCONTROL,
 616				ADV7180_FLCONTROL_FL_ENABLE);
 617		} else {
 618			/* ADI required write */
 619			adv7180_write(state, 0x80d9, 0xc4);
 620			adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
 621		}
 622		break;
 623	case V4L2_CID_TEST_PATTERN:
 624		ret = adv7180_test_pattern(state, val);
 625		break;
 626	default:
 627		ret = -EINVAL;
 628	}
 629
 630	return ret;
 631}
 632
 633static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
 634	.s_ctrl = adv7180_s_ctrl,
 635};
 636
 637static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
 638	.ops = &adv7180_ctrl_ops,
 639	.id = V4L2_CID_ADV_FAST_SWITCH,
 640	.name = "Fast Switching",
 641	.type = V4L2_CTRL_TYPE_BOOLEAN,
 642	.min = 0,
 643	.max = 1,
 644	.step = 1,
 645};
 646
 647static int adv7180_init_controls(struct adv7180_state *state)
 648{
 649	v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
 650	state->ctrl_hdl.lock = &state->mutex;
 651
 652	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
 653			  V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
 654			  ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
 655	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
 656			  V4L2_CID_CONTRAST, ADV7180_CON_MIN,
 657			  ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
 658	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
 659			  V4L2_CID_SATURATION, ADV7180_SAT_MIN,
 660			  ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
 661	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
 662			  V4L2_CID_HUE, ADV7180_HUE_MIN,
 663			  ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
 664	v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
 665
 666	if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) {
 667		v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl,
 668					     &adv7180_ctrl_ops,
 669					     V4L2_CID_TEST_PATTERN,
 670					     ARRAY_SIZE(test_pattern_menu) - 1,
 671					     0,
 672					     ARRAY_SIZE(test_pattern_menu) - 1,
 673					     test_pattern_menu);
 674	}
 675
 676	state->sd.ctrl_handler = &state->ctrl_hdl;
 677	if (state->ctrl_hdl.error) {
 678		int err = state->ctrl_hdl.error;
 679
 680		v4l2_ctrl_handler_free(&state->ctrl_hdl);
 681		return err;
 682	}
 683
 684	return 0;
 685}
 686static void adv7180_exit_controls(struct adv7180_state *state)
 687{
 688	v4l2_ctrl_handler_free(&state->ctrl_hdl);
 689}
 690
 691static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
 692				  struct v4l2_subdev_state *sd_state,
 693				  struct v4l2_subdev_mbus_code_enum *code)
 694{
 695	if (code->index != 0)
 696		return -EINVAL;
 697
 698	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
 699
 700	return 0;
 701}
 702
 703static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
 704			    struct v4l2_mbus_framefmt *fmt)
 705{
 706	struct adv7180_state *state = to_state(sd);
 707
 708	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
 709	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
 710	fmt->width = 720;
 711	fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
 712
 713	if (state->field == V4L2_FIELD_ALTERNATE)
 714		fmt->height /= 2;
 715
 716	return 0;
 717}
 718
 719static int adv7180_set_field_mode(struct adv7180_state *state)
 720{
 721	if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
 722		return 0;
 723
 724	if (state->field == V4L2_FIELD_NONE) {
 725		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 726			adv7180_csi_write(state, 0x01, 0x20);
 727			adv7180_csi_write(state, 0x02, 0x28);
 728			adv7180_csi_write(state, 0x03, 0x38);
 729			adv7180_csi_write(state, 0x04, 0x30);
 730			adv7180_csi_write(state, 0x05, 0x30);
 731			adv7180_csi_write(state, 0x06, 0x80);
 732			adv7180_csi_write(state, 0x07, 0x70);
 733			adv7180_csi_write(state, 0x08, 0x50);
 734		}
 735		adv7180_vpp_write(state, 0xa3, 0x00);
 736		adv7180_vpp_write(state, 0x5b, 0x00);
 737		adv7180_vpp_write(state, 0x55, 0x80);
 738	} else {
 739		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 740			adv7180_csi_write(state, 0x01, 0x18);
 741			adv7180_csi_write(state, 0x02, 0x18);
 742			adv7180_csi_write(state, 0x03, 0x30);
 743			adv7180_csi_write(state, 0x04, 0x20);
 744			adv7180_csi_write(state, 0x05, 0x28);
 745			adv7180_csi_write(state, 0x06, 0x40);
 746			adv7180_csi_write(state, 0x07, 0x58);
 747			adv7180_csi_write(state, 0x08, 0x30);
 748		}
 749		adv7180_vpp_write(state, 0xa3, 0x70);
 750		adv7180_vpp_write(state, 0x5b, 0x80);
 751		adv7180_vpp_write(state, 0x55, 0x00);
 752	}
 753
 754	return 0;
 755}
 756
 757static int adv7180_get_pad_format(struct v4l2_subdev *sd,
 758				  struct v4l2_subdev_state *sd_state,
 759				  struct v4l2_subdev_format *format)
 760{
 761	struct adv7180_state *state = to_state(sd);
 762
 763	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 764		format->format = *v4l2_subdev_state_get_format(sd_state, 0);
 765	} else {
 766		adv7180_mbus_fmt(sd, &format->format);
 767		format->format.field = state->field;
 768	}
 769
 770	return 0;
 771}
 772
 773static int adv7180_set_pad_format(struct v4l2_subdev *sd,
 774				  struct v4l2_subdev_state *sd_state,
 775				  struct v4l2_subdev_format *format)
 776{
 777	struct adv7180_state *state = to_state(sd);
 778	struct v4l2_mbus_framefmt *framefmt;
 779	int ret;
 780
 781	switch (format->format.field) {
 782	case V4L2_FIELD_NONE:
 783		if (state->chip_info->flags & ADV7180_FLAG_I2P)
 784			break;
 785		fallthrough;
 786	default:
 787		format->format.field = V4L2_FIELD_ALTERNATE;
 788		break;
 789	}
 790
 791	ret = adv7180_mbus_fmt(sd,  &format->format);
 792
 793	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 794		state->field = format->format.field;
 795	} else {
 796		framefmt = v4l2_subdev_state_get_format(sd_state, 0);
 797		*framefmt = format->format;
 798	}
 799
 800	return ret;
 801}
 802
 803static int adv7180_init_state(struct v4l2_subdev *sd,
 804			      struct v4l2_subdev_state *sd_state)
 805{
 806	struct v4l2_subdev_format fmt = {
 807		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
 808		: V4L2_SUBDEV_FORMAT_ACTIVE,
 809	};
 810
 811	return adv7180_set_pad_format(sd, sd_state, &fmt);
 812}
 813
 814static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
 815				   unsigned int pad,
 816				   struct v4l2_mbus_config *cfg)
 817{
 818	struct adv7180_state *state = to_state(sd);
 819
 820	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 821		cfg->type = V4L2_MBUS_CSI2_DPHY;
 822		cfg->bus.mipi_csi2.num_data_lanes = 1;
 823		cfg->bus.mipi_csi2.flags = 0;
 824	} else {
 825		/*
 826		 * The ADV7180 sensor supports BT.601/656 output modes.
 827		 * The BT.656 is default and not yet configurable by s/w.
 828		 */
 829		cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
 830					  V4L2_MBUS_PCLK_SAMPLE_RISING |
 831					  V4L2_MBUS_DATA_ACTIVE_HIGH;
 832		cfg->type = V4L2_MBUS_BT656;
 833	}
 834
 835	return 0;
 836}
 837
 838static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
 839{
 840	*frames = ADV7180_NUM_OF_SKIP_FRAMES;
 841
 842	return 0;
 843}
 844
 845static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
 846{
 847	*norm = V4L2_STD_ALL;
 848	return 0;
 849}
 850
 851static int init_device(struct adv7180_state *state)
 852{
 853	int ret;
 854
 855	lockdep_assert_held(&state->mutex);
 856
 857	ret = adv7180_program_std(state);
 858	if (ret)
 859		return ret;
 860
 861	adv7180_set_field_mode(state);
 862
 863	__v4l2_ctrl_handler_setup(&state->ctrl_hdl);
 864
 865	return ret;
 866}
 867
 868static int adv7180_reset_device(struct adv7180_state *state)
 869{
 870	int ret;
 871
 872	lockdep_assert_held(&state->mutex);
 873
 874	adv7180_set_power_pin(state, true);
 875	adv7180_set_reset_pin(state, false);
 876
 877	adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
 878	usleep_range(5000, 10000);
 879
 880	/*
 881	 * If the devices decoder is power on after reset, power off so the
 882	 * device can be configured.
 883	 */
 884	if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
 885		adv7180_set_power(state, false);
 886
 887	ret = state->chip_info->init(state);
 888	if (ret)
 889		return ret;
 890
 891	ret = init_device(state);
 892	if (ret)
 893		return ret;
 894
 895	/* register for interrupts */
 896	if (state->irq > 0) {
 897		/* config the Interrupt pin to be active low */
 898		ret = adv7180_write(state, ADV7180_REG_ICONF1,
 899				    ADV7180_ICONF1_ACTIVE_LOW |
 900				    ADV7180_ICONF1_PSYNC_ONLY);
 901		if (ret < 0)
 902			return ret;
 903
 904		ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
 905		if (ret < 0)
 906			return ret;
 907
 908		ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
 909		if (ret < 0)
 910			return ret;
 911
 912		/* enable AD change interrupts */
 913		ret = adv7180_write(state, ADV7180_REG_IMR3,
 914				    ADV7180_IRQ3_AD_CHANGE);
 915		if (ret < 0)
 916			return ret;
 917
 918		ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
 919		if (ret < 0)
 920			return ret;
 921	}
 922
 923	/*
 924	 * If the devices decoder is power on after reset, restore the power
 925	 * after configuration. This is to preserve the behavior of the driver,
 926	 * not doing this result in the first 35+ frames captured being garbage.
 927	 */
 928	if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
 929		adv7180_set_power(state, true);
 930
 931	return 0;
 932}
 933
 934static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
 935{
 936	struct adv7180_state *state = to_state(sd);
 937	int ret;
 938
 939	/* Must wait until querystd released the lock */
 940	guard(mutex)(&state->mutex);
 941
 942	/*
 943	 * Always power off the decoder even if streaming is to be enabled, the
 944	 * decoder needs to be off for the device to be configured.
 945	 */
 946	ret = adv7180_set_power(state, false);
 947	if (ret)
 948		return ret;
 949
 950	if (enable) {
 951		ret = init_device(state);
 952		if (ret)
 953			return ret;
 954
 955		ret = adv7180_set_power(state, true);
 956		if (ret)
 957			return ret;
 958	}
 959
 960	state->streaming = enable;
 961
 962	return 0;
 963}
 964
 965static int adv7180_subscribe_event(struct v4l2_subdev *sd,
 966				   struct v4l2_fh *fh,
 967				   struct v4l2_event_subscription *sub)
 968{
 969	switch (sub->type) {
 970	case V4L2_EVENT_SOURCE_CHANGE:
 971		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
 972	case V4L2_EVENT_CTRL:
 973		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
 974	default:
 975		return -EINVAL;
 976	}
 977}
 978
 979static const struct v4l2_subdev_video_ops adv7180_video_ops = {
 980	.s_std = adv7180_s_std,
 981	.g_std = adv7180_g_std,
 982	.querystd = adv7180_querystd,
 983	.g_input_status = adv7180_g_input_status,
 984	.s_routing = adv7180_s_routing,
 985	.g_tvnorms = adv7180_g_tvnorms,
 986	.s_stream = adv7180_s_stream,
 987};
 988
 989static const struct v4l2_subdev_core_ops adv7180_core_ops = {
 990	.subscribe_event = adv7180_subscribe_event,
 991	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
 992};
 993
 994static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
 995	.enum_mbus_code = adv7180_enum_mbus_code,
 996	.set_fmt = adv7180_set_pad_format,
 997	.get_fmt = adv7180_get_pad_format,
 998	.get_frame_interval = adv7180_get_frame_interval,
 999	.get_mbus_config = adv7180_get_mbus_config,
1000};
1001
1002static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
1003	.g_skip_frames = adv7180_get_skip_frames,
1004};
1005
1006static const struct v4l2_subdev_ops adv7180_ops = {
1007	.core = &adv7180_core_ops,
1008	.video = &adv7180_video_ops,
1009	.pad = &adv7180_pad_ops,
1010	.sensor = &adv7180_sensor_ops,
1011};
1012
1013static const struct v4l2_subdev_internal_ops adv7180_internal_ops = {
1014	.init_state = adv7180_init_state,
1015};
1016
1017static irqreturn_t adv7180_irq(int irq, void *devid)
1018{
1019	struct adv7180_state *state = devid;
1020	u8 isr3;
1021
1022	mutex_lock(&state->mutex);
1023	isr3 = adv7180_read(state, ADV7180_REG_ISR3);
1024	/* clear */
1025	adv7180_write(state, ADV7180_REG_ICR3, isr3);
1026
1027	if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
1028		static const struct v4l2_event src_ch = {
1029			.type = V4L2_EVENT_SOURCE_CHANGE,
1030			.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1031		};
1032
1033		v4l2_subdev_notify_event(&state->sd, &src_ch);
1034	}
1035	mutex_unlock(&state->mutex);
1036
1037	return IRQ_HANDLED;
1038}
1039
1040static int adv7180_init(struct adv7180_state *state)
1041{
1042	int ret;
1043
1044	/* ITU-R BT.656-4 compatible */
1045	ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1046			ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1047	if (ret < 0)
1048		return ret;
1049
1050	/* Manually set V bit end position in NTSC mode */
1051	return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
1052					ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1053}
1054
1055static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
1056{
1057	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
1058		(std << 4) | state->input);
1059}
1060
1061static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
1062{
1063	int ret;
1064
1065	ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
1066	if (ret < 0)
1067		return ret;
1068
1069	ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1070	ret |= input;
1071	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1072}
1073
1074static int adv7182_init(struct adv7180_state *state)
1075{
1076	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1077		adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1078			ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
1079
1080	if (state->chip_info->flags & ADV7180_FLAG_I2P)
1081		adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1082			ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
1083
1084	if (state->chip_info->flags & ADV7180_FLAG_V2) {
1085		/* ADI recommended writes for improved video quality */
1086		adv7180_write(state, 0x0080, 0x51);
1087		adv7180_write(state, 0x0081, 0x51);
1088		adv7180_write(state, 0x0082, 0x68);
1089	}
1090
1091	/* ADI required writes */
1092	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1093		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1094		adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1095		adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1096	} else {
1097		if (state->chip_info->flags & ADV7180_FLAG_V2) {
1098			if (state->force_bt656_4) {
1099				/* ITU-R BT.656-4 compatible */
1100				adv7180_write(state,
1101					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1102					      ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1103				/* Manually set NEWAVMODE */
1104				adv7180_write(state,
1105					      ADV7180_REG_VSYNC_FIELD_CTL_1,
1106					      ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1107				/* Manually set V bit end position in NTSC mode */
1108				adv7180_write(state,
1109					      ADV7180_REG_NTSC_V_BIT_END,
1110					      ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1111			} else {
1112				adv7180_write(state,
1113					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1114					      0x17);
1115			}
1116		} else {
1117			adv7180_write(state,
1118				      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1119				      0x07);
1120		}
1121		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1122		adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1123	}
1124
1125	adv7180_write(state, 0x0013, 0x00);
1126
1127	return 0;
1128}
1129
1130static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1131{
1132	/* Failing to set the reserved bit can result in increased video noise */
1133	return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1134			     (std << 4) | ADV7182_REG_INPUT_RESERVED);
1135}
1136
1137enum adv7182_input_type {
1138	ADV7182_INPUT_TYPE_CVBS,
1139	ADV7182_INPUT_TYPE_DIFF_CVBS,
1140	ADV7182_INPUT_TYPE_SVIDEO,
1141	ADV7182_INPUT_TYPE_YPBPR,
1142};
1143
1144static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1145{
1146	switch (input) {
1147	case ADV7182_INPUT_CVBS_AIN1:
1148	case ADV7182_INPUT_CVBS_AIN2:
1149	case ADV7182_INPUT_CVBS_AIN3:
1150	case ADV7182_INPUT_CVBS_AIN4:
1151	case ADV7182_INPUT_CVBS_AIN5:
1152	case ADV7182_INPUT_CVBS_AIN6:
1153	case ADV7182_INPUT_CVBS_AIN7:
1154	case ADV7182_INPUT_CVBS_AIN8:
1155		return ADV7182_INPUT_TYPE_CVBS;
1156	case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1157	case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1158	case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1159	case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1160		return ADV7182_INPUT_TYPE_SVIDEO;
1161	case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1162	case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1163		return ADV7182_INPUT_TYPE_YPBPR;
1164	case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1165	case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1166	case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1167	case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1168		return ADV7182_INPUT_TYPE_DIFF_CVBS;
1169	default: /* Will never happen */
1170		return 0;
1171	}
1172}
1173
1174/* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1175static unsigned int adv7182_lbias_settings[][3] = {
1176	[ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1177	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1178	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1179	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1180};
1181
1182static unsigned int adv7280_lbias_settings[][3] = {
1183	[ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1184	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1185	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1186	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1187};
1188
1189static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1190{
1191	enum adv7182_input_type input_type;
1192	unsigned int *lbias;
1193	unsigned int i;
1194	int ret;
1195
1196	ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1197	if (ret)
1198		return ret;
1199
1200	/* Reset clamp circuitry - ADI recommended writes */
1201	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1202	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1203
1204	input_type = adv7182_get_input_type(input);
1205
1206	switch (input_type) {
1207	case ADV7182_INPUT_TYPE_CVBS:
1208	case ADV7182_INPUT_TYPE_DIFF_CVBS:
1209		/* ADI recommends to use the SH1 filter */
1210		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1211		break;
1212	default:
1213		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1214		break;
1215	}
1216
1217	if (state->chip_info->flags & ADV7180_FLAG_V2)
1218		lbias = adv7280_lbias_settings[input_type];
1219	else
1220		lbias = adv7182_lbias_settings[input_type];
1221
1222	for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1223		adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1224
1225	if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1226		/* ADI required writes to make differential CVBS work */
1227		adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1228		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1229		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1230		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1231		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1232	} else {
1233		adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1234		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1235		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1236		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1237		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1238	}
1239
1240	return 0;
1241}
1242
1243static const struct adv7180_chip_info adv7180_info = {
1244	.flags = ADV7180_FLAG_RESET_POWERED,
1245	/* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1246	 * all inputs and let the card driver take care of validation
1247	 */
1248	.valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1249		BIT(ADV7180_INPUT_CVBS_AIN2) |
1250		BIT(ADV7180_INPUT_CVBS_AIN3) |
1251		BIT(ADV7180_INPUT_CVBS_AIN4) |
1252		BIT(ADV7180_INPUT_CVBS_AIN5) |
1253		BIT(ADV7180_INPUT_CVBS_AIN6) |
1254		BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1255		BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1256		BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1257		BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1258		BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1259	.init = adv7180_init,
1260	.set_std = adv7180_set_std,
1261	.select_input = adv7180_select_input,
1262};
1263
1264static const struct adv7180_chip_info adv7182_info = {
1265	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1266		BIT(ADV7182_INPUT_CVBS_AIN2) |
1267		BIT(ADV7182_INPUT_CVBS_AIN3) |
1268		BIT(ADV7182_INPUT_CVBS_AIN4) |
1269		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1270		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1271		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1272		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1273		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1274	.init = adv7182_init,
1275	.set_std = adv7182_set_std,
1276	.select_input = adv7182_select_input,
1277};
1278
1279static const struct adv7180_chip_info adv7280_info = {
1280	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1281	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1282		BIT(ADV7182_INPUT_CVBS_AIN2) |
1283		BIT(ADV7182_INPUT_CVBS_AIN3) |
1284		BIT(ADV7182_INPUT_CVBS_AIN4) |
1285		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1286		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1287		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1288	.init = adv7182_init,
1289	.set_std = adv7182_set_std,
1290	.select_input = adv7182_select_input,
1291};
1292
1293static const struct adv7180_chip_info adv7280_m_info = {
1294	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1295		ADV7180_FLAG_TEST_PATTERN,
1296	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1297		BIT(ADV7182_INPUT_CVBS_AIN2) |
1298		BIT(ADV7182_INPUT_CVBS_AIN3) |
1299		BIT(ADV7182_INPUT_CVBS_AIN4) |
1300		BIT(ADV7182_INPUT_CVBS_AIN5) |
1301		BIT(ADV7182_INPUT_CVBS_AIN6) |
1302		BIT(ADV7182_INPUT_CVBS_AIN7) |
1303		BIT(ADV7182_INPUT_CVBS_AIN8) |
1304		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1305		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1306		BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1307		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1308		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1309		BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1310	.init = adv7182_init,
1311	.set_std = adv7182_set_std,
1312	.select_input = adv7182_select_input,
1313};
1314
1315static const struct adv7180_chip_info adv7281_info = {
1316	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1317		ADV7180_FLAG_TEST_PATTERN,
1318	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1319		BIT(ADV7182_INPUT_CVBS_AIN2) |
1320		BIT(ADV7182_INPUT_CVBS_AIN7) |
1321		BIT(ADV7182_INPUT_CVBS_AIN8) |
1322		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1323		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1324		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1325		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1326	.init = adv7182_init,
1327	.set_std = adv7182_set_std,
1328	.select_input = adv7182_select_input,
1329};
1330
1331static const struct adv7180_chip_info adv7281_m_info = {
1332	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1333		ADV7180_FLAG_TEST_PATTERN,
1334	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1335		BIT(ADV7182_INPUT_CVBS_AIN2) |
1336		BIT(ADV7182_INPUT_CVBS_AIN3) |
1337		BIT(ADV7182_INPUT_CVBS_AIN4) |
1338		BIT(ADV7182_INPUT_CVBS_AIN7) |
1339		BIT(ADV7182_INPUT_CVBS_AIN8) |
1340		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1341		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1342		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1343		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1344		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1345		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1346		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1347	.init = adv7182_init,
1348	.set_std = adv7182_set_std,
1349	.select_input = adv7182_select_input,
1350};
1351
1352static const struct adv7180_chip_info adv7281_ma_info = {
1353	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1354		ADV7180_FLAG_TEST_PATTERN,
1355	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1356		BIT(ADV7182_INPUT_CVBS_AIN2) |
1357		BIT(ADV7182_INPUT_CVBS_AIN3) |
1358		BIT(ADV7182_INPUT_CVBS_AIN4) |
1359		BIT(ADV7182_INPUT_CVBS_AIN5) |
1360		BIT(ADV7182_INPUT_CVBS_AIN6) |
1361		BIT(ADV7182_INPUT_CVBS_AIN7) |
1362		BIT(ADV7182_INPUT_CVBS_AIN8) |
1363		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1364		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1365		BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1366		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1367		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1368		BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1369		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1370		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1371		BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1372		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1373	.init = adv7182_init,
1374	.set_std = adv7182_set_std,
1375	.select_input = adv7182_select_input,
1376};
1377
1378static const struct adv7180_chip_info adv7282_info = {
1379	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1380	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1381		BIT(ADV7182_INPUT_CVBS_AIN2) |
1382		BIT(ADV7182_INPUT_CVBS_AIN7) |
1383		BIT(ADV7182_INPUT_CVBS_AIN8) |
1384		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1385		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1386		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1387		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1388	.init = adv7182_init,
1389	.set_std = adv7182_set_std,
1390	.select_input = adv7182_select_input,
1391};
1392
1393static const struct adv7180_chip_info adv7282_m_info = {
1394	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1395		ADV7180_FLAG_TEST_PATTERN,
1396	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1397		BIT(ADV7182_INPUT_CVBS_AIN2) |
1398		BIT(ADV7182_INPUT_CVBS_AIN3) |
1399		BIT(ADV7182_INPUT_CVBS_AIN4) |
1400		BIT(ADV7182_INPUT_CVBS_AIN7) |
1401		BIT(ADV7182_INPUT_CVBS_AIN8) |
1402		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1403		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1404		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1405		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1406		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1407		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1408	.init = adv7182_init,
1409	.set_std = adv7182_set_std,
1410	.select_input = adv7182_select_input,
1411};
1412
1413static int adv7180_probe(struct i2c_client *client)
1414{
1415	struct device_node *np = client->dev.of_node;
1416	struct adv7180_state *state;
1417	struct v4l2_subdev *sd;
1418	int ret;
1419
1420	/* Check if the adapter supports the needed features */
1421	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1422		return -EIO;
1423
1424	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1425	if (state == NULL)
1426		return -ENOMEM;
1427
1428	state->client = client;
1429	state->field = V4L2_FIELD_ALTERNATE;
1430	state->chip_info = i2c_get_match_data(client);
1431
1432	state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1433						   GPIOD_OUT_HIGH);
1434	if (IS_ERR(state->pwdn_gpio)) {
1435		ret = PTR_ERR(state->pwdn_gpio);
1436		v4l_err(client, "request for power pin failed: %d\n", ret);
1437		return ret;
1438	}
1439
1440	state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1441						  GPIOD_OUT_HIGH);
1442	if (IS_ERR(state->rst_gpio)) {
1443		ret = PTR_ERR(state->rst_gpio);
1444		v4l_err(client, "request for reset pin failed: %d\n", ret);
1445		return ret;
1446	}
1447
1448	if (of_property_read_bool(np, "adv,force-bt656-4") ||
1449	    of_property_read_bool(np, "adi,force-bt656-4"))
1450		state->force_bt656_4 = true;
1451
1452	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1453		state->csi_client = i2c_new_dummy_device(client->adapter,
1454				ADV7180_DEFAULT_CSI_I2C_ADDR);
1455		if (IS_ERR(state->csi_client))
1456			return PTR_ERR(state->csi_client);
1457	}
1458
1459	if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1460		state->vpp_client = i2c_new_dummy_device(client->adapter,
1461				ADV7180_DEFAULT_VPP_I2C_ADDR);
1462		if (IS_ERR(state->vpp_client)) {
1463			ret = PTR_ERR(state->vpp_client);
1464			goto err_unregister_csi_client;
1465		}
1466	}
1467
1468	state->irq = client->irq;
1469	mutex_init(&state->mutex);
1470	state->curr_norm = V4L2_STD_NTSC;
1471
1472	state->input = 0;
1473	sd = &state->sd;
1474	v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1475	sd->internal_ops = &adv7180_internal_ops;
1476	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1477
1478	ret = adv7180_init_controls(state);
1479	if (ret)
1480		goto err_unregister_vpp_client;
1481
1482	state->pad.flags = MEDIA_PAD_FL_SOURCE;
1483	sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1484	ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1485	if (ret)
1486		goto err_free_ctrl;
1487
1488	mutex_lock(&state->mutex);
1489	ret = adv7180_reset_device(state);
1490	mutex_unlock(&state->mutex);
1491	if (ret)
1492		goto err_media_entity_cleanup;
1493
1494	if (state->irq > 0) {
1495		ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1496					   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1497					   KBUILD_MODNAME, state);
1498		if (ret)
1499			goto err_media_entity_cleanup;
1500	}
1501
1502	ret = v4l2_async_register_subdev(sd);
1503	if (ret)
1504		goto err_free_irq;
1505
1506	mutex_lock(&state->mutex);
1507	ret = adv7180_read(state, ADV7180_REG_IDENT);
1508	mutex_unlock(&state->mutex);
1509	if (ret < 0)
1510		goto err_v4l2_async_unregister;
1511
1512	v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1513		 ret, client->addr, client->adapter->name);
1514
1515	return 0;
1516
1517err_v4l2_async_unregister:
1518	v4l2_async_unregister_subdev(sd);
1519err_free_irq:
1520	if (state->irq > 0)
1521		free_irq(client->irq, state);
1522err_media_entity_cleanup:
1523	media_entity_cleanup(&sd->entity);
1524err_free_ctrl:
1525	adv7180_exit_controls(state);
1526err_unregister_vpp_client:
1527	i2c_unregister_device(state->vpp_client);
1528err_unregister_csi_client:
1529	i2c_unregister_device(state->csi_client);
1530	mutex_destroy(&state->mutex);
1531	return ret;
1532}
1533
1534static void adv7180_remove(struct i2c_client *client)
1535{
1536	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1537	struct adv7180_state *state = to_state(sd);
1538
1539	v4l2_async_unregister_subdev(sd);
1540
1541	if (state->irq > 0)
1542		free_irq(client->irq, state);
1543
1544	media_entity_cleanup(&sd->entity);
1545	adv7180_exit_controls(state);
1546
1547	i2c_unregister_device(state->vpp_client);
1548	i2c_unregister_device(state->csi_client);
1549
1550	adv7180_set_reset_pin(state, true);
1551	adv7180_set_power_pin(state, false);
1552
1553	mutex_destroy(&state->mutex);
1554}
1555
1556#ifdef CONFIG_PM_SLEEP
1557static int adv7180_suspend(struct device *dev)
1558{
1559	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1560	struct adv7180_state *state = to_state(sd);
1561
1562	guard(mutex)(&state->mutex);
1563
1564	return adv7180_set_power(state, false);
1565}
1566
1567static int adv7180_resume(struct device *dev)
1568{
1569	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1570	struct adv7180_state *state = to_state(sd);
1571	int ret;
1572
1573	guard(mutex)(&state->mutex);
1574
1575	ret = adv7180_reset_device(state);
1576	if (ret < 0)
1577		return ret;
1578
1579	/* If we were streaming when suspending, start decoder. */
1580	if (state->streaming) {
1581		ret = adv7180_set_power(state, true);
1582		if (ret)
1583			return ret;
1584	}
1585
1586	return 0;
1587}
1588
1589static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1590#define ADV7180_PM_OPS (&adv7180_pm_ops)
1591
1592#else
1593#define ADV7180_PM_OPS NULL
1594#endif
1595
1596static const struct i2c_device_id adv7180_id[] = {
1597	{ "adv7180", (kernel_ulong_t)&adv7180_info },
1598	{ "adv7180cp", (kernel_ulong_t)&adv7180_info },
1599	{ "adv7180st", (kernel_ulong_t)&adv7180_info },
1600	{ "adv7182", (kernel_ulong_t)&adv7182_info },
1601	{ "adv7280", (kernel_ulong_t)&adv7280_info },
1602	{ "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1603	{ "adv7281", (kernel_ulong_t)&adv7281_info },
1604	{ "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1605	{ "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1606	{ "adv7282", (kernel_ulong_t)&adv7282_info },
1607	{ "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1608	{}
1609};
1610MODULE_DEVICE_TABLE(i2c, adv7180_id);
1611
1612static const struct of_device_id adv7180_of_id[] = {
1613	{ .compatible = "adi,adv7180", &adv7180_info },
1614	{ .compatible = "adi,adv7180cp", &adv7180_info },
1615	{ .compatible = "adi,adv7180st", &adv7180_info },
1616	{ .compatible = "adi,adv7182", &adv7182_info },
1617	{ .compatible = "adi,adv7280", &adv7280_info },
1618	{ .compatible = "adi,adv7280-m", &adv7280_m_info },
1619	{ .compatible = "adi,adv7281", &adv7281_info },
1620	{ .compatible = "adi,adv7281-m", &adv7281_m_info },
1621	{ .compatible = "adi,adv7281-ma", &adv7281_ma_info },
1622	{ .compatible = "adi,adv7282", &adv7282_info },
1623	{ .compatible = "adi,adv7282-m", &adv7282_m_info },
1624	{}
1625};
1626MODULE_DEVICE_TABLE(of, adv7180_of_id);
1627
1628static struct i2c_driver adv7180_driver = {
1629	.driver = {
1630		   .name = KBUILD_MODNAME,
1631		   .pm = ADV7180_PM_OPS,
1632		   .of_match_table = adv7180_of_id,
1633		   },
1634	.probe = adv7180_probe,
1635	.remove = adv7180_remove,
1636	.id_table = adv7180_id,
1637};
1638
1639module_i2c_driver(adv7180_driver);
1640
1641MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1642MODULE_AUTHOR("Mocean Laboratories");
1643MODULE_LICENSE("GPL v2");