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dib8000.c
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linux-6.19.14/drivers/media/dvb-frontends/dib8000.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T). 4 * 5 * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/) 6 */ 7 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10#include <linux/kernel.h> 11#include <linux/slab.h> 12#include <linux/i2c.h> 13#include <linux/mutex.h> 14#include <asm/div64.h> 15 16#include <linux/int_log.h> 17 18#include <media/dvb_frontend.h> 19 20#include "dib8000.h" 21 22#define LAYER_ALL -1 23#define LAYER_A 1 24#define LAYER_B 2 25#define LAYER_C 3 26 27#define MAX_NUMBER_OF_FRONTENDS 6 28/* #define DIB8000_AGC_FREEZE */ 29 30static int debug; 31module_param(debug, int, 0644); 32MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 33 34#define dprintk(fmt, arg...) do { \ 35 if (debug) \ 36 printk(KERN_DEBUG pr_fmt("%s: " fmt), \ 37 __func__, ##arg); \ 38} while (0) 39 40struct i2c_device { 41 struct i2c_adapter *adap; 42 u8 addr; 43 u8 *i2c_write_buffer; 44 u8 *i2c_read_buffer; 45 struct mutex *i2c_buffer_lock; 46}; 47 48enum param_loop_step { 49 LOOP_TUNE_1, 50 LOOP_TUNE_2 51}; 52 53enum dib8000_autosearch_step { 54 AS_START = 0, 55 AS_SEARCHING_FFT, 56 AS_SEARCHING_GUARD, 57 AS_DONE = 100, 58}; 59 60enum timeout_mode { 61 SYMBOL_DEPENDENT_OFF = 0, 62 SYMBOL_DEPENDENT_ON, 63}; 64 65struct dib8000_state { 66 struct dib8000_config cfg; 67 68 struct i2c_device i2c; 69 70 struct dibx000_i2c_master i2c_master; 71 72 u16 wbd_ref; 73 74 u8 current_band; 75 u32 current_bandwidth; 76 struct dibx000_agc_config *current_agc; 77 u32 timf; 78 u32 timf_default; 79 80 u8 div_force_off:1; 81 u8 div_state:1; 82 u16 div_sync_wait; 83 84 u8 agc_state; 85 u8 differential_constellation; 86 u8 diversity_onoff; 87 88 s16 ber_monitored_layer; 89 u16 gpio_dir; 90 u16 gpio_val; 91 92 u16 revision; 93 u8 isdbt_cfg_loaded; 94 enum frontend_tune_state tune_state; 95 s32 status; 96 97 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS]; 98 99 /* for the I2C transfer */ 100 struct i2c_msg msg[2]; 101 u8 i2c_write_buffer[4]; 102 u8 i2c_read_buffer[2]; 103 struct mutex i2c_buffer_lock; 104 u8 input_mode_mpeg; 105 106 u16 tuner_enable; 107 struct i2c_adapter dib8096p_tuner_adap; 108 u16 current_demod_bw; 109 110 u16 seg_mask; 111 u16 seg_diff_mask; 112 u16 mode; 113 u8 layer_b_nb_seg; 114 u8 layer_c_nb_seg; 115 116 u8 channel_parameters_set; 117 u16 autosearch_state; 118 u16 found_nfft; 119 u16 found_guard; 120 u8 subchannel; 121 u8 symbol_duration; 122 unsigned long timeout; 123 u8 longest_intlv_layer; 124 u16 output_mode; 125 126 /* for DVBv5 stats */ 127 s64 init_ucb; 128 unsigned long per_jiffies_stats; 129 unsigned long ber_jiffies_stats; 130 unsigned long ber_jiffies_stats_layer[3]; 131 132#ifdef DIB8000_AGC_FREEZE 133 u16 agc1_max; 134 u16 agc1_min; 135 u16 agc2_max; 136 u16 agc2_min; 137#endif 138}; 139 140enum dib8000_power_mode { 141 DIB8000_POWER_ALL = 0, 142 DIB8000_POWER_INTERFACE_ONLY, 143}; 144 145static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg) 146{ 147 u16 ret; 148 struct i2c_msg msg[2] = { 149 {.addr = i2c->addr >> 1, .flags = 0, .len = 2}, 150 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2}, 151 }; 152 153 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { 154 dprintk("could not acquire lock\n"); 155 return 0; 156 } 157 158 msg[0].buf = i2c->i2c_write_buffer; 159 msg[0].buf[0] = reg >> 8; 160 msg[0].buf[1] = reg & 0xff; 161 msg[1].buf = i2c->i2c_read_buffer; 162 163 if (i2c_transfer(i2c->adap, msg, 2) != 2) 164 dprintk("i2c read error on %d\n", reg); 165 166 ret = (msg[1].buf[0] << 8) | msg[1].buf[1]; 167 mutex_unlock(i2c->i2c_buffer_lock); 168 return ret; 169} 170 171static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg) 172{ 173 u16 ret; 174 175 state->i2c_write_buffer[0] = reg >> 8; 176 state->i2c_write_buffer[1] = reg & 0xff; 177 178 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); 179 state->msg[0].addr = state->i2c.addr >> 1; 180 state->msg[0].flags = 0; 181 state->msg[0].buf = state->i2c_write_buffer; 182 state->msg[0].len = 2; 183 state->msg[1].addr = state->i2c.addr >> 1; 184 state->msg[1].flags = I2C_M_RD; 185 state->msg[1].buf = state->i2c_read_buffer; 186 state->msg[1].len = 2; 187 188 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) 189 dprintk("i2c read error on %d\n", reg); 190 191 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; 192 193 return ret; 194} 195 196static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) 197{ 198 u16 ret; 199 200 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { 201 dprintk("could not acquire lock\n"); 202 return 0; 203 } 204 205 ret = __dib8000_read_word(state, reg); 206 207 mutex_unlock(&state->i2c_buffer_lock); 208 209 return ret; 210} 211 212static u32 dib8000_read32(struct dib8000_state *state, u16 reg) 213{ 214 u16 rw[2]; 215 216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { 217 dprintk("could not acquire lock\n"); 218 return 0; 219 } 220 221 rw[0] = __dib8000_read_word(state, reg + 0); 222 rw[1] = __dib8000_read_word(state, reg + 1); 223 224 mutex_unlock(&state->i2c_buffer_lock); 225 226 return ((rw[0] << 16) | (rw[1])); 227} 228 229static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) 230{ 231 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4}; 232 int ret = 0; 233 234 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { 235 dprintk("could not acquire lock\n"); 236 return -EINVAL; 237 } 238 239 msg.buf = i2c->i2c_write_buffer; 240 msg.buf[0] = (reg >> 8) & 0xff; 241 msg.buf[1] = reg & 0xff; 242 msg.buf[2] = (val >> 8) & 0xff; 243 msg.buf[3] = val & 0xff; 244 245 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 246 mutex_unlock(i2c->i2c_buffer_lock); 247 248 return ret; 249} 250 251static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) 252{ 253 int ret; 254 255 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { 256 dprintk("could not acquire lock\n"); 257 return -EINVAL; 258 } 259 260 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; 261 state->i2c_write_buffer[1] = reg & 0xff; 262 state->i2c_write_buffer[2] = (val >> 8) & 0xff; 263 state->i2c_write_buffer[3] = val & 0xff; 264 265 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); 266 state->msg[0].addr = state->i2c.addr >> 1; 267 state->msg[0].flags = 0; 268 state->msg[0].buf = state->i2c_write_buffer; 269 state->msg[0].len = 4; 270 271 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? 272 -EREMOTEIO : 0); 273 mutex_unlock(&state->i2c_buffer_lock); 274 275 return ret; 276} 277 278static const s16 coeff_2k_sb_1seg_dqpsk[8] = { 279 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c, 280 (920 << 5) | 0x09 281}; 282 283static const s16 coeff_2k_sb_1seg[8] = { 284 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f 285}; 286 287static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = { 288 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11, 289 (-931 << 5) | 0x0f 290}; 291 292static const s16 coeff_2k_sb_3seg_0dqpsk[8] = { 293 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e, 294 (982 << 5) | 0x0c 295}; 296 297static const s16 coeff_2k_sb_3seg_1dqpsk[8] = { 298 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12, 299 (-720 << 5) | 0x0d 300}; 301 302static const s16 coeff_2k_sb_3seg[8] = { 303 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e, 304 (-610 << 5) | 0x0a 305}; 306 307static const s16 coeff_4k_sb_1seg_dqpsk[8] = { 308 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f, 309 (-922 << 5) | 0x0d 310}; 311 312static const s16 coeff_4k_sb_1seg[8] = { 313 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d, 314 (-655 << 5) | 0x0a 315}; 316 317static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = { 318 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14, 319 (-958 << 5) | 0x13 320}; 321 322static const s16 coeff_4k_sb_3seg_0dqpsk[8] = { 323 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12, 324 (-568 << 5) | 0x0f 325}; 326 327static const s16 coeff_4k_sb_3seg_1dqpsk[8] = { 328 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14, 329 (-848 << 5) | 0x13 330}; 331 332static const s16 coeff_4k_sb_3seg[8] = { 333 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12, 334 (-869 << 5) | 0x13 335}; 336 337static const s16 coeff_8k_sb_1seg_dqpsk[8] = { 338 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13, 339 (-598 << 5) | 0x10 340}; 341 342static const s16 coeff_8k_sb_1seg[8] = { 343 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f, 344 (585 << 5) | 0x0f 345}; 346 347static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = { 348 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18, 349 (0 << 5) | 0x14 350}; 351 352static const s16 coeff_8k_sb_3seg_0dqpsk[8] = { 353 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15, 354 (-877 << 5) | 0x15 355}; 356 357static const s16 coeff_8k_sb_3seg_1dqpsk[8] = { 358 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18, 359 (-921 << 5) | 0x14 360}; 361 362static const s16 coeff_8k_sb_3seg[8] = { 363 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15, 364 (690 << 5) | 0x14 365}; 366 367static const s16 ana_fe_coeff_3seg[24] = { 368 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017 369}; 370 371static const s16 ana_fe_coeff_1seg[24] = { 372 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003 373}; 374 375static const s16 ana_fe_coeff_13seg[24] = { 376 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1 377}; 378 379static u16 fft_to_mode(struct dib8000_state *state) 380{ 381 u16 mode; 382 switch (state->fe[0]->dtv_property_cache.transmission_mode) { 383 case TRANSMISSION_MODE_2K: 384 mode = 1; 385 break; 386 case TRANSMISSION_MODE_4K: 387 mode = 2; 388 break; 389 default: 390 case TRANSMISSION_MODE_AUTO: 391 case TRANSMISSION_MODE_8K: 392 mode = 3; 393 break; 394 } 395 return mode; 396} 397 398static void dib8000_set_acquisition_mode(struct dib8000_state *state) 399{ 400 u16 nud = dib8000_read_word(state, 298); 401 nud |= (1 << 3) | (1 << 0); 402 dprintk("acquisition mode activated\n"); 403 dib8000_write_word(state, 298, nud); 404} 405static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode) 406{ 407 struct dib8000_state *state = fe->demodulator_priv; 408 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ 409 410 state->output_mode = mode; 411 outreg = 0; 412 fifo_threshold = 1792; 413 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); 414 415 dprintk("-I- Setting output mode for demod %p to %d\n", 416 &state->fe[0], mode); 417 418 switch (mode) { 419 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 420 outreg = (1 << 10); /* 0x0400 */ 421 break; 422 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock 423 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ 424 break; 425 case OUTMODE_MPEG2_SERIAL: // STBs with serial input 426 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ 427 break; 428 case OUTMODE_DIVERSITY: 429 if (state->cfg.hostbus_diversity) { 430 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ 431 sram &= 0xfdff; 432 } else 433 sram |= 0x0c00; 434 break; 435 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding 436 smo_mode |= (3 << 1); 437 fifo_threshold = 512; 438 outreg = (1 << 10) | (5 << 6); 439 break; 440 case OUTMODE_HIGH_Z: // disable 441 outreg = 0; 442 break; 443 444 case OUTMODE_ANALOG_ADC: 445 outreg = (1 << 10) | (3 << 6); 446 dib8000_set_acquisition_mode(state); 447 break; 448 449 default: 450 dprintk("Unhandled output_mode passed to be set for demod %p\n", 451 &state->fe[0]); 452 return -EINVAL; 453 } 454 455 if (state->cfg.output_mpeg2_in_188_bytes) 456 smo_mode |= (1 << 5); 457 458 dib8000_write_word(state, 299, smo_mode); 459 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ 460 dib8000_write_word(state, 1286, outreg); 461 dib8000_write_word(state, 1291, sram); 462 463 return 0; 464} 465 466static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff) 467{ 468 struct dib8000_state *state = fe->demodulator_priv; 469 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0; 470 471 dprintk("set diversity input to %i\n", onoff); 472 if (!state->differential_constellation) { 473 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 474 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 475 } else { 476 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 477 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 478 } 479 state->diversity_onoff = onoff; 480 481 switch (onoff) { 482 case 0: /* only use the internal way - not the diversity input */ 483 dib8000_write_word(state, 270, 1); 484 dib8000_write_word(state, 271, 0); 485 break; 486 case 1: /* both ways */ 487 dib8000_write_word(state, 270, 6); 488 dib8000_write_word(state, 271, 6); 489 break; 490 case 2: /* only the diversity input */ 491 dib8000_write_word(state, 270, 0); 492 dib8000_write_word(state, 271, 1); 493 break; 494 } 495 496 if (state->revision == 0x8002) { 497 tmp = dib8000_read_word(state, 903); 498 dib8000_write_word(state, 903, tmp & ~(1 << 3)); 499 msleep(30); 500 dib8000_write_word(state, 903, tmp | (1 << 3)); 501 } 502 return 0; 503} 504 505static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode) 506{ 507 /* by default everything is going to be powered off */ 508 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, 509 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, 510 reg_1280; 511 512 if (state->revision != 0x8090) 513 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; 514 else 515 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; 516 517 /* now, depending on the requested mode, we power on */ 518 switch (mode) { 519 /* power up everything in the demod */ 520 case DIB8000_POWER_ALL: 521 reg_774 = 0x0000; 522 reg_775 = 0x0000; 523 reg_776 = 0x0000; 524 reg_900 &= 0xfffc; 525 if (state->revision != 0x8090) 526 reg_1280 &= 0x00ff; 527 else 528 reg_1280 &= 0x707f; 529 break; 530 case DIB8000_POWER_INTERFACE_ONLY: 531 if (state->revision != 0x8090) 532 reg_1280 &= 0x00ff; 533 else 534 reg_1280 &= 0xfa7b; 535 break; 536 } 537 538 dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x\n", reg_774, reg_775, reg_776, reg_900, reg_1280); 539 dib8000_write_word(state, 774, reg_774); 540 dib8000_write_word(state, 775, reg_775); 541 dib8000_write_word(state, 776, reg_776); 542 dib8000_write_word(state, 900, reg_900); 543 dib8000_write_word(state, 1280, reg_1280); 544} 545 546static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) 547{ 548 int ret = 0; 549 u16 reg, reg_907 = dib8000_read_word(state, 907); 550 u16 reg_908 = dib8000_read_word(state, 908); 551 552 switch (no) { 553 case DIBX000_SLOW_ADC_ON: 554 if (state->revision != 0x8090) { 555 reg_908 |= (1 << 1) | (1 << 0); 556 ret |= dib8000_write_word(state, 908, reg_908); 557 reg_908 &= ~(1 << 1); 558 } else { 559 reg = dib8000_read_word(state, 1925); 560 /* en_slowAdc = 1 & reset_sladc = 1 */ 561 dib8000_write_word(state, 1925, reg | 562 (1<<4) | (1<<2)); 563 564 /* read access to make it works... strange ... */ 565 reg = dib8000_read_word(state, 1925); 566 msleep(20); 567 /* en_slowAdc = 1 & reset_sladc = 0 */ 568 dib8000_write_word(state, 1925, reg & ~(1<<4)); 569 570 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) 571 | (0x3 << 12)); 572 /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; 573 (Vin2 = Vcm) */ 574 dib8000_write_word(state, 921, reg | (1 << 14) 575 | (3 << 12)); 576 } 577 break; 578 579 case DIBX000_SLOW_ADC_OFF: 580 if (state->revision == 0x8090) { 581 reg = dib8000_read_word(state, 1925); 582 /* reset_sladc = 1 en_slowAdc = 0 */ 583 dib8000_write_word(state, 1925, 584 (reg & ~(1<<2)) | (1<<4)); 585 } 586 reg_908 |= (1 << 1) | (1 << 0); 587 break; 588 589 case DIBX000_ADC_ON: 590 reg_907 &= 0x0fff; 591 reg_908 &= 0x0003; 592 break; 593 594 case DIBX000_ADC_OFF: // leave the VBG voltage on 595 reg_907 = (1 << 13) | (1 << 12); 596 reg_908 = (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1); 597 break; 598 599 case DIBX000_VBG_ENABLE: 600 reg_907 &= ~(1 << 15); 601 break; 602 603 case DIBX000_VBG_DISABLE: 604 reg_907 |= (1 << 15); 605 break; 606 607 default: 608 break; 609 } 610 611 ret |= dib8000_write_word(state, 907, reg_907); 612 ret |= dib8000_write_word(state, 908, reg_908); 613 614 return ret; 615} 616 617static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw) 618{ 619 struct dib8000_state *state = fe->demodulator_priv; 620 u32 timf; 621 622 if (bw == 0) 623 bw = 6000; 624 625 if (state->timf == 0) { 626 dprintk("using default timf\n"); 627 timf = state->timf_default; 628 } else { 629 dprintk("using updated timf\n"); 630 timf = state->timf; 631 } 632 633 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); 634 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); 635 636 return 0; 637} 638 639static int dib8000_sad_calib(struct dib8000_state *state) 640{ 641 u8 sad_sel = 3; 642 643 if (state->revision == 0x8090) { 644 dib8000_write_word(state, 922, (sad_sel << 2)); 645 dib8000_write_word(state, 923, 2048); 646 647 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); 648 dib8000_write_word(state, 922, (sad_sel << 2)); 649 } else { 650 /* internal */ 651 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); 652 dib8000_write_word(state, 924, 776); 653 654 /* do the calibration */ 655 dib8000_write_word(state, 923, (1 << 0)); 656 dib8000_write_word(state, 923, (0 << 0)); 657 } 658 659 msleep(1); 660 return 0; 661} 662 663static int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value) 664{ 665 struct dib8000_state *state = fe->demodulator_priv; 666 if (value > 4095) 667 value = 4095; 668 state->wbd_ref = value; 669 return dib8000_write_word(state, 106, value); 670} 671 672static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw) 673{ 674 dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25); 675 if (state->revision != 0x8090) { 676 dib8000_write_word(state, 23, 677 (u16) (((bw->internal * 1000) >> 16) & 0xffff)); 678 dib8000_write_word(state, 24, 679 (u16) ((bw->internal * 1000) & 0xffff)); 680 } else { 681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); 682 dib8000_write_word(state, 24, 683 (u16) ((bw->internal / 2 * 1000) & 0xffff)); 684 } 685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); 686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); 687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); 688 689 if (state->revision != 0x8090) 690 dib8000_write_word(state, 922, bw->sad_cfg); 691} 692 693static void dib8000_reset_pll(struct dib8000_state *state) 694{ 695 const struct dibx000_bandwidth_config *pll = state->cfg.pll; 696 u16 clk_cfg1, reg; 697 698 if (state->revision != 0x8090) { 699 dib8000_write_word(state, 901, 700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); 701 702 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | 703 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | 704 (1 << 3) | (pll->pll_range << 1) | 705 (pll->pll_reset << 0); 706 707 dib8000_write_word(state, 902, clk_cfg1); 708 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); 709 dib8000_write_word(state, 902, clk_cfg1); 710 711 dprintk("clk_cfg1: 0x%04x\n", clk_cfg1); 712 713 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ 714 if (state->cfg.pll->ADClkSrc == 0) 715 dib8000_write_word(state, 904, 716 (0 << 15) | (0 << 12) | (0 << 10) | 717 (pll->modulo << 8) | 718 (pll->ADClkSrc << 7) | (0 << 1)); 719 else if (state->cfg.refclksel != 0) 720 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | 721 ((state->cfg.refclksel & 0x3) << 10) | 722 (pll->modulo << 8) | 723 (pll->ADClkSrc << 7) | (0 << 1)); 724 else 725 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | 726 (3 << 10) | (pll->modulo << 8) | 727 (pll->ADClkSrc << 7) | (0 << 1)); 728 } else { 729 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | 730 (pll->pll_range<<12) | (pll->pll_ratio<<6) | 731 (pll->pll_prediv)); 732 733 reg = dib8000_read_word(state, 1857); 734 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); 735 736 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ 737 dib8000_write_word(state, 1858, reg | 1); 738 739 dib8000_write_word(state, 904, (pll->modulo << 8)); 740 } 741 742 dib8000_reset_pll_common(state, pll); 743} 744 745static int dib8000_update_pll(struct dvb_frontend *fe, 746 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio) 747{ 748 struct dib8000_state *state = fe->demodulator_priv; 749 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856); 750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; 751 u32 internal, xtal; 752 753 /* get back old values */ 754 prediv = reg_1856 & 0x3f; 755 loopdiv = (reg_1856 >> 6) & 0x3f; 756 757 if ((pll == NULL) || (pll->pll_prediv == prediv && 758 pll->pll_ratio == loopdiv)) 759 return -EINVAL; 760 761 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); 762 if (state->revision == 0x8090) { 763 reg_1856 &= 0xf000; 764 reg_1857 = dib8000_read_word(state, 1857); 765 /* disable PLL */ 766 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); 767 768 dib8000_write_word(state, 1856, reg_1856 | 769 ((pll->pll_ratio & 0x3f) << 6) | 770 (pll->pll_prediv & 0x3f)); 771 772 /* write new system clk into P_sec_len */ 773 internal = dib8000_read32(state, 23) / 1000; 774 dprintk("Old Internal = %d\n", internal); 775 xtal = 2 * (internal / loopdiv) * prediv; 776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; 777 dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d\n", xtal, internal/1000, internal/2000, internal/8000); 778 dprintk("New Internal = %d\n", internal); 779 780 dib8000_write_word(state, 23, 781 (u16) (((internal / 2) >> 16) & 0xffff)); 782 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); 783 /* enable PLL */ 784 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); 785 786 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) 787 dprintk("Waiting for PLL to lock\n"); 788 789 /* verify */ 790 reg_1856 = dib8000_read_word(state, 1856); 791 dprintk("PLL Updated with prediv = %d and loopdiv = %d\n", 792 reg_1856&0x3f, (reg_1856>>6)&0x3f); 793 } else { 794 if (bw != state->current_demod_bw) { 795 /** Bandwidth change => force PLL update **/ 796 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); 797 798 if (state->cfg.pll->pll_prediv != oldprediv) { 799 /** Full PLL change only if prediv is changed **/ 800 801 /** full update => bypass and reconfigure **/ 802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); 803 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ 804 dib8000_reset_pll(state); 805 dib8000_write_word(state, 898, 0x0004); /* sad */ 806 } else 807 ratio = state->cfg.pll->pll_ratio; 808 809 state->current_demod_bw = bw; 810 } 811 812 if (ratio != 0) { 813 /** ratio update => only change ratio **/ 814 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio); 815 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */ 816 } 817 } 818 819 return 0; 820} 821 822static int dib8000_reset_gpio(struct dib8000_state *st) 823{ 824 /* reset the GPIOs */ 825 dib8000_write_word(st, 1029, st->cfg.gpio_dir); 826 dib8000_write_word(st, 1030, st->cfg.gpio_val); 827 828 /* TODO 782 is P_gpio_od */ 829 830 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos); 831 832 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div); 833 return 0; 834} 835 836static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val) 837{ 838 st->cfg.gpio_dir = dib8000_read_word(st, 1029); 839 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */ 840 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */ 841 dib8000_write_word(st, 1029, st->cfg.gpio_dir); 842 843 st->cfg.gpio_val = dib8000_read_word(st, 1030); 844 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */ 845 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */ 846 dib8000_write_word(st, 1030, st->cfg.gpio_val); 847 848 dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val); 849 850 return 0; 851} 852 853static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) 854{ 855 struct dib8000_state *state = fe->demodulator_priv; 856 return dib8000_cfg_gpio(state, num, dir, val); 857} 858 859static const u16 dib8000_defaults[] = { 860 /* auto search configuration - lock0 by default waiting 861 * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */ 862 3, 7, 863 0x0004, 864 0x0400, 865 0x0814, 866 867 12, 11, 868 0x001b, 869 0x7740, 870 0x005b, 871 0x8d80, 872 0x01c9, 873 0xc380, 874 0x0000, 875 0x0080, 876 0x0000, 877 0x0090, 878 0x0001, 879 0xd4c0, 880 881 /*1, 32, 882 0x6680 // P_corm_thres Lock algorithms configuration */ 883 884 11, 80, /* set ADC level to -16 */ 885 (1 << 13) - 825 - 117, 886 (1 << 13) - 837 - 117, 887 (1 << 13) - 811 - 117, 888 (1 << 13) - 766 - 117, 889 (1 << 13) - 737 - 117, 890 (1 << 13) - 693 - 117, 891 (1 << 13) - 648 - 117, 892 (1 << 13) - 619 - 117, 893 (1 << 13) - 575 - 117, 894 (1 << 13) - 531 - 117, 895 (1 << 13) - 501 - 117, 896 897 4, 108, 898 0, 899 0, 900 0, 901 0, 902 903 1, 175, 904 0x0410, 905 1, 179, 906 8192, // P_fft_nb_to_cut 907 908 6, 181, 909 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800 910 0x2800, 911 0x2800, 912 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800 913 0x2800, 914 0x2800, 915 916 2, 193, 917 0x0666, // P_pha3_thres 918 0x0000, // P_cti_use_cpe, P_cti_use_prog 919 920 2, 205, 921 0x200f, // P_cspu_regul, P_cspu_win_cut 922 0x000f, // P_des_shift_work 923 924 5, 215, 925 0x023d, // P_adp_regul_cnt 926 0x00a4, // P_adp_noise_cnt 927 0x00a4, // P_adp_regul_ext 928 0x7ff0, // P_adp_noise_ext 929 0x3ccc, // P_adp_fil 930 931 1, 230, 932 0x0000, // P_2d_byp_ti_num 933 934 1, 263, 935 0x800, //P_equal_thres_wgn 936 937 1, 268, 938 (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode 939 940 1, 270, 941 0x0001, // P_div_lock0_wait 942 1, 285, 943 0x0020, //p_fec_ 944 1, 299, 945 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */ 946 947 1, 338, 948 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1 949 (1 << 10) | 950 (0 << 9) | /* P_ctrl_pre_freq_inh=0 */ 951 (3 << 5) | /* P_ctrl_pre_freq_step=3 */ 952 (1 << 0), /* P_pre_freq_win_len=1 */ 953 954 0, 955}; 956 957static u16 dib8000_identify(struct i2c_device *client) 958{ 959 u16 value; 960 961 //because of glitches sometimes 962 value = dib8000_i2c_read16(client, 896); 963 964 if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) { 965 dprintk("wrong Vendor ID (read=0x%x)\n", value); 966 return 0; 967 } 968 969 value = dib8000_i2c_read16(client, 897); 970 if (value != 0x8000 && value != 0x8001 && 971 value != 0x8002 && value != 0x8090) { 972 dprintk("wrong Device ID (%x)\n", value); 973 return 0; 974 } 975 976 switch (value) { 977 case 0x8000: 978 dprintk("found DiB8000A\n"); 979 break; 980 case 0x8001: 981 dprintk("found DiB8000B\n"); 982 break; 983 case 0x8002: 984 dprintk("found DiB8000C\n"); 985 break; 986 case 0x8090: 987 dprintk("found DiB8096P\n"); 988 break; 989 } 990 return value; 991} 992 993static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 *unc); 994 995static void dib8000_reset_stats(struct dvb_frontend *fe) 996{ 997 struct dib8000_state *state = fe->demodulator_priv; 998 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 999 u32 ucb; 1000 1001 memset(&c->strength, 0, sizeof(c->strength)); 1002 memset(&c->cnr, 0, sizeof(c->cnr)); 1003 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 1004 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 1005 memset(&c->block_error, 0, sizeof(c->block_error)); 1006 1007 c->strength.len = 1; 1008 c->cnr.len = 1; 1009 c->block_error.len = 1; 1010 c->block_count.len = 1; 1011 c->post_bit_error.len = 1; 1012 c->post_bit_count.len = 1; 1013 1014 c->strength.stat[0].scale = FE_SCALE_DECIBEL; 1015 c->strength.stat[0].uvalue = 0; 1016 1017 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1018 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1019 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1020 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1021 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1022 1023 dib8000_read_unc_blocks(fe, &ucb); 1024 1025 state->init_ucb = -ucb; 1026 state->ber_jiffies_stats = 0; 1027 state->per_jiffies_stats = 0; 1028 memset(&state->ber_jiffies_stats_layer, 0, 1029 sizeof(state->ber_jiffies_stats_layer)); 1030} 1031 1032static int dib8000_reset(struct dvb_frontend *fe) 1033{ 1034 struct dib8000_state *state = fe->demodulator_priv; 1035 1036 if ((state->revision = dib8000_identify(&state->i2c)) == 0) 1037 return -EINVAL; 1038 1039 /* sram lead in, rdy */ 1040 if (state->revision != 0x8090) 1041 dib8000_write_word(state, 1287, 0x0003); 1042 1043 if (state->revision == 0x8000) 1044 dprintk("error : dib8000 MA not supported\n"); 1045 1046 dibx000_reset_i2c_master(&state->i2c_master); 1047 1048 dib8000_set_power_mode(state, DIB8000_POWER_ALL); 1049 1050 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */ 1051 dib8000_set_adc_state(state, DIBX000_ADC_OFF); 1052 1053 /* restart all parts */ 1054 dib8000_write_word(state, 770, 0xffff); 1055 dib8000_write_word(state, 771, 0xffff); 1056 dib8000_write_word(state, 772, 0xfffc); 1057 dib8000_write_word(state, 898, 0x000c); /* restart sad */ 1058 if (state->revision == 0x8090) 1059 dib8000_write_word(state, 1280, 0x0045); 1060 else 1061 dib8000_write_word(state, 1280, 0x004d); 1062 dib8000_write_word(state, 1281, 0x000c); 1063 1064 dib8000_write_word(state, 770, 0x0000); 1065 dib8000_write_word(state, 771, 0x0000); 1066 dib8000_write_word(state, 772, 0x0000); 1067 dib8000_write_word(state, 898, 0x0004); // sad 1068 dib8000_write_word(state, 1280, 0x0000); 1069 dib8000_write_word(state, 1281, 0x0000); 1070 1071 /* drives */ 1072 if (state->revision != 0x8090) { 1073 if (state->cfg.drives) 1074 dib8000_write_word(state, 906, state->cfg.drives); 1075 else { 1076 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.\n"); 1077 /* min drive SDRAM - not optimal - adjust */ 1078 dib8000_write_word(state, 906, 0x2d98); 1079 } 1080 } 1081 1082 dib8000_reset_pll(state); 1083 if (state->revision != 0x8090) 1084 dib8000_write_word(state, 898, 0x0004); 1085 1086 if (dib8000_reset_gpio(state) != 0) 1087 dprintk("GPIO reset was not successful.\n"); 1088 1089 if ((state->revision != 0x8090) && 1090 (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0)) 1091 dprintk("OUTPUT_MODE could not be reset.\n"); 1092 1093 state->current_agc = NULL; 1094 1095 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ... 1096 /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */ 1097 if (state->cfg.pll->ifreq == 0) 1098 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ 1099 else 1100 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ 1101 1102 { 1103 u16 l = 0, r; 1104 const u16 *n; 1105 n = dib8000_defaults; 1106 l = *n++; 1107 while (l) { 1108 r = *n++; 1109 do { 1110 dib8000_write_word(state, r, *n++); 1111 r++; 1112 } while (--l); 1113 l = *n++; 1114 } 1115 } 1116 1117 state->isdbt_cfg_loaded = 0; 1118 1119 //div_cfg override for special configs 1120 if ((state->revision != 8090) && (state->cfg.div_cfg != 0)) 1121 dib8000_write_word(state, 903, state->cfg.div_cfg); 1122 1123 /* unforce divstr regardless whether i2c enumeration was done or not */ 1124 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); 1125 1126 dib8000_set_bandwidth(fe, 6000); 1127 1128 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); 1129 dib8000_sad_calib(state); 1130 if (state->revision != 0x8090) 1131 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 1132 1133 /* ber_rs_len = 3 */ 1134 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); 1135 1136 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); 1137 1138 dib8000_reset_stats(fe); 1139 1140 return 0; 1141} 1142 1143static void dib8000_restart_agc(struct dib8000_state *state) 1144{ 1145 // P_restart_iqc & P_restart_agc 1146 dib8000_write_word(state, 770, 0x0a00); 1147 dib8000_write_word(state, 770, 0x0000); 1148} 1149 1150static int dib8000_update_lna(struct dib8000_state *state) 1151{ 1152 u16 dyn_gain; 1153 1154 if (state->cfg.update_lna) { 1155 // read dyn_gain here (because it is demod-dependent and not tuner) 1156 dyn_gain = dib8000_read_word(state, 390); 1157 1158 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { 1159 dib8000_restart_agc(state); 1160 return 1; 1161 } 1162 } 1163 return 0; 1164} 1165 1166static int dib8000_set_agc_config(struct dib8000_state *state, u8 band) 1167{ 1168 struct dibx000_agc_config *agc = NULL; 1169 int i; 1170 u16 reg; 1171 1172 if (state->current_band == band && state->current_agc != NULL) 1173 return 0; 1174 state->current_band = band; 1175 1176 for (i = 0; i < state->cfg.agc_config_count; i++) 1177 if (state->cfg.agc[i].band_caps & band) { 1178 agc = &state->cfg.agc[i]; 1179 break; 1180 } 1181 1182 if (agc == NULL) { 1183 dprintk("no valid AGC configuration found for band 0x%02x\n", band); 1184 return -EINVAL; 1185 } 1186 1187 state->current_agc = agc; 1188 1189 /* AGC */ 1190 dib8000_write_word(state, 76, agc->setup); 1191 dib8000_write_word(state, 77, agc->inv_gain); 1192 dib8000_write_word(state, 78, agc->time_stabiliz); 1193 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); 1194 1195 // Demod AGC loop configuration 1196 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); 1197 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); 1198 1199 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n", 1200 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); 1201 1202 /* AGC continued */ 1203 if (state->wbd_ref != 0) 1204 dib8000_write_word(state, 106, state->wbd_ref); 1205 else // use default 1206 dib8000_write_word(state, 106, agc->wbd_ref); 1207 1208 if (state->revision == 0x8090) { 1209 reg = dib8000_read_word(state, 922) & (0x3 << 2); 1210 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); 1211 } 1212 1213 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); 1214 dib8000_write_word(state, 108, agc->agc1_max); 1215 dib8000_write_word(state, 109, agc->agc1_min); 1216 dib8000_write_word(state, 110, agc->agc2_max); 1217 dib8000_write_word(state, 111, agc->agc2_min); 1218 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); 1219 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); 1220 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); 1221 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 1222 1223 dib8000_write_word(state, 75, agc->agc1_pt3); 1224 if (state->revision != 0x8090) 1225 dib8000_write_word(state, 923, 1226 (dib8000_read_word(state, 923) & 0xffe3) | 1227 (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); 1228 1229 return 0; 1230} 1231 1232static void dib8000_pwm_agc_reset(struct dvb_frontend *fe) 1233{ 1234 struct dib8000_state *state = fe->demodulator_priv; 1235 dib8000_set_adc_state(state, DIBX000_ADC_ON); 1236 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))); 1237} 1238 1239static int dib8000_agc_soft_split(struct dib8000_state *state) 1240{ 1241 u16 agc, split_offset; 1242 1243 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) 1244 return 0; 1245 1246 // n_agc_global 1247 agc = dib8000_read_word(state, 390); 1248 1249 if (agc > state->current_agc->split.min_thres) 1250 split_offset = state->current_agc->split.min; 1251 else if (agc < state->current_agc->split.max_thres) 1252 split_offset = state->current_agc->split.max; 1253 else 1254 split_offset = state->current_agc->split.max * 1255 (agc - state->current_agc->split.min_thres) / 1256 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); 1257 1258 dprintk("AGC split_offset: %d\n", split_offset); 1259 1260 // P_agc_force_split and P_agc_split_offset 1261 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); 1262 return 5000; 1263} 1264 1265static int dib8000_agc_startup(struct dvb_frontend *fe) 1266{ 1267 struct dib8000_state *state = fe->demodulator_priv; 1268 enum frontend_tune_state *tune_state = &state->tune_state; 1269 int ret = 0; 1270 u16 reg; 1271 u32 upd_demod_gain_period = 0x8000; 1272 1273 switch (*tune_state) { 1274 case CT_AGC_START: 1275 // set power-up level: interf+analog+AGC 1276 1277 if (state->revision != 0x8090) 1278 dib8000_set_adc_state(state, DIBX000_ADC_ON); 1279 else { 1280 dib8000_set_power_mode(state, DIB8000_POWER_ALL); 1281 1282 reg = dib8000_read_word(state, 1947)&0xff00; 1283 dib8000_write_word(state, 1946, 1284 upd_demod_gain_period & 0xFFFF); 1285 /* bit 14 = enDemodGain */ 1286 dib8000_write_word(state, 1947, reg | (1<<14) | 1287 ((upd_demod_gain_period >> 16) & 0xFF)); 1288 1289 /* enable adc i & q */ 1290 reg = dib8000_read_word(state, 1920); 1291 dib8000_write_word(state, 1920, (reg | 0x3) & 1292 (~(1 << 7))); 1293 } 1294 1295 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) { 1296 *tune_state = CT_AGC_STOP; 1297 state->status = FE_STATUS_TUNE_FAILED; 1298 break; 1299 } 1300 1301 ret = 70; 1302 *tune_state = CT_AGC_STEP_0; 1303 break; 1304 1305 case CT_AGC_STEP_0: 1306 //AGC initialization 1307 if (state->cfg.agc_control) 1308 state->cfg.agc_control(fe, 1); 1309 1310 dib8000_restart_agc(state); 1311 1312 // wait AGC rough lock time 1313 ret = 50; 1314 *tune_state = CT_AGC_STEP_1; 1315 break; 1316 1317 case CT_AGC_STEP_1: 1318 // wait AGC accurate lock time 1319 ret = 70; 1320 1321 if (dib8000_update_lna(state)) 1322 // wait only AGC rough lock time 1323 ret = 50; 1324 else 1325 *tune_state = CT_AGC_STEP_2; 1326 break; 1327 1328 case CT_AGC_STEP_2: 1329 dib8000_agc_soft_split(state); 1330 1331 if (state->cfg.agc_control) 1332 state->cfg.agc_control(fe, 0); 1333 1334 *tune_state = CT_AGC_STOP; 1335 break; 1336 default: 1337 ret = dib8000_agc_soft_split(state); 1338 break; 1339 } 1340 return ret; 1341 1342} 1343 1344static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive) 1345{ 1346 u16 reg; 1347 1348 drive &= 0x7; 1349 1350 /* drive host bus 2, 3, 4 */ 1351 reg = dib8000_read_word(state, 1798) & 1352 ~(0x7 | (0x7 << 6) | (0x7 << 12)); 1353 reg |= (drive<<12) | (drive<<6) | drive; 1354 dib8000_write_word(state, 1798, reg); 1355 1356 /* drive host bus 5,6 */ 1357 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); 1358 reg |= (drive<<8) | (drive<<2); 1359 dib8000_write_word(state, 1799, reg); 1360 1361 /* drive host bus 7, 8, 9 */ 1362 reg = dib8000_read_word(state, 1800) & 1363 ~(0x7 | (0x7 << 6) | (0x7 << 12)); 1364 reg |= (drive<<12) | (drive<<6) | drive; 1365 dib8000_write_word(state, 1800, reg); 1366 1367 /* drive host bus 10, 11 */ 1368 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); 1369 reg |= (drive<<8) | (drive<<2); 1370 dib8000_write_word(state, 1801, reg); 1371 1372 /* drive host bus 12, 13, 14 */ 1373 reg = dib8000_read_word(state, 1802) & 1374 ~(0x7 | (0x7 << 6) | (0x7 << 12)); 1375 reg |= (drive<<12) | (drive<<6) | drive; 1376 dib8000_write_word(state, 1802, reg); 1377} 1378 1379static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout, 1380 u32 insertExtSynchro, u32 syncSize) 1381{ 1382 u32 quantif = 3; 1383 u32 nom = (insertExtSynchro * P_Kin+syncSize); 1384 u32 denom = P_Kout; 1385 u32 syncFreq = ((nom << quantif) / denom); 1386 1387 if ((syncFreq & ((1 << quantif) - 1)) != 0) 1388 syncFreq = (syncFreq >> quantif) + 1; 1389 else 1390 syncFreq = (syncFreq >> quantif); 1391 1392 if (syncFreq != 0) 1393 syncFreq = syncFreq - 1; 1394 1395 return syncFreq; 1396} 1397 1398static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin, 1399 u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, 1400 u32 syncWord, u32 syncSize) 1401{ 1402 dprintk("Configure DibStream Tx\n"); 1403 1404 dib8000_write_word(state, 1615, 1); 1405 dib8000_write_word(state, 1603, P_Kin); 1406 dib8000_write_word(state, 1605, P_Kout); 1407 dib8000_write_word(state, 1606, insertExtSynchro); 1408 dib8000_write_word(state, 1608, synchroMode); 1409 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); 1410 dib8000_write_word(state, 1610, syncWord & 0xffff); 1411 dib8000_write_word(state, 1612, syncSize); 1412 dib8000_write_word(state, 1615, 0); 1413} 1414 1415static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin, 1416 u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, 1417 u32 syncWord, u32 syncSize, u32 dataOutRate) 1418{ 1419 u32 syncFreq; 1420 1421 dprintk("Configure DibStream Rx synchroMode = %d\n", synchroMode); 1422 1423 if ((P_Kin != 0) && (P_Kout != 0)) { 1424 syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout, 1425 insertExtSynchro, syncSize); 1426 dib8000_write_word(state, 1542, syncFreq); 1427 } 1428 1429 dib8000_write_word(state, 1554, 1); 1430 dib8000_write_word(state, 1536, P_Kin); 1431 dib8000_write_word(state, 1537, P_Kout); 1432 dib8000_write_word(state, 1539, synchroMode); 1433 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); 1434 dib8000_write_word(state, 1541, syncWord & 0xffff); 1435 dib8000_write_word(state, 1543, syncSize); 1436 dib8000_write_word(state, 1544, dataOutRate); 1437 dib8000_write_word(state, 1554, 0); 1438} 1439 1440static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff) 1441{ 1442 u16 reg_1287; 1443 1444 reg_1287 = dib8000_read_word(state, 1287); 1445 1446 switch (onoff) { 1447 case 1: 1448 reg_1287 &= ~(1 << 8); 1449 break; 1450 case 0: 1451 reg_1287 |= (1 << 8); 1452 break; 1453 } 1454 1455 dib8000_write_word(state, 1287, reg_1287); 1456} 1457 1458static void dib8096p_configMpegMux(struct dib8000_state *state, 1459 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2) 1460{ 1461 u16 reg_1287; 1462 1463 dprintk("Enable Mpeg mux\n"); 1464 1465 dib8096p_enMpegMux(state, 0); 1466 1467 /* If the input mode is MPEG do not divide the serial clock */ 1468 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) 1469 enSerialClkDiv2 = 0; 1470 1471 reg_1287 = ((pulseWidth & 0x1f) << 3) | 1472 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1); 1473 dib8000_write_word(state, 1287, reg_1287); 1474 1475 dib8096p_enMpegMux(state, 1); 1476} 1477 1478static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode) 1479{ 1480 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); 1481 1482 switch (mode) { 1483 case MPEG_ON_DIBTX: 1484 dprintk("SET MPEG ON DIBSTREAM TX\n"); 1485 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); 1486 reg_1288 |= (1 << 9); break; 1487 case DIV_ON_DIBTX: 1488 dprintk("SET DIV_OUT ON DIBSTREAM TX\n"); 1489 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); 1490 reg_1288 |= (1 << 8); break; 1491 case ADC_ON_DIBTX: 1492 dprintk("SET ADC_OUT ON DIBSTREAM TX\n"); 1493 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); 1494 reg_1288 |= (1 << 7); break; 1495 default: 1496 break; 1497 } 1498 dib8000_write_word(state, 1288, reg_1288); 1499} 1500 1501static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode) 1502{ 1503 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); 1504 1505 switch (mode) { 1506 case DEMOUT_ON_HOSTBUS: 1507 dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n"); 1508 dib8096p_enMpegMux(state, 0); 1509 reg_1288 |= (1 << 6); 1510 break; 1511 case DIBTX_ON_HOSTBUS: 1512 dprintk("SET DIBSTREAM TX ON HOST BUS\n"); 1513 dib8096p_enMpegMux(state, 0); 1514 reg_1288 |= (1 << 5); 1515 break; 1516 case MPEG_ON_HOSTBUS: 1517 dprintk("SET MPEG MUX ON HOST BUS\n"); 1518 reg_1288 |= (1 << 4); 1519 break; 1520 default: 1521 break; 1522 } 1523 dib8000_write_word(state, 1288, reg_1288); 1524} 1525 1526static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff) 1527{ 1528 struct dib8000_state *state = fe->demodulator_priv; 1529 u16 reg_1287; 1530 1531 switch (onoff) { 1532 case 0: /* only use the internal way - not the diversity input */ 1533 dprintk("%s mode OFF : by default Enable Mpeg INPUT\n", 1534 __func__); 1535 /* outputRate = 8 */ 1536 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); 1537 1538 /* Do not divide the serial clock of MPEG MUX in 1539 SERIAL MODE in case input mode MPEG is used */ 1540 reg_1287 = dib8000_read_word(state, 1287); 1541 /* enSerialClkDiv2 == 1 ? */ 1542 if ((reg_1287 & 0x1) == 1) { 1543 /* force enSerialClkDiv2 = 0 */ 1544 reg_1287 &= ~0x1; 1545 dib8000_write_word(state, 1287, reg_1287); 1546 } 1547 state->input_mode_mpeg = 1; 1548 break; 1549 case 1: /* both ways */ 1550 case 2: /* only the diversity input */ 1551 dprintk("%s ON : Enable diversity INPUT\n", __func__); 1552 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); 1553 state->input_mode_mpeg = 0; 1554 break; 1555 } 1556 1557 dib8000_set_diversity_in(state->fe[0], onoff); 1558 return 0; 1559} 1560 1561static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode) 1562{ 1563 struct dib8000_state *state = fe->demodulator_priv; 1564 u16 outreg, smo_mode, fifo_threshold; 1565 u8 prefer_mpeg_mux_use = 1; 1566 int ret = 0; 1567 1568 state->output_mode = mode; 1569 dib8096p_host_bus_drive(state, 1); 1570 1571 fifo_threshold = 1792; 1572 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); 1573 outreg = dib8000_read_word(state, 1286) & 1574 ~((1 << 10) | (0x7 << 6) | (1 << 1)); 1575 1576 switch (mode) { 1577 case OUTMODE_HIGH_Z: 1578 outreg = 0; 1579 break; 1580 1581 case OUTMODE_MPEG2_SERIAL: 1582 if (prefer_mpeg_mux_use) { 1583 dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux\n"); 1584 dib8096p_configMpegMux(state, 3, 1, 1); 1585 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); 1586 } else {/* Use Smooth block */ 1587 dprintk("dib8096P setting output mode TS_SERIAL using Smooth block\n"); 1588 dib8096p_setHostBusMux(state, 1589 DEMOUT_ON_HOSTBUS); 1590 outreg |= (2 << 6) | (0 << 1); 1591 } 1592 break; 1593 1594 case OUTMODE_MPEG2_PAR_GATED_CLK: 1595 if (prefer_mpeg_mux_use) { 1596 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux\n"); 1597 dib8096p_configMpegMux(state, 2, 0, 0); 1598 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); 1599 } else { /* Use Smooth block */ 1600 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block\n"); 1601 dib8096p_setHostBusMux(state, 1602 DEMOUT_ON_HOSTBUS); 1603 outreg |= (0 << 6); 1604 } 1605 break; 1606 1607 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */ 1608 dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block\n"); 1609 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 1610 outreg |= (1 << 6); 1611 break; 1612 1613 case OUTMODE_MPEG2_FIFO: 1614 /* Using Smooth block because not supported 1615 * by new Mpeg Mux block 1616 */ 1617 dprintk("dib8096P setting output mode TS_FIFO using Smooth block\n"); 1618 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 1619 outreg |= (5 << 6); 1620 smo_mode |= (3 << 1); 1621 fifo_threshold = 512; 1622 break; 1623 1624 case OUTMODE_DIVERSITY: 1625 dprintk("dib8096P setting output mode MODE_DIVERSITY\n"); 1626 dib8096p_setDibTxMux(state, DIV_ON_DIBTX); 1627 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); 1628 break; 1629 1630 case OUTMODE_ANALOG_ADC: 1631 dprintk("dib8096P setting output mode MODE_ANALOG_ADC\n"); 1632 dib8096p_setDibTxMux(state, ADC_ON_DIBTX); 1633 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); 1634 break; 1635 } 1636 1637 if (mode != OUTMODE_HIGH_Z) 1638 outreg |= (1<<10); 1639 1640 dprintk("output_mpeg2_in_188_bytes = %d\n", 1641 state->cfg.output_mpeg2_in_188_bytes); 1642 if (state->cfg.output_mpeg2_in_188_bytes) 1643 smo_mode |= (1 << 5); 1644 1645 ret |= dib8000_write_word(state, 299, smo_mode); 1646 /* synchronous fread */ 1647 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); 1648 ret |= dib8000_write_word(state, 1286, outreg); 1649 1650 return ret; 1651} 1652 1653static int map_addr_to_serpar_number(struct i2c_msg *msg) 1654{ 1655 if (msg->buf[0] <= 15) 1656 msg->buf[0] -= 1; 1657 else if (msg->buf[0] == 17) 1658 msg->buf[0] = 15; 1659 else if (msg->buf[0] == 16) 1660 msg->buf[0] = 17; 1661 else if (msg->buf[0] == 19) 1662 msg->buf[0] = 16; 1663 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25) 1664 msg->buf[0] -= 3; 1665 else if (msg->buf[0] == 28) 1666 msg->buf[0] = 23; 1667 else if (msg->buf[0] == 99) 1668 msg->buf[0] = 99; 1669 else 1670 return -EINVAL; 1671 return 0; 1672} 1673 1674static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap, 1675 struct i2c_msg msg[], int num) 1676{ 1677 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); 1678 u8 n_overflow = 1; 1679 u16 i = 1000; 1680 u16 serpar_num = msg[0].buf[0]; 1681 1682 while (n_overflow == 1 && i) { 1683 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; 1684 i--; 1685 if (i == 0) 1686 dprintk("Tuner ITF: write busy (overflow)\n"); 1687 } 1688 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); 1689 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); 1690 1691 return num; 1692} 1693 1694static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap, 1695 struct i2c_msg msg[], int num) 1696{ 1697 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); 1698 u8 n_overflow = 1, n_empty = 1; 1699 u16 i = 1000; 1700 u16 serpar_num = msg[0].buf[0]; 1701 u16 read_word; 1702 1703 while (n_overflow == 1 && i) { 1704 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; 1705 i--; 1706 if (i == 0) 1707 dprintk("TunerITF: read busy (overflow)\n"); 1708 } 1709 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); 1710 1711 i = 1000; 1712 while (n_empty == 1 && i) { 1713 n_empty = dib8000_read_word(state, 1984)&0x1; 1714 i--; 1715 if (i == 0) 1716 dprintk("TunerITF: read busy (empty)\n"); 1717 } 1718 1719 read_word = dib8000_read_word(state, 1987); 1720 msg[1].buf[0] = (read_word >> 8) & 0xff; 1721 msg[1].buf[1] = (read_word) & 0xff; 1722 1723 return num; 1724} 1725 1726static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, 1727 struct i2c_msg msg[], int num) 1728{ 1729 if (map_addr_to_serpar_number(&msg[0]) == 0) { 1730 if (num == 1) /* write */ 1731 return dib8096p_tuner_write_serpar(i2c_adap, msg, 1); 1732 else /* read */ 1733 return dib8096p_tuner_read_serpar(i2c_adap, msg, 2); 1734 } 1735 return num; 1736} 1737 1738static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap, 1739 struct i2c_msg msg[], int num, u16 apb_address) 1740{ 1741 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); 1742 u16 word; 1743 1744 if (num == 1) { /* write */ 1745 dib8000_write_word(state, apb_address, 1746 ((msg[0].buf[1] << 8) | (msg[0].buf[2]))); 1747 } else { 1748 word = dib8000_read_word(state, apb_address); 1749 msg[1].buf[0] = (word >> 8) & 0xff; 1750 msg[1].buf[1] = (word) & 0xff; 1751 } 1752 return num; 1753} 1754 1755static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap, 1756 struct i2c_msg msg[], int num) 1757{ 1758 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); 1759 u16 apb_address = 0, word; 1760 int i = 0; 1761 1762 switch (msg[0].buf[0]) { 1763 case 0x12: 1764 apb_address = 1920; 1765 break; 1766 case 0x14: 1767 apb_address = 1921; 1768 break; 1769 case 0x24: 1770 apb_address = 1922; 1771 break; 1772 case 0x1a: 1773 apb_address = 1923; 1774 break; 1775 case 0x22: 1776 apb_address = 1924; 1777 break; 1778 case 0x33: 1779 apb_address = 1926; 1780 break; 1781 case 0x34: 1782 apb_address = 1927; 1783 break; 1784 case 0x35: 1785 apb_address = 1928; 1786 break; 1787 case 0x36: 1788 apb_address = 1929; 1789 break; 1790 case 0x37: 1791 apb_address = 1930; 1792 break; 1793 case 0x38: 1794 apb_address = 1931; 1795 break; 1796 case 0x39: 1797 apb_address = 1932; 1798 break; 1799 case 0x2a: 1800 apb_address = 1935; 1801 break; 1802 case 0x2b: 1803 apb_address = 1936; 1804 break; 1805 case 0x2c: 1806 apb_address = 1937; 1807 break; 1808 case 0x2d: 1809 apb_address = 1938; 1810 break; 1811 case 0x2e: 1812 apb_address = 1939; 1813 break; 1814 case 0x2f: 1815 apb_address = 1940; 1816 break; 1817 case 0x30: 1818 apb_address = 1941; 1819 break; 1820 case 0x31: 1821 apb_address = 1942; 1822 break; 1823 case 0x32: 1824 apb_address = 1943; 1825 break; 1826 case 0x3e: 1827 apb_address = 1944; 1828 break; 1829 case 0x3f: 1830 apb_address = 1945; 1831 break; 1832 case 0x40: 1833 apb_address = 1948; 1834 break; 1835 case 0x25: 1836 apb_address = 936; 1837 break; 1838 case 0x26: 1839 apb_address = 937; 1840 break; 1841 case 0x27: 1842 apb_address = 938; 1843 break; 1844 case 0x28: 1845 apb_address = 939; 1846 break; 1847 case 0x1d: 1848 /* get sad sel request */ 1849 i = ((dib8000_read_word(state, 921) >> 12)&0x3); 1850 word = dib8000_read_word(state, 924+i); 1851 msg[1].buf[0] = (word >> 8) & 0xff; 1852 msg[1].buf[1] = (word) & 0xff; 1853 return num; 1854 case 0x1f: 1855 if (num == 1) { /* write */ 1856 word = (u16) ((msg[0].buf[1] << 8) | 1857 msg[0].buf[2]); 1858 /* in the VGAMODE Sel are located on bit 0/1 */ 1859 word &= 0x3; 1860 word = (dib8000_read_word(state, 921) & 1861 ~(3<<12)) | (word<<12); 1862 /* Set the proper input */ 1863 dib8000_write_word(state, 921, word); 1864 return num; 1865 } 1866 } 1867 1868 if (apb_address != 0) /* R/W access via APB */ 1869 return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address); 1870 else /* R/W access via SERPAR */ 1871 return dib8096p_tuner_rw_serpar(i2c_adap, msg, num); 1872 1873 return 0; 1874} 1875 1876static u32 dib8096p_i2c_func(struct i2c_adapter *adapter) 1877{ 1878 return I2C_FUNC_I2C; 1879} 1880 1881static const struct i2c_algorithm dib8096p_tuner_xfer_algo = { 1882 .master_xfer = dib8096p_tuner_xfer, 1883 .functionality = dib8096p_i2c_func, 1884}; 1885 1886static struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe) 1887{ 1888 struct dib8000_state *st = fe->demodulator_priv; 1889 return &st->dib8096p_tuner_adap; 1890} 1891 1892static int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff) 1893{ 1894 struct dib8000_state *state = fe->demodulator_priv; 1895 u16 en_cur_state; 1896 1897 dprintk("sleep dib8096p: %d\n", onoff); 1898 1899 en_cur_state = dib8000_read_word(state, 1922); 1900 1901 /* LNAs and MIX are ON and therefore it is a valid configuration */ 1902 if (en_cur_state > 0xff) 1903 state->tuner_enable = en_cur_state ; 1904 1905 if (onoff) 1906 en_cur_state &= 0x00ff; 1907 else { 1908 if (state->tuner_enable != 0) 1909 en_cur_state = state->tuner_enable; 1910 } 1911 1912 dib8000_write_word(state, 1922, en_cur_state); 1913 1914 return 0; 1915} 1916 1917static const s32 lut_1000ln_mant[] = 1918{ 1919 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600 1920}; 1921 1922static s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode) 1923{ 1924 struct dib8000_state *state = fe->demodulator_priv; 1925 u32 ix = 0, tmp_val = 0, exp = 0, mant = 0; 1926 s32 val; 1927 1928 val = dib8000_read32(state, 384); 1929 if (mode) { 1930 tmp_val = val; 1931 while (tmp_val >>= 1) 1932 exp++; 1933 mant = (val * 1000 / (1<<exp)); 1934 ix = (u8)((mant-1000)/100); /* index of the LUT */ 1935 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); 1936 val = (val*256)/1000; 1937 } 1938 return val; 1939} 1940 1941static int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ) 1942{ 1943 struct dib8000_state *state = fe->demodulator_priv; 1944 int val = 0; 1945 1946 switch (IQ) { 1947 case 1: 1948 val = dib8000_read_word(state, 403); 1949 break; 1950 case 0: 1951 val = dib8000_read_word(state, 404); 1952 break; 1953 } 1954 if (val & 0x200) 1955 val -= 1024; 1956 1957 return val; 1958} 1959 1960static void dib8000_update_timf(struct dib8000_state *state) 1961{ 1962 u32 timf = state->timf = dib8000_read32(state, 435); 1963 1964 dib8000_write_word(state, 29, (u16) (timf >> 16)); 1965 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); 1966 dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default); 1967} 1968 1969static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf) 1970{ 1971 struct dib8000_state *state = fe->demodulator_priv; 1972 1973 switch (op) { 1974 case DEMOD_TIMF_SET: 1975 state->timf = timf; 1976 break; 1977 case DEMOD_TIMF_UPDATE: 1978 dib8000_update_timf(state); 1979 break; 1980 case DEMOD_TIMF_GET: 1981 break; 1982 } 1983 dib8000_set_bandwidth(state->fe[0], 6000); 1984 1985 return state->timf; 1986} 1987 1988static const u16 adc_target_16dB[11] = { 1989 7250, 7238, 7264, 7309, 7338, 7382, 7427, 7456, 7500, 7544, 7574 1990}; 1991 1992static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 }; 1993 1994static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation) 1995{ 1996 u8 cr, constellation, time_intlv; 1997 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 1998 1999 switch (c->layer[layer_index].modulation) { 2000 case DQPSK: 2001 constellation = 0; 2002 break; 2003 case QPSK: 2004 constellation = 1; 2005 break; 2006 case QAM_16: 2007 constellation = 2; 2008 break; 2009 case QAM_64: 2010 default: 2011 constellation = 3; 2012 break; 2013 } 2014 2015 switch (c->layer[layer_index].fec) { 2016 case FEC_1_2: 2017 cr = 1; 2018 break; 2019 case FEC_2_3: 2020 cr = 2; 2021 break; 2022 case FEC_3_4: 2023 cr = 3; 2024 break; 2025 case FEC_5_6: 2026 cr = 5; 2027 break; 2028 case FEC_7_8: 2029 default: 2030 cr = 7; 2031 break; 2032 } 2033 2034 time_intlv = fls(c->layer[layer_index].interleaving); 2035 if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1)) 2036 time_intlv = 0; 2037 2038 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv); 2039 if (c->layer[layer_index].segment_count > 0) { 2040 switch (max_constellation) { 2041 case DQPSK: 2042 case QPSK: 2043 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64) 2044 max_constellation = c->layer[layer_index].modulation; 2045 break; 2046 case QAM_16: 2047 if (c->layer[layer_index].modulation == QAM_64) 2048 max_constellation = c->layer[layer_index].modulation; 2049 break; 2050 } 2051 } 2052 2053 return max_constellation; 2054} 2055 2056static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */ 2057static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */ 2058static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp_noise_cnt -0.01, P_adp_regul_ext 0.1, P_adp_noise_ext -0.002 */ 2059static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation) 2060{ 2061 u16 i, ana_gain = 0; 2062 const u16 *adp; 2063 2064 /* channel estimation fine configuration */ 2065 switch (max_constellation) { 2066 case QAM_64: 2067 ana_gain = 0x7; 2068 adp = &adp_Q64[0]; 2069 break; 2070 case QAM_16: 2071 ana_gain = 0x7; 2072 adp = &adp_Q16[0]; 2073 break; 2074 default: 2075 ana_gain = 0; 2076 adp = &adp_Qdefault[0]; 2077 break; 2078 } 2079 2080 for (i = 0; i < 4; i++) 2081 dib8000_write_word(state, 215 + i, adp[i]); 2082 2083 return ana_gain; 2084} 2085 2086static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain) 2087{ 2088 u16 i; 2089 2090 dib8000_write_word(state, 116, ana_gain); 2091 2092 /* update ADC target depending on ana_gain */ 2093 if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */ 2094 for (i = 0; i < 10; i++) 2095 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); 2096 } else { /* set -22dB ADC target for ana_gain=0 */ 2097 for (i = 0; i < 10; i++) 2098 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); 2099 } 2100} 2101 2102static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe) 2103{ 2104 u16 mode = 0; 2105 2106 if (state->isdbt_cfg_loaded == 0) 2107 for (mode = 0; mode < 24; mode++) 2108 dib8000_write_word(state, 117 + mode, ana_fe[mode]); 2109} 2110 2111static const u16 lut_prbs_2k[13] = { 2112 0x423, 0x009, 0x5C7, 2113 0x7A6, 0x3D8, 0x527, 2114 0x7FF, 0x79B, 0x3D6, 2115 0x3A2, 0x53B, 0x2F4, 2116 0x213 2117}; 2118 2119static const u16 lut_prbs_4k[13] = { 2120 0x208, 0x0C3, 0x7B9, 2121 0x423, 0x5C7, 0x3D8, 2122 0x7FF, 0x3D6, 0x53B, 2123 0x213, 0x029, 0x0D0, 2124 0x48E 2125}; 2126 2127static const u16 lut_prbs_8k[13] = { 2128 0x740, 0x069, 0x7DD, 2129 0x208, 0x7B9, 0x5C7, 2130 0x7FF, 0x53B, 0x029, 2131 0x48E, 0x4C4, 0x367, 2132 0x684 2133}; 2134 2135static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel) 2136{ 2137 int sub_channel_prbs_group = 0; 2138 int prbs_group; 2139 2140 sub_channel_prbs_group = subchannel / 3; 2141 if (sub_channel_prbs_group >= ARRAY_SIZE(lut_prbs_2k)) 2142 return 0; 2143 2144 switch (state->fe[0]->dtv_property_cache.transmission_mode) { 2145 case TRANSMISSION_MODE_2K: 2146 prbs_group = lut_prbs_2k[sub_channel_prbs_group]; 2147 break; 2148 case TRANSMISSION_MODE_4K: 2149 prbs_group = lut_prbs_4k[sub_channel_prbs_group]; 2150 break; 2151 default: 2152 case TRANSMISSION_MODE_8K: 2153 prbs_group = lut_prbs_8k[sub_channel_prbs_group]; 2154 } 2155 2156 dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x\n", 2157 sub_channel_prbs_group, subchannel, prbs_group); 2158 2159 return prbs_group; 2160} 2161 2162static void dib8000_set_13seg_channel(struct dib8000_state *state) 2163{ 2164 u16 i; 2165 u16 coff_pow = 0x2800; 2166 2167 state->seg_mask = 0x1fff; /* All 13 segments enabled */ 2168 2169 /* ---- COFF ---- Carloff, the most robust --- */ 2170 if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */ 2171 dib8000_write_word(state, 180, (16 << 6) | 9); 2172 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); 2173 coff_pow = 0x2800; 2174 for (i = 0; i < 6; i++) 2175 dib8000_write_word(state, 181+i, coff_pow); 2176 2177 /* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */ 2178 /* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */ 2179 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); 2180 2181 /* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */ 2182 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); 2183 /* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */ 2184 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); 2185 2186 dib8000_write_word(state, 228, 0); /* default value */ 2187 dib8000_write_word(state, 265, 31); /* default value */ 2188 dib8000_write_word(state, 205, 0x200f); /* init value */ 2189 } 2190 2191 /* 2192 * make the cpil_coff_lock more robust but slower p_coff_winlen 2193 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed) 2194 */ 2195 2196 if (state->cfg.pll->ifreq == 0) 2197 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ 2198 2199 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg); 2200} 2201 2202static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs) 2203{ 2204 u16 reg_1; 2205 2206 reg_1 = dib8000_read_word(state, 1); 2207 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ 2208} 2209 2210static void dib8000_small_fine_tune(struct dib8000_state *state) 2211{ 2212 u16 i; 2213 const s16 *ncoeff; 2214 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2215 2216 dib8000_write_word(state, 352, state->seg_diff_mask); 2217 dib8000_write_word(state, 353, state->seg_mask); 2218 2219 /* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */ 2220 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); 2221 2222 if (c->isdbt_sb_mode) { 2223 /* ---- SMALL ---- */ 2224 switch (c->transmission_mode) { 2225 case TRANSMISSION_MODE_2K: 2226 if (c->isdbt_partial_reception == 0) { /* 1-seg */ 2227 if (c->layer[0].modulation == DQPSK) /* DQPSK */ 2228 ncoeff = coeff_2k_sb_1seg_dqpsk; 2229 else /* QPSK or QAM */ 2230 ncoeff = coeff_2k_sb_1seg; 2231 } else { /* 3-segments */ 2232 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ 2233 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2234 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk; 2235 else /* QPSK or QAM on external segments */ 2236 ncoeff = coeff_2k_sb_3seg_0dqpsk; 2237 } else { /* QPSK or QAM on central segment */ 2238 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2239 ncoeff = coeff_2k_sb_3seg_1dqpsk; 2240 else /* QPSK or QAM on external segments */ 2241 ncoeff = coeff_2k_sb_3seg; 2242 } 2243 } 2244 break; 2245 case TRANSMISSION_MODE_4K: 2246 if (c->isdbt_partial_reception == 0) { /* 1-seg */ 2247 if (c->layer[0].modulation == DQPSK) /* DQPSK */ 2248 ncoeff = coeff_4k_sb_1seg_dqpsk; 2249 else /* QPSK or QAM */ 2250 ncoeff = coeff_4k_sb_1seg; 2251 } else { /* 3-segments */ 2252 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ 2253 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2254 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk; 2255 else /* QPSK or QAM on external segments */ 2256 ncoeff = coeff_4k_sb_3seg_0dqpsk; 2257 } else { /* QPSK or QAM on central segment */ 2258 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2259 ncoeff = coeff_4k_sb_3seg_1dqpsk; 2260 else /* QPSK or QAM on external segments */ 2261 ncoeff = coeff_4k_sb_3seg; 2262 } 2263 } 2264 break; 2265 case TRANSMISSION_MODE_AUTO: 2266 case TRANSMISSION_MODE_8K: 2267 default: 2268 if (c->isdbt_partial_reception == 0) { /* 1-seg */ 2269 if (c->layer[0].modulation == DQPSK) /* DQPSK */ 2270 ncoeff = coeff_8k_sb_1seg_dqpsk; 2271 else /* QPSK or QAM */ 2272 ncoeff = coeff_8k_sb_1seg; 2273 } else { /* 3-segments */ 2274 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ 2275 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2276 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk; 2277 else /* QPSK or QAM on external segments */ 2278 ncoeff = coeff_8k_sb_3seg_0dqpsk; 2279 } else { /* QPSK or QAM on central segment */ 2280 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ 2281 ncoeff = coeff_8k_sb_3seg_1dqpsk; 2282 else /* QPSK or QAM on external segments */ 2283 ncoeff = coeff_8k_sb_3seg; 2284 } 2285 } 2286 break; 2287 } 2288 2289 for (i = 0; i < 8; i++) 2290 dib8000_write_word(state, 343 + i, ncoeff[i]); 2291 } 2292} 2293 2294static const u16 coff_thres_1seg[3] = {300, 150, 80}; 2295static const u16 coff_thres_3seg[3] = {350, 300, 250}; 2296static void dib8000_set_sb_channel(struct dib8000_state *state) 2297{ 2298 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2299 const u16 *coff; 2300 u16 i; 2301 2302 if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) { 2303 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ 2304 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */ 2305 } else { 2306 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ 2307 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */ 2308 } 2309 2310 if (c->isdbt_partial_reception == 1) /* 3-segments */ 2311 state->seg_mask = 0x00E0; 2312 else /* 1-segment */ 2313 state->seg_mask = 0x0040; 2314 2315 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); 2316 2317 /* ---- COFF ---- Carloff, the most robust --- */ 2318 /* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 */ 2319 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3); 2320 2321 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */ 2322 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */ 2323 2324 /* Sound Broadcasting mode 1 seg */ 2325 if (c->isdbt_partial_reception == 0) { 2326 /* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */ 2327 if (state->mode == 3) 2328 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); 2329 else 2330 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); 2331 2332 /* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 */ 2333 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); 2334 coff = &coff_thres_1seg[0]; 2335 } else { /* Sound Broadcasting mode 3 seg */ 2336 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); 2337 /* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 */ 2338 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); 2339 coff = &coff_thres_3seg[0]; 2340 } 2341 2342 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */ 2343 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ 2344 2345 if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K) 2346 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */ 2347 2348 /* Write COFF thres */ 2349 for (i = 0 ; i < 3; i++) { 2350 dib8000_write_word(state, 181+i, coff[i]); 2351 dib8000_write_word(state, 184+i, coff[i]); 2352 } 2353 2354 /* 2355 * make the cpil_coff_lock more robust but slower p_coff_winlen 2356 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed) 2357 */ 2358 2359 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */ 2360 2361 if (c->isdbt_partial_reception == 0) 2362 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */ 2363 else 2364 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ 2365} 2366 2367static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching) 2368{ 2369 u16 p_cfr_left_edge = 0, p_cfr_right_edge = 0; 2370 u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ; 2371 u16 max_constellation = DQPSK; 2372 int init_prbs; 2373 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2374 2375 if (autosearching) 2376 c->isdbt_partial_reception = 1; 2377 2378 /* P_mode */ 2379 dib8000_write_word(state, 10, (seq << 4)); 2380 2381 /* init mode */ 2382 state->mode = fft_to_mode(state); 2383 2384 /* set guard */ 2385 tmp = dib8000_read_word(state, 1); 2386 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); 2387 2388 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4)); 2389 2390 /* signal optimization parameter */ 2391 if (c->isdbt_partial_reception) { 2392 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; 2393 for (i = 1; i < 3; i++) 2394 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; 2395 for (i = 0; i < nbseg_diff; i++) 2396 state->seg_diff_mask |= 1 << permu_seg[i+1]; 2397 } else { 2398 for (i = 0; i < 3; i++) 2399 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; 2400 for (i = 0; i < nbseg_diff; i++) 2401 state->seg_diff_mask |= 1 << permu_seg[i]; 2402 } 2403 2404 if (state->seg_diff_mask) 2405 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); 2406 else 2407 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */ 2408 2409 for (i = 0; i < 3; i++) 2410 max_constellation = dib8000_set_layer(state, i, max_constellation); 2411 if (autosearching == 0) { 2412 state->layer_b_nb_seg = c->layer[1].segment_count; 2413 state->layer_c_nb_seg = c->layer[2].segment_count; 2414 } 2415 2416 /* WRITE: Mode & Diff mask */ 2417 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); 2418 2419 state->differential_constellation = (state->seg_diff_mask != 0); 2420 2421 /* channel estimation fine configuration */ 2422 ana_gain = dib8000_adp_fine_tune(state, max_constellation); 2423 2424 /* update ana_gain depending on max constellation */ 2425 dib8000_update_ana_gain(state, ana_gain); 2426 2427 /* ---- ANA_FE ---- */ 2428 if (c->isdbt_partial_reception) /* 3-segments */ 2429 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg); 2430 else 2431 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */ 2432 2433 /* TSB or ISDBT ? apply it now */ 2434 if (c->isdbt_sb_mode) { 2435 dib8000_set_sb_channel(state); 2436 init_prbs = dib8000_get_init_prbs(state, 2437 c->isdbt_sb_subchannel); 2438 } else { 2439 dib8000_set_13seg_channel(state); 2440 init_prbs = 0xfff; 2441 } 2442 2443 /* SMALL */ 2444 dib8000_small_fine_tune(state); 2445 2446 dib8000_set_subchannel_prbs(state, init_prbs); 2447 2448 /* ---- CHAN_BLK ---- */ 2449 for (i = 0; i < 13; i++) { 2450 if ((((~state->seg_diff_mask) >> i) & 1) == 1) { 2451 p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0)); 2452 p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0)); 2453 } 2454 } 2455 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */ 2456 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */ 2457 /* "P_cspu_left_edge" & "P_cspu_right_edge" not used => do not care */ 2458 2459 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ 2460 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ 2461 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ 2462 2463 if (!autosearching) 2464 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */ 2465 else 2466 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */ 2467 2468 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ 2469 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ 2470 2471 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ 2472 2473 /* ---- TMCC ---- */ 2474 for (i = 0; i < 3; i++) 2475 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ; 2476 2477 /* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */ 2478 /* Threshold is set at 1/4 of max power. */ 2479 tmcc_pow *= (1 << (9-2)); 2480 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */ 2481 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */ 2482 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */ 2483 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */ 2484 2485 /* ---- PHA3 ---- */ 2486 if (state->isdbt_cfg_loaded == 0) 2487 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */ 2488 2489 state->isdbt_cfg_loaded = 0; 2490} 2491 2492static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal, 2493 u32 wait0_ms, u32 wait1_ms, u32 wait2_ms) 2494{ 2495 u32 value = 0; /* P_search_end0 wait time */ 2496 u16 reg = 11; /* P_search_end0 start addr */ 2497 2498 for (reg = 11; reg < 16; reg += 2) { 2499 if (reg == 11) { 2500 if (state->revision == 0x8090) 2501 value = internal * wait1_ms; 2502 else 2503 value = internal * wait0_ms; 2504 } else if (reg == 13) 2505 value = internal * wait1_ms; 2506 else if (reg == 15) 2507 value = internal * wait2_ms; 2508 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); 2509 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); 2510 } 2511 return value; 2512} 2513 2514static int dib8000_autosearch_start(struct dvb_frontend *fe) 2515{ 2516 struct dib8000_state *state = fe->demodulator_priv; 2517 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2518 u8 slist = 0; 2519 u32 value, internal = state->cfg.pll->internal; 2520 2521 if (state->revision == 0x8090) 2522 internal = dib8000_read32(state, 23) / 1000; 2523 2524 if ((state->revision >= 0x8002) && 2525 (state->autosearch_state == AS_SEARCHING_FFT)) { 2526 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ 2527 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ 2528 2529 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */ 2530 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ 2531 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ 2532 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ 2533 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ 2534 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */ 2535 2536 if (state->revision == 0x8090) 2537 value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2538 else 2539 value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2540 2541 dib8000_write_word(state, 17, 0); 2542 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */ 2543 dib8000_write_word(state, 19, 0); 2544 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */ 2545 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ 2546 dib8000_write_word(state, 22, value & 0xffff); 2547 2548 if (state->revision == 0x8090) 2549 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */ 2550 else 2551 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */ 2552 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */ 2553 2554 /* P_search_param_select = (1 | 1<<4 | 1 << 8) */ 2555 dib8000_write_word(state, 356, 0); 2556 dib8000_write_word(state, 357, 0x111); 2557 2558 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */ 2559 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */ 2560 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */ 2561 } else if ((state->revision >= 0x8002) && 2562 (state->autosearch_state == AS_SEARCHING_GUARD)) { 2563 c->transmission_mode = TRANSMISSION_MODE_8K; 2564 c->guard_interval = GUARD_INTERVAL_1_8; 2565 c->inversion = 0; 2566 c->layer[0].modulation = QAM_64; 2567 c->layer[0].fec = FEC_2_3; 2568 c->layer[0].interleaving = 0; 2569 c->layer[0].segment_count = 13; 2570 2571 slist = 16; 2572 c->transmission_mode = state->found_nfft; 2573 2574 dib8000_set_isdbt_common_channel(state, slist, 1); 2575 2576 /* set lock_mask values */ 2577 dib8000_write_word(state, 6, 0x4); 2578 if (state->revision == 0x8090) 2579 dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */ 2580 else 2581 dib8000_write_word(state, 7, 0x8); 2582 dib8000_write_word(state, 8, 0x1000); 2583 2584 /* set lock_mask wait time values */ 2585 if (state->revision == 0x8090) 2586 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2587 else 2588 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2589 2590 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */ 2591 2592 /* P_search_param_select = 0xf; look for the 4 different guard intervals */ 2593 dib8000_write_word(state, 356, 0); 2594 dib8000_write_word(state, 357, 0xf); 2595 2596 value = dib8000_read_word(state, 0); 2597 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); 2598 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ 2599 dib8000_write_word(state, 0, (u16)value); 2600 } else { 2601 c->inversion = 0; 2602 c->layer[0].modulation = QAM_64; 2603 c->layer[0].fec = FEC_2_3; 2604 c->layer[0].interleaving = 0; 2605 c->layer[0].segment_count = 13; 2606 if (!c->isdbt_sb_mode) 2607 c->layer[0].segment_count = 13; 2608 2609 /* choose the right list, in sb, always do everything */ 2610 if (c->isdbt_sb_mode) { 2611 slist = 7; 2612 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); 2613 } else { 2614 if (c->guard_interval == GUARD_INTERVAL_AUTO) { 2615 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { 2616 c->transmission_mode = TRANSMISSION_MODE_8K; 2617 c->guard_interval = GUARD_INTERVAL_1_8; 2618 slist = 7; 2619 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */ 2620 } else { 2621 c->guard_interval = GUARD_INTERVAL_1_8; 2622 slist = 3; 2623 } 2624 } else { 2625 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { 2626 c->transmission_mode = TRANSMISSION_MODE_8K; 2627 slist = 2; 2628 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ 2629 } else 2630 slist = 0; 2631 } 2632 } 2633 dprintk("Using list for autosearch : %d\n", slist); 2634 2635 dib8000_set_isdbt_common_channel(state, slist, 1); 2636 2637 /* set lock_mask values */ 2638 dib8000_write_word(state, 6, 0x4); 2639 if (state->revision == 0x8090) 2640 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10)); 2641 else 2642 dib8000_write_word(state, 7, 0x8); 2643 dib8000_write_word(state, 8, 0x1000); 2644 2645 /* set lock_mask wait time values */ 2646 if (state->revision == 0x8090) 2647 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2648 else 2649 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ 2650 2651 value = dib8000_read_word(state, 0); 2652 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); 2653 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ 2654 dib8000_write_word(state, 0, (u16)value); 2655 } 2656 return 0; 2657} 2658 2659static int dib8000_autosearch_irq(struct dvb_frontend *fe) 2660{ 2661 struct dib8000_state *state = fe->demodulator_priv; 2662 u16 irq_pending = dib8000_read_word(state, 1284); 2663 2664 if ((state->revision >= 0x8002) && 2665 (state->autosearch_state == AS_SEARCHING_FFT)) { 2666 if (irq_pending & 0x1) { 2667 dprintk("dib8000_autosearch_irq: max correlation result available\n"); 2668 return 3; 2669 } 2670 } else { 2671 if (irq_pending & 0x1) { /* failed */ 2672 dprintk("dib8000_autosearch_irq failed\n"); 2673 return 1; 2674 } 2675 2676 if (irq_pending & 0x2) { /* succeeded */ 2677 dprintk("dib8000_autosearch_irq succeeded\n"); 2678 return 2; 2679 } 2680 } 2681 2682 return 0; // still pending 2683} 2684 2685static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff) 2686{ 2687 u16 tmp; 2688 2689 tmp = dib8000_read_word(state, 771); 2690 if (onoff) /* start P_restart_chd : channel_decoder */ 2691 dib8000_write_word(state, 771, tmp & 0xfffd); 2692 else /* stop P_restart_chd : channel_decoder */ 2693 dib8000_write_word(state, 771, tmp | (1<<1)); 2694} 2695 2696static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz) 2697{ 2698 s16 unit_khz_dds_val; 2699 u32 abs_offset_khz = abs(offset_khz); 2700 u32 dds = state->cfg.pll->ifreq & 0x1ffffff; 2701 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25)); 2702 u8 ratio; 2703 2704 if (state->revision == 0x8090) { 2705 u32 internal = dib8000_read32(state, 23) / 1000; 2706 2707 ratio = 4; 2708 2709 unit_khz_dds_val = (1<<26) / (internal ?: 1); 2710 if (offset_khz < 0) 2711 dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val); 2712 else 2713 dds = (abs_offset_khz * unit_khz_dds_val); 2714 2715 if (invert) 2716 dds = (1<<26) - dds; 2717 } else { 2718 ratio = 2; 2719 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal); 2720 2721 if (offset_khz < 0) 2722 unit_khz_dds_val *= -1; 2723 2724 /* IF tuner */ 2725 if (invert) 2726 dds -= abs_offset_khz * unit_khz_dds_val; 2727 else 2728 dds += abs_offset_khz * unit_khz_dds_val; 2729 } 2730 2731 dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val); 2732 2733 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) { 2734 /* Max dds offset is the half of the demod freq */ 2735 dib8000_write_word(state, 26, invert); 2736 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); 2737 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); 2738 } 2739} 2740 2741static void dib8000_set_frequency_offset(struct dib8000_state *state) 2742{ 2743 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2744 int i; 2745 u32 current_rf; 2746 int total_dds_offset_khz; 2747 2748 if (state->fe[0]->ops.tuner_ops.get_frequency) 2749 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf); 2750 else 2751 current_rf = c->frequency; 2752 current_rf /= 1000; 2753 total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000; 2754 2755 if (c->isdbt_sb_mode) { 2756 state->subchannel = c->isdbt_sb_subchannel; 2757 2758 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */ 2759 dib8000_write_word(state, 26, c->inversion ^ i); 2760 2761 if (state->cfg.pll->ifreq == 0) { /* low if tuner */ 2762 if ((c->inversion ^ i) == 0) 2763 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); 2764 } else { 2765 if ((c->inversion ^ i) == 0) 2766 total_dds_offset_khz *= -1; 2767 } 2768 } 2769 2770 dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz); 2771 2772 /* apply dds offset now */ 2773 dib8000_set_dds(state, total_dds_offset_khz); 2774} 2775 2776static u16 LUT_isdbt_symbol_duration[4] = { 26, 101, 63 }; 2777 2778static u32 dib8000_get_symbol_duration(struct dib8000_state *state) 2779{ 2780 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2781 u16 i; 2782 2783 switch (c->transmission_mode) { 2784 case TRANSMISSION_MODE_2K: 2785 i = 0; 2786 break; 2787 case TRANSMISSION_MODE_4K: 2788 i = 2; 2789 break; 2790 default: 2791 case TRANSMISSION_MODE_AUTO: 2792 case TRANSMISSION_MODE_8K: 2793 i = 1; 2794 break; 2795 } 2796 2797 return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1; 2798} 2799 2800static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step) 2801{ 2802 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2803 u16 reg_32 = 0, reg_37 = 0; 2804 2805 switch (loop_step) { 2806 case LOOP_TUNE_1: 2807 if (c->isdbt_sb_mode) { 2808 if (c->isdbt_partial_reception == 0) { 2809 reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */ 2810 reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */ 2811 } else { /* Sound Broadcasting mode 3 seg */ 2812 reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */ 2813 reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */ 2814 } 2815 } else { /* 13-seg start conf offset loop parameters */ 2816 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */ 2817 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */ 2818 } 2819 break; 2820 case LOOP_TUNE_2: 2821 if (c->isdbt_sb_mode) { 2822 if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */ 2823 reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/ 2824 reg_37 = (12-state->mode) | ((5 + state->mode) << 5); 2825 } else { /* Sound Broadcasting mode 3 seg */ 2826 reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */ 2827 reg_37 = (11-state->mode) | ((5 + state->mode) << 5); 2828 } 2829 } else { /* 13 seg */ 2830 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */ 2831 reg_37 = ((5+state->mode) << 5) | (10 - state->mode); 2832 } 2833 break; 2834 } 2835 dib8000_write_word(state, 32, reg_32); 2836 dib8000_write_word(state, 37, reg_37); 2837} 2838 2839static void dib8000_demod_restart(struct dib8000_state *state) 2840{ 2841 dib8000_write_word(state, 770, 0x4000); 2842 dib8000_write_word(state, 770, 0x0000); 2843 return; 2844} 2845 2846static void dib8000_set_sync_wait(struct dib8000_state *state) 2847{ 2848 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 2849 u16 sync_wait = 64; 2850 2851 /* P_dvsy_sync_wait - reuse mode */ 2852 switch (c->transmission_mode) { 2853 case TRANSMISSION_MODE_8K: 2854 sync_wait = 256; 2855 break; 2856 case TRANSMISSION_MODE_4K: 2857 sync_wait = 128; 2858 break; 2859 default: 2860 case TRANSMISSION_MODE_2K: 2861 sync_wait = 64; 2862 break; 2863 } 2864 2865 if (state->cfg.diversity_delay == 0) 2866 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */ 2867 else 2868 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */ 2869 2870 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); 2871} 2872 2873static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode) 2874{ 2875 if (mode == SYMBOL_DEPENDENT_ON) 2876 delay *= state->symbol_duration; 2877 2878 return jiffies + usecs_to_jiffies(delay * 100); 2879} 2880 2881static s32 dib8000_get_status(struct dvb_frontend *fe) 2882{ 2883 struct dib8000_state *state = fe->demodulator_priv; 2884 return state->status; 2885} 2886 2887static enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe) 2888{ 2889 struct dib8000_state *state = fe->demodulator_priv; 2890 return state->tune_state; 2891} 2892 2893static int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) 2894{ 2895 struct dib8000_state *state = fe->demodulator_priv; 2896 2897 state->tune_state = tune_state; 2898 return 0; 2899} 2900 2901static int dib8000_tune_restart_from_demod(struct dvb_frontend *fe) 2902{ 2903 struct dib8000_state *state = fe->demodulator_priv; 2904 2905 state->status = FE_STATUS_TUNE_PENDING; 2906 state->tune_state = CT_DEMOD_START; 2907 return 0; 2908} 2909 2910static u16 dib8000_read_lock(struct dvb_frontend *fe) 2911{ 2912 struct dib8000_state *state = fe->demodulator_priv; 2913 2914 if (state->revision == 0x8090) 2915 return dib8000_read_word(state, 570); 2916 return dib8000_read_word(state, 568); 2917} 2918 2919static int dib8090p_init_sdram(struct dib8000_state *state) 2920{ 2921 u16 reg = 0; 2922 dprintk("init sdram\n"); 2923 2924 reg = dib8000_read_word(state, 274) & 0xfff0; 2925 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ 2926 2927 dib8000_write_word(state, 1803, (7 << 2)); 2928 2929 reg = dib8000_read_word(state, 1280); 2930 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ 2931 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ 2932 2933 return 0; 2934} 2935 2936/** 2937 * is_manual_mode - Check if TMCC should be used for parameters settings 2938 * @c: struct dvb_frontend_properties 2939 * 2940 * By default, TMCC table should be used for parameter settings on most 2941 * usercases. However, sometimes it is desirable to lock the demod to 2942 * use the manual parameters. 2943 * 2944 * On manual mode, the current dib8000_tune state machine is very restrict: 2945 * It requires that both per-layer and per-transponder parameters to be 2946 * properly specified, otherwise the device won't lock. 2947 * 2948 * Check if all those conditions are properly satisfied before allowing 2949 * the device to use the manual frequency lock mode. 2950 */ 2951static int is_manual_mode(struct dtv_frontend_properties *c) 2952{ 2953 int i, n_segs = 0; 2954 2955 /* Use auto mode on DVB-T compat mode */ 2956 if (c->delivery_system != SYS_ISDBT) 2957 return 0; 2958 2959 /* 2960 * Transmission mode is only detected on auto mode, currently 2961 */ 2962 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { 2963 dprintk("transmission mode auto\n"); 2964 return 0; 2965 } 2966 2967 /* 2968 * Guard interval is only detected on auto mode, currently 2969 */ 2970 if (c->guard_interval == GUARD_INTERVAL_AUTO) { 2971 dprintk("guard interval auto\n"); 2972 return 0; 2973 } 2974 2975 /* 2976 * If no layer is enabled, assume auto mode, as at least one 2977 * layer should be enabled 2978 */ 2979 if (!c->isdbt_layer_enabled) { 2980 dprintk("no layer modulation specified\n"); 2981 return 0; 2982 } 2983 2984 /* 2985 * Check if the per-layer parameters aren't auto and 2986 * disable a layer if segment count is 0 or invalid. 2987 */ 2988 for (i = 0; i < 3; i++) { 2989 if (!(c->isdbt_layer_enabled & 1 << i)) 2990 continue; 2991 2992 if ((c->layer[i].segment_count > 13) || 2993 (c->layer[i].segment_count == 0)) { 2994 c->isdbt_layer_enabled &= ~(1 << i); 2995 continue; 2996 } 2997 2998 n_segs += c->layer[i].segment_count; 2999 3000 if ((c->layer[i].modulation == QAM_AUTO) || 3001 (c->layer[i].fec == FEC_AUTO)) { 3002 dprintk("layer %c has either modulation or FEC auto\n", 3003 'A' + i); 3004 return 0; 3005 } 3006 } 3007 3008 /* 3009 * Userspace specified a wrong number of segments. 3010 * fallback to auto mode. 3011 */ 3012 if (n_segs == 0 || n_segs > 13) { 3013 dprintk("number of segments is invalid\n"); 3014 return 0; 3015 } 3016 3017 /* Everything looks ok for manual mode */ 3018 return 1; 3019} 3020 3021static int dib8000_tune(struct dvb_frontend *fe) 3022{ 3023 struct dib8000_state *state = fe->demodulator_priv; 3024 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 3025 enum frontend_tune_state *tune_state = &state->tune_state; 3026 3027 u16 locks, deeper_interleaver = 0, i; 3028 int ret = 1; /* 1 symbol duration (in 100us unit) delay most of the time */ 3029 3030 unsigned long *timeout = &state->timeout; 3031 unsigned long now = jiffies; 3032 u16 init_prbs; 3033#ifdef DIB8000_AGC_FREEZE 3034 u16 agc1, agc2; 3035#endif 3036 3037 u32 corm[4] = {0, 0, 0, 0}; 3038 u8 find_index, max_value; 3039 3040#if 0 3041 if (*tune_state < CT_DEMOD_STOP) 3042 dprintk("IN: context status = %d, TUNE_STATE %d autosearch step = %u jiffies = %lu\n", 3043 state->channel_parameters_set, *tune_state, state->autosearch_state, now); 3044#endif 3045 3046 switch (*tune_state) { 3047 case CT_DEMOD_START: /* 30 */ 3048 dib8000_reset_stats(fe); 3049 3050 if (state->revision == 0x8090) 3051 dib8090p_init_sdram(state); 3052 state->status = FE_STATUS_TUNE_PENDING; 3053 state->channel_parameters_set = is_manual_mode(c); 3054 3055 dprintk("Tuning channel on %s search mode\n", 3056 state->channel_parameters_set ? "manual" : "auto"); 3057 3058 dib8000_viterbi_state(state, 0); /* force chan dec in restart */ 3059 3060 /* Layer monitor */ 3061 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); 3062 3063 dib8000_set_frequency_offset(state); 3064 dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000); 3065 3066 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */ 3067#ifdef DIB8000_AGC_FREEZE 3068 if (state->revision != 0x8090) { 3069 state->agc1_max = dib8000_read_word(state, 108); 3070 state->agc1_min = dib8000_read_word(state, 109); 3071 state->agc2_max = dib8000_read_word(state, 110); 3072 state->agc2_min = dib8000_read_word(state, 111); 3073 agc1 = dib8000_read_word(state, 388); 3074 agc2 = dib8000_read_word(state, 389); 3075 dib8000_write_word(state, 108, agc1); 3076 dib8000_write_word(state, 109, agc1); 3077 dib8000_write_word(state, 110, agc2); 3078 dib8000_write_word(state, 111, agc2); 3079 } 3080#endif 3081 state->autosearch_state = AS_SEARCHING_FFT; 3082 state->found_nfft = TRANSMISSION_MODE_AUTO; 3083 state->found_guard = GUARD_INTERVAL_AUTO; 3084 *tune_state = CT_DEMOD_SEARCH_NEXT; 3085 } else { /* we already know the channel struct so TUNE only ! */ 3086 state->autosearch_state = AS_DONE; 3087 *tune_state = CT_DEMOD_STEP_3; 3088 } 3089 state->symbol_duration = dib8000_get_symbol_duration(state); 3090 break; 3091 3092 case CT_DEMOD_SEARCH_NEXT: /* 51 */ 3093 dib8000_autosearch_start(fe); 3094 if (state->revision == 0x8090) 3095 ret = 50; 3096 else 3097 ret = 15; 3098 *tune_state = CT_DEMOD_STEP_1; 3099 break; 3100 3101 case CT_DEMOD_STEP_1: /* 31 */ 3102 switch (dib8000_autosearch_irq(fe)) { 3103 case 1: /* fail */ 3104 state->status = FE_STATUS_TUNE_FAILED; 3105 state->autosearch_state = AS_DONE; 3106 *tune_state = CT_DEMOD_STOP; /* else we are done here */ 3107 break; 3108 case 2: /* Success */ 3109 state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */ 3110 *tune_state = CT_DEMOD_STEP_3; 3111 if (state->autosearch_state == AS_SEARCHING_GUARD) 3112 *tune_state = CT_DEMOD_STEP_2; 3113 else 3114 state->autosearch_state = AS_DONE; 3115 break; 3116 case 3: /* Autosearch FFT max correlation endded */ 3117 *tune_state = CT_DEMOD_STEP_2; 3118 break; 3119 } 3120 break; 3121 3122 case CT_DEMOD_STEP_2: 3123 switch (state->autosearch_state) { 3124 case AS_SEARCHING_FFT: 3125 /* searching for the correct FFT */ 3126 if (state->revision == 0x8090) { 3127 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); 3128 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); 3129 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601)); 3130 } else { 3131 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595)); 3132 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); 3133 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); 3134 } 3135 /* dprintk("corm fft: %u %u %u\n", corm[0], corm[1], corm[2]); */ 3136 3137 max_value = 0; 3138 for (find_index = 1 ; find_index < 3 ; find_index++) { 3139 if (corm[max_value] < corm[find_index]) 3140 max_value = find_index ; 3141 } 3142 3143 switch (max_value) { 3144 case 0: 3145 state->found_nfft = TRANSMISSION_MODE_2K; 3146 break; 3147 case 1: 3148 state->found_nfft = TRANSMISSION_MODE_4K; 3149 break; 3150 case 2: 3151 default: 3152 state->found_nfft = TRANSMISSION_MODE_8K; 3153 break; 3154 } 3155 /* dprintk("Autosearch FFT has found Mode %d\n", max_value + 1); */ 3156 3157 *tune_state = CT_DEMOD_SEARCH_NEXT; 3158 state->autosearch_state = AS_SEARCHING_GUARD; 3159 if (state->revision == 0x8090) 3160 ret = 50; 3161 else 3162 ret = 10; 3163 break; 3164 case AS_SEARCHING_GUARD: 3165 /* searching for the correct guard interval */ 3166 if (state->revision == 0x8090) 3167 state->found_guard = dib8000_read_word(state, 572) & 0x3; 3168 else 3169 state->found_guard = dib8000_read_word(state, 570) & 0x3; 3170 /* dprintk("guard interval found=%i\n", state->found_guard); */ 3171 3172 *tune_state = CT_DEMOD_STEP_3; 3173 break; 3174 default: 3175 /* the demod should never be in this state */ 3176 state->status = FE_STATUS_TUNE_FAILED; 3177 state->autosearch_state = AS_DONE; 3178 *tune_state = CT_DEMOD_STOP; /* else we are done here */ 3179 break; 3180 } 3181 break; 3182 3183 case CT_DEMOD_STEP_3: /* 33 */ 3184 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1); 3185 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */ 3186 *tune_state = CT_DEMOD_STEP_4; 3187 break; 3188 3189 case CT_DEMOD_STEP_4: /* (34) */ 3190 dib8000_demod_restart(state); 3191 3192 dib8000_set_sync_wait(state); 3193 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); 3194 3195 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */ 3196 /* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */ 3197 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON); 3198 *tune_state = CT_DEMOD_STEP_5; 3199 break; 3200 3201 case CT_DEMOD_STEP_5: /* (35) */ 3202 locks = dib8000_read_lock(fe); 3203 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */ 3204 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */ 3205 if (!state->differential_constellation) { 3206 /* 2 times lmod4_win_len + 10 symbols (pipe delay after coff + nb to compute a 1st correlation) */ 3207 *timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON); 3208 *tune_state = CT_DEMOD_STEP_7; 3209 } else { 3210 *tune_state = CT_DEMOD_STEP_8; 3211 } 3212 } else if (time_after(now, *timeout)) { 3213 *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */ 3214 } 3215 break; 3216 3217 case CT_DEMOD_STEP_6: /* (36) if there is an input (diversity) */ 3218 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) { 3219 /* if there is a diversity fe in input and this fe is has not already failed : wait here until this fe has succeeded or failed */ 3220 if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */ 3221 *tune_state = CT_DEMOD_STEP_8; /* go for mpeg */ 3222 else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failed also, break the current one */ 3223 *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */ 3224 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ 3225 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); 3226 state->status = FE_STATUS_TUNE_FAILED; 3227 } 3228 } else { 3229 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ 3230 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); 3231 *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */ 3232 state->status = FE_STATUS_TUNE_FAILED; 3233 } 3234 break; 3235 3236 case CT_DEMOD_STEP_7: /* 37 */ 3237 locks = dib8000_read_lock(fe); 3238 if (locks & (1<<10)) { /* lmod4_lock */ 3239 ret = 14; /* wait for 14 symbols */ 3240 *tune_state = CT_DEMOD_STEP_8; 3241 } else if (time_after(now, *timeout)) 3242 *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */ 3243 break; 3244 3245 case CT_DEMOD_STEP_8: /* 38 */ 3246 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ 3247 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); 3248 3249 /* mpeg will never lock on this condition because init_prbs is not set : search for it !*/ 3250 if (c->isdbt_sb_mode 3251 && c->isdbt_sb_subchannel < 14 3252 && !state->differential_constellation) { 3253 state->subchannel = 0; 3254 *tune_state = CT_DEMOD_STEP_11; 3255 } else { 3256 *tune_state = CT_DEMOD_STEP_9; 3257 state->status = FE_STATUS_LOCKED; 3258 } 3259 break; 3260 3261 case CT_DEMOD_STEP_9: /* 39 */ 3262 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */ 3263 /* defines timeout for mpeg lock depending on interleaver length of longest layer */ 3264 for (i = 0; i < 3; i++) { 3265 if (c->layer[i].interleaving >= deeper_interleaver) { 3266 dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving); 3267 if (c->layer[i].segment_count > 0) { /* valid layer */ 3268 deeper_interleaver = c->layer[0].interleaving; 3269 state->longest_intlv_layer = i; 3270 } 3271 } 3272 } 3273 3274 if (deeper_interleaver == 0) 3275 locks = 2; /* locks is the tmp local variable name */ 3276 else if (deeper_interleaver == 3) 3277 locks = 8; 3278 else 3279 locks = 2 * deeper_interleaver; 3280 3281 if (state->diversity_onoff != 0) /* because of diversity sync */ 3282 locks *= 2; 3283 3284 *timeout = now + msecs_to_jiffies(200 * locks); /* give the mpeg lock 800ms if sram is present */ 3285 dprintk("Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %ld\n", 3286 deeper_interleaver, state->longest_intlv_layer, locks, *timeout); 3287 3288 *tune_state = CT_DEMOD_STEP_10; 3289 } else 3290 *tune_state = CT_DEMOD_STOP; 3291 break; 3292 3293 case CT_DEMOD_STEP_10: /* 40 */ 3294 locks = dib8000_read_lock(fe); 3295 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */ 3296 dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n", 3297 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", 3298 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", 3299 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); 3300 if (c->isdbt_sb_mode 3301 && c->isdbt_sb_subchannel < 14 3302 && !state->differential_constellation) 3303 /* signal to the upper layer, that there was a channel found and the parameters can be read */ 3304 state->status = FE_STATUS_DEMOD_SUCCESS; 3305 else 3306 state->status = FE_STATUS_DATA_LOCKED; 3307 *tune_state = CT_DEMOD_STOP; 3308 } else if (time_after(now, *timeout)) { 3309 if (c->isdbt_sb_mode 3310 && c->isdbt_sb_subchannel < 14 3311 && !state->differential_constellation) { /* continue to try init prbs autosearch */ 3312 state->subchannel += 3; 3313 *tune_state = CT_DEMOD_STEP_11; 3314 } else { /* we are done mpeg of the longest interleaver xas not locking but let's try if an other layer has locked in the same time */ 3315 if (locks & (0x7 << 5)) { 3316 dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n", 3317 jiffies_to_msecs(now - *timeout), 3318 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", 3319 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", 3320 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); 3321 3322 state->status = FE_STATUS_DATA_LOCKED; 3323 } else 3324 state->status = FE_STATUS_TUNE_FAILED; 3325 *tune_state = CT_DEMOD_STOP; 3326 } 3327 } 3328 break; 3329 3330 case CT_DEMOD_STEP_11: /* 41 : init prbs autosearch */ 3331 init_prbs = dib8000_get_init_prbs(state, state->subchannel); 3332 3333 if (init_prbs) { 3334 dib8000_set_subchannel_prbs(state, init_prbs); 3335 *tune_state = CT_DEMOD_STEP_9; 3336 } else { 3337 *tune_state = CT_DEMOD_STOP; 3338 state->status = FE_STATUS_TUNE_FAILED; 3339 } 3340 break; 3341 3342 default: 3343 break; 3344 } 3345 3346 /* tuning is finished - cleanup the demod */ 3347 switch (*tune_state) { 3348 case CT_DEMOD_STOP: /* (42) */ 3349#ifdef DIB8000_AGC_FREEZE 3350 if ((state->revision != 0x8090) && (state->agc1_max != 0)) { 3351 dib8000_write_word(state, 108, state->agc1_max); 3352 dib8000_write_word(state, 109, state->agc1_min); 3353 dib8000_write_word(state, 110, state->agc2_max); 3354 dib8000_write_word(state, 111, state->agc2_min); 3355 state->agc1_max = 0; 3356 state->agc1_min = 0; 3357 state->agc2_max = 0; 3358 state->agc2_min = 0; 3359 } 3360#endif 3361 ret = 0; 3362 break; 3363 default: 3364 break; 3365 } 3366 3367 if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3)) 3368 return ret * state->symbol_duration; 3369 if ((ret > 0) && (ret < state->symbol_duration)) 3370 return state->symbol_duration; /* at least one symbol */ 3371 return ret; 3372} 3373 3374static int dib8000_wakeup(struct dvb_frontend *fe) 3375{ 3376 struct dib8000_state *state = fe->demodulator_priv; 3377 u8 index_frontend; 3378 int ret; 3379 3380 dib8000_set_power_mode(state, DIB8000_POWER_ALL); 3381 dib8000_set_adc_state(state, DIBX000_ADC_ON); 3382 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) 3383 dprintk("could not start Slow ADC\n"); 3384 3385 if (state->revision == 0x8090) 3386 dib8000_sad_calib(state); 3387 3388 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3389 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); 3390 if (ret < 0) 3391 return ret; 3392 } 3393 3394 return 0; 3395} 3396 3397static int dib8000_sleep(struct dvb_frontend *fe) 3398{ 3399 struct dib8000_state *state = fe->demodulator_priv; 3400 u8 index_frontend; 3401 int ret; 3402 3403 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3404 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); 3405 if (ret < 0) 3406 return ret; 3407 } 3408 3409 if (state->revision != 0x8090) 3410 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z); 3411 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); 3412 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF); 3413} 3414 3415static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat); 3416 3417static int dib8000_get_frontend(struct dvb_frontend *fe, 3418 struct dtv_frontend_properties *c) 3419{ 3420 struct dib8000_state *state = fe->demodulator_priv; 3421 u16 i, val = 0; 3422 enum fe_status stat = 0; 3423 u8 index_frontend, sub_index_frontend; 3424 3425 c->bandwidth_hz = 6000000; 3426 3427 /* 3428 * If called to early, get_frontend makes dib8000_tune to either 3429 * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail. 3430 * So, let's just return if frontend 0 has not locked. 3431 */ 3432 dib8000_read_status(fe, &stat); 3433 if (!(stat & FE_HAS_SYNC)) 3434 return 0; 3435 3436 dprintk("dib8000_get_frontend: TMCC lock\n"); 3437 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3438 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); 3439 if (stat&FE_HAS_SYNC) { 3440 dprintk("TMCC lock on the slave%i\n", index_frontend); 3441 /* synchronize the cache with the other frontends */ 3442 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c); 3443 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) { 3444 if (sub_index_frontend != index_frontend) { 3445 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; 3446 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; 3447 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode; 3448 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval; 3449 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception; 3450 for (i = 0; i < 3; i++) { 3451 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; 3452 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; 3453 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; 3454 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; 3455 } 3456 } 3457 } 3458 return 0; 3459 } 3460 } 3461 3462 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; 3463 3464 if (state->revision == 0x8090) 3465 val = dib8000_read_word(state, 572); 3466 else 3467 val = dib8000_read_word(state, 570); 3468 c->inversion = (val & 0x40) >> 6; 3469 switch ((val & 0x30) >> 4) { 3470 case 1: 3471 c->transmission_mode = TRANSMISSION_MODE_2K; 3472 dprintk("dib8000_get_frontend: transmission mode 2K\n"); 3473 break; 3474 case 2: 3475 c->transmission_mode = TRANSMISSION_MODE_4K; 3476 dprintk("dib8000_get_frontend: transmission mode 4K\n"); 3477 break; 3478 case 3: 3479 default: 3480 c->transmission_mode = TRANSMISSION_MODE_8K; 3481 dprintk("dib8000_get_frontend: transmission mode 8K\n"); 3482 break; 3483 } 3484 3485 switch (val & 0x3) { 3486 case 0: 3487 c->guard_interval = GUARD_INTERVAL_1_32; 3488 dprintk("dib8000_get_frontend: Guard Interval = 1/32\n"); 3489 break; 3490 case 1: 3491 c->guard_interval = GUARD_INTERVAL_1_16; 3492 dprintk("dib8000_get_frontend: Guard Interval = 1/16\n"); 3493 break; 3494 case 2: 3495 dprintk("dib8000_get_frontend: Guard Interval = 1/8\n"); 3496 c->guard_interval = GUARD_INTERVAL_1_8; 3497 break; 3498 case 3: 3499 dprintk("dib8000_get_frontend: Guard Interval = 1/4\n"); 3500 c->guard_interval = GUARD_INTERVAL_1_4; 3501 break; 3502 } 3503 3504 val = dib8000_read_word(state, 505); 3505 c->isdbt_partial_reception = val & 1; 3506 dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception); 3507 3508 for (i = 0; i < 3; i++) { 3509 int show; 3510 3511 val = dib8000_read_word(state, 493 + i) & 0x0f; 3512 c->layer[i].segment_count = val; 3513 3514 if (val == 0 || val > 13) 3515 show = 0; 3516 else 3517 show = 1; 3518 3519 if (show) 3520 dprintk("dib8000_get_frontend: Layer %d segments = %d\n", 3521 i, c->layer[i].segment_count); 3522 3523 val = dib8000_read_word(state, 499 + i) & 0x3; 3524 /* Interleaving can be 0, 1, 2 or 4 */ 3525 if (val == 3) 3526 val = 4; 3527 c->layer[i].interleaving = val; 3528 if (show) 3529 dprintk("dib8000_get_frontend: Layer %d time_intlv = %d\n", 3530 i, c->layer[i].interleaving); 3531 3532 val = dib8000_read_word(state, 481 + i); 3533 switch (val & 0x7) { 3534 case 1: 3535 c->layer[i].fec = FEC_1_2; 3536 if (show) 3537 dprintk("dib8000_get_frontend: Layer %d Code Rate = 1/2\n", i); 3538 break; 3539 case 2: 3540 c->layer[i].fec = FEC_2_3; 3541 if (show) 3542 dprintk("dib8000_get_frontend: Layer %d Code Rate = 2/3\n", i); 3543 break; 3544 case 3: 3545 c->layer[i].fec = FEC_3_4; 3546 if (show) 3547 dprintk("dib8000_get_frontend: Layer %d Code Rate = 3/4\n", i); 3548 break; 3549 case 5: 3550 c->layer[i].fec = FEC_5_6; 3551 if (show) 3552 dprintk("dib8000_get_frontend: Layer %d Code Rate = 5/6\n", i); 3553 break; 3554 default: 3555 c->layer[i].fec = FEC_7_8; 3556 if (show) 3557 dprintk("dib8000_get_frontend: Layer %d Code Rate = 7/8\n", i); 3558 break; 3559 } 3560 3561 val = dib8000_read_word(state, 487 + i); 3562 switch (val & 0x3) { 3563 case 0: 3564 c->layer[i].modulation = DQPSK; 3565 if (show) 3566 dprintk("dib8000_get_frontend: Layer %d DQPSK\n", i); 3567 break; 3568 case 1: 3569 c->layer[i].modulation = QPSK; 3570 if (show) 3571 dprintk("dib8000_get_frontend: Layer %d QPSK\n", i); 3572 break; 3573 case 2: 3574 c->layer[i].modulation = QAM_16; 3575 if (show) 3576 dprintk("dib8000_get_frontend: Layer %d QAM16\n", i); 3577 break; 3578 case 3: 3579 default: 3580 c->layer[i].modulation = QAM_64; 3581 if (show) 3582 dprintk("dib8000_get_frontend: Layer %d QAM64\n", i); 3583 break; 3584 } 3585 } 3586 3587 /* synchronize the cache with the other frontends */ 3588 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3589 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode; 3590 state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion; 3591 state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode; 3592 state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval; 3593 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception; 3594 for (i = 0; i < 3; i++) { 3595 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count; 3596 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving; 3597 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec; 3598 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation; 3599 } 3600 } 3601 return 0; 3602} 3603 3604static int dib8000_set_frontend(struct dvb_frontend *fe) 3605{ 3606 struct dib8000_state *state = fe->demodulator_priv; 3607 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 3608 int l, i, active, time, time_slave = 0; 3609 u8 exit_condition, index_frontend; 3610 unsigned long delay, callback_time; 3611 3612 if (c->frequency == 0) { 3613 dprintk("dib8000: must at least specify frequency\n"); 3614 return 0; 3615 } 3616 3617 if (c->bandwidth_hz == 0) { 3618 dprintk("dib8000: no bandwidth specified, set to default\n"); 3619 c->bandwidth_hz = 6000000; 3620 } 3621 3622 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3623 /* synchronization of the cache */ 3624 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; 3625 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); 3626 3627 /* set output mode and diversity input */ 3628 if (state->revision != 0x8090) { 3629 dib8000_set_diversity_in(state->fe[index_frontend], 1); 3630 if (index_frontend != 0) 3631 dib8000_set_output_mode(state->fe[index_frontend], 3632 OUTMODE_DIVERSITY); 3633 else 3634 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); 3635 } else { 3636 dib8096p_set_diversity_in(state->fe[index_frontend], 1); 3637 if (index_frontend != 0) 3638 dib8096p_set_output_mode(state->fe[index_frontend], 3639 OUTMODE_DIVERSITY); 3640 else 3641 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); 3642 } 3643 3644 /* tune the tuner */ 3645 if (state->fe[index_frontend]->ops.tuner_ops.set_params) 3646 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]); 3647 3648 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); 3649 } 3650 3651 /* turn off the diversity of the last chip */ 3652 if (state->revision != 0x8090) 3653 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0); 3654 else 3655 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0); 3656 3657 /* start up the AGC */ 3658 do { 3659 time = dib8000_agc_startup(state->fe[0]); 3660 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3661 time_slave = dib8000_agc_startup(state->fe[index_frontend]); 3662 if (time == 0) 3663 time = time_slave; 3664 else if ((time_slave != 0) && (time_slave > time)) 3665 time = time_slave; 3666 } 3667 if (time == 0) 3668 break; 3669 3670 /* 3671 * Despite dib8000_agc_startup returns time at a 0.1 ms range, 3672 * the actual sleep time depends on CONFIG_HZ. The worse case 3673 * is when CONFIG_HZ=100. In such case, the minimum granularity 3674 * is 10ms. On some real field tests, the tuner sometimes don't 3675 * lock when this timer is lower than 10ms. So, enforce a 10ms 3676 * granularity. 3677 */ 3678 time = 10 * (time + 99)/100; 3679 usleep_range(time * 1000, (time + 1) * 1000); 3680 exit_condition = 1; 3681 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3682 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { 3683 exit_condition = 0; 3684 break; 3685 } 3686 } 3687 } while (exit_condition == 0); 3688 3689 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3690 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); 3691 3692 active = 1; 3693 do { 3694 callback_time = 0; 3695 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3696 delay = dib8000_tune(state->fe[index_frontend]); 3697 if (delay != 0) { 3698 delay = jiffies + usecs_to_jiffies(100 * delay); 3699 if (!callback_time || delay < callback_time) 3700 callback_time = delay; 3701 } 3702 3703 /* we are in autosearch */ 3704 if (state->channel_parameters_set == 0) { /* searching */ 3705 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) { 3706 dprintk("autosearch succeeded on fe%i\n", index_frontend); 3707 dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */ 3708 state->channel_parameters_set = 1; 3709 3710 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) { 3711 if (l != index_frontend) { /* and for all frontend except the successful one */ 3712 dprintk("Restarting frontend %d\n", l); 3713 dib8000_tune_restart_from_demod(state->fe[l]); 3714 3715 state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; 3716 state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; 3717 state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode; 3718 state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval; 3719 state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception; 3720 for (i = 0; i < 3; i++) { 3721 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; 3722 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; 3723 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; 3724 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; 3725 } 3726 3727 } 3728 } 3729 } 3730 } 3731 } 3732 /* tuning is done when the master frontend is done (failed or success) */ 3733 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED || 3734 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED || 3735 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) { 3736 active = 0; 3737 /* we need to wait for all frontends to be finished */ 3738 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3739 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP) 3740 active = 1; 3741 } 3742 if (active == 0) 3743 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0])); 3744 } 3745 3746 if ((active == 1) && (callback_time == 0)) { 3747 dprintk("strange callback time something went wrong\n"); 3748 active = 0; 3749 } 3750 3751 while ((active == 1) && (time_before(jiffies, callback_time))) 3752 msleep(100); 3753 } while (active); 3754 3755 /* set output mode */ 3756 if (state->revision != 0x8090) 3757 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); 3758 else { 3759 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); 3760 if (state->cfg.enMpegOutput == 0) { 3761 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX); 3762 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); 3763 } 3764 } 3765 3766 return 0; 3767} 3768 3769static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat); 3770 3771static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat) 3772{ 3773 struct dib8000_state *state = fe->demodulator_priv; 3774 u16 lock_slave = 0, lock; 3775 u8 index_frontend; 3776 3777 lock = dib8000_read_lock(fe); 3778 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3779 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); 3780 3781 *stat = 0; 3782 3783 if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1)) 3784 *stat |= FE_HAS_SIGNAL; 3785 3786 if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */ 3787 *stat |= FE_HAS_CARRIER; 3788 3789 if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */ 3790 *stat |= FE_HAS_SYNC; 3791 3792 if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */ 3793 *stat |= FE_HAS_LOCK; 3794 3795 if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) { 3796 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ 3797 if (lock & 0x01) 3798 *stat |= FE_HAS_VITERBI; 3799 3800 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */ 3801 if (lock & 0x01) 3802 *stat |= FE_HAS_VITERBI; 3803 3804 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */ 3805 if (lock & 0x01) 3806 *stat |= FE_HAS_VITERBI; 3807 } 3808 dib8000_get_stats(fe, *stat); 3809 3810 return 0; 3811} 3812 3813static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber) 3814{ 3815 struct dib8000_state *state = fe->demodulator_priv; 3816 3817 /* 13 segments */ 3818 if (state->revision == 0x8090) 3819 *ber = (dib8000_read_word(state, 562) << 16) | 3820 dib8000_read_word(state, 563); 3821 else 3822 *ber = (dib8000_read_word(state, 560) << 16) | 3823 dib8000_read_word(state, 561); 3824 return 0; 3825} 3826 3827static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) 3828{ 3829 struct dib8000_state *state = fe->demodulator_priv; 3830 3831 /* packet error on 13 seg */ 3832 if (state->revision == 0x8090) 3833 *unc = dib8000_read_word(state, 567); 3834 else 3835 *unc = dib8000_read_word(state, 565); 3836 return 0; 3837} 3838 3839static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 3840{ 3841 struct dib8000_state *state = fe->demodulator_priv; 3842 u8 index_frontend; 3843 u16 val; 3844 3845 *strength = 0; 3846 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { 3847 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); 3848 if (val > 65535 - *strength) 3849 *strength = 65535; 3850 else 3851 *strength += val; 3852 } 3853 3854 val = 65535 - dib8000_read_word(state, 390); 3855 if (val > 65535 - *strength) 3856 *strength = 65535; 3857 else 3858 *strength += val; 3859 return 0; 3860} 3861 3862static u32 dib8000_get_snr(struct dvb_frontend *fe) 3863{ 3864 struct dib8000_state *state = fe->demodulator_priv; 3865 u32 n, s, exp; 3866 u16 val; 3867 3868 if (state->revision != 0x8090) 3869 val = dib8000_read_word(state, 542); 3870 else 3871 val = dib8000_read_word(state, 544); 3872 n = (val >> 6) & 0xff; 3873 exp = (val & 0x3f); 3874 if ((exp & 0x20) != 0) 3875 exp -= 0x40; 3876 n <<= exp+16; 3877 3878 if (state->revision != 0x8090) 3879 val = dib8000_read_word(state, 543); 3880 else 3881 val = dib8000_read_word(state, 545); 3882 s = (val >> 6) & 0xff; 3883 exp = (val & 0x3f); 3884 if ((exp & 0x20) != 0) 3885 exp -= 0x40; 3886 s <<= exp+16; 3887 3888 if (n > 0) { 3889 u32 t = (s/n) << 16; 3890 return t + ((s << 16) - n*t) / n; 3891 } 3892 return 0xffffffff; 3893} 3894 3895static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr) 3896{ 3897 struct dib8000_state *state = fe->demodulator_priv; 3898 u8 index_frontend; 3899 u32 snr_master; 3900 3901 snr_master = dib8000_get_snr(fe); 3902 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) 3903 snr_master += dib8000_get_snr(state->fe[index_frontend]); 3904 3905 if ((snr_master >> 16) != 0) { 3906 snr_master = 10*intlog10(snr_master>>16); 3907 *snr = snr_master / ((1 << 24) / 10); 3908 } 3909 else 3910 *snr = 0; 3911 3912 return 0; 3913} 3914 3915struct per_layer_regs { 3916 u16 lock, ber, per; 3917}; 3918 3919static const struct per_layer_regs per_layer_regs[] = { 3920 { 554, 560, 562 }, 3921 { 555, 576, 578 }, 3922 { 556, 581, 583 }, 3923}; 3924 3925struct linear_segments { 3926 unsigned x; 3927 signed y; 3928}; 3929 3930/* 3931 * Table to estimate signal strength in dBm. 3932 * This table was empirically determinated by measuring the signal 3933 * strength generated by a DTA-2111 RF generator directly connected into 3934 * a dib8076 device (a PixelView PV-D231U stick), using a good quality 3935 * 3 meters RC6 cable and good RC6 connectors. 3936 * The real value can actually be different on other devices, depending 3937 * on several factors, like if LNA is enabled or not, if diversity is 3938 * enabled, type of connectors, etc. 3939 * Yet, it is better to use this measure in dB than a random non-linear 3940 * percentage value, especially for antenna adjustments. 3941 * On my tests, the precision of the measure using this table is about 3942 * 0.5 dB, with sounds reasonable enough. 3943 */ 3944static struct linear_segments strength_to_db_table[] = { 3945 { 55953, 108500 }, /* -22.5 dBm */ 3946 { 55394, 108000 }, 3947 { 53834, 107000 }, 3948 { 52863, 106000 }, 3949 { 52239, 105000 }, 3950 { 52012, 104000 }, 3951 { 51803, 103000 }, 3952 { 51566, 102000 }, 3953 { 51356, 101000 }, 3954 { 51112, 100000 }, 3955 { 50869, 99000 }, 3956 { 50600, 98000 }, 3957 { 50363, 97000 }, 3958 { 50117, 96000 }, /* -35 dBm */ 3959 { 49889, 95000 }, 3960 { 49680, 94000 }, 3961 { 49493, 93000 }, 3962 { 49302, 92000 }, 3963 { 48929, 91000 }, 3964 { 48416, 90000 }, 3965 { 48035, 89000 }, 3966 { 47593, 88000 }, 3967 { 47282, 87000 }, 3968 { 46953, 86000 }, 3969 { 46698, 85000 }, 3970 { 45617, 84000 }, 3971 { 44773, 83000 }, 3972 { 43845, 82000 }, 3973 { 43020, 81000 }, 3974 { 42010, 80000 }, /* -51 dBm */ 3975 { 0, 0 }, 3976}; 3977 3978static u32 interpolate_value(u32 value, struct linear_segments *segments, 3979 unsigned len) 3980{ 3981 u64 tmp64; 3982 u32 dx; 3983 s32 dy; 3984 int i, ret; 3985 3986 if (value >= segments[0].x) 3987 return segments[0].y; 3988 if (value < segments[len-1].x) 3989 return segments[len-1].y; 3990 3991 for (i = 1; i < len - 1; i++) { 3992 /* If value is identical, no need to interpolate */ 3993 if (value == segments[i].x) 3994 return segments[i].y; 3995 if (value > segments[i].x) 3996 break; 3997 } 3998 3999 /* Linear interpolation between the two (x,y) points */ 4000 dy = segments[i - 1].y - segments[i].y; 4001 dx = segments[i - 1].x - segments[i].x; 4002 4003 tmp64 = value - segments[i].x; 4004 tmp64 *= dy; 4005 do_div(tmp64, dx); 4006 ret = segments[i].y + tmp64; 4007 4008 return ret; 4009} 4010 4011static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer) 4012{ 4013 struct dib8000_state *state = fe->demodulator_priv; 4014 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 4015 int ini_layer, end_layer, i; 4016 u64 time_us, tmp64; 4017 u32 tmp, denom; 4018 int guard, rate_num, rate_denum = 1, bits_per_symbol, nsegs; 4019 int interleaving = 0, fft_div; 4020 4021 if (layer >= 0) { 4022 ini_layer = layer; 4023 end_layer = layer + 1; 4024 } else { 4025 ini_layer = 0; 4026 end_layer = 3; 4027 } 4028 4029 switch (c->guard_interval) { 4030 case GUARD_INTERVAL_1_4: 4031 guard = 4; 4032 break; 4033 case GUARD_INTERVAL_1_8: 4034 guard = 8; 4035 break; 4036 case GUARD_INTERVAL_1_16: 4037 guard = 16; 4038 break; 4039 default: 4040 case GUARD_INTERVAL_1_32: 4041 guard = 32; 4042 break; 4043 } 4044 4045 switch (c->transmission_mode) { 4046 case TRANSMISSION_MODE_2K: 4047 fft_div = 4; 4048 break; 4049 case TRANSMISSION_MODE_4K: 4050 fft_div = 2; 4051 break; 4052 default: 4053 case TRANSMISSION_MODE_8K: 4054 fft_div = 1; 4055 break; 4056 } 4057 4058 denom = 0; 4059 for (i = ini_layer; i < end_layer; i++) { 4060 nsegs = c->layer[i].segment_count; 4061 if (nsegs == 0 || nsegs > 13) 4062 continue; 4063 4064 switch (c->layer[i].modulation) { 4065 case DQPSK: 4066 case QPSK: 4067 bits_per_symbol = 2; 4068 break; 4069 case QAM_16: 4070 bits_per_symbol = 4; 4071 break; 4072 default: 4073 case QAM_64: 4074 bits_per_symbol = 6; 4075 break; 4076 } 4077 4078 switch (c->layer[i].fec) { 4079 case FEC_1_2: 4080 rate_num = 1; 4081 rate_denum = 2; 4082 break; 4083 case FEC_2_3: 4084 rate_num = 2; 4085 rate_denum = 3; 4086 break; 4087 case FEC_3_4: 4088 rate_num = 3; 4089 rate_denum = 4; 4090 break; 4091 case FEC_5_6: 4092 rate_num = 5; 4093 rate_denum = 6; 4094 break; 4095 default: 4096 case FEC_7_8: 4097 rate_num = 7; 4098 rate_denum = 8; 4099 break; 4100 } 4101 4102 interleaving = c->layer[i].interleaving; 4103 4104 denom += bits_per_symbol * rate_num * fft_div * nsegs * 384; 4105 } 4106 4107 /* If all goes wrong, wait for 1s for the next stats */ 4108 if (!denom) 4109 return 0; 4110 4111 /* Estimate the period for the total bit rate */ 4112 time_us = rate_denum * (1008 * 1562500L); 4113 tmp64 = time_us; 4114 do_div(tmp64, guard); 4115 time_us = time_us + tmp64; 4116 time_us += denom / 2; 4117 do_div(time_us, denom); 4118 4119 tmp = 1008 * 96 * interleaving; 4120 time_us += tmp + tmp / guard; 4121 4122 return time_us; 4123} 4124 4125static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat) 4126{ 4127 struct dib8000_state *state = fe->demodulator_priv; 4128 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; 4129 int i; 4130 int show_per_stats = 0; 4131 u32 time_us = 0, snr, val; 4132 u64 blocks; 4133 s32 db; 4134 u16 strength; 4135 4136 /* Get Signal strength */ 4137 dib8000_read_signal_strength(fe, &strength); 4138 val = strength; 4139 db = interpolate_value(val, 4140 strength_to_db_table, 4141 ARRAY_SIZE(strength_to_db_table)) - 131000; 4142 c->strength.stat[0].svalue = db; 4143 4144 /* UCB/BER/CNR measures require lock */ 4145 if (!(stat & FE_HAS_LOCK)) { 4146 c->cnr.len = 1; 4147 c->block_count.len = 1; 4148 c->block_error.len = 1; 4149 c->post_bit_error.len = 1; 4150 c->post_bit_count.len = 1; 4151 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4152 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4153 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4154 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4155 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 4156 return 0; 4157 } 4158 4159 /* Check if time for stats was elapsed */ 4160 if (time_after(jiffies, state->per_jiffies_stats)) { 4161 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); 4162 4163 /* Get SNR */ 4164 snr = dib8000_get_snr(fe); 4165 for (i = 1; i < MAX_NUMBER_OF_FRONTENDS; i++) { 4166 if (state->fe[i]) 4167 snr += dib8000_get_snr(state->fe[i]); 4168 } 4169 snr = snr >> 16; 4170 4171 if (snr) { 4172 snr = 10 * intlog10(snr); 4173 snr = (1000L * snr) >> 24; 4174 } else { 4175 snr = 0; 4176 } 4177 c->cnr.stat[0].svalue = snr; 4178 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 4179 4180 /* Get UCB measures */ 4181 dib8000_read_unc_blocks(fe, &val); 4182 if (val < state->init_ucb) 4183 state->init_ucb += 0x100000000LL; 4184 4185 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 4186 c->block_error.stat[0].uvalue = val + state->init_ucb; 4187 4188 /* Estimate the number of packets based on bitrate */ 4189 if (!time_us) 4190 time_us = dib8000_get_time_us(fe, -1); 4191 4192 if (time_us) { 4193 blocks = 1250000ULL * 1000000ULL; 4194 do_div(blocks, time_us * 8 * 204); 4195 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 4196 c->block_count.stat[0].uvalue += blocks; 4197 } 4198 4199 show_per_stats = 1; 4200 } 4201 4202 /* Get post-BER measures */ 4203 if (time_after(jiffies, state->ber_jiffies_stats)) { 4204 time_us = dib8000_get_time_us(fe, -1); 4205 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); 4206 4207 dprintk("Next all layers stats available in %u us.\n", time_us); 4208 4209 dib8000_read_ber(fe, &val); 4210 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 4211 c->post_bit_error.stat[0].uvalue += val; 4212 4213 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 4214 c->post_bit_count.stat[0].uvalue += 100000000; 4215 } 4216 4217 if (state->revision < 0x8002) 4218 return 0; 4219 4220 c->block_error.len = 4; 4221 c->post_bit_error.len = 4; 4222 c->post_bit_count.len = 4; 4223 4224 for (i = 0; i < 3; i++) { 4225 unsigned nsegs = c->layer[i].segment_count; 4226 4227 if (nsegs == 0 || nsegs > 13) 4228 continue; 4229 4230 time_us = 0; 4231 4232 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) { 4233 time_us = dib8000_get_time_us(fe, i); 4234 4235 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000); 4236 dprintk("Next layer %c stats will be available in %u us\n", 4237 'A' + i, time_us); 4238 4239 val = dib8000_read_word(state, per_layer_regs[i].ber); 4240 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 4241 c->post_bit_error.stat[1 + i].uvalue += val; 4242 4243 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 4244 c->post_bit_count.stat[1 + i].uvalue += 100000000; 4245 } 4246 4247 if (show_per_stats) { 4248 val = dib8000_read_word(state, per_layer_regs[i].per); 4249 4250 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER; 4251 c->block_error.stat[1 + i].uvalue += val; 4252 4253 if (!time_us) 4254 time_us = dib8000_get_time_us(fe, i); 4255 if (time_us) { 4256 blocks = 1250000ULL * 1000000ULL; 4257 do_div(blocks, time_us * 8 * 204); 4258 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 4259 c->block_count.stat[0].uvalue += blocks; 4260 } 4261 } 4262 } 4263 return 0; 4264} 4265 4266static int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave) 4267{ 4268 struct dib8000_state *state = fe->demodulator_priv; 4269 u8 index_frontend = 1; 4270 4271 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) 4272 index_frontend++; 4273 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) { 4274 dprintk("set slave fe %p to index %i\n", fe_slave, index_frontend); 4275 state->fe[index_frontend] = fe_slave; 4276 return 0; 4277 } 4278 4279 dprintk("too many slave frontend\n"); 4280 return -ENOMEM; 4281} 4282 4283static struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) 4284{ 4285 struct dib8000_state *state = fe->demodulator_priv; 4286 4287 if (slave_index >= MAX_NUMBER_OF_FRONTENDS) 4288 return NULL; 4289 return state->fe[slave_index]; 4290} 4291 4292static int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, 4293 u8 default_addr, u8 first_addr, u8 is_dib8096p) 4294{ 4295 int k = 0, ret = 0; 4296 u8 new_addr = 0; 4297 struct i2c_device client = {.adap = host }; 4298 4299 client.i2c_write_buffer = kzalloc(4, GFP_KERNEL); 4300 if (!client.i2c_write_buffer) { 4301 dprintk("%s: not enough memory\n", __func__); 4302 return -ENOMEM; 4303 } 4304 client.i2c_read_buffer = kzalloc(4, GFP_KERNEL); 4305 if (!client.i2c_read_buffer) { 4306 dprintk("%s: not enough memory\n", __func__); 4307 ret = -ENOMEM; 4308 goto error_memory_read; 4309 } 4310 client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL); 4311 if (!client.i2c_buffer_lock) { 4312 dprintk("%s: not enough memory\n", __func__); 4313 ret = -ENOMEM; 4314 goto error_memory_lock; 4315 } 4316 mutex_init(client.i2c_buffer_lock); 4317 4318 for (k = no_of_demods - 1; k >= 0; k--) { 4319 /* designated i2c address */ 4320 new_addr = first_addr + (k << 1); 4321 4322 client.addr = new_addr; 4323 if (!is_dib8096p) 4324 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ 4325 if (dib8000_identify(&client) == 0) { 4326 /* sram lead in, rdy */ 4327 if (!is_dib8096p) 4328 dib8000_i2c_write16(&client, 1287, 0x0003); 4329 client.addr = default_addr; 4330 if (dib8000_identify(&client) == 0) { 4331 dprintk("#%d: not identified\n", k); 4332 ret = -EINVAL; 4333 goto error; 4334 } 4335 } 4336 4337 /* start diversity to pull_down div_str - just for i2c-enumeration */ 4338 dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6)); 4339 4340 /* set new i2c address and force divstart */ 4341 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2); 4342 client.addr = new_addr; 4343 dib8000_identify(&client); 4344 4345 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); 4346 } 4347 4348 for (k = 0; k < no_of_demods; k++) { 4349 new_addr = first_addr | (k << 1); 4350 client.addr = new_addr; 4351 4352 // unforce divstr 4353 dib8000_i2c_write16(&client, 1285, new_addr << 2); 4354 4355 /* deactivate div - it was just for i2c-enumeration */ 4356 dib8000_i2c_write16(&client, 1286, 0); 4357 } 4358 4359error: 4360 kfree(client.i2c_buffer_lock); 4361error_memory_lock: 4362 kfree(client.i2c_read_buffer); 4363error_memory_read: 4364 kfree(client.i2c_write_buffer); 4365 4366 return ret; 4367} 4368 4369static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune) 4370{ 4371 tune->min_delay_ms = 1000; 4372 tune->step_size = 0; 4373 tune->max_drift = 0; 4374 return 0; 4375} 4376 4377static void dib8000_release(struct dvb_frontend *fe) 4378{ 4379 struct dib8000_state *st = fe->demodulator_priv; 4380 u8 index_frontend; 4381 4382 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++) 4383 dvb_frontend_detach(st->fe[index_frontend]); 4384 4385 dibx000_exit_i2c_master(&st->i2c_master); 4386 i2c_del_adapter(&st->dib8096p_tuner_adap); 4387 kfree(st->fe[0]); 4388 kfree(st); 4389} 4390 4391static struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating) 4392{ 4393 struct dib8000_state *st = fe->demodulator_priv; 4394 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); 4395} 4396 4397static int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) 4398{ 4399 struct dib8000_state *st = fe->demodulator_priv; 4400 u16 val = dib8000_read_word(st, 299) & 0xffef; 4401 val |= (onoff & 0x1) << 4; 4402 4403 dprintk("pid filter enabled %d\n", onoff); 4404 return dib8000_write_word(st, 299, val); 4405} 4406 4407static int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 4408{ 4409 struct dib8000_state *st = fe->demodulator_priv; 4410 dprintk("Index %x, PID %d, OnOff %d\n", id, pid, onoff); 4411 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0); 4412} 4413 4414static const struct dvb_frontend_ops dib8000_ops = { 4415 .delsys = { SYS_ISDBT }, 4416 .info = { 4417 .name = "DiBcom 8000 ISDB-T", 4418 .frequency_min_hz = 44250 * kHz, 4419 .frequency_max_hz = 867250 * kHz, 4420 .frequency_stepsize_hz = 62500, 4421 .caps = FE_CAN_INVERSION_AUTO | 4422 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 4423 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 4424 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 4425 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO, 4426 }, 4427 4428 .release = dib8000_release, 4429 4430 .init = dib8000_wakeup, 4431 .sleep = dib8000_sleep, 4432 4433 .set_frontend = dib8000_set_frontend, 4434 .get_tune_settings = dib8000_fe_get_tune_settings, 4435 .get_frontend = dib8000_get_frontend, 4436 4437 .read_status = dib8000_read_status, 4438 .read_ber = dib8000_read_ber, 4439 .read_signal_strength = dib8000_read_signal_strength, 4440 .read_snr = dib8000_read_snr, 4441 .read_ucblocks = dib8000_read_unc_blocks, 4442}; 4443 4444static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg) 4445{ 4446 struct dvb_frontend *fe; 4447 struct dib8000_state *state; 4448 4449 dprintk("dib8000_init\n"); 4450 4451 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); 4452 if (state == NULL) 4453 return NULL; 4454 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL); 4455 if (fe == NULL) 4456 goto error; 4457 4458 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); 4459 state->i2c.adap = i2c_adap; 4460 state->i2c.addr = i2c_addr; 4461 state->i2c.i2c_write_buffer = state->i2c_write_buffer; 4462 state->i2c.i2c_read_buffer = state->i2c_read_buffer; 4463 mutex_init(&state->i2c_buffer_lock); 4464 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock; 4465 state->gpio_val = cfg->gpio_val; 4466 state->gpio_dir = cfg->gpio_dir; 4467 4468 /* Ensure the output mode remains at the previous default if it's 4469 * not specifically set by the caller. 4470 */ 4471 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) 4472 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; 4473 4474 state->fe[0] = fe; 4475 fe->demodulator_priv = state; 4476 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); 4477 4478 state->timf_default = cfg->pll->timf; 4479 4480 if (dib8000_identify(&state->i2c) == 0) { 4481 kfree(fe); 4482 goto error; 4483 } 4484 4485 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); 4486 4487 /* init 8096p tuner adapter */ 4488 strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface", 4489 sizeof(state->dib8096p_tuner_adap.name)); 4490 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo; 4491 state->dib8096p_tuner_adap.algo_data = NULL; 4492 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent; 4493 i2c_set_adapdata(&state->dib8096p_tuner_adap, state); 4494 i2c_add_adapter(&state->dib8096p_tuner_adap); 4495 4496 dib8000_reset(fe); 4497 4498 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */ 4499 state->current_demod_bw = 6000; 4500 4501 return fe; 4502 4503error: 4504 kfree(state); 4505 return NULL; 4506} 4507 4508void *dib8000_attach(struct dib8000_ops *ops) 4509{ 4510 if (!ops) 4511 return NULL; 4512 4513 ops->pwm_agc_reset = dib8000_pwm_agc_reset; 4514 ops->get_dc_power = dib8090p_get_dc_power; 4515 ops->set_gpio = dib8000_set_gpio; 4516 ops->get_slave_frontend = dib8000_get_slave_frontend; 4517 ops->set_tune_state = dib8000_set_tune_state; 4518 ops->pid_filter_ctrl = dib8000_pid_filter_ctrl; 4519 ops->get_adc_power = dib8000_get_adc_power; 4520 ops->update_pll = dib8000_update_pll; 4521 ops->tuner_sleep = dib8096p_tuner_sleep; 4522 ops->get_tune_state = dib8000_get_tune_state; 4523 ops->get_i2c_tuner = dib8096p_get_i2c_tuner; 4524 ops->set_slave_frontend = dib8000_set_slave_frontend; 4525 ops->pid_filter = dib8000_pid_filter; 4526 ops->ctrl_timf = dib8000_ctrl_timf; 4527 ops->init = dib8000_init; 4528 ops->get_i2c_master = dib8000_get_i2c_master; 4529 ops->i2c_enumeration = dib8000_i2c_enumeration; 4530 ops->set_wbd_ref = dib8000_set_wbd_ref; 4531 4532 return ops; 4533} 4534EXPORT_SYMBOL_GPL(dib8000_attach); 4535 4536MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@parrot.com, Patrick Boettcher <patrick.boettcher@posteo.de>"); 4537MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator"); 4538MODULE_LICENSE("GPL");
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