pl320-ipc.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright 2012 Calxeda, Inc.
  4 */
  5#include <linux/types.h>
  6#include <linux/err.h>
  7#include <linux/delay.h>
  8#include <linux/export.h>
  9#include <linux/io.h>
 10#include <linux/interrupt.h>
 11#include <linux/completion.h>
 12#include <linux/mutex.h>
 13#include <linux/notifier.h>
 14#include <linux/spinlock.h>
 15#include <linux/device.h>
 16#include <linux/amba/bus.h>
 17
 18#include <linux/pl320-ipc.h>
 19
 20#define IPCMxSOURCE(m)		((m) * 0x40)
 21#define IPCMxDSET(m)		(((m) * 0x40) + 0x004)
 22#define IPCMxDCLEAR(m)		(((m) * 0x40) + 0x008)
 23#define IPCMxDSTATUS(m)		(((m) * 0x40) + 0x00C)
 24#define IPCMxMODE(m)		(((m) * 0x40) + 0x010)
 25#define IPCMxMSET(m)		(((m) * 0x40) + 0x014)
 26#define IPCMxMCLEAR(m)		(((m) * 0x40) + 0x018)
 27#define IPCMxMSTATUS(m)		(((m) * 0x40) + 0x01C)
 28#define IPCMxSEND(m)		(((m) * 0x40) + 0x020)
 29#define IPCMxDR(m, dr)		(((m) * 0x40) + ((dr) * 4) + 0x024)
 30
 31#define IPCMMIS(irq)		(((irq) * 8) + 0x800)
 32#define IPCMRIS(irq)		(((irq) * 8) + 0x804)
 33
 34#define MBOX_MASK(n)		(1 << (n))
 35#define IPC_TX_MBOX		1
 36#define IPC_RX_MBOX		2
 37
 38#define CHAN_MASK(n)		(1 << (n))
 39#define A9_SOURCE		1
 40#define M3_SOURCE		0
 41
 42static void __iomem *ipc_base;
 43static int ipc_irq;
 44static DEFINE_MUTEX(ipc_m1_lock);
 45static DECLARE_COMPLETION(ipc_completion);
 46static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
 47
 48static void __ipc_send(int mbox, u32 *data)
 49{
 50	int i;
 51	for (i = 0; i < 7; i++)
 52		writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
 53	writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
 54}
 55
 56static u32 __ipc_rcv(int mbox, u32 *data)
 57{
 58	int i;
 59	for (i = 0; i < 7; i++)
 60		data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
 61	return data[1];
 62}
 63
 64/* blocking implementation from the A9 side, not usable in interrupts! */
 65int pl320_ipc_transmit(u32 *data)
 66{
 67	int ret;
 68
 69	mutex_lock(&ipc_m1_lock);
 70
 71	init_completion(&ipc_completion);
 72	__ipc_send(IPC_TX_MBOX, data);
 73	ret = wait_for_completion_timeout(&ipc_completion,
 74					  msecs_to_jiffies(1000));
 75	if (ret == 0) {
 76		ret = -ETIMEDOUT;
 77		goto out;
 78	}
 79
 80	ret = __ipc_rcv(IPC_TX_MBOX, data);
 81out:
 82	mutex_unlock(&ipc_m1_lock);
 83	return ret;
 84}
 85EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
 86
 87static irqreturn_t ipc_handler(int irq, void *dev)
 88{
 89	u32 irq_stat;
 90	u32 data[7];
 91
 92	irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
 93	if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
 94		writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
 95		complete(&ipc_completion);
 96	}
 97	if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
 98		__ipc_rcv(IPC_RX_MBOX, data);
 99		atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
100		writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
101	}
102
103	return IRQ_HANDLED;
104}
105
106int pl320_ipc_register_notifier(struct notifier_block *nb)
107{
108	return atomic_notifier_chain_register(&ipc_notifier, nb);
109}
110EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
111
112int pl320_ipc_unregister_notifier(struct notifier_block *nb)
113{
114	return atomic_notifier_chain_unregister(&ipc_notifier, nb);
115}
116EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
117
118static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
119{
120	int ret;
121
122	ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
123	if (ipc_base == NULL)
124		return -ENOMEM;
125
126	writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
127
128	ipc_irq = adev->irq[0];
129	ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
130	if (ret < 0)
131		goto err;
132
133	/* Init slow mailbox */
134	writel_relaxed(CHAN_MASK(A9_SOURCE),
135		       ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
136	writel_relaxed(CHAN_MASK(M3_SOURCE),
137		       ipc_base + IPCMxDSET(IPC_TX_MBOX));
138	writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
139		       ipc_base + IPCMxMSET(IPC_TX_MBOX));
140
141	/* Init receive mailbox */
142	writel_relaxed(CHAN_MASK(M3_SOURCE),
143		       ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
144	writel_relaxed(CHAN_MASK(A9_SOURCE),
145		       ipc_base + IPCMxDSET(IPC_RX_MBOX));
146	writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
147		       ipc_base + IPCMxMSET(IPC_RX_MBOX));
148
149	return 0;
150err:
151	iounmap(ipc_base);
152	return ret;
153}
154
155static const struct amba_id pl320_ids[] = {
156	{
157		.id	= 0x00041320,
158		.mask	= 0x000fffff,
159	},
160	{ 0, 0 },
161};
162
163static struct amba_driver pl320_driver = {
164	.drv = {
165		.name	= "pl320",
166	},
167	.id_table	= pl320_ids,
168	.probe		= pl320_probe,
169};
170
171static int __init ipc_init(void)
172{
173	return amba_driver_register(&pl320_driver);
174}
175subsys_initcall(ipc_init);