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imx-mailbox.c
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linux-6.19.14/drivers/mailbox/imx-mailbox.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 4 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com> 5 */ 6 7#include <linux/bitfield.h> 8#include <linux/clk.h> 9#include <linux/firmware/imx/ipc.h> 10#include <linux/firmware/imx/s4.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14#include <linux/jiffies.h> 15#include <linux/kernel.h> 16#include <linux/mailbox_controller.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_platform.h> 20#include <linux/platform_device.h> 21#include <linux/pm_runtime.h> 22#include <linux/suspend.h> 23#include <linux/slab.h> 24#include <linux/workqueue.h> 25 26#include "mailbox.h" 27 28#define IMX_MU_CHANS 24 29/* TX0/RX0/RXDB[0-3] */ 30#define IMX_MU_SCU_CHANS 6 31/* TX0/RX0 */ 32#define IMX_MU_S4_CHANS 2 33#define IMX_MU_CHAN_NAME_SIZE 32 34 35#define IMX_MU_V2_PAR_OFF 0x4 36#define IMX_MU_V2_TR_MASK GENMASK(7, 0) 37#define IMX_MU_V2_RR_MASK GENMASK(15, 8) 38 39#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) 40#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) 41 42/* Please not change TX & RX */ 43enum imx_mu_chan_type { 44 IMX_MU_TYPE_TX = 0, /* Tx */ 45 IMX_MU_TYPE_RX = 1, /* Rx */ 46 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ 47 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ 48 IMX_MU_TYPE_RST = 4, /* Reset */ 49 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */ 50}; 51 52enum imx_mu_xcr { 53 IMX_MU_CR, 54 IMX_MU_GIER, 55 IMX_MU_GCR, 56 IMX_MU_TCR, 57 IMX_MU_RCR, 58 IMX_MU_xCR_MAX, 59}; 60 61enum imx_mu_xsr { 62 IMX_MU_SR, 63 IMX_MU_GSR, 64 IMX_MU_TSR, 65 IMX_MU_RSR, 66 IMX_MU_xSR_MAX, 67}; 68 69struct imx_sc_rpc_msg_max { 70 struct imx_sc_rpc_msg hdr; 71 u32 data[30]; 72}; 73 74struct imx_s4_rpc_msg_max { 75 struct imx_s4_rpc_msg hdr; 76 u32 data[254]; 77}; 78 79struct imx_mu_con_priv { 80 unsigned int idx; 81 char irq_desc[IMX_MU_CHAN_NAME_SIZE]; 82 enum imx_mu_chan_type type; 83 struct mbox_chan *chan; 84 struct work_struct txdb_work; 85}; 86 87struct imx_mu_priv { 88 struct device *dev; 89 void __iomem *base; 90 void *msg; 91 spinlock_t xcr_lock; /* control register lock */ 92 93 struct mbox_controller mbox; 94 struct mbox_chan mbox_chans[IMX_MU_CHANS]; 95 96 struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; 97 const struct imx_mu_dcfg *dcfg; 98 struct clk *clk; 99 int irq[IMX_MU_CHANS]; 100 bool suspend; 101 bool side_b; 102 103 u32 xcr[IMX_MU_xCR_MAX]; 104 u32 num_tr; 105 u32 num_rr; 106}; 107 108enum imx_mu_type { 109 IMX_MU_V1, 110 IMX_MU_V2 = BIT(1), 111 IMX_MU_V2_S4 = BIT(15), 112 IMX_MU_V2_IRQ = BIT(16), 113}; 114 115struct imx_mu_dcfg { 116 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); 117 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 118 int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 119 int (*init)(struct imx_mu_priv *priv); 120 enum imx_mu_type type; 121 u32 xTR; /* Transmit Register0 */ 122 u32 xRR; /* Receive Register0 */ 123 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 124 u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 125 bool skip_suspend_flag; 126}; 127 128#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 129#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 130#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 131 132/* General Purpose Interrupt Enable */ 133#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 134/* Receive Interrupt Enable */ 135#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 136/* Transmit Interrupt Enable */ 137#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) 138/* General Purpose Interrupt Request */ 139#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) 140/* MU reset */ 141#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) 142#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) 143 144 145static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) 146{ 147 return container_of(mbox, struct imx_mu_priv, mbox); 148} 149 150static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) 151{ 152 iowrite32(val, priv->base + offs); 153} 154 155static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) 156{ 157 return ioread32(priv->base + offs); 158} 159 160static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) 161{ 162 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; 163 u32 status; 164 u32 can_write; 165 166 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); 167 168 do { 169 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 170 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); 171 } while (!can_write && time_is_after_jiffies64(timeout_time)); 172 173 if (!can_write) { 174 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", 175 val, idx, status); 176 return -ETIME; 177 } 178 179 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); 180 181 return 0; 182} 183 184static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) 185{ 186 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; 187 u32 status; 188 u32 can_read; 189 190 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); 191 192 do { 193 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 194 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); 195 } while (!can_read && time_is_after_jiffies64(timeout_time)); 196 197 if (!can_read) { 198 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", 199 idx, status); 200 return -ETIME; 201 } 202 203 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); 204 dev_dbg(priv->dev, "Read %.8x\n", *val); 205 206 return 0; 207} 208 209static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) 210{ 211 unsigned long flags; 212 u32 val; 213 214 spin_lock_irqsave(&priv->xcr_lock, flags); 215 val = imx_mu_read(priv, priv->dcfg->xCR[type]); 216 val &= ~clr; 217 val |= set; 218 imx_mu_write(priv, val, priv->dcfg->xCR[type]); 219 spin_unlock_irqrestore(&priv->xcr_lock, flags); 220 221 return val; 222} 223 224static int imx_mu_generic_tx(struct imx_mu_priv *priv, 225 struct imx_mu_con_priv *cp, 226 void *data) 227{ 228 u32 *arg = data; 229 u32 val; 230 int ret, count; 231 232 switch (cp->type) { 233 case IMX_MU_TYPE_TX: 234 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); 235 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 236 break; 237 case IMX_MU_TYPE_TXDB: 238 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 239 queue_work(system_bh_wq, &cp->txdb_work); 240 break; 241 case IMX_MU_TYPE_TXDB_V2: 242 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 243 priv->dcfg->xCR[IMX_MU_GCR]); 244 ret = -ETIMEDOUT; 245 count = 0; 246 while (ret && (count < 10)) { 247 ret = 248 readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val, 249 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)), 250 0, 10000); 251 252 if (ret) { 253 dev_warn_ratelimited(priv->dev, 254 "channel type: %d timeout, %d times, retry\n", 255 cp->type, ++count); 256 } 257 } 258 break; 259 default: 260 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 261 return -EINVAL; 262 } 263 264 return 0; 265} 266 267static int imx_mu_generic_rx(struct imx_mu_priv *priv, 268 struct imx_mu_con_priv *cp) 269{ 270 u32 dat; 271 272 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); 273 mbox_chan_received_data(cp->chan, (void *)&dat); 274 275 return 0; 276} 277 278static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, 279 struct imx_mu_con_priv *cp) 280{ 281 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 282 priv->dcfg->xSR[IMX_MU_GSR]); 283 mbox_chan_received_data(cp->chan, NULL); 284 285 return 0; 286} 287 288static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) 289{ 290 u32 *arg = data; 291 u32 num_tr = priv->num_tr; 292 int i, ret; 293 u32 xsr; 294 u32 size, max_size; 295 296 if (priv->dcfg->type & IMX_MU_V2_S4) { 297 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; 298 max_size = sizeof(struct imx_s4_rpc_msg_max); 299 } else { 300 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; 301 max_size = sizeof(struct imx_sc_rpc_msg_max); 302 } 303 304 switch (cp->type) { 305 case IMX_MU_TYPE_TX: 306 /* 307 * msg->hdr.size specifies the number of u32 words while 308 * sizeof yields bytes. 309 */ 310 311 if (size > max_size / 4) { 312 /* 313 * The real message size can be different to 314 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size 315 */ 316 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2); 317 return -EINVAL; 318 } 319 320 for (i = 0; i < num_tr && i < size; i++) 321 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 322 for (; i < size; i++) { 323 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], 324 xsr, 325 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), 326 0, 5 * USEC_PER_SEC); 327 if (ret) { 328 dev_err(priv->dev, "Send data index: %d timeout\n", i); 329 return ret; 330 } 331 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); 332 } 333 334 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); 335 break; 336 default: 337 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 338 return -EINVAL; 339 } 340 341 return 0; 342} 343 344static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 345{ 346 u32 *data; 347 int i, ret; 348 u32 xsr; 349 u32 size, max_size; 350 u32 num_rr = priv->num_rr; 351 352 data = (u32 *)priv->msg; 353 354 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); 355 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 356 357 if (priv->dcfg->type & IMX_MU_V2_S4) { 358 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; 359 max_size = sizeof(struct imx_s4_rpc_msg_max); 360 } else { 361 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; 362 max_size = sizeof(struct imx_sc_rpc_msg_max); 363 } 364 365 if (size > max_size / 4) { 366 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2); 367 return -EINVAL; 368 } 369 370 for (i = 1; i < size; i++) { 371 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, 372 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, 373 5 * USEC_PER_SEC); 374 if (ret) { 375 dev_err(priv->dev, "timeout read idx %d\n", i); 376 return ret; 377 } 378 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); 379 } 380 381 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); 382 mbox_chan_received_data(cp->chan, (void *)priv->msg); 383 384 return 0; 385} 386 387static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, 388 void *data) 389{ 390 struct imx_sc_rpc_msg_max *msg = data; 391 u32 *arg = data; 392 u32 byte_size; 393 int err; 394 int i; 395 396 dev_dbg(priv->dev, "Sending message\n"); 397 398 switch (cp->type) { 399 case IMX_MU_TYPE_TXDB: 400 byte_size = msg->hdr.size * sizeof(u32); 401 if (byte_size > sizeof(*msg)) { 402 /* 403 * The real message size can be different to 404 * struct imx_sc_rpc_msg_max size 405 */ 406 dev_err(priv->dev, 407 "Exceed max msg size (%zu) on TX, got: %i\n", 408 sizeof(*msg), byte_size); 409 return -EINVAL; 410 } 411 412 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, 413 data, byte_size, false); 414 415 /* Send first word */ 416 dev_dbg(priv->dev, "Sending header\n"); 417 imx_mu_write(priv, *arg++, priv->dcfg->xTR); 418 419 /* Send signaling */ 420 dev_dbg(priv->dev, "Sending signaling\n"); 421 imx_mu_xcr_rmw(priv, IMX_MU_GCR, 422 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); 423 424 /* Send words to fill the mailbox */ 425 for (i = 1; i < 4 && i < msg->hdr.size; i++) { 426 dev_dbg(priv->dev, "Sending word %d\n", i); 427 imx_mu_write(priv, *arg++, 428 priv->dcfg->xTR + (i % 4) * 4); 429 } 430 431 /* Send rest of message waiting for remote read */ 432 for (; i < msg->hdr.size; i++) { 433 dev_dbg(priv->dev, "Sending word %d\n", i); 434 err = imx_mu_tx_waiting_write(priv, *arg++, i); 435 if (err) { 436 dev_err(priv->dev, "Timeout tx %d\n", i); 437 return err; 438 } 439 } 440 441 /* Simulate hack for mbox framework */ 442 queue_work(system_bh_wq, &cp->txdb_work); 443 444 break; 445 default: 446 dev_warn_ratelimited(priv->dev, 447 "Send data on wrong channel type: %d\n", 448 cp->type); 449 return -EINVAL; 450 } 451 452 return 0; 453} 454 455static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) 456{ 457 struct imx_sc_rpc_msg_max msg; 458 u32 *data = (u32 *)&msg; 459 u32 byte_size; 460 int err = 0; 461 int i; 462 463 dev_dbg(priv->dev, "Receiving message\n"); 464 465 /* Read header */ 466 dev_dbg(priv->dev, "Receiving header\n"); 467 *data++ = imx_mu_read(priv, priv->dcfg->xRR); 468 byte_size = msg.hdr.size * sizeof(u32); 469 if (byte_size > sizeof(msg)) { 470 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", 471 sizeof(msg), byte_size); 472 err = -EINVAL; 473 goto error; 474 } 475 476 /* Read message waiting they are written */ 477 for (i = 1; i < msg.hdr.size; i++) { 478 dev_dbg(priv->dev, "Receiving word %d\n", i); 479 err = imx_mu_rx_waiting_read(priv, data++, i); 480 if (err) { 481 dev_err(priv->dev, "Timeout rx %d\n", i); 482 goto error; 483 } 484 } 485 486 /* Clear GIP */ 487 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), 488 priv->dcfg->xSR[IMX_MU_GSR]); 489 490 print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, 491 &msg, byte_size, false); 492 493 /* send data to client */ 494 dev_dbg(priv->dev, "Sending message to client\n"); 495 mbox_chan_received_data(cp->chan, (void *)&msg); 496 497 goto exit; 498 499error: 500 mbox_chan_received_data(cp->chan, ERR_PTR(err)); 501 502exit: 503 return err; 504} 505 506static void imx_mu_txdb_work(struct work_struct *t) 507{ 508 struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work); 509 510 mbox_chan_txdone(cp->chan, 0); 511} 512 513static irqreturn_t imx_mu_isr(int irq, void *p) 514{ 515 struct mbox_chan *chan = p; 516 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 517 struct imx_mu_con_priv *cp = chan->con_priv; 518 u32 val, ctrl; 519 520 switch (cp->type) { 521 case IMX_MU_TYPE_TX: 522 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); 523 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); 524 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & 525 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 526 break; 527 case IMX_MU_TYPE_RX: 528 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); 529 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); 530 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & 531 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 532 break; 533 case IMX_MU_TYPE_RXDB: 534 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); 535 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 536 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & 537 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 538 break; 539 case IMX_MU_TYPE_RST: 540 return IRQ_NONE; 541 default: 542 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", 543 cp->type); 544 return IRQ_NONE; 545 } 546 547 if (!val) 548 return IRQ_NONE; 549 550 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && 551 (cp->type == IMX_MU_TYPE_TX)) { 552 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 553 mbox_chan_txdone(chan, 0); 554 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && 555 (cp->type == IMX_MU_TYPE_RX)) { 556 priv->dcfg->rx(priv, cp); 557 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && 558 (cp->type == IMX_MU_TYPE_RXDB)) { 559 priv->dcfg->rxdb(priv, cp); 560 } else { 561 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); 562 return IRQ_NONE; 563 } 564 565 if (priv->suspend) 566 pm_system_wakeup(); 567 568 return IRQ_HANDLED; 569} 570 571static int imx_mu_send_data(struct mbox_chan *chan, void *data) 572{ 573 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 574 struct imx_mu_con_priv *cp = chan->con_priv; 575 576 return priv->dcfg->tx(priv, cp, data); 577} 578 579static int imx_mu_startup(struct mbox_chan *chan) 580{ 581 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 582 struct imx_mu_con_priv *cp = chan->con_priv; 583 unsigned long irq_flag = 0; 584 int ret; 585 586 pm_runtime_get_sync(priv->dev); 587 if (cp->type == IMX_MU_TYPE_TXDB_V2) 588 return 0; 589 590 if (cp->type == IMX_MU_TYPE_TXDB) { 591 /* Tx doorbell don't have ACK support */ 592 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work); 593 return 0; 594 } 595 596 /* IPC MU should be with IRQF_NO_SUSPEND set */ 597 if (!priv->dev->pm_domain) 598 irq_flag |= IRQF_NO_SUSPEND; 599 600 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) 601 irq_flag |= IRQF_SHARED; 602 603 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); 604 if (ret) { 605 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); 606 return ret; 607 } 608 609 switch (cp->type) { 610 case IMX_MU_TYPE_RX: 611 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); 612 break; 613 case IMX_MU_TYPE_RXDB: 614 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); 615 break; 616 default: 617 break; 618 } 619 620 return 0; 621} 622 623static void imx_mu_shutdown(struct mbox_chan *chan) 624{ 625 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 626 struct imx_mu_con_priv *cp = chan->con_priv; 627 int ret; 628 u32 sr; 629 630 if (cp->type == IMX_MU_TYPE_TXDB_V2) { 631 pm_runtime_put_sync(priv->dev); 632 return; 633 } 634 635 if (cp->type == IMX_MU_TYPE_TXDB) { 636 cancel_work_sync(&cp->txdb_work); 637 pm_runtime_put_sync(priv->dev); 638 return; 639 } 640 641 switch (cp->type) { 642 case IMX_MU_TYPE_TX: 643 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); 644 break; 645 case IMX_MU_TYPE_RX: 646 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); 647 break; 648 case IMX_MU_TYPE_RXDB: 649 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); 650 break; 651 case IMX_MU_TYPE_RST: 652 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); 653 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, 654 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); 655 if (ret) 656 dev_warn(priv->dev, "RST channel timeout\n"); 657 break; 658 default: 659 break; 660 } 661 662 free_irq(priv->irq[cp->type], chan); 663 pm_runtime_put_sync(priv->dev); 664} 665 666static const struct mbox_chan_ops imx_mu_ops = { 667 .send_data = imx_mu_send_data, 668 .startup = imx_mu_startup, 669 .shutdown = imx_mu_shutdown, 670}; 671 672static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, 673 const struct of_phandle_args *sp) 674{ 675 u32 type, idx, chan; 676 677 if (sp->args_count != 2) { 678 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 679 return ERR_PTR(-EINVAL); 680 } 681 682 type = sp->args[0]; /* channel type */ 683 idx = sp->args[1]; /* index */ 684 685 switch (type) { 686 case IMX_MU_TYPE_TX: 687 case IMX_MU_TYPE_RX: 688 if (idx != 0) 689 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); 690 chan = type; 691 break; 692 case IMX_MU_TYPE_RXDB: 693 chan = 2 + idx; 694 break; 695 default: 696 dev_err(mbox->dev, "Invalid chan type: %d\n", type); 697 return ERR_PTR(-EINVAL); 698 } 699 700 if (chan >= mbox->num_chans) { 701 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 702 return ERR_PTR(-EINVAL); 703 } 704 705 return &mbox->chans[chan]; 706} 707 708static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, 709 const struct of_phandle_args *sp) 710{ 711 struct mbox_chan *p_chan; 712 u32 type, idx, chan; 713 714 if (sp->args_count != 2) { 715 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 716 return ERR_PTR(-EINVAL); 717 } 718 719 type = sp->args[0]; /* channel type */ 720 idx = sp->args[1]; /* index */ 721 722 /* RST only supports 1 channel */ 723 if ((type == IMX_MU_TYPE_RST) && idx) { 724 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); 725 return ERR_PTR(-EINVAL); 726 } 727 728 chan = type * 4 + idx; 729 if (chan >= mbox->num_chans) { 730 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 731 return ERR_PTR(-EINVAL); 732 } 733 734 p_chan = &mbox->chans[chan]; 735 736 if (type == IMX_MU_TYPE_TXDB_V2) 737 p_chan->txdone_method = TXDONE_BY_ACK; 738 739 return p_chan; 740} 741 742static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, 743 const struct of_phandle_args *sp) 744{ 745 u32 type; 746 747 if (sp->args_count < 1) { 748 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 749 return ERR_PTR(-EINVAL); 750 } 751 752 type = sp->args[0]; /* channel type */ 753 754 /* Only supports TXDB and RXDB */ 755 if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { 756 dev_err(mbox->dev, "Invalid type: %d\n", type); 757 return ERR_PTR(-EINVAL); 758 } 759 760 return imx_mu_xlate(mbox, sp); 761} 762 763static void imx_mu_get_tr_rr(struct imx_mu_priv *priv) 764{ 765 u32 val; 766 767 if (priv->dcfg->type & IMX_MU_V2) { 768 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF); 769 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); 770 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); 771 } else { 772 priv->num_tr = 4; 773 priv->num_rr = 4; 774 } 775} 776 777static int imx_mu_init_generic(struct imx_mu_priv *priv) 778{ 779 unsigned int i; 780 unsigned int val; 781 782 if (priv->num_rr > 4 || priv->num_tr > 4) { 783 WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); 784 return -EOPNOTSUPP; 785 } 786 787 for (i = 0; i < IMX_MU_CHANS; i++) { 788 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 789 790 cp->idx = i % 4; 791 cp->type = i >> 2; 792 cp->chan = &priv->mbox_chans[i]; 793 priv->mbox_chans[i].con_priv = cp; 794 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 795 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 796 } 797 798 priv->mbox.num_chans = IMX_MU_CHANS; 799 priv->mbox.of_xlate = imx_mu_xlate; 800 801 if (priv->side_b) 802 return 0; 803 804 /* Set default MU configuration */ 805 for (i = 0; i < IMX_MU_xCR_MAX; i++) 806 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 807 808 /* Clear any pending GIP */ 809 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); 810 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); 811 812 /* Clear any pending RSR */ 813 for (i = 0; i < priv->num_rr; i++) 814 imx_mu_read(priv, priv->dcfg->xRR + i * 4); 815 816 return 0; 817} 818 819static int imx_mu_init_specific(struct imx_mu_priv *priv) 820{ 821 unsigned int i; 822 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; 823 824 for (i = 0; i < num_chans; i++) { 825 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 826 827 cp->idx = i < 2 ? 0 : i - 2; 828 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; 829 cp->chan = &priv->mbox_chans[i]; 830 priv->mbox_chans[i].con_priv = cp; 831 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 832 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx); 833 } 834 835 priv->mbox.num_chans = num_chans; 836 priv->mbox.of_xlate = imx_mu_specific_xlate; 837 838 /* Set default MU configuration */ 839 for (i = 0; i < IMX_MU_xCR_MAX; i++) 840 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); 841 842 return 0; 843} 844 845static int imx_mu_init_seco(struct imx_mu_priv *priv) 846{ 847 int ret; 848 849 ret = imx_mu_init_generic(priv); 850 if (ret) 851 return ret; 852 priv->mbox.of_xlate = imx_mu_seco_xlate; 853 854 return 0; 855} 856 857static int imx_mu_probe(struct platform_device *pdev) 858{ 859 struct device *dev = &pdev->dev; 860 struct device_node *np = dev->of_node; 861 struct imx_mu_priv *priv; 862 const struct imx_mu_dcfg *dcfg; 863 int i, ret; 864 u32 size; 865 866 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 867 if (!priv) 868 return -ENOMEM; 869 870 priv->dev = dev; 871 872 priv->base = devm_platform_ioremap_resource(pdev, 0); 873 if (IS_ERR(priv->base)) 874 return PTR_ERR(priv->base); 875 876 dcfg = of_device_get_match_data(dev); 877 if (!dcfg) 878 return -EINVAL; 879 priv->dcfg = dcfg; 880 if (priv->dcfg->type & IMX_MU_V2_IRQ) { 881 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); 882 if (priv->irq[IMX_MU_TYPE_TX] < 0) 883 return priv->irq[IMX_MU_TYPE_TX]; 884 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); 885 if (priv->irq[IMX_MU_TYPE_RX] < 0) 886 return priv->irq[IMX_MU_TYPE_RX]; 887 } else { 888 ret = platform_get_irq(pdev, 0); 889 if (ret < 0) 890 return ret; 891 892 for (i = 0; i < IMX_MU_CHANS; i++) 893 priv->irq[i] = ret; 894 } 895 896 if (priv->dcfg->type & IMX_MU_V2_S4) 897 size = sizeof(struct imx_s4_rpc_msg_max); 898 else 899 size = sizeof(struct imx_sc_rpc_msg_max); 900 901 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); 902 if (!priv->msg) 903 return -ENOMEM; 904 905 priv->clk = devm_clk_get(dev, NULL); 906 if (IS_ERR(priv->clk)) { 907 if (PTR_ERR(priv->clk) != -ENOENT) 908 return PTR_ERR(priv->clk); 909 910 priv->clk = NULL; 911 } 912 913 ret = clk_prepare_enable(priv->clk); 914 if (ret) { 915 dev_err(dev, "Failed to enable clock\n"); 916 return ret; 917 } 918 919 imx_mu_get_tr_rr(priv); 920 921 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); 922 923 ret = priv->dcfg->init(priv); 924 if (ret) { 925 dev_err(dev, "Failed to init MU\n"); 926 goto disable_clk; 927 } 928 929 spin_lock_init(&priv->xcr_lock); 930 931 priv->mbox.dev = dev; 932 priv->mbox.ops = &imx_mu_ops; 933 priv->mbox.chans = priv->mbox_chans; 934 priv->mbox.txdone_irq = true; 935 936 platform_set_drvdata(pdev, priv); 937 938 ret = devm_mbox_controller_register(dev, &priv->mbox); 939 if (ret) 940 goto disable_clk; 941 942 of_platform_populate(dev->of_node, NULL, NULL, dev); 943 944 pm_runtime_enable(dev); 945 946 ret = pm_runtime_resume_and_get(dev); 947 if (ret < 0) 948 goto disable_runtime_pm; 949 950 ret = pm_runtime_put_sync(dev); 951 if (ret < 0) 952 goto disable_runtime_pm; 953 954 clk_disable_unprepare(priv->clk); 955 956 return 0; 957 958disable_runtime_pm: 959 pm_runtime_disable(dev); 960disable_clk: 961 clk_disable_unprepare(priv->clk); 962 return ret; 963} 964 965static void imx_mu_remove(struct platform_device *pdev) 966{ 967 struct imx_mu_priv *priv = platform_get_drvdata(pdev); 968 969 pm_runtime_disable(priv->dev); 970} 971 972static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 973 .tx = imx_mu_generic_tx, 974 .rx = imx_mu_generic_rx, 975 .rxdb = imx_mu_generic_rxdb, 976 .init = imx_mu_init_generic, 977 .xTR = 0x0, 978 .xRR = 0x10, 979 .xSR = {0x20, 0x20, 0x20, 0x20}, 980 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 981}; 982 983static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 984 .tx = imx_mu_generic_tx, 985 .rx = imx_mu_generic_rx, 986 .rxdb = imx_mu_generic_rxdb, 987 .init = imx_mu_init_generic, 988 .xTR = 0x20, 989 .xRR = 0x40, 990 .xSR = {0x60, 0x60, 0x60, 0x60}, 991 .xCR = {0x64, 0x64, 0x64, 0x64, 0x64}, 992 .skip_suspend_flag = true, 993}; 994 995static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 996 .tx = imx_mu_generic_tx, 997 .rx = imx_mu_generic_rx, 998 .rxdb = imx_mu_generic_rxdb, 999 .init = imx_mu_init_generic, 1000 .type = IMX_MU_V2, 1001 .xTR = 0x200, 1002 .xRR = 0x280, 1003 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1004 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1005}; 1006 1007static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { 1008 .tx = imx_mu_specific_tx, 1009 .rx = imx_mu_specific_rx, 1010 .init = imx_mu_init_specific, 1011 .type = IMX_MU_V2 | IMX_MU_V2_S4, 1012 .xTR = 0x200, 1013 .xRR = 0x280, 1014 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1015 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1016}; 1017 1018static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { 1019 .tx = imx_mu_specific_tx, 1020 .rx = imx_mu_specific_rx, 1021 .init = imx_mu_init_specific, 1022 .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ, 1023 .xTR = 0x200, 1024 .xRR = 0x280, 1025 .xSR = {0xC, 0x118, 0x124, 0x12C}, 1026 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, 1027}; 1028 1029static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { 1030 .tx = imx_mu_specific_tx, 1031 .rx = imx_mu_specific_rx, 1032 .init = imx_mu_init_specific, 1033 .rxdb = imx_mu_generic_rxdb, 1034 .xTR = 0x0, 1035 .xRR = 0x10, 1036 .xSR = {0x20, 0x20, 0x20, 0x20}, 1037 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1038}; 1039 1040static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { 1041 .tx = imx_mu_seco_tx, 1042 .rx = imx_mu_generic_rx, 1043 .rxdb = imx_mu_seco_rxdb, 1044 .init = imx_mu_init_seco, 1045 .xTR = 0x0, 1046 .xRR = 0x10, 1047 .xSR = {0x20, 0x20, 0x20, 0x20}, 1048 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, 1049}; 1050 1051static const struct of_device_id imx_mu_dt_ids[] = { 1052 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, 1053 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, 1054 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, 1055 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, 1056 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, 1057 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp }, 1058 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 }, 1059 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 }, 1060 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, 1061 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, 1062 { }, 1063}; 1064MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); 1065 1066static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) 1067{ 1068 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1069 int i; 1070 1071 if (!priv->clk) { 1072 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1073 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); 1074 } 1075 1076 if (!priv->dcfg->skip_suspend_flag) 1077 priv->suspend = true; 1078 1079 return 0; 1080} 1081 1082static int __maybe_unused imx_mu_resume_noirq(struct device *dev) 1083{ 1084 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1085 int i; 1086 1087 /* 1088 * ONLY restore MU when context lost, the TIE could 1089 * be set during noirq resume as there is MU data 1090 * communication going on, and restore the saved 1091 * value will overwrite the TIE and cause MU data 1092 * send failed, may lead to system freeze. This issue 1093 * is observed by testing freeze mode suspend. 1094 */ 1095 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { 1096 for (i = 0; i < IMX_MU_xCR_MAX; i++) 1097 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); 1098 } 1099 1100 if (!priv->dcfg->skip_suspend_flag) 1101 priv->suspend = false; 1102 1103 return 0; 1104} 1105 1106static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 1107{ 1108 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1109 1110 clk_disable_unprepare(priv->clk); 1111 1112 return 0; 1113} 1114 1115static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 1116{ 1117 struct imx_mu_priv *priv = dev_get_drvdata(dev); 1118 int ret; 1119 1120 ret = clk_prepare_enable(priv->clk); 1121 if (ret) 1122 dev_err(dev, "failed to enable clock\n"); 1123 1124 return ret; 1125} 1126 1127static const struct dev_pm_ops imx_mu_pm_ops = { 1128 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, 1129 imx_mu_resume_noirq) 1130 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 1131 imx_mu_runtime_resume, NULL) 1132}; 1133 1134static struct platform_driver imx_mu_driver = { 1135 .probe = imx_mu_probe, 1136 .remove = imx_mu_remove, 1137 .driver = { 1138 .name = "imx_mu", 1139 .of_match_table = imx_mu_dt_ids, 1140 .pm = &imx_mu_pm_ops, 1141 }, 1142}; 1143module_platform_driver(imx_mu_driver); 1144 1145MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 1146MODULE_DESCRIPTION("Message Unit driver for i.MX"); 1147MODULE_LICENSE("GPL v2");
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