exynos-mailbox.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright 2020 Samsung Electronics Co., Ltd.
  4 * Copyright 2020 Google LLC.
  5 * Copyright 2024 Linaro Ltd.
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/bits.h>
 10#include <linux/clk.h>
 11#include <linux/io.h>
 12#include <linux/mailbox_controller.h>
 13#include <linux/mailbox/exynos-message.h>
 14#include <linux/module.h>
 15#include <linux/of.h>
 16#include <linux/platform_device.h>
 17#include <linux/slab.h>
 18
 19#define EXYNOS_MBOX_MCUCTRL		0x0	/* Mailbox Control Register */
 20#define EXYNOS_MBOX_INTCR0		0x24	/* Interrupt Clear Register 0 */
 21#define EXYNOS_MBOX_INTMR0		0x28	/* Interrupt Mask Register 0 */
 22#define EXYNOS_MBOX_INTSR0		0x2c	/* Interrupt Status Register 0 */
 23#define EXYNOS_MBOX_INTMSR0		0x30	/* Interrupt Mask Status Register 0 */
 24#define EXYNOS_MBOX_INTGR1		0x40	/* Interrupt Generation Register 1 */
 25#define EXYNOS_MBOX_INTMR1		0x48	/* Interrupt Mask Register 1 */
 26#define EXYNOS_MBOX_INTSR1		0x4c	/* Interrupt Status Register 1 */
 27#define EXYNOS_MBOX_INTMSR1		0x50	/* Interrupt Mask Status Register 1 */
 28
 29#define EXYNOS_MBOX_INTMR0_MASK		GENMASK(15, 0)
 30#define EXYNOS_MBOX_INTGR1_MASK		GENMASK(15, 0)
 31
 32#define EXYNOS_MBOX_CHAN_COUNT		HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK)
 33
 34/**
 35 * struct exynos_mbox - driver's private data.
 36 * @regs:	mailbox registers base address.
 37 * @mbox:	pointer to the mailbox controller.
 38 * @pclk:	pointer to the mailbox peripheral clock.
 39 */
 40struct exynos_mbox {
 41	void __iomem *regs;
 42	struct mbox_controller *mbox;
 43	struct clk *pclk;
 44};
 45
 46static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
 47{
 48	struct device *dev = chan->mbox->dev;
 49	struct exynos_mbox *exynos_mbox = dev_get_drvdata(dev);
 50	struct exynos_mbox_msg *msg = data;
 51
 52	if (msg->chan_id >= exynos_mbox->mbox->num_chans) {
 53		dev_err(dev, "Invalid channel ID %d\n", msg->chan_id);
 54		return -EINVAL;
 55	}
 56
 57	if (msg->chan_type != EXYNOS_MBOX_CHAN_TYPE_DOORBELL) {
 58		dev_err(dev, "Unsupported channel type [%d]\n", msg->chan_type);
 59		return -EINVAL;
 60	}
 61
 62	writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
 63
 64	return 0;
 65}
 66
 67static const struct mbox_chan_ops exynos_mbox_chan_ops = {
 68	.send_data = exynos_mbox_send_data,
 69};
 70
 71static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox,
 72					      const struct of_phandle_args *sp)
 73{
 74	int i;
 75
 76	if (sp->args_count != 0)
 77		return ERR_PTR(-EINVAL);
 78
 79	/*
 80	 * Return the first available channel. When we don't pass the
 81	 * channel ID from device tree, each channel populated by the driver is
 82	 * just a software construct or a virtual channel. We use 'void *data'
 83	 * in send_data() to pass the channel identifiers.
 84	 */
 85	for (i = 0; i < mbox->num_chans; i++)
 86		if (mbox->chans[i].cl == NULL)
 87			return &mbox->chans[i];
 88	return ERR_PTR(-EINVAL);
 89}
 90
 91static const struct of_device_id exynos_mbox_match[] = {
 92	{ .compatible = "google,gs101-mbox" },
 93	{},
 94};
 95MODULE_DEVICE_TABLE(of, exynos_mbox_match);
 96
 97static int exynos_mbox_probe(struct platform_device *pdev)
 98{
 99	struct device *dev = &pdev->dev;
100	struct exynos_mbox *exynos_mbox;
101	struct mbox_controller *mbox;
102	struct mbox_chan *chans;
103	int i;
104
105	exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL);
106	if (!exynos_mbox)
107		return -ENOMEM;
108
109	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
110	if (!mbox)
111		return -ENOMEM;
112
113	chans = devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans),
114			     GFP_KERNEL);
115	if (!chans)
116		return -ENOMEM;
117
118	exynos_mbox->regs = devm_platform_ioremap_resource(pdev, 0);
119	if (IS_ERR(exynos_mbox->regs))
120		return PTR_ERR(exynos_mbox->regs);
121
122	exynos_mbox->pclk = devm_clk_get_enabled(dev, "pclk");
123	if (IS_ERR(exynos_mbox->pclk))
124		return dev_err_probe(dev, PTR_ERR(exynos_mbox->pclk),
125				     "Failed to enable clock.\n");
126
127	mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT;
128	mbox->chans = chans;
129	mbox->dev = dev;
130	mbox->ops = &exynos_mbox_chan_ops;
131	mbox->of_xlate = exynos_mbox_of_xlate;
132
133	for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++)
134		chans[i].mbox = mbox;
135
136	exynos_mbox->mbox = mbox;
137
138	platform_set_drvdata(pdev, exynos_mbox);
139
140	/* Mask out all interrupts. We support just polling channels for now. */
141	writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
142
143	return devm_mbox_controller_register(dev, mbox);
144}
145
146static struct platform_driver exynos_mbox_driver = {
147	.probe	= exynos_mbox_probe,
148	.driver	= {
149		.name = "exynos-acpm-mbox",
150		.of_match_table	= exynos_mbox_match,
151	},
152};
153module_platform_driver(exynos_mbox_driver);
154
155MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@linaro.org>");
156MODULE_DESCRIPTION("Samsung Exynos mailbox driver");
157MODULE_LICENSE("GPL");