irq-sifive-plic.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2017 SiFive
  4 * Copyright (C) 2018 Christoph Hellwig
  5 */
  6#define pr_fmt(fmt) "riscv-plic: " fmt
  7#include <linux/acpi.h>
  8#include <linux/cpu.h>
  9#include <linux/interrupt.h>
 10#include <linux/io.h>
 11#include <linux/irq.h>
 12#include <linux/irqchip.h>
 13#include <linux/irqchip/chained_irq.h>
 14#include <linux/irqdomain.h>
 15#include <linux/module.h>
 16#include <linux/of.h>
 17#include <linux/of_address.h>
 18#include <linux/of_irq.h>
 19#include <linux/platform_device.h>
 20#include <linux/spinlock.h>
 21#include <linux/syscore_ops.h>
 22#include <asm/smp.h>
 23
 24/*
 25 * This driver implements a version of the RISC-V PLIC with the actual layout
 26 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
 27 *
 28 *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
 29 *
 30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
 31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
 32 * Spec.
 33 */
 34
 35#define MAX_DEVICES			1024
 36#define MAX_CONTEXTS			15872
 37
 38/*
 39 * Each interrupt source has a priority register associated with it.
 40 * We always hardwire it to one in Linux.
 41 */
 42#define PRIORITY_BASE			0
 43#define     PRIORITY_PER_ID		4
 44
 45/*
 46 * Each hart context has a vector of interrupt enable bits associated with it.
 47 * There's one bit for each interrupt source.
 48 */
 49#define CONTEXT_ENABLE_BASE		0x2000
 50#define     CONTEXT_ENABLE_SIZE		0x80
 51
 52#define PENDING_BASE			0x1000
 53
 54/*
 55 * Each hart context has a set of control registers associated with it.  Right
 56 * now there's only two: a source priority threshold over which the hart will
 57 * take an interrupt, and a register to claim interrupts.
 58 */
 59#define CONTEXT_BASE			0x200000
 60#define     CONTEXT_SIZE		0x1000
 61#define     CONTEXT_THRESHOLD		0x00
 62#define     CONTEXT_CLAIM		0x04
 63
 64#define	PLIC_DISABLE_THRESHOLD		0x7
 65#define	PLIC_ENABLE_THRESHOLD		0
 66
 67#define PLIC_QUIRK_EDGE_INTERRUPT	0
 68#define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM	1
 69
 70struct plic_priv {
 71	struct fwnode_handle	*fwnode;
 72	struct cpumask		lmask;
 73	struct irq_domain	*irqdomain;
 74	void __iomem		*regs;
 75	unsigned long		plic_quirks;
 76	/* device interrupts + 1 to compensate for the reserved hwirq 0 */
 77	unsigned int __private	total_irqs;
 78	unsigned int		irq_groups;
 79	unsigned long		*prio_save;
 80	u32			gsi_base;
 81	int			acpi_plic_id;
 82};
 83
 84struct plic_handler {
 85	bool			present;
 86	void __iomem		*hart_base;
 87	/*
 88	 * Protect mask operations on the registers given that we can't
 89	 * assume atomic memory operations work on them.
 90	 */
 91	raw_spinlock_t		enable_lock;
 92	void __iomem		*enable_base;
 93	u32			*enable_save;
 94	struct plic_priv	*priv;
 95};
 96
 97/*
 98 * Macro to deal with the insanity of hardware interrupt 0 being reserved */
 99#define for_each_device_irq(iter, priv)	\
100	for (unsigned int iter = 1; iter < ACCESS_PRIVATE(priv, total_irqs); iter++)
101
102static int plic_parent_irq __ro_after_init;
103static bool plic_global_setup_done __ro_after_init;
104static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
105
106static int plic_irq_set_type(struct irq_data *d, unsigned int type);
107
108static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable)
109{
110	u32 __iomem *base = handler->enable_base;
111	u32 hwirq_mask = 1 << (hwirq % 32);
112	int group = hwirq / 32;
113	u32 value;
114
115	value = readl(base + group);
116
117	if (enable)
118		value |= hwirq_mask;
119	else
120		value &= ~hwirq_mask;
121
122	handler->enable_save[group] = value;
123	writel(value, base + group);
124}
125
126static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
127{
128	unsigned long flags;
129
130	raw_spin_lock_irqsave(&handler->enable_lock, flags);
131	__plic_toggle(handler, hwirq, enable);
132	raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
133}
134
135static inline void plic_irq_toggle(const struct cpumask *mask,
136				   struct irq_data *d, int enable)
137{
138	int cpu;
139
140	for_each_cpu(cpu, mask) {
141		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
142
143		plic_toggle(handler, d->hwirq, enable);
144	}
145}
146
147static void plic_irq_unmask(struct irq_data *d)
148{
149	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
150
151	writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
152}
153
154static void plic_irq_mask(struct irq_data *d)
155{
156	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
157
158	writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
159}
160
161static void plic_irq_enable(struct irq_data *d)
162{
163	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
164	plic_irq_unmask(d);
165}
166
167static void plic_irq_disable(struct irq_data *d)
168{
169	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
170}
171
172static void plic_irq_eoi(struct irq_data *d)
173{
174	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
175	u32 __iomem *reg;
176	bool enabled;
177
178	reg = handler->enable_base + (d->hwirq / 32) * sizeof(u32);
179	enabled = readl(reg) & BIT(d->hwirq % 32);
180
181	if (unlikely(!enabled)) {
182		plic_toggle(handler, d->hwirq, 1);
183		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
184		plic_toggle(handler, d->hwirq, 0);
185	} else {
186		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
187	}
188}
189
190#ifdef CONFIG_SMP
191static int plic_set_affinity(struct irq_data *d,
192			     const struct cpumask *mask_val, bool force)
193{
194	unsigned int cpu;
195	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
196
197	if (force)
198		cpu = cpumask_first_and(&priv->lmask, mask_val);
199	else
200		cpu = cpumask_first_and_and(&priv->lmask, mask_val, cpu_online_mask);
201
202	if (cpu >= nr_cpu_ids)
203		return -EINVAL;
204
205	/* Invalidate the original routing entry */
206	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
207
208	irq_data_update_effective_affinity(d, cpumask_of(cpu));
209
210	/* Setting the new routing entry if irq is enabled */
211	if (!irqd_irq_disabled(d))
212		plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
213
214	return IRQ_SET_MASK_OK_DONE;
215}
216#endif
217
218static struct irq_chip plic_edge_chip = {
219	.name		= "SiFive PLIC",
220	.irq_enable	= plic_irq_enable,
221	.irq_disable	= plic_irq_disable,
222	.irq_ack	= plic_irq_eoi,
223	.irq_mask	= plic_irq_mask,
224	.irq_unmask	= plic_irq_unmask,
225#ifdef CONFIG_SMP
226	.irq_set_affinity = plic_set_affinity,
227#endif
228	.irq_set_type	= plic_irq_set_type,
229	.flags		= IRQCHIP_SKIP_SET_WAKE |
230			  IRQCHIP_AFFINITY_PRE_STARTUP,
231};
232
233static struct irq_chip plic_chip = {
234	.name		= "SiFive PLIC",
235	.irq_enable	= plic_irq_enable,
236	.irq_disable	= plic_irq_disable,
237	.irq_mask	= plic_irq_mask,
238	.irq_unmask	= plic_irq_unmask,
239	.irq_eoi	= plic_irq_eoi,
240#ifdef CONFIG_SMP
241	.irq_set_affinity = plic_set_affinity,
242#endif
243	.irq_set_type	= plic_irq_set_type,
244	.flags		= IRQCHIP_SKIP_SET_WAKE |
245			  IRQCHIP_AFFINITY_PRE_STARTUP,
246};
247
248static int plic_irq_set_type(struct irq_data *d, unsigned int type)
249{
250	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
251
252	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
253		return IRQ_SET_MASK_OK_NOCOPY;
254
255	switch (type) {
256	case IRQ_TYPE_EDGE_RISING:
257		irq_set_chip_handler_name_locked(d, &plic_edge_chip,
258						 handle_edge_irq, NULL);
259		break;
260	case IRQ_TYPE_LEVEL_HIGH:
261		irq_set_chip_handler_name_locked(d, &plic_chip,
262						 handle_fasteoi_irq, NULL);
263		break;
264	default:
265		return -EINVAL;
266	}
267
268	return IRQ_SET_MASK_OK;
269}
270
271static int plic_irq_suspend(void *data)
272{
273	struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv;
274
275	for_each_device_irq(irq, priv) {
276		__assign_bit(irq, priv->prio_save,
277			     readl(priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID));
278	}
279
280	return 0;
281}
282
283static void plic_irq_resume(void *data)
284{
285	struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv;
286	unsigned int index, cpu;
287	unsigned long flags;
288	u32 __iomem *reg;
289
290	for_each_device_irq(irq, priv) {
291		index = BIT_WORD(irq);
292		writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0,
293		       priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID);
294	}
295
296	for_each_present_cpu(cpu) {
297		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
298
299		if (!handler->present)
300			continue;
301
302		raw_spin_lock_irqsave(&handler->enable_lock, flags);
303		for (unsigned int i = 0; i < priv->irq_groups; i++) {
304			reg = handler->enable_base + i * sizeof(u32);
305			writel(handler->enable_save[i], reg);
306		}
307		raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
308	}
309}
310
311static const struct syscore_ops plic_irq_syscore_ops = {
312	.suspend	= plic_irq_suspend,
313	.resume		= plic_irq_resume,
314};
315
316static struct syscore plic_irq_syscore = {
317	.ops = &plic_irq_syscore_ops,
318};
319
320static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
321			      irq_hw_number_t hwirq)
322{
323	struct plic_priv *priv = d->host_data;
324
325	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
326			    handle_fasteoi_irq, NULL, NULL);
327	irq_set_noprobe(irq);
328	irq_set_affinity(irq, &priv->lmask);
329	return 0;
330}
331
332static int plic_irq_domain_translate(struct irq_domain *d,
333				     struct irq_fwspec *fwspec,
334				     unsigned long *hwirq,
335				     unsigned int *type)
336{
337	struct plic_priv *priv = d->host_data;
338
339	/* For DT, gsi_base is always zero. */
340	if (fwspec->param[0] >= priv->gsi_base)
341		fwspec->param[0] = fwspec->param[0] - priv->gsi_base;
342
343	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
344		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
345
346	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
347}
348
349static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
350				 unsigned int nr_irqs, void *arg)
351{
352	int i, ret;
353	irq_hw_number_t hwirq;
354	unsigned int type;
355	struct irq_fwspec *fwspec = arg;
356
357	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
358	if (ret)
359		return ret;
360
361	for (i = 0; i < nr_irqs; i++) {
362		ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
363		if (ret)
364			return ret;
365	}
366
367	return 0;
368}
369
370static const struct irq_domain_ops plic_irqdomain_ops = {
371	.translate	= plic_irq_domain_translate,
372	.alloc		= plic_irq_domain_alloc,
373	.free		= irq_domain_free_irqs_top,
374};
375
376/*
377 * Handling an interrupt is a two-step process: first you claim the interrupt
378 * by reading the claim register, then you complete the interrupt by writing
379 * that source ID back to the same claim register.  This automatically enables
380 * and disables the interrupt, so there's nothing else to do.
381 */
382static void plic_handle_irq(struct irq_desc *desc)
383{
384	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
385	struct irq_chip *chip = irq_desc_get_chip(desc);
386	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
387	irq_hw_number_t hwirq;
388
389	WARN_ON_ONCE(!handler->present);
390
391	chained_irq_enter(chip, desc);
392
393	while ((hwirq = readl(claim))) {
394		int err = generic_handle_domain_irq(handler->priv->irqdomain,
395						    hwirq);
396		if (unlikely(err)) {
397			pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
398					    handler->priv->fwnode, hwirq);
399		}
400	}
401
402	chained_irq_exit(chip, desc);
403}
404
405static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *handler)
406{
407	u32 __iomem *pending = handler->priv->regs + PENDING_BASE;
408	u32 __iomem *enable = handler->enable_base;
409	u32 pending_irqs = 0;
410	int i, j;
411
412	/* Look for first pending interrupt */
413	for (i = 0; i < nr_irq_groups; i++) {
414		/* Any pending interrupts would be annihilated, so skip checking them */
415		if (!handler->enable_save[i])
416			continue;
417
418		pending_irqs = handler->enable_save[i] & readl_relaxed(pending + i);
419		if (pending_irqs)
420			break;
421	}
422
423	if (!pending_irqs)
424		return 0;
425
426	/* Isolate lowest set bit */
427	pending_irqs &= -pending_irqs;
428
429	/* Disable all interrupts but the first pending one */
430	for (j = 0; j < nr_irq_groups; j++) {
431		u32 new_mask = j == i ? pending_irqs : 0;
432
433		if (new_mask != handler->enable_save[j])
434			writel_relaxed(new_mask, enable + j);
435	}
436	return pending_irqs;
437}
438
439static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim)
440{
441	int nr_irq_groups = handler->priv->irq_groups;
442	u32 __iomem *enable = handler->enable_base;
443	irq_hw_number_t hwirq = 0;
444	u32 iso_mask;
445	int i;
446
447	guard(raw_spinlock)(&handler->enable_lock);
448
449	/* Existing enable state is already cached in enable_save */
450	iso_mask = cp100_isolate_pending_irq(nr_irq_groups, handler);
451	if (!iso_mask)
452		return 0;
453
454	/*
455	 * Interrupts delievered to hardware still become pending, but only
456	 * interrupts that are both pending and enabled can be claimed.
457	 * Clearing the enable bit for all interrupts but the first pending
458	 * one avoids a hardware bug that occurs during read from the claim
459	 * register with more than one eligible interrupt.
460	 */
461	hwirq = readl(claim);
462
463	/* Restore previous state */
464	for (i = 0; i < nr_irq_groups; i++) {
465		u32 written = i == hwirq / 32 ? iso_mask : 0;
466		u32 stored = handler->enable_save[i];
467
468		if (stored != written)
469			writel_relaxed(stored, enable + i);
470	}
471	return hwirq;
472}
473
474static void plic_handle_irq_cp100(struct irq_desc *desc)
475{
476	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
477	struct irq_chip *chip = irq_desc_get_chip(desc);
478	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
479	irq_hw_number_t hwirq;
480
481	WARN_ON_ONCE(!handler->present);
482
483	chained_irq_enter(chip, desc);
484
485	while ((hwirq = cp100_get_hwirq(handler, claim))) {
486		int err = generic_handle_domain_irq(handler->priv->irqdomain, hwirq);
487
488		if (unlikely(err)) {
489			pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
490					    handler->priv->fwnode, hwirq);
491		}
492	}
493
494	chained_irq_exit(chip, desc);
495}
496
497static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
498{
499	/* priority must be > threshold to trigger an interrupt */
500	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
501}
502
503static int plic_dying_cpu(unsigned int cpu)
504{
505	if (plic_parent_irq)
506		disable_percpu_irq(plic_parent_irq);
507
508	return 0;
509}
510
511static int plic_starting_cpu(unsigned int cpu)
512{
513	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
514
515	if (plic_parent_irq)
516		enable_percpu_irq(plic_parent_irq,
517				  irq_get_trigger_type(plic_parent_irq));
518	else
519		pr_warn("%pfwP: cpu%d: parent irq not available\n",
520			handler->priv->fwnode, cpu);
521	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
522
523	return 0;
524}
525
526static const struct of_device_id plic_match[] = {
527	{ .compatible = "sifive,plic-1.0.0" },
528	{ .compatible = "riscv,plic0" },
529	{ .compatible = "andestech,nceplic100",
530	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
531	{ .compatible = "thead,c900-plic",
532	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
533	{ .compatible = "ultrarisc,cp100-plic",
534	  .data = (const void *)BIT(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM) },
535	{}
536};
537
538#ifdef CONFIG_ACPI
539
540static const struct acpi_device_id plic_acpi_match[] = {
541	{ "RSCV0001", 0 },
542	{}
543};
544MODULE_DEVICE_TABLE(acpi, plic_acpi_match);
545
546#endif
547static int plic_parse_nr_irqs_and_contexts(struct fwnode_handle *fwnode,
548					   u32 *nr_irqs, u32 *nr_contexts,
549					   u32 *gsi_base, u32 *id)
550{
551	int rc;
552
553	if (!is_of_node(fwnode)) {
554		rc = riscv_acpi_get_gsi_info(fwnode, gsi_base, id, nr_irqs, NULL);
555		if (rc) {
556			pr_err("%pfwP: failed to find GSI mapping\n", fwnode);
557			return rc;
558		}
559
560		*nr_contexts = acpi_rintc_get_plic_nr_contexts(*id);
561		if (WARN_ON(!*nr_contexts)) {
562			pr_err("%pfwP: no PLIC context available\n", fwnode);
563			return -EINVAL;
564		}
565
566		return 0;
567	}
568
569	rc = of_property_read_u32(to_of_node(fwnode), "riscv,ndev", nr_irqs);
570	if (rc) {
571		pr_err("%pfwP: riscv,ndev property not available\n", fwnode);
572		return rc;
573	}
574
575	*nr_contexts = of_irq_count(to_of_node(fwnode));
576	if (WARN_ON(!(*nr_contexts))) {
577		pr_err("%pfwP: no PLIC context available\n", fwnode);
578		return -EINVAL;
579	}
580
581	*gsi_base = 0;
582	*id = 0;
583
584	return 0;
585}
586
587static int plic_parse_context_parent(struct fwnode_handle *fwnode, u32 context,
588				     u32 *parent_hwirq, int *parent_cpu, u32 id)
589{
590	struct of_phandle_args parent;
591	unsigned long hartid;
592	int rc;
593
594	if (!is_of_node(fwnode)) {
595		hartid = acpi_rintc_ext_parent_to_hartid(id, context);
596		if (hartid == INVALID_HARTID)
597			return -EINVAL;
598
599		*parent_cpu = riscv_hartid_to_cpuid(hartid);
600		*parent_hwirq = RV_IRQ_EXT;
601		return 0;
602	}
603
604	rc = of_irq_parse_one(to_of_node(fwnode), context, &parent);
605	if (rc)
606		return rc;
607
608	rc = riscv_of_parent_hartid(parent.np, &hartid);
609	if (rc)
610		return rc;
611
612	*parent_hwirq = parent.args[0];
613	*parent_cpu = riscv_hartid_to_cpuid(hartid);
614	return 0;
615}
616
617static int plic_probe(struct fwnode_handle *fwnode)
618{
619	int error = 0, nr_contexts, nr_handlers = 0, cpu, i;
620	unsigned long plic_quirks = 0;
621	struct plic_handler *handler;
622	u32 nr_irqs, parent_hwirq;
623	struct plic_priv *priv;
624	void __iomem *regs;
625	int id, context_id;
626	u32 gsi_base;
627
628	if (is_of_node(fwnode)) {
629		const struct of_device_id *id;
630
631		id = of_match_node(plic_match, to_of_node(fwnode));
632		if (id)
633			plic_quirks = (unsigned long)id->data;
634
635		regs = of_iomap(to_of_node(fwnode), 0);
636		if (!regs)
637			return -ENOMEM;
638	} else {
639		regs = devm_platform_ioremap_resource(to_platform_device(fwnode->dev), 0);
640		if (IS_ERR(regs))
641			return PTR_ERR(regs);
642	}
643
644	error = plic_parse_nr_irqs_and_contexts(fwnode, &nr_irqs, &nr_contexts, &gsi_base, &id);
645	if (error)
646		goto fail_free_regs;
647
648	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
649	if (!priv) {
650		error = -ENOMEM;
651		goto fail_free_regs;
652	}
653
654	priv->fwnode = fwnode;
655	priv->plic_quirks = plic_quirks;
656	/*
657	 * The firmware provides the number of device interrupts. As
658	 * hardware interrupt 0 is reserved, the number of total interrupts
659	 * is nr_irqs + 1.
660	 */
661	nr_irqs++;
662	ACCESS_PRIVATE(priv, total_irqs) = nr_irqs;
663	/* Precalculate the number of register groups */
664	priv->irq_groups = DIV_ROUND_UP(nr_irqs, 32);
665
666	priv->regs = regs;
667	priv->gsi_base = gsi_base;
668	priv->acpi_plic_id = id;
669
670	priv->prio_save = bitmap_zalloc(nr_irqs, GFP_KERNEL);
671	if (!priv->prio_save) {
672		error = -ENOMEM;
673		goto fail_free_priv;
674	}
675
676	for (i = 0; i < nr_contexts; i++) {
677		error = plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu,
678						  priv->acpi_plic_id);
679		if (error) {
680			pr_warn("%pfwP: hwirq for context%d not found\n", fwnode, i);
681			continue;
682		}
683
684		if (is_of_node(fwnode)) {
685			context_id = i;
686		} else {
687			context_id = acpi_rintc_get_plic_context(priv->acpi_plic_id, i);
688			if (context_id == INVALID_CONTEXT) {
689				pr_warn("%pfwP: invalid context id for context%d\n", fwnode, i);
690				continue;
691			}
692		}
693
694		/*
695		 * Skip contexts other than external interrupts for our
696		 * privilege level.
697		 */
698		if (parent_hwirq != RV_IRQ_EXT) {
699			/* Disable S-mode enable bits if running in M-mode. */
700			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
701				u32 __iomem *enable_base = priv->regs +	CONTEXT_ENABLE_BASE +
702							   i * CONTEXT_ENABLE_SIZE;
703
704				for (int j = 0; j < priv->irq_groups; j++)
705					writel(0, enable_base + j);
706			}
707			continue;
708		}
709
710		if (cpu < 0) {
711			pr_warn("%pfwP: Invalid cpuid for context %d\n", fwnode, i);
712			continue;
713		}
714
715		/*
716		 * When running in M-mode we need to ignore the S-mode handler.
717		 * Here we assume it always comes later, but that might be a
718		 * little fragile.
719		 */
720		handler = per_cpu_ptr(&plic_handlers, cpu);
721		if (handler->present) {
722			pr_warn("%pfwP: handler already present for context %d.\n", fwnode, i);
723			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
724			goto done;
725		}
726
727		cpumask_set_cpu(cpu, &priv->lmask);
728		handler->present = true;
729		handler->hart_base = priv->regs + CONTEXT_BASE +
730			context_id * CONTEXT_SIZE;
731		raw_spin_lock_init(&handler->enable_lock);
732		handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
733			context_id * CONTEXT_ENABLE_SIZE;
734		handler->priv = priv;
735
736		handler->enable_save = kcalloc(priv->irq_groups, sizeof(*handler->enable_save),
737					       GFP_KERNEL);
738		if (!handler->enable_save) {
739			error = -ENOMEM;
740			goto fail_cleanup_contexts;
741		}
742done:
743		for_each_device_irq(hwirq, priv) {
744			plic_toggle(handler, hwirq, 0);
745			writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
746		}
747		nr_handlers++;
748	}
749
750	priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs, &plic_irqdomain_ops, priv);
751	if (WARN_ON(!priv->irqdomain)) {
752		error = -ENOMEM;
753		goto fail_cleanup_contexts;
754	}
755
756	/*
757	 * We can have multiple PLIC instances so setup global state
758	 * and register syscore operations only once after context
759	 * handlers of all online CPUs are initialized.
760	 */
761	if (!plic_global_setup_done) {
762		struct irq_domain *domain;
763		bool global_setup = true;
764
765		for_each_online_cpu(cpu) {
766			handler = per_cpu_ptr(&plic_handlers, cpu);
767			if (!handler->present) {
768				global_setup = false;
769				break;
770			}
771		}
772
773		if (global_setup) {
774			void (*handler_fn)(struct irq_desc *) = plic_handle_irq;
775
776			if (test_bit(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM, &handler->priv->plic_quirks))
777				handler_fn = plic_handle_irq_cp100;
778
779			/* Find parent domain and register chained handler */
780			domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
781			if (domain)
782				plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
783			if (plic_parent_irq)
784				irq_set_chained_handler(plic_parent_irq, handler_fn);
785
786			cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
787					  "irqchip/sifive/plic:starting",
788					  plic_starting_cpu, plic_dying_cpu);
789			register_syscore(&plic_irq_syscore);
790			plic_global_setup_done = true;
791		}
792	}
793
794#ifdef CONFIG_ACPI
795	if (!acpi_disabled)
796		acpi_dev_clear_dependencies(ACPI_COMPANION(fwnode->dev));
797#endif
798
799	pr_info("%pfwP: mapped %d interrupts with %d handlers for %d contexts.\n",
800		fwnode, nr_irqs, nr_handlers, nr_contexts);
801	return 0;
802
803fail_cleanup_contexts:
804	for (i = 0; i < nr_contexts; i++) {
805		if (plic_parse_context_parent(fwnode, i, &parent_hwirq, &cpu, priv->acpi_plic_id))
806			continue;
807		if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
808			continue;
809
810		handler = per_cpu_ptr(&plic_handlers, cpu);
811		handler->present = false;
812		handler->hart_base = NULL;
813		handler->enable_base = NULL;
814		kfree(handler->enable_save);
815		handler->enable_save = NULL;
816		handler->priv = NULL;
817	}
818	bitmap_free(priv->prio_save);
819fail_free_priv:
820	kfree(priv);
821fail_free_regs:
822	iounmap(regs);
823	return error;
824}
825
826static int plic_platform_probe(struct platform_device *pdev)
827{
828	return plic_probe(pdev->dev.fwnode);
829}
830
831static struct platform_driver plic_driver = {
832	.driver = {
833		.name		= "riscv-plic",
834		.of_match_table	= plic_match,
835		.suppress_bind_attrs = true,
836		.acpi_match_table = ACPI_PTR(plic_acpi_match),
837	},
838	.probe = plic_platform_probe,
839};
840builtin_platform_driver(plic_driver);
841
842static int __init plic_early_probe(struct device_node *node,
843				   struct device_node *parent)
844{
845	return plic_probe(&node->fwnode);
846}
847
848IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe);