irq-riscv-imsic-state.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
  4 * Copyright (C) 2022 Ventana Micro Systems Inc.
  5 */
  6
  7#define pr_fmt(fmt) "riscv-imsic: " fmt
  8#include <linux/acpi.h>
  9#include <linux/cpu.h>
 10#include <linux/bitmap.h>
 11#include <linux/interrupt.h>
 12#include <linux/irq.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/of_address.h>
 16#include <linux/of_irq.h>
 17#include <linux/seq_file.h>
 18#include <linux/spinlock.h>
 19#include <linux/smp.h>
 20#include <asm/hwcap.h>
 21
 22#include "irq-riscv-imsic-state.h"
 23
 24#define IMSIC_DISABLE_EIDELIVERY		0
 25#define IMSIC_ENABLE_EIDELIVERY			1
 26#define IMSIC_DISABLE_EITHRESHOLD		1
 27#define IMSIC_ENABLE_EITHRESHOLD		0
 28
 29static inline void imsic_csr_write(unsigned long reg, unsigned long val)
 30{
 31	csr_write(CSR_ISELECT, reg);
 32	csr_write(CSR_IREG, val);
 33}
 34
 35static inline unsigned long imsic_csr_read(unsigned long reg)
 36{
 37	csr_write(CSR_ISELECT, reg);
 38	return csr_read(CSR_IREG);
 39}
 40
 41static inline unsigned long imsic_csr_read_clear(unsigned long reg, unsigned long val)
 42{
 43	csr_write(CSR_ISELECT, reg);
 44	return csr_read_clear(CSR_IREG, val);
 45}
 46
 47static inline void imsic_csr_set(unsigned long reg, unsigned long val)
 48{
 49	csr_write(CSR_ISELECT, reg);
 50	csr_set(CSR_IREG, val);
 51}
 52
 53static inline void imsic_csr_clear(unsigned long reg, unsigned long val)
 54{
 55	csr_write(CSR_ISELECT, reg);
 56	csr_clear(CSR_IREG, val);
 57}
 58
 59struct imsic_priv *imsic;
 60
 61const struct imsic_global_config *imsic_get_global_config(void)
 62{
 63	return imsic ? &imsic->global : NULL;
 64}
 65EXPORT_SYMBOL_GPL(imsic_get_global_config);
 66
 67static bool __imsic_eix_read_clear(unsigned long id, bool pend)
 68{
 69	unsigned long isel, imask;
 70
 71	isel = id / BITS_PER_LONG;
 72	isel *= BITS_PER_LONG / IMSIC_EIPx_BITS;
 73	isel += pend ? IMSIC_EIP0 : IMSIC_EIE0;
 74	imask = BIT(id & (__riscv_xlen - 1));
 75
 76	return !!(imsic_csr_read_clear(isel, imask) & imask);
 77}
 78
 79static inline bool __imsic_id_read_clear_enabled(unsigned long id)
 80{
 81	return __imsic_eix_read_clear(id, false);
 82}
 83
 84static inline bool __imsic_id_read_clear_pending(unsigned long id)
 85{
 86	return __imsic_eix_read_clear(id, true);
 87}
 88
 89void __imsic_eix_update(unsigned long base_id, unsigned long num_id, bool pend, bool val)
 90{
 91	unsigned long id = base_id, last_id = base_id + num_id;
 92	unsigned long i, isel, ireg;
 93
 94	while (id < last_id) {
 95		isel = id / BITS_PER_LONG;
 96		isel *= BITS_PER_LONG / IMSIC_EIPx_BITS;
 97		isel += pend ? IMSIC_EIP0 : IMSIC_EIE0;
 98
 99		/*
100		 * Prepare the ID mask to be programmed in the
101		 * IMSIC EIEx and EIPx registers. These registers
102		 * are XLEN-wide and we must not touch IDs which
103		 * are < base_id and >= (base_id + num_id).
104		 */
105		ireg = 0;
106		for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) {
107			ireg |= BIT(i);
108			id++;
109		}
110
111		/*
112		 * The IMSIC EIEx and EIPx registers are indirectly
113		 * accessed via using ISELECT and IREG CSRs so we
114		 * need to access these CSRs without getting preempted.
115		 *
116		 * All existing users of this function call this
117		 * function with local IRQs disabled so we don't
118		 * need to do anything special here.
119		 */
120		if (val)
121			imsic_csr_set(isel, ireg);
122		else
123			imsic_csr_clear(isel, ireg);
124	}
125}
126
127static bool __imsic_local_sync(struct imsic_local_priv *lpriv)
128{
129	struct imsic_local_config *tlocal, *mlocal;
130	struct imsic_vector *vec, *tvec, *mvec;
131	bool ret = true;
132	int i;
133
134	lockdep_assert_held(&lpriv->lock);
135
136	for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) {
137		if (!i || (!imsic_noipi && i == IMSIC_IPI_ID))
138			goto skip;
139		vec = &lpriv->vectors[i];
140
141		if (READ_ONCE(vec->enable))
142			__imsic_id_set_enable(i);
143		else
144			__imsic_id_clear_enable(i);
145
146		/*
147		 * Clear the previous vector pointer of the new vector only
148		 * after the movement is complete on the old CPU.
149		 */
150		mvec = READ_ONCE(vec->move_prev);
151		if (mvec) {
152			/*
153			 * If the old vector has not been updated then
154			 * try again in the next sync-up call.
155			 */
156			if (READ_ONCE(mvec->move_next)) {
157				ret = false;
158				continue;
159			}
160
161			WRITE_ONCE(vec->move_prev, NULL);
162		}
163
164		/*
165		 * If a vector was being moved to a new vector on some other
166		 * CPU then we can get a MSI during the movement so check the
167		 * ID pending bit and re-trigger the new ID on other CPU using
168		 * MMIO write.
169		 */
170		mvec = READ_ONCE(vec->move_next);
171		if (mvec) {
172			/*
173			 * Devices having non-atomic MSI update might see
174			 * an intermediate state so check both old ID and
175			 * new ID for pending interrupts.
176			 *
177			 * For details, see imsic_irq_set_affinity().
178			 */
179			tvec = vec->local_id == mvec->local_id ?
180				NULL : &lpriv->vectors[mvec->local_id];
181
182			if (tvec && !irq_can_move_in_process_context(irq_get_irq_data(vec->irq)) &&
183			    __imsic_id_read_clear_pending(tvec->local_id)) {
184				/* Retrigger temporary vector if it was already in-use */
185				if (READ_ONCE(tvec->enable)) {
186					tlocal = per_cpu_ptr(imsic->global.local, tvec->cpu);
187					writel_relaxed(tvec->local_id, tlocal->msi_va);
188				}
189
190				mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu);
191				writel_relaxed(mvec->local_id, mlocal->msi_va);
192			}
193
194			if (__imsic_id_read_clear_pending(vec->local_id)) {
195				mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu);
196				writel_relaxed(mvec->local_id, mlocal->msi_va);
197			}
198
199			WRITE_ONCE(vec->move_next, NULL);
200			imsic_vector_free(vec);
201		}
202
203skip:
204		bitmap_clear(lpriv->dirty_bitmap, i, 1);
205	}
206
207	return ret;
208}
209
210#ifdef CONFIG_SMP
211static void __imsic_local_timer_start(struct imsic_local_priv *lpriv, unsigned int cpu)
212{
213	lockdep_assert_held(&lpriv->lock);
214
215	if (!timer_pending(&lpriv->timer)) {
216		lpriv->timer.expires = jiffies + 1;
217		add_timer_on(&lpriv->timer, cpu);
218	}
219}
220#else
221static inline void __imsic_local_timer_start(struct imsic_local_priv *lpriv, unsigned int cpu)
222{
223}
224#endif
225
226void imsic_local_sync_all(bool force_all)
227{
228	struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv);
229	unsigned long flags;
230
231	raw_spin_lock_irqsave(&lpriv->lock, flags);
232
233	if (force_all)
234		bitmap_fill(lpriv->dirty_bitmap, imsic->global.nr_ids + 1);
235	if (!__imsic_local_sync(lpriv))
236		__imsic_local_timer_start(lpriv, smp_processor_id());
237
238	raw_spin_unlock_irqrestore(&lpriv->lock, flags);
239}
240
241void imsic_local_delivery(bool enable)
242{
243	if (enable) {
244		imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD);
245		imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY);
246		return;
247	}
248
249	imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY);
250	imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD);
251}
252
253#ifdef CONFIG_SMP
254static void imsic_local_timer_callback(struct timer_list *timer)
255{
256	imsic_local_sync_all(false);
257}
258
259static void __imsic_remote_sync(struct imsic_local_priv *lpriv, unsigned int cpu)
260{
261	lockdep_assert_held(&lpriv->lock);
262
263	/*
264	 * The spinlock acquire/release semantics ensure that changes
265	 * to vector enable, vector move and dirty bitmap are visible
266	 * to the target CPU.
267	 */
268
269	/*
270	 * We schedule a timer on the target CPU if the target CPU is not
271	 * same as the current CPU. An offline CPU will unconditionally
272	 * synchronize IDs through imsic_starting_cpu() when the
273	 * CPU is brought up.
274	 */
275	if (cpu_online(cpu)) {
276		if (cpu == smp_processor_id()) {
277			if (__imsic_local_sync(lpriv))
278				return;
279		}
280
281		__imsic_local_timer_start(lpriv, cpu);
282	}
283}
284#else
285static void __imsic_remote_sync(struct imsic_local_priv *lpriv, unsigned int cpu)
286{
287	lockdep_assert_held(&lpriv->lock);
288	__imsic_local_sync(lpriv);
289}
290#endif
291
292void imsic_vector_mask(struct imsic_vector *vec)
293{
294	struct imsic_local_priv *lpriv;
295
296	lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu);
297	if (WARN_ON_ONCE(&lpriv->vectors[vec->local_id] != vec))
298		return;
299
300	/*
301	 * This function is called through Linux irq subsystem with
302	 * irqs disabled so no need to save/restore irq flags.
303	 */
304
305	raw_spin_lock(&lpriv->lock);
306
307	WRITE_ONCE(vec->enable, false);
308	bitmap_set(lpriv->dirty_bitmap, vec->local_id, 1);
309	__imsic_remote_sync(lpriv, vec->cpu);
310
311	raw_spin_unlock(&lpriv->lock);
312}
313
314void imsic_vector_unmask(struct imsic_vector *vec)
315{
316	struct imsic_local_priv *lpriv;
317
318	lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu);
319	if (WARN_ON_ONCE(&lpriv->vectors[vec->local_id] != vec))
320		return;
321
322	/*
323	 * This function is called through Linux irq subsystem with
324	 * irqs disabled so no need to save/restore irq flags.
325	 */
326
327	raw_spin_lock(&lpriv->lock);
328
329	WRITE_ONCE(vec->enable, true);
330	bitmap_set(lpriv->dirty_bitmap, vec->local_id, 1);
331	__imsic_remote_sync(lpriv, vec->cpu);
332
333	raw_spin_unlock(&lpriv->lock);
334}
335
336void imsic_vector_force_move_cleanup(struct imsic_vector *vec)
337{
338	struct imsic_local_priv *lpriv;
339	struct imsic_vector *mvec;
340	unsigned long flags;
341
342	lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu);
343	raw_spin_lock_irqsave(&lpriv->lock, flags);
344
345	mvec = READ_ONCE(vec->move_prev);
346	WRITE_ONCE(vec->move_prev, NULL);
347	if (mvec)
348		imsic_vector_free(mvec);
349
350	raw_spin_unlock_irqrestore(&lpriv->lock, flags);
351}
352
353static bool imsic_vector_move_update(struct imsic_local_priv *lpriv,
354				     struct imsic_vector *vec, bool is_old_vec,
355				     bool new_enable, struct imsic_vector *move_vec)
356{
357	unsigned long flags;
358	bool enabled;
359
360	raw_spin_lock_irqsave(&lpriv->lock, flags);
361
362	/* Update enable and move details */
363	enabled = READ_ONCE(vec->enable);
364	WRITE_ONCE(vec->enable, new_enable);
365	if (is_old_vec)
366		WRITE_ONCE(vec->move_next, move_vec);
367	else
368		WRITE_ONCE(vec->move_prev, move_vec);
369
370	/* Mark the vector as dirty and synchronize */
371	bitmap_set(lpriv->dirty_bitmap, vec->local_id, 1);
372	__imsic_remote_sync(lpriv, vec->cpu);
373
374	raw_spin_unlock_irqrestore(&lpriv->lock, flags);
375
376	return enabled;
377}
378
379void imsic_vector_move(struct imsic_vector *old_vec, struct imsic_vector *new_vec)
380{
381	struct imsic_local_priv *old_lpriv, *new_lpriv;
382	bool enabled;
383
384	if (WARN_ON_ONCE(old_vec->cpu == new_vec->cpu))
385		return;
386
387	old_lpriv = per_cpu_ptr(imsic->lpriv, old_vec->cpu);
388	if (WARN_ON_ONCE(&old_lpriv->vectors[old_vec->local_id] != old_vec))
389		return;
390
391	new_lpriv = per_cpu_ptr(imsic->lpriv, new_vec->cpu);
392	if (WARN_ON_ONCE(&new_lpriv->vectors[new_vec->local_id] != new_vec))
393		return;
394
395	/*
396	 * Move and re-trigger the new vector based on the pending
397	 * state of the old vector because we might get a device
398	 * interrupt on the old vector while device was being moved
399	 * to the new vector.
400	 */
401	enabled = imsic_vector_move_update(old_lpriv, old_vec, true, false, new_vec);
402	imsic_vector_move_update(new_lpriv, new_vec, false, enabled, old_vec);
403}
404
405#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
406void imsic_vector_debug_show(struct seq_file *m, struct imsic_vector *vec, int ind)
407{
408	struct imsic_local_priv *lpriv;
409	struct imsic_vector *mvec;
410	bool is_enabled;
411
412	lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu);
413	if (WARN_ON_ONCE(&lpriv->vectors[vec->local_id] != vec))
414		return;
415
416	is_enabled = imsic_vector_isenabled(vec);
417	mvec = imsic_vector_get_move(vec);
418
419	seq_printf(m, "%*starget_cpu      : %5u\n", ind, "", vec->cpu);
420	seq_printf(m, "%*starget_local_id : %5u\n", ind, "", vec->local_id);
421	seq_printf(m, "%*sis_reserved     : %5u\n", ind, "",
422		   (!imsic_noipi && vec->local_id <= IMSIC_IPI_ID) ? 1 : 0);
423	seq_printf(m, "%*sis_enabled      : %5u\n", ind, "", is_enabled ? 1 : 0);
424	seq_printf(m, "%*sis_move_pending : %5u\n", ind, "", mvec ? 1 : 0);
425	if (mvec) {
426		seq_printf(m, "%*smove_cpu        : %5u\n", ind, "", mvec->cpu);
427		seq_printf(m, "%*smove_local_id   : %5u\n", ind, "", mvec->local_id);
428	}
429}
430
431void imsic_vector_debug_show_summary(struct seq_file *m, int ind)
432{
433	irq_matrix_debug_show(m, imsic->matrix, ind);
434}
435#endif
436
437struct imsic_vector *imsic_vector_alloc(unsigned int irq, const struct cpumask *mask)
438{
439	struct imsic_vector *vec = NULL;
440	struct imsic_local_priv *lpriv;
441	unsigned long flags;
442	unsigned int cpu;
443	int local_id;
444
445	raw_spin_lock_irqsave(&imsic->matrix_lock, flags);
446	local_id = irq_matrix_alloc(imsic->matrix, mask, false, &cpu);
447	raw_spin_unlock_irqrestore(&imsic->matrix_lock, flags);
448	if (local_id < 0)
449		return NULL;
450
451	lpriv = per_cpu_ptr(imsic->lpriv, cpu);
452	vec = &lpriv->vectors[local_id];
453	vec->irq = irq;
454	vec->enable = false;
455	vec->move_next = NULL;
456	vec->move_prev = NULL;
457
458	return vec;
459}
460
461void imsic_vector_free(struct imsic_vector *vec)
462{
463	unsigned long flags;
464
465	raw_spin_lock_irqsave(&imsic->matrix_lock, flags);
466	vec->irq = 0;
467	irq_matrix_free(imsic->matrix, vec->cpu, vec->local_id, false);
468	raw_spin_unlock_irqrestore(&imsic->matrix_lock, flags);
469}
470
471static void __init imsic_local_cleanup(void)
472{
473	struct imsic_local_priv *lpriv;
474	int cpu;
475
476	for_each_possible_cpu(cpu) {
477		lpriv = per_cpu_ptr(imsic->lpriv, cpu);
478
479		bitmap_free(lpriv->dirty_bitmap);
480		kfree(lpriv->vectors);
481	}
482
483	free_percpu(imsic->lpriv);
484}
485
486static int __init imsic_local_init(void)
487{
488	struct imsic_global_config *global = &imsic->global;
489	struct imsic_local_priv *lpriv;
490	struct imsic_vector *vec;
491	int cpu, i;
492
493	/* Allocate per-CPU private state */
494	imsic->lpriv = alloc_percpu(typeof(*imsic->lpriv));
495	if (!imsic->lpriv)
496		return -ENOMEM;
497
498	/* Setup per-CPU private state */
499	for_each_possible_cpu(cpu) {
500		lpriv = per_cpu_ptr(imsic->lpriv, cpu);
501
502		raw_spin_lock_init(&lpriv->lock);
503
504		/* Allocate dirty bitmap */
505		lpriv->dirty_bitmap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL);
506		if (!lpriv->dirty_bitmap)
507			goto fail_local_cleanup;
508
509#ifdef CONFIG_SMP
510		/* Setup lazy timer for synchronization */
511		timer_setup(&lpriv->timer, imsic_local_timer_callback, TIMER_PINNED);
512#endif
513
514		/* Allocate vector array */
515		lpriv->vectors = kcalloc(global->nr_ids + 1, sizeof(*lpriv->vectors),
516					 GFP_KERNEL);
517		if (!lpriv->vectors)
518			goto fail_local_cleanup;
519
520		/* Setup vector array */
521		for (i = 0; i <= global->nr_ids; i++) {
522			vec = &lpriv->vectors[i];
523			vec->cpu = cpu;
524			vec->local_id = i;
525			vec->irq = 0;
526		}
527	}
528
529	return 0;
530
531fail_local_cleanup:
532	imsic_local_cleanup();
533	return -ENOMEM;
534}
535
536void imsic_state_online(void)
537{
538	unsigned long flags;
539
540	raw_spin_lock_irqsave(&imsic->matrix_lock, flags);
541	irq_matrix_online(imsic->matrix);
542	raw_spin_unlock_irqrestore(&imsic->matrix_lock, flags);
543}
544
545void imsic_state_offline(void)
546{
547	unsigned long flags;
548
549	raw_spin_lock_irqsave(&imsic->matrix_lock, flags);
550	irq_matrix_offline(imsic->matrix);
551	raw_spin_unlock_irqrestore(&imsic->matrix_lock, flags);
552
553#ifdef CONFIG_SMP
554	struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv);
555
556	raw_spin_lock_irqsave(&lpriv->lock, flags);
557	WARN_ON_ONCE(timer_delete_sync_try(&lpriv->timer) < 0);
558	raw_spin_unlock_irqrestore(&lpriv->lock, flags);
559#endif
560}
561
562static int __init imsic_matrix_init(void)
563{
564	struct imsic_global_config *global = &imsic->global;
565
566	raw_spin_lock_init(&imsic->matrix_lock);
567	imsic->matrix = irq_alloc_matrix(global->nr_ids + 1,
568					 0, global->nr_ids + 1);
569	if (!imsic->matrix)
570		return -ENOMEM;
571
572	/* Reserve ID#0 because it is special and never implemented */
573	irq_matrix_assign_system(imsic->matrix, 0, false);
574
575	/* Reserve IPI ID because it is special and used internally */
576	if (!imsic_noipi)
577		irq_matrix_assign_system(imsic->matrix, IMSIC_IPI_ID, false);
578
579	return 0;
580}
581
582static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode,
583					   struct imsic_global_config *global,
584					   u32 *nr_parent_irqs)
585{
586	int rc;
587
588	/* Find number of guest index bits in MSI address */
589	rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
590				  &global->guest_index_bits);
591	if (rc)
592		global->guest_index_bits = 0;
593
594	/* Find number of HART index bits */
595	rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
596				  &global->hart_index_bits);
597	if (rc) {
598		/* Assume default value */
599		global->hart_index_bits = __fls(*nr_parent_irqs);
600		if (BIT(global->hart_index_bits) < *nr_parent_irqs)
601			global->hart_index_bits++;
602	}
603
604	/* Find number of group index bits */
605	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
606				  &global->group_index_bits);
607	if (rc)
608		global->group_index_bits = 0;
609
610	/*
611	 * Find first bit position of group index.
612	 * If not specified assumed the default APLIC-IMSIC configuration.
613	 */
614	rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
615				  &global->group_index_shift);
616	if (rc)
617		global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
618
619	/* Find number of interrupt identities */
620	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
621				  &global->nr_ids);
622	if (rc) {
623		pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
624		return rc;
625	}
626
627	/* Find number of guest interrupt identities */
628	rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
629				  &global->nr_guest_ids);
630	if (rc)
631		global->nr_guest_ids = global->nr_ids;
632
633	return 0;
634}
635
636static int __init imsic_populate_global_acpi(struct fwnode_handle *fwnode,
637					     struct imsic_global_config *global,
638					     u32 *nr_parent_irqs, void *opaque)
639{
640	struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)opaque;
641
642	global->guest_index_bits = imsic->guest_index_bits;
643	global->hart_index_bits = imsic->hart_index_bits;
644	global->group_index_bits = imsic->group_index_bits;
645	global->group_index_shift = imsic->group_index_shift;
646	global->nr_ids = imsic->num_ids;
647	global->nr_guest_ids = imsic->num_guest_ids;
648	return 0;
649}
650
651static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
652					  u32 index, unsigned long *hartid)
653{
654	struct of_phandle_args parent;
655	int rc;
656
657	if (!is_of_node(fwnode)) {
658		if (hartid)
659			*hartid = acpi_rintc_index_to_hartid(index);
660
661		if (!hartid || (*hartid == INVALID_HARTID))
662			return -EINVAL;
663
664		return 0;
665	}
666
667	rc = of_irq_parse_one(to_of_node(fwnode), index, &parent);
668	if (rc)
669		return rc;
670
671	/*
672	 * Skip interrupts other than external interrupts for
673	 * current privilege level.
674	 */
675	if (parent.args[0] != RV_IRQ_EXT)
676		return -EINVAL;
677
678	return riscv_of_parent_hartid(parent.np, hartid);
679}
680
681static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode,
682					  u32 index, struct resource *res)
683{
684	if (!is_of_node(fwnode))
685		return acpi_rintc_get_imsic_mmio_info(index, res);
686
687	return of_address_to_resource(to_of_node(fwnode), index, res);
688}
689
690static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
691				     struct imsic_global_config *global,
692				     u32 *nr_parent_irqs,
693				     u32 *nr_mmios,
694				     void *opaque)
695{
696	unsigned long hartid;
697	struct resource res;
698	int rc;
699	u32 i;
700
701	*nr_parent_irqs = 0;
702	*nr_mmios = 0;
703
704	/* Find number of parent interrupts */
705	while (!imsic_get_parent_hartid(fwnode, *nr_parent_irqs, &hartid))
706		(*nr_parent_irqs)++;
707	if (!*nr_parent_irqs) {
708		pr_err("%pfwP: no parent irqs available\n", fwnode);
709		return -EINVAL;
710	}
711
712	if (is_of_node(fwnode))
713		rc = imsic_populate_global_dt(fwnode, global, nr_parent_irqs);
714	else
715		rc = imsic_populate_global_acpi(fwnode, global, nr_parent_irqs, opaque);
716
717	if (rc)
718		return rc;
719
720	/* Sanity check guest index bits */
721	i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
722	if (i < global->guest_index_bits) {
723		pr_err("%pfwP: guest index bits too big\n", fwnode);
724		return -EINVAL;
725	}
726
727	/* Sanity check HART index bits */
728	i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits;
729	if (i < global->hart_index_bits) {
730		pr_err("%pfwP: HART index bits too big\n", fwnode);
731		return -EINVAL;
732	}
733
734	/* Sanity check group index bits */
735	i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT -
736	    global->guest_index_bits - global->hart_index_bits;
737	if (i < global->group_index_bits) {
738		pr_err("%pfwP: group index bits too big\n", fwnode);
739		return -EINVAL;
740	}
741
742	/* Sanity check group index shift */
743	i = global->group_index_bits + global->group_index_shift - 1;
744	if (i >= BITS_PER_LONG) {
745		pr_err("%pfwP: group index shift too big\n", fwnode);
746		return -EINVAL;
747	}
748
749	/* Sanity check number of interrupt identities */
750	if (global->nr_ids < IMSIC_MIN_ID ||
751	    global->nr_ids >= IMSIC_MAX_ID ||
752	    (global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID) {
753		pr_err("%pfwP: invalid number of interrupt identities\n", fwnode);
754		return -EINVAL;
755	}
756
757	/* Sanity check number of guest interrupt identities */
758	if (global->nr_guest_ids < IMSIC_MIN_ID ||
759	    global->nr_guest_ids >= IMSIC_MAX_ID ||
760	    (global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID) {
761		pr_err("%pfwP: invalid number of guest interrupt identities\n", fwnode);
762		return -EINVAL;
763	}
764
765	/* Compute base address */
766	rc = imsic_get_mmio_resource(fwnode, 0, &res);
767	if (rc) {
768		pr_err("%pfwP: first MMIO resource not found\n", fwnode);
769		return -EINVAL;
770	}
771	global->base_addr = res.start;
772	global->base_addr &= ~(BIT(global->guest_index_bits +
773				   global->hart_index_bits +
774				   IMSIC_MMIO_PAGE_SHIFT) - 1);
775	global->base_addr &= ~((BIT(global->group_index_bits) - 1) <<
776			       global->group_index_shift);
777
778	/* Find number of MMIO register sets */
779	while (!imsic_get_mmio_resource(fwnode, *nr_mmios, &res))
780		(*nr_mmios)++;
781
782	return 0;
783}
784
785int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque)
786{
787	u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers = 0;
788	struct imsic_global_config *global;
789	struct imsic_local_config *local;
790	void __iomem **mmios_va = NULL;
791	struct resource *mmios = NULL;
792	unsigned long reloff, hartid;
793	phys_addr_t base_addr;
794	int rc, cpu;
795
796	/*
797	 * Only one IMSIC instance allowed in a platform for clean
798	 * implementation of SMP IRQ affinity and per-CPU IPIs.
799	 *
800	 * This means on a multi-socket (or multi-die) platform we
801	 * will have multiple MMIO regions for one IMSIC instance.
802	 */
803	if (imsic) {
804		pr_err("%pfwP: already initialized hence ignoring\n", fwnode);
805		return -EALREADY;
806	}
807
808	if (!riscv_isa_extension_available(NULL, SxAIA)) {
809		pr_err("%pfwP: AIA support not available\n", fwnode);
810		return -ENODEV;
811	}
812
813	imsic = kzalloc(sizeof(*imsic), GFP_KERNEL);
814	if (!imsic)
815		return -ENOMEM;
816	imsic->fwnode = fwnode;
817	global = &imsic->global;
818
819	global->local = alloc_percpu(typeof(*global->local));
820	if (!global->local) {
821		rc = -ENOMEM;
822		goto out_free_priv;
823	}
824
825	/* Parse IMSIC fwnode */
826	rc = imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opaque);
827	if (rc)
828		goto out_free_local;
829
830	/* Allocate MMIO resource array */
831	mmios = kcalloc(nr_mmios, sizeof(*mmios), GFP_KERNEL);
832	if (!mmios) {
833		rc = -ENOMEM;
834		goto out_free_local;
835	}
836
837	/* Allocate MMIO virtual address array */
838	mmios_va = kcalloc(nr_mmios, sizeof(*mmios_va), GFP_KERNEL);
839	if (!mmios_va) {
840		rc = -ENOMEM;
841		goto out_iounmap;
842	}
843
844	/* Parse and map MMIO register sets */
845	for (i = 0; i < nr_mmios; i++) {
846		rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]);
847		if (rc) {
848			pr_err("%pfwP: unable to parse MMIO regset %d\n", fwnode, i);
849			goto out_iounmap;
850		}
851
852		base_addr = mmios[i].start;
853		base_addr &= ~(BIT(global->guest_index_bits +
854				   global->hart_index_bits +
855				   IMSIC_MMIO_PAGE_SHIFT) - 1);
856		base_addr &= ~((BIT(global->group_index_bits) - 1) <<
857			       global->group_index_shift);
858		if (base_addr != global->base_addr) {
859			rc = -EINVAL;
860			pr_err("%pfwP: address mismatch for regset %d\n", fwnode, i);
861			goto out_iounmap;
862		}
863
864		mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i]));
865		if (!mmios_va[i]) {
866			rc = -EIO;
867			pr_err("%pfwP: unable to map MMIO regset %d\n", fwnode, i);
868			goto out_iounmap;
869		}
870	}
871
872	/* Initialize local (or per-CPU )state */
873	rc = imsic_local_init();
874	if (rc) {
875		pr_err("%pfwP: failed to initialize local state\n",
876		       fwnode);
877		goto out_iounmap;
878	}
879
880	/* Configure handlers for target CPUs */
881	for (i = 0; i < nr_parent_irqs; i++) {
882		rc = imsic_get_parent_hartid(fwnode, i, &hartid);
883		if (rc) {
884			pr_warn("%pfwP: hart ID for parent irq%d not found\n", fwnode, i);
885			continue;
886		}
887
888		cpu = riscv_hartid_to_cpuid(hartid);
889		if (cpu < 0) {
890			pr_warn("%pfwP: invalid cpuid for parent irq%d\n", fwnode, i);
891			continue;
892		}
893
894		/* Find MMIO location of MSI page */
895		index = nr_mmios;
896		reloff = i * BIT(global->guest_index_bits) *
897			 IMSIC_MMIO_PAGE_SZ;
898		for (j = 0; nr_mmios; j++) {
899			if (reloff < resource_size(&mmios[j])) {
900				index = j;
901				break;
902			}
903
904			/*
905			 * MMIO region size may not be aligned to
906			 * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ
907			 * if holes are present.
908			 */
909			reloff -= ALIGN(resource_size(&mmios[j]),
910			BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ);
911		}
912		if (index >= nr_mmios) {
913			pr_warn("%pfwP: MMIO not found for parent irq%d\n", fwnode, i);
914			continue;
915		}
916
917		local = per_cpu_ptr(global->local, cpu);
918		local->msi_pa = mmios[index].start + reloff;
919		local->msi_va = mmios_va[index] + reloff;
920
921		nr_handlers++;
922	}
923
924	/* If no CPU handlers found then can't take interrupts */
925	if (!nr_handlers) {
926		pr_err("%pfwP: No CPU handlers found\n", fwnode);
927		rc = -ENODEV;
928		goto out_local_cleanup;
929	}
930
931	/* Initialize matrix allocator */
932	rc = imsic_matrix_init();
933	if (rc) {
934		pr_err("%pfwP: failed to create matrix allocator\n", fwnode);
935		goto out_local_cleanup;
936	}
937
938	/* We don't need MMIO arrays anymore so let's free-up */
939	kfree(mmios_va);
940	kfree(mmios);
941
942	return 0;
943
944out_local_cleanup:
945	imsic_local_cleanup();
946out_iounmap:
947	for (i = 0; i < nr_mmios; i++) {
948		if (mmios_va[i])
949			iounmap(mmios_va[i]);
950	}
951	kfree(mmios_va);
952	kfree(mmios);
953out_free_local:
954	free_percpu(imsic->global.local);
955out_free_priv:
956	kfree(imsic);
957	imsic = NULL;
958	return rc;
959}