irq-loongson-pch-msi.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
  4 *  Loongson PCH MSI support
  5 */
  6
  7#define pr_fmt(fmt) "pch-msi: " fmt
  8
  9#include <linux/irqchip.h>
 10#include <linux/msi.h>
 11#include <linux/of.h>
 12#include <linux/of_address.h>
 13#include <linux/of_irq.h>
 14#include <linux/of_pci.h>
 15#include <linux/pci.h>
 16#include <linux/slab.h>
 17
 18#include <linux/irqchip/irq-msi-lib.h>
 19#include "irq-loongson.h"
 20
 21static int nr_pics;
 22
 23struct pch_msi_data {
 24	struct mutex	msi_map_lock;
 25	phys_addr_t	doorbell;
 26	u32		irq_first;	/* The vector number that MSIs starts */
 27	u32		num_irqs;	/* The number of vectors for MSIs */
 28	unsigned long	*msi_map;
 29};
 30
 31static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
 32
 33static int pch_msi_allocate_hwirq(struct pch_msi_data *priv, int num_req)
 34{
 35	int first;
 36
 37	mutex_lock(&priv->msi_map_lock);
 38
 39	first = bitmap_find_free_region(priv->msi_map, priv->num_irqs,
 40					get_count_order(num_req));
 41	if (first < 0) {
 42		mutex_unlock(&priv->msi_map_lock);
 43		return -ENOSPC;
 44	}
 45
 46	mutex_unlock(&priv->msi_map_lock);
 47
 48	return priv->irq_first + first;
 49}
 50
 51static void pch_msi_free_hwirq(struct pch_msi_data *priv,
 52				int hwirq, int num_req)
 53{
 54	int first = hwirq - priv->irq_first;
 55
 56	mutex_lock(&priv->msi_map_lock);
 57	bitmap_release_region(priv->msi_map, first, get_count_order(num_req));
 58	mutex_unlock(&priv->msi_map_lock);
 59}
 60
 61static void pch_msi_compose_msi_msg(struct irq_data *data,
 62					struct msi_msg *msg)
 63{
 64	struct pch_msi_data *priv = irq_data_get_irq_chip_data(data);
 65
 66	msg->address_hi = upper_32_bits(priv->doorbell);
 67	msg->address_lo = lower_32_bits(priv->doorbell);
 68	msg->data = data->hwirq;
 69}
 70
 71static struct irq_chip middle_irq_chip = {
 72	.name			= "PCH MSI",
 73	.irq_mask		= irq_chip_mask_parent,
 74	.irq_unmask		= irq_chip_unmask_parent,
 75	.irq_ack		= irq_chip_ack_parent,
 76	.irq_set_affinity	= irq_chip_set_affinity_parent,
 77	.irq_compose_msi_msg	= pch_msi_compose_msi_msg,
 78};
 79
 80static int pch_msi_parent_domain_alloc(struct irq_domain *domain,
 81					unsigned int virq, int hwirq)
 82{
 83	struct irq_fwspec fwspec;
 84
 85	fwspec.fwnode = domain->parent->fwnode;
 86	fwspec.param_count = 1;
 87	fwspec.param[0] = hwirq;
 88
 89	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
 90}
 91
 92static int pch_msi_middle_domain_alloc(struct irq_domain *domain,
 93					   unsigned int virq,
 94					   unsigned int nr_irqs, void *args)
 95{
 96	struct pch_msi_data *priv = domain->host_data;
 97	int hwirq, err, i;
 98
 99	hwirq = pch_msi_allocate_hwirq(priv, nr_irqs);
100	if (hwirq < 0)
101		return hwirq;
102
103	for (i = 0; i < nr_irqs; i++) {
104		err = pch_msi_parent_domain_alloc(domain, virq + i, hwirq + i);
105		if (err)
106			goto err_hwirq;
107
108		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
109					      &middle_irq_chip, priv);
110	}
111
112	return 0;
113
114err_hwirq:
115	pch_msi_free_hwirq(priv, hwirq, nr_irqs);
116	irq_domain_free_irqs_parent(domain, virq, i);
117
118	return err;
119}
120
121static void pch_msi_middle_domain_free(struct irq_domain *domain,
122					   unsigned int virq,
123					   unsigned int nr_irqs)
124{
125	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
126	struct pch_msi_data *priv = irq_data_get_irq_chip_data(d);
127
128	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
129	pch_msi_free_hwirq(priv, d->hwirq, nr_irqs);
130}
131
132static const struct irq_domain_ops pch_msi_middle_domain_ops = {
133	.alloc	= pch_msi_middle_domain_alloc,
134	.free	= pch_msi_middle_domain_free,
135	.select	= msi_lib_irq_domain_select,
136};
137
138#define PCH_MSI_FLAGS_REQUIRED  (MSI_FLAG_USE_DEF_DOM_OPS |	\
139				 MSI_FLAG_USE_DEF_CHIP_OPS |	\
140				 MSI_FLAG_PCI_MSI_MASK_PARENT)
141
142#define PCH_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK |	\
143				 MSI_FLAG_PCI_MSIX      |	\
144				 MSI_FLAG_MULTI_PCI_MSI)
145
146static struct msi_parent_ops pch_msi_parent_ops = {
147	.required_flags		= PCH_MSI_FLAGS_REQUIRED,
148	.supported_flags	= PCH_MSI_FLAGS_SUPPORTED,
149	.chip_flags		= MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK,
150	.bus_select_mask	= MATCH_PCI_MSI,
151	.bus_select_token	= DOMAIN_BUS_NEXUS,
152	.prefix			= "PCH-",
153	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
154};
155
156static int pch_msi_init_domains(struct pch_msi_data *priv, struct irq_domain *parent,
157				struct fwnode_handle *domain_handle)
158{
159	struct irq_domain_info info = {
160		.ops		= &pch_msi_middle_domain_ops,
161		.size		= priv->num_irqs,
162		.parent		= parent,
163		.host_data	= priv,
164		.fwnode		= domain_handle,
165	};
166
167	if (!msi_create_parent_irq_domain(&info, &pch_msi_parent_ops)) {
168		pr_err("Failed to create the MSI middle domain\n");
169		return -ENOMEM;
170	}
171	return 0;
172}
173
174static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
175			struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
176{
177	int ret;
178	struct pch_msi_data *priv;
179
180	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
181	if (!priv)
182		return -ENOMEM;
183
184	mutex_init(&priv->msi_map_lock);
185
186	priv->doorbell = msg_address;
187	priv->irq_first = irq_base;
188	priv->num_irqs = irq_count;
189
190	priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
191	if (!priv->msi_map)
192		goto err_priv;
193
194	pr_debug("Registering %d MSIs, starting at %d\n",
195		 priv->num_irqs, priv->irq_first);
196
197	ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
198	if (ret)
199		goto err_map;
200
201	pch_msi_handle[nr_pics++] = domain_handle;
202	return 0;
203
204err_map:
205	bitmap_free(priv->msi_map);
206err_priv:
207	kfree(priv);
208
209	return -EINVAL;
210}
211
212#ifdef CONFIG_OF
213static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
214{
215	int err;
216	int irq_base, irq_count;
217	struct resource res;
218	struct irq_domain *parent_domain;
219
220	parent_domain = irq_find_host(parent);
221	if (!parent_domain) {
222		pr_err("Failed to find the parent domain\n");
223		return -ENXIO;
224	}
225
226	if (of_address_to_resource(node, 0, &res)) {
227		pr_err("Failed to allocate resource\n");
228		return -EINVAL;
229	}
230
231	if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
232		pr_err("Unable to parse MSI vec base\n");
233		return -EINVAL;
234	}
235
236	if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
237		pr_err("Unable to parse MSI vec number\n");
238		return -EINVAL;
239	}
240
241	err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_fwnode_handle(node));
242	if (err < 0)
243		return err;
244
245	return 0;
246}
247
248IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
249#endif
250
251#ifdef CONFIG_ACPI
252struct fwnode_handle *get_pch_msi_handle(int pci_segment)
253{
254	if (cpu_has_avecint)
255		return pch_msi_handle[0];
256
257	for (int i = 0; i < MAX_IO_PICS; i++) {
258		if (msi_group[i].pci_segment == pci_segment)
259			return pch_msi_handle[i];
260	}
261	return pch_msi_handle[0];
262}
263
264int __init pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_msi_pic *acpi_pchmsi)
265{
266	int ret;
267	struct fwnode_handle *domain_handle;
268
269	domain_handle = irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address);
270	ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
271				acpi_pchmsi->count, parent, domain_handle);
272	if (ret < 0)
273		irq_domain_free_fwnode(domain_handle);
274
275	return ret;
276}
277
278int __init pch_msi_acpi_init_avec(struct irq_domain *parent)
279{
280	if (pch_msi_handle[0])
281		return 0;
282
283	pch_msi_handle[0] = parent->fwnode;
284	irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
285
286	parent->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
287	parent->msi_parent_ops = &pch_msi_parent_ops;
288
289	return 0;
290}
291#endif