irq-imx-gpcv2.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4 */
  5
  6#include <linux/of_address.h>
  7#include <linux/of_irq.h>
  8#include <linux/slab.h>
  9#include <linux/irqchip.h>
 10#include <linux/syscore_ops.h>
 11
 12#define IMR_NUM			4
 13#define GPC_MAX_IRQS            (IMR_NUM * 32)
 14
 15#define GPC_IMR1_CORE0		0x30
 16#define GPC_IMR1_CORE1		0x40
 17#define GPC_IMR1_CORE2		0x1c0
 18#define GPC_IMR1_CORE3		0x1d0
 19
 20
 21struct gpcv2_irqchip_data {
 22	struct raw_spinlock	rlock;
 23	void __iomem		*gpc_base;
 24	u32			wakeup_sources[IMR_NUM];
 25	u32			saved_irq_mask[IMR_NUM];
 26	u32			cpu2wakeup;
 27};
 28
 29static struct gpcv2_irqchip_data *imx_gpcv2_instance __ro_after_init;
 30
 31static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
 32{
 33	return cd->gpc_base + cd->cpu2wakeup + i * 4;
 34}
 35
 36static int gpcv2_wakeup_source_save(void *data)
 37{
 38	struct gpcv2_irqchip_data *cd;
 39	void __iomem *reg;
 40	int i;
 41
 42	cd = imx_gpcv2_instance;
 43	if (!cd)
 44		return 0;
 45
 46	for (i = 0; i < IMR_NUM; i++) {
 47		reg = gpcv2_idx_to_reg(cd, i);
 48		cd->saved_irq_mask[i] = readl_relaxed(reg);
 49		writel_relaxed(cd->wakeup_sources[i], reg);
 50	}
 51
 52	return 0;
 53}
 54
 55static void gpcv2_wakeup_source_restore(void *data)
 56{
 57	struct gpcv2_irqchip_data *cd;
 58	int i;
 59
 60	cd = imx_gpcv2_instance;
 61	if (!cd)
 62		return;
 63
 64	for (i = 0; i < IMR_NUM; i++)
 65		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
 66}
 67
 68static const struct syscore_ops gpcv2_syscore_ops = {
 69	.suspend = gpcv2_wakeup_source_save,
 70	.resume = gpcv2_wakeup_source_restore,
 71};
 72
 73static struct syscore gpcv2_syscore = {
 74	.ops = &gpcv2_syscore_ops,
 75};
 76
 77static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
 78{
 79	struct gpcv2_irqchip_data *cd = d->chip_data;
 80	unsigned int idx = d->hwirq / 32;
 81	unsigned long flags;
 82	u32 mask, val;
 83
 84	raw_spin_lock_irqsave(&cd->rlock, flags);
 85	mask = BIT(d->hwirq % 32);
 86	val = cd->wakeup_sources[idx];
 87
 88	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
 89	raw_spin_unlock_irqrestore(&cd->rlock, flags);
 90
 91	/*
 92	 * Do *not* call into the parent, as the GIC doesn't have any
 93	 * wake-up facility...
 94	 */
 95
 96	return 0;
 97}
 98
 99static void imx_gpcv2_irq_unmask(struct irq_data *d)
100{
101	struct gpcv2_irqchip_data *cd = d->chip_data;
102	void __iomem *reg;
103	u32 val;
104
105	raw_spin_lock(&cd->rlock);
106	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
107	val = readl_relaxed(reg);
108	val &= ~BIT(d->hwirq % 32);
109	writel_relaxed(val, reg);
110	raw_spin_unlock(&cd->rlock);
111
112	irq_chip_unmask_parent(d);
113}
114
115static void imx_gpcv2_irq_mask(struct irq_data *d)
116{
117	struct gpcv2_irqchip_data *cd = d->chip_data;
118	void __iomem *reg;
119	u32 val;
120
121	raw_spin_lock(&cd->rlock);
122	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
123	val = readl_relaxed(reg);
124	val |= BIT(d->hwirq % 32);
125	writel_relaxed(val, reg);
126	raw_spin_unlock(&cd->rlock);
127
128	irq_chip_mask_parent(d);
129}
130
131static struct irq_chip gpcv2_irqchip_data_chip = {
132	.name			= "GPCv2",
133	.irq_eoi		= irq_chip_eoi_parent,
134	.irq_mask		= imx_gpcv2_irq_mask,
135	.irq_unmask		= imx_gpcv2_irq_unmask,
136	.irq_set_wake		= imx_gpcv2_irq_set_wake,
137	.irq_retrigger		= irq_chip_retrigger_hierarchy,
138	.irq_set_type		= irq_chip_set_type_parent,
139#ifdef CONFIG_SMP
140	.irq_set_affinity	= irq_chip_set_affinity_parent,
141#endif
142};
143
144static int imx_gpcv2_domain_translate(struct irq_domain *d,
145				      struct irq_fwspec *fwspec,
146				      unsigned long *hwirq,
147				      unsigned int *type)
148{
149	if (is_of_node(fwspec->fwnode)) {
150		if (fwspec->param_count != 3)
151			return -EINVAL;
152
153		/* No PPI should point to this domain */
154		if (fwspec->param[0] != 0)
155			return -EINVAL;
156
157		*hwirq = fwspec->param[1];
158		*type = fwspec->param[2];
159		return 0;
160	}
161
162	return -EINVAL;
163}
164
165static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
166				  unsigned int irq, unsigned int nr_irqs,
167				  void *data)
168{
169	struct irq_fwspec *fwspec = data;
170	struct irq_fwspec parent_fwspec;
171	irq_hw_number_t hwirq;
172	unsigned int type;
173	int err;
174	int i;
175
176	err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
177	if (err)
178		return err;
179
180	if (hwirq >= GPC_MAX_IRQS)
181		return -EINVAL;
182
183	for (i = 0; i < nr_irqs; i++) {
184		irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
185				&gpcv2_irqchip_data_chip, domain->host_data);
186	}
187
188	parent_fwspec = *fwspec;
189	parent_fwspec.fwnode = domain->parent->fwnode;
190	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
191					    &parent_fwspec);
192}
193
194static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
195	.translate	= imx_gpcv2_domain_translate,
196	.alloc		= imx_gpcv2_domain_alloc,
197	.free		= irq_domain_free_irqs_common,
198};
199
200static const struct of_device_id gpcv2_of_match[] = {
201	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
202	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
203	{ /* END */ }
204};
205
206static int __init imx_gpcv2_irqchip_init(struct device_node *node,
207			       struct device_node *parent)
208{
209	struct irq_domain *parent_domain, *domain;
210	struct gpcv2_irqchip_data *cd;
211	const struct of_device_id *id;
212	unsigned long core_num;
213	int i;
214
215	if (!parent) {
216		pr_err("%pOF: no parent, giving up\n", node);
217		return -ENODEV;
218	}
219
220	id = of_match_node(gpcv2_of_match, node);
221	if (!id) {
222		pr_err("%pOF: unknown compatibility string\n", node);
223		return -ENODEV;
224	}
225
226	core_num = (unsigned long)id->data;
227
228	parent_domain = irq_find_host(parent);
229	if (!parent_domain) {
230		pr_err("%pOF: unable to get parent domain\n", node);
231		return -ENXIO;
232	}
233
234	cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
235	if (!cd)
236		return -ENOMEM;
237
238	raw_spin_lock_init(&cd->rlock);
239
240	cd->gpc_base = of_iomap(node, 0);
241	if (!cd->gpc_base) {
242		pr_err("%pOF: unable to map gpc registers\n", node);
243		kfree(cd);
244		return -ENOMEM;
245	}
246
247	domain = irq_domain_create_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
248				of_fwnode_handle(node), &gpcv2_irqchip_data_domain_ops, cd);
249	if (!domain) {
250		iounmap(cd->gpc_base);
251		kfree(cd);
252		return -ENOMEM;
253	}
254	irq_set_default_domain(domain);
255
256	/* Initially mask all interrupts */
257	for (i = 0; i < IMR_NUM; i++) {
258		void __iomem *reg = cd->gpc_base + i * 4;
259
260		switch (core_num) {
261		case 4:
262			writel_relaxed(~0, reg + GPC_IMR1_CORE2);
263			writel_relaxed(~0, reg + GPC_IMR1_CORE3);
264			fallthrough;
265		case 2:
266			writel_relaxed(~0, reg + GPC_IMR1_CORE0);
267			writel_relaxed(~0, reg + GPC_IMR1_CORE1);
268		}
269		cd->wakeup_sources[i] = ~0;
270	}
271
272	/* Let CORE0 as the default CPU to wake up by GPC */
273	cd->cpu2wakeup = GPC_IMR1_CORE0;
274
275	/*
276	 * Due to hardware design failure, need to make sure GPR
277	 * interrupt(#32) is unmasked during RUN mode to avoid entering
278	 * DSM by mistake.
279	 */
280	writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
281
282	imx_gpcv2_instance = cd;
283	register_syscore(&gpcv2_syscore);
284
285	/*
286	 * Clear the OF_POPULATED flag set in of_irq_init so that
287	 * later the GPC power domain driver will not be skipped.
288	 */
289	of_node_clear_flag(node, OF_POPULATED);
290	fwnode_dev_initialized(domain->fwnode, false);
291	return 0;
292}
293
294IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
295IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);