irq-dw-apb-ictl.c

  1/*
  2 * Synopsys DW APB ICTL irqchip driver.
  3 *
  4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  5 *
  6 * based on GPL'ed 2.6 kernel sources
  7 *  (c) Marvell International Ltd.
  8 *
  9 * This file is licensed under the terms of the GNU General Public
 10 * License version 2.  This program is licensed "as is" without any
 11 * warranty of any kind, whether express or implied.
 12 */
 13
 14#include <linux/io.h>
 15#include <linux/irq.h>
 16#include <linux/irqchip.h>
 17#include <linux/irqchip/chained_irq.h>
 18#include <linux/of_address.h>
 19#include <linux/of_irq.h>
 20#include <linux/interrupt.h>
 21
 22#define APB_INT_ENABLE_L	0x00
 23#define APB_INT_ENABLE_H	0x04
 24#define APB_INT_MASK_L		0x08
 25#define APB_INT_MASK_H		0x0c
 26#define APB_INT_FINALSTATUS_L	0x30
 27#define APB_INT_FINALSTATUS_H	0x34
 28#define APB_INT_BASE_OFFSET	0x04
 29
 30/* irq domain of the primary interrupt controller. */
 31static struct irq_domain *dw_apb_ictl_irq_domain;
 32
 33static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs)
 34{
 35	struct irq_domain *d = dw_apb_ictl_irq_domain;
 36	int n;
 37
 38	for (n = 0; n < d->revmap_size; n += 32) {
 39		struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
 40		u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
 41
 42		while (stat) {
 43			u32 hwirq = ffs(stat) - 1;
 44
 45			generic_handle_domain_irq(d, hwirq);
 46			stat &= ~BIT(hwirq);
 47		}
 48	}
 49}
 50
 51static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)
 52{
 53	struct irq_domain *d = irq_desc_get_handler_data(desc);
 54	struct irq_chip *chip = irq_desc_get_chip(desc);
 55	int n;
 56
 57	chained_irq_enter(chip, desc);
 58
 59	for (n = 0; n < d->revmap_size; n += 32) {
 60		struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
 61		u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
 62
 63		while (stat) {
 64			u32 hwirq = ffs(stat) - 1;
 65			generic_handle_domain_irq(d, gc->irq_base + hwirq);
 66
 67			stat &= ~BIT(hwirq);
 68		}
 69	}
 70
 71	chained_irq_exit(chip, desc);
 72}
 73
 74static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 75				unsigned int nr_irqs, void *arg)
 76{
 77	int i, ret;
 78	irq_hw_number_t hwirq;
 79	unsigned int type = IRQ_TYPE_NONE;
 80	struct irq_fwspec *fwspec = arg;
 81
 82	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
 83	if (ret)
 84		return ret;
 85
 86	for (i = 0; i < nr_irqs; i++)
 87		irq_map_generic_chip(domain, virq + i, hwirq + i);
 88
 89	return 0;
 90}
 91
 92static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = {
 93	.translate = irq_domain_translate_onecell,
 94	.alloc = dw_apb_ictl_irq_domain_alloc,
 95	.free = irq_domain_free_irqs_top,
 96};
 97
 98#ifdef CONFIG_PM
 99static void dw_apb_ictl_resume(struct irq_data *d)
100{
101	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
102	struct irq_chip_type *ct = irq_data_get_chip_type(d);
103
104	guard(raw_spinlock)(&gc->lock);
105	writel_relaxed(~0, gc->reg_base + ct->regs.enable);
106	writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
107}
108#else
109#define dw_apb_ictl_resume	NULL
110#endif /* CONFIG_PM */
111
112static int __init dw_apb_ictl_init(struct device_node *np,
113				   struct device_node *parent)
114{
115	const struct irq_domain_ops *domain_ops;
116	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
117	struct resource r;
118	struct irq_domain *domain;
119	struct irq_chip_generic *gc;
120	void __iomem *iobase;
121	int ret, nrirqs, parent_irq, i;
122	u32 reg;
123
124	if (!parent) {
125		/* Used as the primary interrupt controller */
126		parent_irq = 0;
127		domain_ops = &dw_apb_ictl_irq_domain_ops;
128	} else {
129		/* Map the parent interrupt for the chained handler */
130		parent_irq = irq_of_parse_and_map(np, 0);
131		if (parent_irq <= 0) {
132			pr_err("%pOF: unable to parse irq\n", np);
133			return -EINVAL;
134		}
135		domain_ops = &irq_generic_chip_ops;
136	}
137
138	ret = of_address_to_resource(np, 0, &r);
139	if (ret) {
140		pr_err("%pOF: unable to get resource\n", np);
141		return ret;
142	}
143
144	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
145		pr_err("%pOF: unable to request mem region\n", np);
146		return -ENOMEM;
147	}
148
149	iobase = ioremap(r.start, resource_size(&r));
150	if (!iobase) {
151		pr_err("%pOF: unable to map resource\n", np);
152		ret = -ENOMEM;
153		goto err_release;
154	}
155
156	/*
157	 * DW IP can be configured to allow 2-64 irqs. We can determine
158	 * the number of irqs supported by writing into enable register
159	 * and look for bits not set, as corresponding flip-flops will
160	 * have been removed by synthesis tool.
161	 */
162
163	/* mask and enable all interrupts */
164	writel_relaxed(~0, iobase + APB_INT_MASK_L);
165	writel_relaxed(~0, iobase + APB_INT_MASK_H);
166	writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
167	writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
168
169	reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
170	if (reg)
171		nrirqs = 32 + fls(reg);
172	else
173		nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
174
175	domain = irq_domain_create_linear(of_fwnode_handle(np), nrirqs, domain_ops, NULL);
176	if (!domain) {
177		pr_err("%pOF: unable to add irq domain\n", np);
178		ret = -ENOMEM;
179		goto err_unmap;
180	}
181
182	ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name,
183					     handle_level_irq, clr, 0,
184					     IRQ_GC_INIT_MASK_CACHE);
185	if (ret) {
186		pr_err("%pOF: unable to alloc irq domain gc\n", np);
187		goto err_unmap;
188	}
189
190	for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) {
191		gc = irq_get_domain_generic_chip(domain, i * 32);
192		gc->reg_base = iobase + i * APB_INT_BASE_OFFSET;
193		gc->chip_types[0].regs.mask = APB_INT_MASK_L;
194		gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;
195		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
196		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
197		gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
198	}
199
200	if (parent_irq) {
201		irq_set_chained_handler_and_data(parent_irq,
202				dw_apb_ictl_handle_irq_cascaded, domain);
203	} else {
204		dw_apb_ictl_irq_domain = domain;
205		set_handle_irq(dw_apb_ictl_handle_irq);
206	}
207
208	return 0;
209
210err_unmap:
211	iounmap(iobase);
212err_release:
213	release_mem_region(r.start, resource_size(&r));
214	return ret;
215}
216IRQCHIP_DECLARE(dw_apb_ictl,
217		"snps,dw-apb-ictl", dw_apb_ictl_init);