irq-csky-apb-intc.c

  1// SPDX-License-Identifier: GPL-2.0
  2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
  3
  4#include <linux/kernel.h>
  5#include <linux/init.h>
  6#include <linux/of.h>
  7#include <linux/of_address.h>
  8#include <linux/module.h>
  9#include <linux/irqdomain.h>
 10#include <linux/irqchip.h>
 11#include <linux/irq.h>
 12#include <linux/interrupt.h>
 13#include <linux/io.h>
 14#include <asm/irq.h>
 15
 16#define INTC_IRQS		64
 17
 18#define CK_INTC_ICR		0x00
 19#define CK_INTC_PEN31_00	0x14
 20#define CK_INTC_PEN63_32	0x2c
 21#define CK_INTC_NEN31_00	0x10
 22#define CK_INTC_NEN63_32	0x28
 23#define CK_INTC_SOURCE		0x40
 24#define CK_INTC_DUAL_BASE	0x100
 25
 26#define GX_INTC_PEN31_00	0x00
 27#define GX_INTC_PEN63_32	0x04
 28#define GX_INTC_NEN31_00	0x40
 29#define GX_INTC_NEN63_32	0x44
 30#define GX_INTC_NMASK31_00	0x50
 31#define GX_INTC_NMASK63_32	0x54
 32#define GX_INTC_SOURCE		0x60
 33
 34static void __iomem *reg_base;
 35static struct irq_domain *root_domain;
 36
 37static int nr_irq = INTC_IRQS;
 38
 39/*
 40 * When controller support pulse signal, the PEN_reg will hold on signal
 41 * without software trigger.
 42 *
 43 * So, to support pulse signal we need to clear IFR_reg and the address of
 44 * IFR_offset is NEN_offset - 8.
 45 */
 46static void irq_ck_mask_set_bit(struct irq_data *d)
 47{
 48	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 49	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 50	unsigned long ifr = ct->regs.mask - 8;
 51	u32 mask = d->mask;
 52
 53	guard(raw_spinlock)(&gc->lock);
 54	*ct->mask_cache |= mask;
 55	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
 56	irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
 57}
 58
 59static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base,
 60			     u32 mask_reg, u32 irq_base)
 61{
 62	struct irq_chip_generic *gc;
 63
 64	gc = irq_get_domain_generic_chip(root_domain, irq_base);
 65	gc->reg_base = reg_base;
 66	gc->chip_types[0].regs.mask = mask_reg;
 67	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
 68	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
 69
 70	if (of_property_read_bool(node, "csky,support-pulse-signal"))
 71		gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit;
 72}
 73
 74static inline u32 build_channel_val(u32 idx, u32 magic)
 75{
 76	u32 res;
 77
 78	/*
 79	 * Set the same index for each channel
 80	 */
 81	res = idx | (idx << 8) | (idx << 16) | (idx << 24);
 82
 83	/*
 84	 * Set the channel magic number in descending order.
 85	 * The magic is 0x00010203 for ck-intc
 86	 * The magic is 0x03020100 for gx6605s-intc
 87	 */
 88	return res | magic;
 89}
 90
 91static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr)
 92{
 93	u32 i;
 94
 95	/* Setup 64 channel slots */
 96	for (i = 0; i < INTC_IRQS; i += 4)
 97		writel(build_channel_val(i, magic), reg_addr + i);
 98}
 99
100static int __init
101ck_intc_init_comm(struct device_node *node, struct device_node *parent)
102{
103	int ret;
104
105	if (parent) {
106		pr_err("C-SKY Intc not a root irq controller\n");
107		return -EINVAL;
108	}
109
110	reg_base = of_iomap(node, 0);
111	if (!reg_base) {
112		pr_err("C-SKY Intc unable to map: %p.\n", node);
113		return -EINVAL;
114	}
115
116	root_domain = irq_domain_create_linear(of_fwnode_handle(node), nr_irq,
117					    &irq_generic_chip_ops, NULL);
118	if (!root_domain) {
119		pr_err("C-SKY Intc irq_domain_add failed.\n");
120		return -ENOMEM;
121	}
122
123	ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
124			"csky_intc", handle_level_irq,
125			IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0, 0);
126	if (ret) {
127		pr_err("C-SKY Intc irq_alloc_gc failed.\n");
128		return -ENOMEM;
129	}
130
131	return 0;
132}
133
134static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq,
135				     u32 irq_base)
136{
137	if (hwirq == 0)
138		return false;
139
140	generic_handle_domain_irq(root_domain, irq_base + __fls(hwirq));
141
142	return true;
143}
144
145/* gx6605s 64 irqs interrupt controller */
146static void gx_irq_handler(struct pt_regs *regs)
147{
148	bool ret;
149
150retry:
151	ret = handle_irq_perbit(regs,
152			readl(reg_base + GX_INTC_PEN63_32), 32);
153	if (ret)
154		goto retry;
155
156	ret = handle_irq_perbit(regs,
157			readl(reg_base + GX_INTC_PEN31_00), 0);
158	if (ret)
159		goto retry;
160}
161
162static int __init
163gx_intc_init(struct device_node *node, struct device_node *parent)
164{
165	int ret;
166
167	ret = ck_intc_init_comm(node, parent);
168	if (ret)
169		return ret;
170
171	/*
172	 * Initial enable reg to disable all interrupts
173	 */
174	writel(0x0, reg_base + GX_INTC_NEN31_00);
175	writel(0x0, reg_base + GX_INTC_NEN63_32);
176
177	/*
178	 * Initial mask reg with all unmasked, because we only use enable reg
179	 */
180	writel(0x0, reg_base + GX_INTC_NMASK31_00);
181	writel(0x0, reg_base + GX_INTC_NMASK63_32);
182
183	setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE);
184
185	ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0);
186	ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32);
187
188	set_handle_irq(gx_irq_handler);
189
190	return 0;
191}
192IRQCHIP_DECLARE(csky_gx6605s_intc, "csky,gx6605s-intc", gx_intc_init);
193
194/*
195 * C-SKY simple 64 irqs interrupt controller, dual-together could support 128
196 * irqs.
197 */
198static void ck_irq_handler(struct pt_regs *regs)
199{
200	bool ret;
201	void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00;
202	void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32;
203
204retry:
205	/* handle 0 - 63 irqs */
206	ret = handle_irq_perbit(regs, readl(reg_pen_hi), 32);
207	if (ret)
208		goto retry;
209
210	ret = handle_irq_perbit(regs, readl(reg_pen_lo), 0);
211	if (ret)
212		goto retry;
213
214	if (nr_irq == INTC_IRQS)
215		return;
216
217	/* handle 64 - 127 irqs */
218	ret = handle_irq_perbit(regs,
219			readl(reg_pen_hi + CK_INTC_DUAL_BASE), 96);
220	if (ret)
221		goto retry;
222
223	ret = handle_irq_perbit(regs,
224			readl(reg_pen_lo + CK_INTC_DUAL_BASE), 64);
225	if (ret)
226		goto retry;
227}
228
229static int __init
230ck_intc_init(struct device_node *node, struct device_node *parent)
231{
232	int ret;
233
234	ret = ck_intc_init_comm(node, parent);
235	if (ret)
236		return ret;
237
238	/* Initial enable reg to disable all interrupts */
239	writel(0, reg_base + CK_INTC_NEN31_00);
240	writel(0, reg_base + CK_INTC_NEN63_32);
241
242	/* Enable irq intc */
243	writel(BIT(31), reg_base + CK_INTC_ICR);
244
245	ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0);
246	ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32);
247
248	setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE);
249
250	set_handle_irq(ck_irq_handler);
251
252	return 0;
253}
254IRQCHIP_DECLARE(ck_intc, "csky,apb-intc", ck_intc_init);
255
256static int __init
257ck_dual_intc_init(struct device_node *node, struct device_node *parent)
258{
259	int ret;
260
261	/* dual-apb-intc up to 128 irq sources*/
262	nr_irq = INTC_IRQS * 2;
263
264	ret = ck_intc_init(node, parent);
265	if (ret)
266		return ret;
267
268	/* Initial enable reg to disable all interrupts */
269	writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE);
270	writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE);
271
272	ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64);
273	ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96);
274
275	setup_irq_channel(0x00010203,
276			  reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE);
277
278	return 0;
279}
280IRQCHIP_DECLARE(ck_dual_intc, "csky,dual-apb-intc", ck_dual_intc_init);