irq-atmel-aic.c

  1/*
  2 * Atmel AT91 AIC (Advanced Interrupt Controller) driver
  3 *
  4 *  Copyright (C) 2004 SAN People
  5 *  Copyright (C) 2004 ATMEL
  6 *  Copyright (C) Rick Bronson
  7 *  Copyright (C) 2014 Free Electrons
  8 *
  9 *  Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 10 *
 11 * This file is licensed under the terms of the GNU General Public
 12 * License version 2.  This program is licensed "as is" without any
 13 * warranty of any kind, whether express or implied.
 14 */
 15
 16#include <linux/init.h>
 17#include <linux/module.h>
 18#include <linux/mm.h>
 19#include <linux/bitmap.h>
 20#include <linux/types.h>
 21#include <linux/irq.h>
 22#include <linux/irqchip.h>
 23#include <linux/of.h>
 24#include <linux/of_address.h>
 25#include <linux/of_irq.h>
 26#include <linux/irqdomain.h>
 27#include <linux/err.h>
 28#include <linux/slab.h>
 29#include <linux/io.h>
 30
 31#include <asm/exception.h>
 32#include <asm/mach/irq.h>
 33
 34#include "irq-atmel-aic-common.h"
 35
 36/* Number of irq lines managed by AIC */
 37#define NR_AIC_IRQS	32
 38
 39#define AT91_AIC_SMR(n)			((n) * 4)
 40
 41#define AT91_AIC_SVR(n)			(0x80 + ((n) * 4))
 42#define AT91_AIC_IVR			0x100
 43#define AT91_AIC_FVR			0x104
 44#define AT91_AIC_ISR			0x108
 45
 46#define AT91_AIC_IPR			0x10c
 47#define AT91_AIC_IMR			0x110
 48#define AT91_AIC_CISR			0x114
 49
 50#define AT91_AIC_IECR			0x120
 51#define AT91_AIC_IDCR			0x124
 52#define AT91_AIC_ICCR			0x128
 53#define AT91_AIC_ISCR			0x12c
 54#define AT91_AIC_EOICR			0x130
 55#define AT91_AIC_SPU			0x134
 56#define AT91_AIC_DCR			0x138
 57
 58static struct irq_domain *aic_domain;
 59
 60static void __exception_irq_entry aic_handle(struct pt_regs *regs)
 61{
 62	struct irq_domain_chip_generic *dgc = aic_domain->gc;
 63	struct irq_chip_generic *gc = dgc->gc[0];
 64	u32 irqnr;
 65	u32 irqstat;
 66
 67	irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
 68	irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
 69
 70	if (!irqstat)
 71		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
 72	else
 73		generic_handle_domain_irq(aic_domain, irqnr);
 74}
 75
 76static int aic_retrigger(struct irq_data *d)
 77{
 78	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 79
 80	/* Enable interrupt on AIC5 */
 81	guard(raw_spinlock)(&gc->lock);
 82	irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
 83
 84	return 1;
 85}
 86
 87static int aic_set_type(struct irq_data *d, unsigned type)
 88{
 89	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 90	unsigned int smr;
 91	int ret;
 92
 93	smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
 94	ret = aic_common_set_type(d, type, &smr);
 95	if (ret)
 96		return ret;
 97
 98	irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
 99
100	return 0;
101}
102
103#ifdef CONFIG_PM
104static void aic_suspend(struct irq_data *d)
105{
106	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
107
108	guard(raw_spinlock)(&gc->lock);
109	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
110	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
111}
112
113static void aic_resume(struct irq_data *d)
114{
115	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
116
117	guard(raw_spinlock)(&gc->lock);
118	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
119	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
120}
121
122static void aic_pm_shutdown(struct irq_data *d)
123{
124	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
125
126	guard(raw_spinlock)(&gc->lock);
127	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
128	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
129}
130#else
131#define aic_suspend		NULL
132#define aic_resume		NULL
133#define aic_pm_shutdown		NULL
134#endif /* CONFIG_PM */
135
136static void __init aic_hw_init(struct irq_domain *domain)
137{
138	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
139	int i;
140
141	/*
142	 * Perform 8 End Of Interrupt Command to make sure AIC
143	 * will not Lock out nIRQ
144	 */
145	for (i = 0; i < 8; i++)
146		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
147
148	/*
149	 * Spurious Interrupt ID in Spurious Vector Register.
150	 * When there is no current interrupt, the IRQ Vector Register
151	 * reads the value stored in AIC_SPU
152	 */
153	irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
154
155	/* No debugging in AIC: Debug (Protect) Control Register */
156	irq_reg_writel(gc, 0, AT91_AIC_DCR);
157
158	/* Disable and clear all interrupts initially */
159	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
160	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
161
162	for (i = 0; i < 32; i++)
163		irq_reg_writel(gc, i, AT91_AIC_SVR(i));
164}
165
166static int aic_irq_domain_xlate(struct irq_domain *d,
167				struct device_node *ctrlr,
168				const u32 *intspec, unsigned int intsize,
169				irq_hw_number_t *out_hwirq,
170				unsigned int *out_type)
171{
172	struct irq_domain_chip_generic *dgc = d->gc;
173	struct irq_chip_generic *gc;
174	unsigned smr;
175	int idx, ret;
176
177	if (!dgc)
178		return -EINVAL;
179
180	ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
181					  out_hwirq, out_type);
182	if (ret)
183		return ret;
184
185	idx = intspec[0] / dgc->irqs_per_chip;
186	if (idx >= dgc->num_chips)
187		return -EINVAL;
188
189	gc = dgc->gc[idx];
190
191	guard(raw_spinlock_irqsave)(&gc->lock);
192	smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
193	aic_common_set_priority(intspec[2], &smr);
194	irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
195
196	return ret;
197}
198
199static const struct irq_domain_ops aic_irq_ops = {
200	.map	= irq_map_generic_chip,
201	.xlate	= aic_irq_domain_xlate,
202};
203
204static void __init at91rm9200_aic_irq_fixup(void)
205{
206	aic_common_rtc_irq_fixup();
207}
208
209static void __init at91sam9260_aic_irq_fixup(void)
210{
211	aic_common_rtt_irq_fixup();
212}
213
214static void __init at91sam9g45_aic_irq_fixup(void)
215{
216	aic_common_rtc_irq_fixup();
217	aic_common_rtt_irq_fixup();
218}
219
220static const struct of_device_id aic_irq_fixups[] __initconst = {
221	{ .compatible = "atmel,at91rm9200", .data = at91rm9200_aic_irq_fixup },
222	{ .compatible = "atmel,at91sam9g45", .data = at91sam9g45_aic_irq_fixup },
223	{ .compatible = "atmel,at91sam9n12", .data = at91rm9200_aic_irq_fixup },
224	{ .compatible = "atmel,at91sam9rl", .data = at91sam9g45_aic_irq_fixup },
225	{ .compatible = "atmel,at91sam9x5", .data = at91rm9200_aic_irq_fixup },
226	{ .compatible = "atmel,at91sam9260", .data = at91sam9260_aic_irq_fixup },
227	{ .compatible = "atmel,at91sam9261", .data = at91sam9260_aic_irq_fixup },
228	{ .compatible = "atmel,at91sam9263", .data = at91sam9260_aic_irq_fixup },
229	{ .compatible = "atmel,at91sam9g20", .data = at91sam9260_aic_irq_fixup },
230	{ /* sentinel */ },
231};
232
233static int __init aic_of_init(struct device_node *node,
234			      struct device_node *parent)
235{
236	struct irq_chip_generic *gc;
237	struct irq_domain *domain;
238
239	if (aic_domain)
240		return -EEXIST;
241
242	domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
243				    NR_AIC_IRQS, aic_irq_fixups);
244	if (IS_ERR(domain))
245		return PTR_ERR(domain);
246
247	aic_domain = domain;
248	gc = irq_get_domain_generic_chip(domain, 0);
249
250	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
251	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
252	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
253	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
254	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
255	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
256	gc->chip_types[0].chip.irq_set_type = aic_set_type;
257	gc->chip_types[0].chip.irq_suspend = aic_suspend;
258	gc->chip_types[0].chip.irq_resume = aic_resume;
259	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
260
261	aic_hw_init(domain);
262	set_handle_irq(aic_handle);
263
264	return 0;
265}
266IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);