irq-atmel-aic-common.c

  1/*
  2 * Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
  3 * irq-atmel-aic and irq-atmel-aic5 drivers
  4 *
  5 *  Copyright (C) 2004 SAN People
  6 *  Copyright (C) 2004 ATMEL
  7 *  Copyright (C) Rick Bronson
  8 *  Copyright (C) 2014 Free Electrons
  9 *
 10 *  Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 11 *
 12 * This file is licensed under the terms of the GNU General Public
 13 * License version 2.  This program is licensed "as is" without any
 14 * warranty of any kind, whether express or implied.
 15 */
 16
 17#include <linux/errno.h>
 18#include <linux/io.h>
 19#include <linux/irq.h>
 20#include <linux/irqdomain.h>
 21#include <linux/of.h>
 22#include <linux/of_address.h>
 23#include <linux/slab.h>
 24
 25#include "irq-atmel-aic-common.h"
 26
 27#define AT91_AIC_PRIOR			GENMASK(2, 0)
 28#define AT91_AIC_IRQ_MIN_PRIORITY	0
 29#define AT91_AIC_IRQ_MAX_PRIORITY	7
 30
 31#define AT91_AIC_SRCTYPE		GENMASK(6, 5)
 32#define AT91_AIC_SRCTYPE_LOW		(0 << 5)
 33#define AT91_AIC_SRCTYPE_FALLING	(1 << 5)
 34#define AT91_AIC_SRCTYPE_HIGH		(2 << 5)
 35#define AT91_AIC_SRCTYPE_RISING		(3 << 5)
 36
 37struct aic_chip_data {
 38	u32 ext_irqs;
 39};
 40
 41static void aic_common_shutdown(struct irq_data *d)
 42{
 43	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 44
 45	ct->chip.irq_mask(d);
 46}
 47
 48int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
 49{
 50	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 51	struct aic_chip_data *aic = gc->private;
 52	unsigned aic_type;
 53
 54	switch (type) {
 55	case IRQ_TYPE_LEVEL_HIGH:
 56		aic_type = AT91_AIC_SRCTYPE_HIGH;
 57		break;
 58	case IRQ_TYPE_EDGE_RISING:
 59		aic_type = AT91_AIC_SRCTYPE_RISING;
 60		break;
 61	case IRQ_TYPE_LEVEL_LOW:
 62		if (!(d->mask & aic->ext_irqs))
 63			return -EINVAL;
 64
 65		aic_type = AT91_AIC_SRCTYPE_LOW;
 66		break;
 67	case IRQ_TYPE_EDGE_FALLING:
 68		if (!(d->mask & aic->ext_irqs))
 69			return -EINVAL;
 70
 71		aic_type = AT91_AIC_SRCTYPE_FALLING;
 72		break;
 73	default:
 74		return -EINVAL;
 75	}
 76
 77	*val &= ~AT91_AIC_SRCTYPE;
 78	*val |= aic_type;
 79
 80	return 0;
 81}
 82
 83void aic_common_set_priority(int priority, unsigned *val)
 84{
 85	*val &= ~AT91_AIC_PRIOR;
 86	*val |= priority;
 87}
 88
 89int aic_common_irq_domain_xlate(struct irq_domain *d,
 90				struct device_node *ctrlr,
 91				const u32 *intspec,
 92				unsigned int intsize,
 93				irq_hw_number_t *out_hwirq,
 94				unsigned int *out_type)
 95{
 96	if (WARN_ON(intsize < 3))
 97		return -EINVAL;
 98
 99	if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
100		    (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
101		return -EINVAL;
102
103	*out_hwirq = intspec[0];
104	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
105
106	return 0;
107}
108
109static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
110{
111	struct device_node *node = irq_domain_get_of_node(domain);
112	struct irq_chip_generic *gc;
113	struct aic_chip_data *aic;
114	u32 hwirq;
115
116	gc = irq_get_domain_generic_chip(domain, 0);
117
118	aic = gc->private;
119	aic->ext_irqs |= 1;
120
121	of_property_for_each_u32(node, "atmel,external-irqs", hwirq) {
122		gc = irq_get_domain_generic_chip(domain, hwirq);
123		if (!gc) {
124			pr_warn("AIC: external irq %d >= %d skip it\n",
125				hwirq, domain->revmap_size);
126			continue;
127		}
128
129		aic = gc->private;
130		aic->ext_irqs |= (1 << (hwirq % 32));
131	}
132}
133
134#define AT91_RTC_IDR           0x24
135#define AT91_RTC_IMR           0x28
136#define AT91_RTC_IRQ_MASK      0x1f
137
138void __init aic_common_rtc_irq_fixup(void)
139{
140	struct device_node *np;
141	void __iomem *regs;
142
143	np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-rtc");
144	if (!np)
145		np = of_find_compatible_node(NULL, NULL,
146					     "atmel,at91sam9x5-rtc");
147
148	if (!np)
149		return;
150
151	regs = of_iomap(np, 0);
152	of_node_put(np);
153
154	if (!regs)
155		return;
156
157	writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
158
159	iounmap(regs);
160}
161
162#define AT91_RTT_MR		0x00			/* Real-time Mode Register */
163#define AT91_RTT_ALMIEN		(1 << 16)		/* Alarm Interrupt Enable */
164#define AT91_RTT_RTTINCIEN	(1 << 17)		/* Real Time Timer Increment Interrupt Enable */
165
166void __init aic_common_rtt_irq_fixup(void)
167{
168	struct device_node *np;
169	void __iomem *regs;
170
171	/*
172	 * The at91sam9263 SoC has 2 instances of the RTT block, hence we
173	 * iterate over the DT to find each occurrence.
174	 */
175	for_each_compatible_node(np, NULL, "atmel,at91sam9260-rtt") {
176		regs = of_iomap(np, 0);
177		if (!regs)
178			continue;
179
180		writel(readl(regs + AT91_RTT_MR) &
181		       ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN),
182		       regs + AT91_RTT_MR);
183
184		iounmap(regs);
185	}
186}
187
188static void __init aic_common_irq_fixup(const struct of_device_id *matches)
189{
190	void (*fixup)(void);
191
192	fixup = of_machine_get_match_data(matches);
193	if (fixup)
194		fixup();
195}
196
197struct irq_domain *__init aic_common_of_init(struct device_node *node,
198					     const struct irq_domain_ops *ops,
199					     const char *name, int nirqs,
200					     const struct of_device_id *matches)
201{
202	struct irq_chip_generic *gc;
203	struct irq_domain *domain;
204	struct aic_chip_data *aic;
205	void __iomem *reg_base;
206	int nchips;
207	int ret;
208	int i;
209
210	nchips = DIV_ROUND_UP(nirqs, 32);
211
212	reg_base = of_iomap(node, 0);
213	if (!reg_base)
214		return ERR_PTR(-ENOMEM);
215
216	aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
217	if (!aic) {
218		ret = -ENOMEM;
219		goto err_iounmap;
220	}
221
222	domain = irq_domain_create_linear(of_fwnode_handle(node), nchips * 32, ops, aic);
223	if (!domain) {
224		ret = -ENOMEM;
225		goto err_free_aic;
226	}
227
228	ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
229					     handle_fasteoi_irq,
230					     IRQ_NOREQUEST | IRQ_NOPROBE |
231					     IRQ_NOAUTOEN, 0, 0);
232	if (ret)
233		goto err_domain_remove;
234
235	for (i = 0; i < nchips; i++) {
236		gc = irq_get_domain_generic_chip(domain, i * 32);
237
238		gc->reg_base = reg_base;
239
240		gc->unused = 0;
241		gc->wake_enabled = ~0;
242		gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
243		gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
244		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
245		gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
246		gc->private = &aic[i];
247	}
248
249	aic_common_ext_irq_of_init(domain);
250	aic_common_irq_fixup(matches);
251
252	return domain;
253
254err_domain_remove:
255	irq_domain_remove(domain);
256
257err_free_aic:
258	kfree(aic);
259
260err_iounmap:
261	iounmap(reg_base);
262
263	return ERR_PTR(ret);
264}