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rockchip-iommu.c
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linux-6.19.14/drivers/iommu/rockchip-iommu.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * IOMMU API for Rockchip 4 * 5 * Module Authors: Simon Xue <xxm@rock-chips.com> 6 * Daniel Kurtz <djkurtz@chromium.org> 7 */ 8 9#include <linux/clk.h> 10#include <linux/compiler.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/dma-mapping.h> 14#include <linux/errno.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/iommu.h> 18#include <linux/iopoll.h> 19#include <linux/list.h> 20#include <linux/mm.h> 21#include <linux/init.h> 22#include <linux/of.h> 23#include <linux/of_platform.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26#include <linux/slab.h> 27#include <linux/spinlock.h> 28#include <linux/string_choices.h> 29 30#include "iommu-pages.h" 31 32/** MMU register offsets */ 33#define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ 34#define RK_MMU_STATUS 0x04 35#define RK_MMU_COMMAND 0x08 36#define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ 37#define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ 38#define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ 39#define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ 40#define RK_MMU_INT_MASK 0x1C /* IRQ enable */ 41#define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ 42#define RK_MMU_AUTO_GATING 0x24 43 44#define DTE_ADDR_DUMMY 0xCAFEBABE 45 46#define RK_MMU_POLL_PERIOD_US 100 47#define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 48#define RK_MMU_POLL_TIMEOUT_US 1000 49 50/* RK_MMU_STATUS fields */ 51#define RK_MMU_STATUS_PAGING_ENABLED BIT(0) 52#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 53#define RK_MMU_STATUS_STALL_ACTIVE BIT(2) 54#define RK_MMU_STATUS_IDLE BIT(3) 55#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 56#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 57#define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) 58 59/* RK_MMU_COMMAND command values */ 60#define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 61#define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 62#define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 63#define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 64#define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 65#define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 66#define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ 67 68/* RK_MMU_INT_* register fields */ 69#define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 70#define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 71#define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) 72 73#define NUM_DT_ENTRIES 1024 74#define NUM_PT_ENTRIES 1024 75 76#define SPAGE_ORDER 12 77#define SPAGE_SIZE (1 << SPAGE_ORDER) 78 79 /* 80 * Support mapping any size that fits in one page table: 81 * 4 KiB to 4 MiB 82 */ 83#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 84 85struct rk_iommu_domain { 86 struct list_head iommus; 87 u32 *dt; /* page directory table */ 88 dma_addr_t dt_dma; 89 spinlock_t iommus_lock; /* lock for iommus list */ 90 spinlock_t dt_lock; /* lock for modifying page directory table */ 91 struct device *dma_dev; 92 93 struct iommu_domain domain; 94}; 95 96/* list of clocks required by IOMMU */ 97static const char * const rk_iommu_clocks[] = { 98 "aclk", "iface", 99}; 100 101struct rk_iommu_ops { 102 phys_addr_t (*pt_address)(u32 dte); 103 u32 (*mk_dtentries)(dma_addr_t pt_dma); 104 u32 (*mk_ptentries)(phys_addr_t page, int prot); 105 u64 dma_bit_mask; 106 gfp_t gfp_flags; 107}; 108 109struct rk_iommu { 110 struct device *dev; 111 void __iomem **bases; 112 int num_mmu; 113 int num_irq; 114 struct clk_bulk_data *clocks; 115 int num_clocks; 116 bool reset_disabled; 117 struct iommu_device iommu; 118 struct list_head node; /* entry in rk_iommu_domain.iommus */ 119 struct iommu_domain *domain; /* domain to which iommu is attached */ 120}; 121 122struct rk_iommudata { 123 struct device_link *link; /* runtime PM link from IOMMU to master */ 124 struct rk_iommu *iommu; 125}; 126 127static const struct rk_iommu_ops *rk_ops; 128static struct iommu_domain rk_identity_domain; 129 130static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, 131 unsigned int count) 132{ 133 size_t size = count * sizeof(u32); /* count of u32 entry */ 134 135 dma_sync_single_for_device(dom->dma_dev, dma, size, DMA_TO_DEVICE); 136} 137 138static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) 139{ 140 return container_of(dom, struct rk_iommu_domain, domain); 141} 142 143/* 144 * The Rockchip rk3288 iommu uses a 2-level page table. 145 * The first level is the "Directory Table" (DT). 146 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing 147 * to a "Page Table". 148 * The second level is the 1024 Page Tables (PT). 149 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to 150 * a 4 KB page of physical memory. 151 * 152 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). 153 * Each iommu device has a MMU_DTE_ADDR register that contains the physical 154 * address of the start of the DT page. 155 * 156 * The structure of the page table is as follows: 157 * 158 * DT 159 * MMU_DTE_ADDR -> +-----+ 160 * | | 161 * +-----+ PT 162 * | DTE | -> +-----+ 163 * +-----+ | | Memory 164 * | | +-----+ Page 165 * | | | PTE | -> +-----+ 166 * +-----+ +-----+ | | 167 * | | | | 168 * | | | | 169 * +-----+ | | 170 * | | 171 * | | 172 * +-----+ 173 */ 174 175/* 176 * Each DTE has a PT address and a valid bit: 177 * +---------------------+-----------+-+ 178 * | PT address | Reserved |V| 179 * +---------------------+-----------+-+ 180 * 31:12 - PT address (PTs always starts on a 4 KB boundary) 181 * 11: 1 - Reserved 182 * 0 - 1 if PT @ PT address is valid 183 */ 184#define RK_DTE_PT_ADDRESS_MASK 0xfffff000 185#define RK_DTE_PT_VALID BIT(0) 186 187static inline phys_addr_t rk_dte_pt_address(u32 dte) 188{ 189 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; 190} 191 192/* 193 * In v2: 194 * 31:12 - PT address bit 31:0 195 * 11: 8 - PT address bit 35:32 196 * 7: 4 - PT address bit 39:36 197 * 3: 1 - Reserved 198 * 0 - 1 if PT @ PT address is valid 199 */ 200#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4) 201#define DTE_HI_MASK1 GENMASK(11, 8) 202#define DTE_HI_MASK2 GENMASK(7, 4) 203#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ 204#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ 205#define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32) 206#define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36) 207 208static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) 209{ 210 u64 dte_v2 = dte; 211 212 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) | 213 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) | 214 (dte_v2 & RK_DTE_PT_ADDRESS_MASK); 215 216 return (phys_addr_t)dte_v2; 217} 218 219static inline bool rk_dte_is_pt_valid(u32 dte) 220{ 221 return dte & RK_DTE_PT_VALID; 222} 223 224static inline u32 rk_mk_dte(dma_addr_t pt_dma) 225{ 226 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; 227} 228 229static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma) 230{ 231 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) | 232 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) | 233 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2; 234 235 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID; 236} 237 238/* 239 * Each PTE has a Page address, some flags and a valid bit: 240 * +---------------------+---+-------+-+ 241 * | Page address |Rsv| Flags |V| 242 * +---------------------+---+-------+-+ 243 * 31:12 - Page address (Pages always start on a 4 KB boundary) 244 * 11: 9 - Reserved 245 * 8: 1 - Flags 246 * 8 - Read allocate - allocate cache space on read misses 247 * 7 - Read cache - enable cache & prefetch of data 248 * 6 - Write buffer - enable delaying writes on their way to memory 249 * 5 - Write allocate - allocate cache space on write misses 250 * 4 - Write cache - different writes can be merged together 251 * 3 - Override cache attributes 252 * if 1, bits 4-8 control cache attributes 253 * if 0, the system bus defaults are used 254 * 2 - Writable 255 * 1 - Readable 256 * 0 - 1 if Page @ Page address is valid 257 */ 258#define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 259#define RK_PTE_PAGE_FLAGS_MASK 0x000001fe 260#define RK_PTE_PAGE_WRITABLE BIT(2) 261#define RK_PTE_PAGE_READABLE BIT(1) 262#define RK_PTE_PAGE_VALID BIT(0) 263 264static inline bool rk_pte_is_page_valid(u32 pte) 265{ 266 return pte & RK_PTE_PAGE_VALID; 267} 268 269/* TODO: set cache flags per prot IOMMU_CACHE */ 270static u32 rk_mk_pte(phys_addr_t page, int prot) 271{ 272 u32 flags = 0; 273 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 274 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 275 page &= RK_PTE_PAGE_ADDRESS_MASK; 276 return page | flags | RK_PTE_PAGE_VALID; 277} 278 279/* 280 * In v2: 281 * 31:12 - Page address bit 31:0 282 * 11: 8 - Page address bit 35:32 283 * 7: 4 - Page address bit 39:36 284 * 3 - Security 285 * 2 - Writable 286 * 1 - Readable 287 * 0 - 1 if Page @ Page address is valid 288 */ 289 290static u32 rk_mk_pte_v2(phys_addr_t page, int prot) 291{ 292 u32 flags = 0; 293 294 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 295 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 296 297 return rk_mk_dte_v2(page) | flags; 298} 299 300static u32 rk_mk_pte_invalid(u32 pte) 301{ 302 return pte & ~RK_PTE_PAGE_VALID; 303} 304 305/* 306 * rk3288 iova (IOMMU Virtual Address) format 307 * 31 22.21 12.11 0 308 * +-----------+-----------+-------------+ 309 * | DTE index | PTE index | Page offset | 310 * +-----------+-----------+-------------+ 311 * 31:22 - DTE index - index of DTE in DT 312 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address 313 * 11: 0 - Page offset - offset into page @ PTE.page_address 314 */ 315#define RK_IOVA_DTE_MASK 0xffc00000 316#define RK_IOVA_DTE_SHIFT 22 317#define RK_IOVA_PTE_MASK 0x003ff000 318#define RK_IOVA_PTE_SHIFT 12 319#define RK_IOVA_PAGE_MASK 0x00000fff 320#define RK_IOVA_PAGE_SHIFT 0 321 322static u32 rk_iova_dte_index(dma_addr_t iova) 323{ 324 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; 325} 326 327static u32 rk_iova_pte_index(dma_addr_t iova) 328{ 329 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; 330} 331 332static u32 rk_iova_page_offset(dma_addr_t iova) 333{ 334 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; 335} 336 337static u32 rk_iommu_read(void __iomem *base, u32 offset) 338{ 339 return readl(base + offset); 340} 341 342static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) 343{ 344 writel(value, base + offset); 345} 346 347static void rk_iommu_command(struct rk_iommu *iommu, u32 command) 348{ 349 int i; 350 351 for (i = 0; i < iommu->num_mmu; i++) 352 writel(command, iommu->bases[i] + RK_MMU_COMMAND); 353} 354 355static void rk_iommu_base_command(void __iomem *base, u32 command) 356{ 357 writel(command, base + RK_MMU_COMMAND); 358} 359static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, 360 size_t size) 361{ 362 int i; 363 dma_addr_t iova_end = iova_start + size; 364 /* 365 * TODO(djkurtz): Figure out when it is more efficient to shootdown the 366 * entire iotlb rather than iterate over individual iovas. 367 */ 368 for (i = 0; i < iommu->num_mmu; i++) { 369 dma_addr_t iova; 370 371 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) 372 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); 373 } 374} 375 376static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) 377{ 378 bool active = true; 379 int i; 380 381 for (i = 0; i < iommu->num_mmu; i++) 382 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 383 RK_MMU_STATUS_STALL_ACTIVE); 384 385 return active; 386} 387 388static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) 389{ 390 bool enable = true; 391 int i; 392 393 for (i = 0; i < iommu->num_mmu; i++) 394 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 395 RK_MMU_STATUS_PAGING_ENABLED); 396 397 return enable; 398} 399 400static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) 401{ 402 bool done = true; 403 int i; 404 405 for (i = 0; i < iommu->num_mmu; i++) 406 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; 407 408 return done; 409} 410 411static int rk_iommu_enable_stall(struct rk_iommu *iommu) 412{ 413 int ret, i; 414 bool val; 415 416 if (rk_iommu_is_stall_active(iommu)) 417 return 0; 418 419 /* Stall can only be enabled if paging is enabled */ 420 if (!rk_iommu_is_paging_enabled(iommu)) 421 return 0; 422 423 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); 424 425 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 426 val, RK_MMU_POLL_PERIOD_US, 427 RK_MMU_POLL_TIMEOUT_US); 428 if (ret) 429 for (i = 0; i < iommu->num_mmu; i++) 430 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", 431 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 432 433 return ret; 434} 435 436static int rk_iommu_disable_stall(struct rk_iommu *iommu) 437{ 438 int ret, i; 439 bool val; 440 441 if (!rk_iommu_is_stall_active(iommu)) 442 return 0; 443 444 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); 445 446 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 447 !val, RK_MMU_POLL_PERIOD_US, 448 RK_MMU_POLL_TIMEOUT_US); 449 if (ret) 450 for (i = 0; i < iommu->num_mmu; i++) 451 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", 452 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 453 454 return ret; 455} 456 457static int rk_iommu_enable_paging(struct rk_iommu *iommu) 458{ 459 int ret, i; 460 bool val; 461 462 if (rk_iommu_is_paging_enabled(iommu)) 463 return 0; 464 465 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); 466 467 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 468 val, RK_MMU_POLL_PERIOD_US, 469 RK_MMU_POLL_TIMEOUT_US); 470 if (ret) 471 for (i = 0; i < iommu->num_mmu; i++) 472 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", 473 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 474 475 return ret; 476} 477 478static int rk_iommu_disable_paging(struct rk_iommu *iommu) 479{ 480 int ret, i; 481 bool val; 482 483 if (!rk_iommu_is_paging_enabled(iommu)) 484 return 0; 485 486 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); 487 488 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 489 !val, RK_MMU_POLL_PERIOD_US, 490 RK_MMU_POLL_TIMEOUT_US); 491 if (ret) 492 for (i = 0; i < iommu->num_mmu; i++) 493 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", 494 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 495 496 return ret; 497} 498 499static int rk_iommu_force_reset(struct rk_iommu *iommu) 500{ 501 int ret, i; 502 u32 dte_addr; 503 bool val; 504 505 if (iommu->reset_disabled) 506 return 0; 507 508 /* 509 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY 510 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back. 511 */ 512 for (i = 0; i < iommu->num_mmu; i++) { 513 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); 514 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 515 516 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { 517 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); 518 return -EFAULT; 519 } 520 } 521 522 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); 523 524 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, 525 val, RK_MMU_FORCE_RESET_TIMEOUT_US, 526 RK_MMU_POLL_TIMEOUT_US); 527 if (ret) { 528 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); 529 return ret; 530 } 531 532 return 0; 533} 534 535static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) 536{ 537 void __iomem *base = iommu->bases[index]; 538 u32 dte_index, pte_index, page_offset; 539 u32 mmu_dte_addr; 540 phys_addr_t mmu_dte_addr_phys, dte_addr_phys; 541 u32 *dte_addr; 542 u32 dte; 543 phys_addr_t pte_addr_phys = 0; 544 u32 *pte_addr = NULL; 545 u32 pte = 0; 546 phys_addr_t page_addr_phys = 0; 547 u32 page_flags = 0; 548 549 dte_index = rk_iova_dte_index(iova); 550 pte_index = rk_iova_pte_index(iova); 551 page_offset = rk_iova_page_offset(iova); 552 553 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); 554 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr); 555 556 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); 557 dte_addr = phys_to_virt(dte_addr_phys); 558 dte = *dte_addr; 559 560 if (!rk_dte_is_pt_valid(dte)) 561 goto print_it; 562 563 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); 564 pte_addr = phys_to_virt(pte_addr_phys); 565 pte = *pte_addr; 566 567 if (!rk_pte_is_page_valid(pte)) 568 goto print_it; 569 570 page_addr_phys = rk_ops->pt_address(pte) + page_offset; 571 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; 572 573print_it: 574 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", 575 &iova, dte_index, pte_index, page_offset); 576 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", 577 &mmu_dte_addr_phys, &dte_addr_phys, dte, 578 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, 579 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); 580} 581 582static irqreturn_t rk_iommu_irq(int irq, void *dev_id) 583{ 584 struct rk_iommu *iommu = dev_id; 585 u32 status; 586 u32 int_status; 587 dma_addr_t iova; 588 irqreturn_t ret = IRQ_NONE; 589 int i, err; 590 591 err = pm_runtime_get_if_in_use(iommu->dev); 592 if (!err || WARN_ON_ONCE(err < 0)) 593 return ret; 594 595 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 596 goto out; 597 598 for (i = 0; i < iommu->num_mmu; i++) { 599 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); 600 if (int_status == 0) 601 continue; 602 603 ret = IRQ_HANDLED; 604 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); 605 606 if (int_status & RK_MMU_IRQ_PAGE_FAULT) { 607 int flags; 608 609 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); 610 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? 611 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 612 613 dev_err(iommu->dev, "Page fault at %pad of type %s\n", 614 &iova, 615 str_write_read(flags == IOMMU_FAULT_WRITE)); 616 617 log_iova(iommu, i, iova); 618 619 /* 620 * Report page fault to any installed handlers. 621 * Ignore the return code, though, since we always zap cache 622 * and clear the page fault anyway. 623 */ 624 if (iommu->domain != &rk_identity_domain) 625 report_iommu_fault(iommu->domain, iommu->dev, iova, 626 flags); 627 else 628 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); 629 630 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 631 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); 632 } 633 634 if (int_status & RK_MMU_IRQ_BUS_ERROR) 635 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); 636 637 if (int_status & ~RK_MMU_IRQ_MASK) 638 dev_err(iommu->dev, "unexpected int_status: %#08x\n", 639 int_status); 640 641 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); 642 } 643 644 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 645 646out: 647 pm_runtime_put(iommu->dev); 648 return ret; 649} 650 651static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, 652 dma_addr_t iova) 653{ 654 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 655 unsigned long flags; 656 phys_addr_t pt_phys, phys = 0; 657 u32 dte, pte; 658 u32 *page_table; 659 660 spin_lock_irqsave(&rk_domain->dt_lock, flags); 661 662 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 663 if (!rk_dte_is_pt_valid(dte)) 664 goto out; 665 666 pt_phys = rk_ops->pt_address(dte); 667 page_table = (u32 *)phys_to_virt(pt_phys); 668 pte = page_table[rk_iova_pte_index(iova)]; 669 if (!rk_pte_is_page_valid(pte)) 670 goto out; 671 672 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); 673out: 674 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 675 676 return phys; 677} 678 679static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, 680 dma_addr_t iova, size_t size) 681{ 682 struct list_head *pos; 683 unsigned long flags; 684 685 /* shootdown these iova from all iommus using this domain */ 686 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 687 list_for_each(pos, &rk_domain->iommus) { 688 struct rk_iommu *iommu; 689 int ret; 690 691 iommu = list_entry(pos, struct rk_iommu, node); 692 693 /* Only zap TLBs of IOMMUs that are powered on. */ 694 ret = pm_runtime_get_if_in_use(iommu->dev); 695 if (WARN_ON_ONCE(ret < 0)) 696 continue; 697 if (ret) { 698 WARN_ON(clk_bulk_enable(iommu->num_clocks, 699 iommu->clocks)); 700 rk_iommu_zap_lines(iommu, iova, size); 701 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 702 pm_runtime_put(iommu->dev); 703 } 704 } 705 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 706} 707 708static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, 709 dma_addr_t iova, size_t size) 710{ 711 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); 712 if (size > SPAGE_SIZE) 713 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, 714 SPAGE_SIZE); 715} 716 717static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, 718 dma_addr_t iova) 719{ 720 u32 *page_table, *dte_addr; 721 u32 dte_index, dte; 722 phys_addr_t pt_phys; 723 dma_addr_t pt_dma; 724 725 assert_spin_locked(&rk_domain->dt_lock); 726 727 dte_index = rk_iova_dte_index(iova); 728 dte_addr = &rk_domain->dt[dte_index]; 729 dte = *dte_addr; 730 if (rk_dte_is_pt_valid(dte)) 731 goto done; 732 733 page_table = iommu_alloc_pages_sz(GFP_ATOMIC | rk_ops->gfp_flags, 734 SPAGE_SIZE); 735 if (!page_table) 736 return ERR_PTR(-ENOMEM); 737 738 pt_dma = dma_map_single(rk_domain->dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); 739 if (dma_mapping_error(rk_domain->dma_dev, pt_dma)) { 740 dev_err(rk_domain->dma_dev, "DMA mapping error while allocating page table\n"); 741 iommu_free_pages(page_table); 742 return ERR_PTR(-ENOMEM); 743 } 744 745 dte = rk_ops->mk_dtentries(pt_dma); 746 *dte_addr = dte; 747 748 rk_table_flush(rk_domain, 749 rk_domain->dt_dma + dte_index * sizeof(u32), 1); 750done: 751 pt_phys = rk_ops->pt_address(dte); 752 return (u32 *)phys_to_virt(pt_phys); 753} 754 755static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, 756 u32 *pte_addr, dma_addr_t pte_dma, 757 size_t size) 758{ 759 unsigned int pte_count; 760 unsigned int pte_total = size / SPAGE_SIZE; 761 762 assert_spin_locked(&rk_domain->dt_lock); 763 764 for (pte_count = 0; pte_count < pte_total; pte_count++) { 765 u32 pte = pte_addr[pte_count]; 766 if (!rk_pte_is_page_valid(pte)) 767 break; 768 769 pte_addr[pte_count] = rk_mk_pte_invalid(pte); 770 } 771 772 rk_table_flush(rk_domain, pte_dma, pte_count); 773 774 return pte_count * SPAGE_SIZE; 775} 776 777static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, 778 dma_addr_t pte_dma, dma_addr_t iova, 779 phys_addr_t paddr, size_t size, int prot) 780{ 781 unsigned int pte_count; 782 unsigned int pte_total = size / SPAGE_SIZE; 783 phys_addr_t page_phys; 784 785 assert_spin_locked(&rk_domain->dt_lock); 786 787 for (pte_count = 0; pte_count < pte_total; pte_count++) { 788 u32 pte = pte_addr[pte_count]; 789 790 if (rk_pte_is_page_valid(pte)) 791 goto unwind; 792 793 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); 794 795 paddr += SPAGE_SIZE; 796 } 797 798 rk_table_flush(rk_domain, pte_dma, pte_total); 799 800 /* 801 * Zap the first and last iova to evict from iotlb any previously 802 * mapped cachelines holding stale values for its dte and pte. 803 * We only zap the first and last iova, since only they could have 804 * dte or pte shared with an existing mapping. 805 */ 806 rk_iommu_zap_iova_first_last(rk_domain, iova, size); 807 808 return 0; 809unwind: 810 /* Unmap the range of iovas that we just mapped */ 811 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, 812 pte_count * SPAGE_SIZE); 813 814 iova += pte_count * SPAGE_SIZE; 815 page_phys = rk_ops->pt_address(pte_addr[pte_count]); 816 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", 817 &iova, &page_phys, &paddr, prot); 818 819 return -EADDRINUSE; 820} 821 822static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, 823 phys_addr_t paddr, size_t size, size_t count, 824 int prot, gfp_t gfp, size_t *mapped) 825{ 826 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 827 unsigned long flags; 828 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 829 u32 *page_table, *pte_addr; 830 u32 dte_index, pte_index; 831 int ret; 832 833 spin_lock_irqsave(&rk_domain->dt_lock, flags); 834 835 /* 836 * pgsize_bitmap specifies iova sizes that fit in one page table 837 * (1024 4-KiB pages = 4 MiB). 838 * So, size will always be 4096 <= size <= 4194304. 839 * Since iommu_map() guarantees that both iova and size will be 840 * aligned, we will always only be mapping from a single dte here. 841 */ 842 page_table = rk_dte_get_page_table(rk_domain, iova); 843 if (IS_ERR(page_table)) { 844 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 845 return PTR_ERR(page_table); 846 } 847 848 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; 849 pte_index = rk_iova_pte_index(iova); 850 pte_addr = &page_table[pte_index]; 851 852 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); 853 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, 854 paddr, size, prot); 855 856 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 857 if (!ret) 858 *mapped = size; 859 860 return ret; 861} 862 863static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, 864 size_t size, size_t count, struct iommu_iotlb_gather *gather) 865{ 866 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 867 unsigned long flags; 868 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 869 phys_addr_t pt_phys; 870 u32 dte; 871 u32 *pte_addr; 872 size_t unmap_size; 873 874 spin_lock_irqsave(&rk_domain->dt_lock, flags); 875 876 /* 877 * pgsize_bitmap specifies iova sizes that fit in one page table 878 * (1024 4-KiB pages = 4 MiB). 879 * So, size will always be 4096 <= size <= 4194304. 880 * Since iommu_unmap() guarantees that both iova and size will be 881 * aligned, we will always only be unmapping from a single dte here. 882 */ 883 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 884 /* Just return 0 if iova is unmapped */ 885 if (!rk_dte_is_pt_valid(dte)) { 886 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 887 return 0; 888 } 889 890 pt_phys = rk_ops->pt_address(dte); 891 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); 892 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); 893 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); 894 895 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 896 897 /* Shootdown iotlb entries for iova range that was just unmapped */ 898 rk_iommu_zap_iova(rk_domain, iova, unmap_size); 899 900 return unmap_size; 901} 902 903static struct rk_iommu *rk_iommu_from_dev(struct device *dev) 904{ 905 struct rk_iommudata *data = dev_iommu_priv_get(dev); 906 907 return data ? data->iommu : NULL; 908} 909 910/* Must be called with iommu powered on and attached */ 911static void rk_iommu_disable(struct rk_iommu *iommu) 912{ 913 int i; 914 915 /* Ignore error while disabling, just keep going */ 916 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); 917 rk_iommu_enable_stall(iommu); 918 rk_iommu_disable_paging(iommu); 919 for (i = 0; i < iommu->num_mmu; i++) { 920 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); 921 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); 922 } 923 rk_iommu_disable_stall(iommu); 924 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 925} 926 927/* Must be called with iommu powered on and attached */ 928static int rk_iommu_enable(struct rk_iommu *iommu) 929{ 930 struct iommu_domain *domain = iommu->domain; 931 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 932 int ret, i; 933 934 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); 935 if (ret) 936 return ret; 937 938 ret = rk_iommu_enable_stall(iommu); 939 if (ret) 940 goto out_disable_clocks; 941 942 ret = rk_iommu_force_reset(iommu); 943 if (ret) 944 goto out_disable_stall; 945 946 for (i = 0; i < iommu->num_mmu; i++) { 947 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 948 rk_ops->mk_dtentries(rk_domain->dt_dma)); 949 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 950 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 951 } 952 953 ret = rk_iommu_enable_paging(iommu); 954 955out_disable_stall: 956 rk_iommu_disable_stall(iommu); 957out_disable_clocks: 958 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 959 return ret; 960} 961 962static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, 963 struct device *dev, 964 struct iommu_domain *old) 965{ 966 struct rk_iommu *iommu; 967 struct rk_iommu_domain *rk_domain; 968 unsigned long flags; 969 int ret; 970 971 /* Allow 'virtual devices' (eg drm) to detach from domain */ 972 iommu = rk_iommu_from_dev(dev); 973 if (!iommu) 974 return -ENODEV; 975 976 rk_domain = to_rk_domain(iommu->domain); 977 978 dev_dbg(dev, "Detaching from iommu domain\n"); 979 980 if (iommu->domain == identity_domain) 981 return 0; 982 983 iommu->domain = identity_domain; 984 985 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 986 list_del_init(&iommu->node); 987 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 988 989 ret = pm_runtime_get_if_in_use(iommu->dev); 990 WARN_ON_ONCE(ret < 0); 991 if (ret > 0) { 992 rk_iommu_disable(iommu); 993 pm_runtime_put(iommu->dev); 994 } 995 996 return 0; 997} 998 999static struct iommu_domain_ops rk_identity_ops = { 1000 .attach_dev = rk_iommu_identity_attach, 1001}; 1002 1003static struct iommu_domain rk_identity_domain = { 1004 .type = IOMMU_DOMAIN_IDENTITY, 1005 .ops = &rk_identity_ops, 1006}; 1007 1008static int rk_iommu_attach_device(struct iommu_domain *domain, 1009 struct device *dev, struct iommu_domain *old) 1010{ 1011 struct rk_iommu *iommu; 1012 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1013 unsigned long flags; 1014 int ret; 1015 1016 /* 1017 * Allow 'virtual devices' (e.g., drm) to attach to domain. 1018 * Such a device does not belong to an iommu group. 1019 */ 1020 iommu = rk_iommu_from_dev(dev); 1021 if (!iommu) 1022 return 0; 1023 1024 dev_dbg(dev, "Attaching to iommu domain\n"); 1025 1026 /* iommu already attached */ 1027 if (iommu->domain == domain) 1028 return 0; 1029 1030 ret = rk_iommu_identity_attach(&rk_identity_domain, dev, old); 1031 if (ret) 1032 return ret; 1033 1034 iommu->domain = domain; 1035 1036 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1037 list_add_tail(&iommu->node, &rk_domain->iommus); 1038 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1039 1040 ret = pm_runtime_get_if_in_use(iommu->dev); 1041 if (!ret || WARN_ON_ONCE(ret < 0)) 1042 return 0; 1043 1044 ret = rk_iommu_enable(iommu); 1045 if (ret) { 1046 /* 1047 * Note rk_iommu_identity_attach() might fail before physically 1048 * attaching the dev to iommu->domain, in which case the actual 1049 * old domain for this revert should be rk_identity_domain v.s. 1050 * iommu->domain. Since rk_iommu_identity_attach() does not care 1051 * about the old domain argument for now, this is not a problem. 1052 */ 1053 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev, 1054 iommu->domain)); 1055 } 1056 1057 pm_runtime_put(iommu->dev); 1058 1059 return ret; 1060} 1061 1062static struct iommu_domain *rk_iommu_domain_alloc_paging(struct device *dev) 1063{ 1064 struct rk_iommu_domain *rk_domain; 1065 struct rk_iommu *iommu; 1066 1067 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL); 1068 if (!rk_domain) 1069 return NULL; 1070 1071 /* 1072 * rk32xx iommus use a 2 level pagetable. 1073 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. 1074 * Allocate one 4 KiB page for each table. 1075 */ 1076 rk_domain->dt = iommu_alloc_pages_sz(GFP_KERNEL | rk_ops->gfp_flags, 1077 SPAGE_SIZE); 1078 if (!rk_domain->dt) 1079 goto err_free_domain; 1080 1081 iommu = rk_iommu_from_dev(dev); 1082 rk_domain->dma_dev = iommu->dev; 1083 rk_domain->dt_dma = dma_map_single(rk_domain->dma_dev, rk_domain->dt, 1084 SPAGE_SIZE, DMA_TO_DEVICE); 1085 if (dma_mapping_error(rk_domain->dma_dev, rk_domain->dt_dma)) { 1086 dev_err(rk_domain->dma_dev, "DMA map error for DT\n"); 1087 goto err_free_dt; 1088 } 1089 1090 spin_lock_init(&rk_domain->iommus_lock); 1091 spin_lock_init(&rk_domain->dt_lock); 1092 INIT_LIST_HEAD(&rk_domain->iommus); 1093 1094 rk_domain->domain.pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP; 1095 1096 rk_domain->domain.geometry.aperture_start = 0; 1097 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); 1098 rk_domain->domain.geometry.force_aperture = true; 1099 1100 return &rk_domain->domain; 1101 1102err_free_dt: 1103 iommu_free_pages(rk_domain->dt); 1104err_free_domain: 1105 kfree(rk_domain); 1106 1107 return NULL; 1108} 1109 1110static void rk_iommu_domain_free(struct iommu_domain *domain) 1111{ 1112 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1113 int i; 1114 1115 WARN_ON(!list_empty(&rk_domain->iommus)); 1116 1117 for (i = 0; i < NUM_DT_ENTRIES; i++) { 1118 u32 dte = rk_domain->dt[i]; 1119 if (rk_dte_is_pt_valid(dte)) { 1120 phys_addr_t pt_phys = rk_ops->pt_address(dte); 1121 u32 *page_table = phys_to_virt(pt_phys); 1122 dma_unmap_single(rk_domain->dma_dev, pt_phys, 1123 SPAGE_SIZE, DMA_TO_DEVICE); 1124 iommu_free_pages(page_table); 1125 } 1126 } 1127 1128 dma_unmap_single(rk_domain->dma_dev, rk_domain->dt_dma, 1129 SPAGE_SIZE, DMA_TO_DEVICE); 1130 iommu_free_pages(rk_domain->dt); 1131 1132 kfree(rk_domain); 1133} 1134 1135static struct iommu_device *rk_iommu_probe_device(struct device *dev) 1136{ 1137 struct rk_iommudata *data; 1138 struct rk_iommu *iommu; 1139 1140 data = dev_iommu_priv_get(dev); 1141 if (!data) 1142 return ERR_PTR(-ENODEV); 1143 1144 iommu = rk_iommu_from_dev(dev); 1145 1146 data->link = device_link_add(dev, iommu->dev, 1147 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1148 1149 return &iommu->iommu; 1150} 1151 1152static void rk_iommu_release_device(struct device *dev) 1153{ 1154 struct rk_iommudata *data = dev_iommu_priv_get(dev); 1155 1156 device_link_del(data->link); 1157} 1158 1159static int rk_iommu_of_xlate(struct device *dev, 1160 const struct of_phandle_args *args) 1161{ 1162 struct platform_device *iommu_dev; 1163 struct rk_iommudata *data; 1164 1165 iommu_dev = of_find_device_by_node(args->np); 1166 1167 data = devm_kzalloc(&iommu_dev->dev, sizeof(*data), GFP_KERNEL); 1168 if (!data) 1169 return -ENOMEM; 1170 1171 data->iommu = platform_get_drvdata(iommu_dev); 1172 dev_iommu_priv_set(dev, data); 1173 1174 platform_device_put(iommu_dev); 1175 1176 return 0; 1177} 1178 1179static const struct iommu_ops rk_iommu_ops = { 1180 .identity_domain = &rk_identity_domain, 1181 .domain_alloc_paging = rk_iommu_domain_alloc_paging, 1182 .probe_device = rk_iommu_probe_device, 1183 .release_device = rk_iommu_release_device, 1184 .device_group = generic_single_device_group, 1185 .of_xlate = rk_iommu_of_xlate, 1186 .default_domain_ops = &(const struct iommu_domain_ops) { 1187 .attach_dev = rk_iommu_attach_device, 1188 .map_pages = rk_iommu_map, 1189 .unmap_pages = rk_iommu_unmap, 1190 .iova_to_phys = rk_iommu_iova_to_phys, 1191 .free = rk_iommu_domain_free, 1192 } 1193}; 1194 1195static int rk_iommu_probe(struct platform_device *pdev) 1196{ 1197 struct device *dev = &pdev->dev; 1198 struct rk_iommu *iommu; 1199 struct resource *res; 1200 const struct rk_iommu_ops *ops; 1201 int num_res = pdev->num_resources; 1202 int err, i; 1203 1204 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 1205 if (!iommu) 1206 return -ENOMEM; 1207 1208 iommu->domain = &rk_identity_domain; 1209 1210 platform_set_drvdata(pdev, iommu); 1211 iommu->dev = dev; 1212 iommu->num_mmu = 0; 1213 1214 ops = of_device_get_match_data(dev); 1215 if (!rk_ops) 1216 rk_ops = ops; 1217 1218 /* 1219 * That should not happen unless different versions of the 1220 * hardware block are embedded the same SoC 1221 */ 1222 if (WARN_ON(rk_ops != ops)) 1223 return -EINVAL; 1224 1225 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), 1226 GFP_KERNEL); 1227 if (!iommu->bases) 1228 return -ENOMEM; 1229 1230 for (i = 0; i < num_res; i++) { 1231 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1232 if (!res) 1233 continue; 1234 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); 1235 if (IS_ERR(iommu->bases[i])) 1236 continue; 1237 iommu->num_mmu++; 1238 } 1239 if (iommu->num_mmu == 0) 1240 return PTR_ERR(iommu->bases[0]); 1241 1242 iommu->num_irq = platform_irq_count(pdev); 1243 if (iommu->num_irq < 0) 1244 return iommu->num_irq; 1245 1246 iommu->reset_disabled = device_property_read_bool(dev, 1247 "rockchip,disable-mmu-reset"); 1248 1249 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); 1250 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, 1251 sizeof(*iommu->clocks), GFP_KERNEL); 1252 if (!iommu->clocks) 1253 return -ENOMEM; 1254 1255 for (i = 0; i < iommu->num_clocks; ++i) 1256 iommu->clocks[i].id = rk_iommu_clocks[i]; 1257 1258 /* 1259 * iommu clocks should be present for all new devices and devicetrees 1260 * but there are older devicetrees without clocks out in the wild. 1261 * So clocks as optional for the time being. 1262 */ 1263 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); 1264 if (err == -ENOENT) 1265 iommu->num_clocks = 0; 1266 else if (err) 1267 return err; 1268 1269 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); 1270 if (err) 1271 return err; 1272 1273 pm_runtime_enable(dev); 1274 1275 for (i = 0; i < iommu->num_irq; i++) { 1276 int irq = platform_get_irq(pdev, i); 1277 1278 if (irq < 0) { 1279 err = irq; 1280 goto err_pm_disable; 1281 } 1282 1283 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1284 IRQF_SHARED, dev_name(dev), iommu); 1285 if (err) 1286 goto err_pm_disable; 1287 } 1288 1289 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); 1290 1291 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); 1292 if (err) 1293 goto err_pm_disable; 1294 1295 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); 1296 if (err) 1297 goto err_remove_sysfs; 1298 1299 return 0; 1300err_remove_sysfs: 1301 iommu_device_sysfs_remove(&iommu->iommu); 1302err_pm_disable: 1303 pm_runtime_disable(dev); 1304 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); 1305 return err; 1306} 1307 1308static void rk_iommu_shutdown(struct platform_device *pdev) 1309{ 1310 struct rk_iommu *iommu = platform_get_drvdata(pdev); 1311 int i; 1312 1313 for (i = 0; i < iommu->num_irq; i++) { 1314 int irq = platform_get_irq(pdev, i); 1315 1316 devm_free_irq(iommu->dev, irq, iommu); 1317 } 1318 1319 pm_runtime_force_suspend(&pdev->dev); 1320} 1321 1322static int __maybe_unused rk_iommu_suspend(struct device *dev) 1323{ 1324 struct rk_iommu *iommu = dev_get_drvdata(dev); 1325 1326 if (iommu->domain == &rk_identity_domain) 1327 return 0; 1328 1329 rk_iommu_disable(iommu); 1330 return 0; 1331} 1332 1333static int __maybe_unused rk_iommu_resume(struct device *dev) 1334{ 1335 struct rk_iommu *iommu = dev_get_drvdata(dev); 1336 1337 if (iommu->domain == &rk_identity_domain) 1338 return 0; 1339 1340 return rk_iommu_enable(iommu); 1341} 1342 1343static const struct dev_pm_ops rk_iommu_pm_ops = { 1344 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) 1345 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1346 pm_runtime_force_resume) 1347}; 1348 1349static struct rk_iommu_ops iommu_data_ops_v1 = { 1350 .pt_address = &rk_dte_pt_address, 1351 .mk_dtentries = &rk_mk_dte, 1352 .mk_ptentries = &rk_mk_pte, 1353 .dma_bit_mask = DMA_BIT_MASK(32), 1354 .gfp_flags = GFP_DMA32, 1355}; 1356 1357static struct rk_iommu_ops iommu_data_ops_v2 = { 1358 .pt_address = &rk_dte_pt_address_v2, 1359 .mk_dtentries = &rk_mk_dte_v2, 1360 .mk_ptentries = &rk_mk_pte_v2, 1361 .dma_bit_mask = DMA_BIT_MASK(40), 1362 .gfp_flags = 0, 1363}; 1364 1365static const struct of_device_id rk_iommu_dt_ids[] = { 1366 { .compatible = "rockchip,iommu", 1367 .data = &iommu_data_ops_v1, 1368 }, 1369 { .compatible = "rockchip,rk3568-iommu", 1370 .data = &iommu_data_ops_v2, 1371 }, 1372 { /* sentinel */ } 1373}; 1374 1375static struct platform_driver rk_iommu_driver = { 1376 .probe = rk_iommu_probe, 1377 .shutdown = rk_iommu_shutdown, 1378 .driver = { 1379 .name = "rk_iommu", 1380 .of_match_table = rk_iommu_dt_ids, 1381 .pm = &rk_iommu_pm_ops, 1382 .suppress_bind_attrs = true, 1383 }, 1384}; 1385builtin_platform_driver(rk_iommu_driver);
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