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mtk_iommu.c
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linux-6.19.14/drivers/iommu/mtk_iommu.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6#include <linux/arm-smccc.h> 7#include <linux/bitfield.h> 8#include <linux/bug.h> 9#include <linux/clk.h> 10#include <linux/component.h> 11#include <linux/device.h> 12#include <linux/err.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/iommu.h> 16#include <linux/iopoll.h> 17#include <linux/io-pgtable.h> 18#include <linux/list.h> 19#include <linux/mfd/syscon.h> 20#include <linux/module.h> 21#include <linux/of_address.h> 22#include <linux/of_irq.h> 23#include <linux/of_platform.h> 24#include <linux/pci.h> 25#include <linux/platform_device.h> 26#include <linux/pm_runtime.h> 27#include <linux/regmap.h> 28#include <linux/slab.h> 29#include <linux/spinlock.h> 30#include <linux/soc/mediatek/infracfg.h> 31#include <linux/soc/mediatek/mtk_sip_svc.h> 32#include <linux/string_choices.h> 33#include <asm/barrier.h> 34#include <soc/mediatek/smi.h> 35 36#include <dt-bindings/memory/mtk-memory-port.h> 37 38#define REG_MMU_PT_BASE_ADDR 0x000 39 40#define REG_MMU_INVALIDATE 0x020 41#define F_ALL_INVLD 0x2 42#define F_MMU_INV_RANGE 0x1 43 44#define REG_MMU_INVLD_START_A 0x024 45#define REG_MMU_INVLD_END_A 0x028 46 47#define REG_MMU_INV_SEL_GEN2 0x02c 48#define REG_MMU_INV_SEL_GEN1 0x038 49#define F_INVLD_EN0 BIT(0) 50#define F_INVLD_EN1 BIT(1) 51 52#define REG_MMU_MISC_CTRL 0x048 53#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 54#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 55 56#define REG_MMU_DCM_DIS 0x050 57#define F_MMU_DCM BIT(8) 58 59#define REG_MMU_WR_LEN_CTRL 0x054 60#define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 61 62#define REG_MMU_CTRL_REG 0x110 63#define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 64#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 65#define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 66 67#define REG_MMU_IVRP_PADDR 0x114 68 69#define REG_MMU_VLD_PA_RNG 0x118 70#define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 71 72#define REG_MMU_INT_CONTROL0 0x120 73#define F_L2_MULIT_HIT_EN BIT(0) 74#define F_TABLE_WALK_FAULT_INT_EN BIT(1) 75#define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 76#define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 77#define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 78#define F_MISS_FIFO_ERR_INT_EN BIT(6) 79#define F_INT_CLR_BIT BIT(12) 80 81#define REG_MMU_INT_MAIN_CONTROL 0x124 82 /* mmu0 | mmu1 */ 83#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 84#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 85#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 86#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 87#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 88#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 89#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 90 91#define REG_MMU_CPE_DONE 0x12C 92 93#define REG_MMU_FAULT_ST1 0x134 94#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 95#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 96 97#define REG_MMU0_FAULT_VA 0x13c 98#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 99#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 100#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 101#define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 102#define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 103 104#define REG_MMU0_INVLD_PA 0x140 105#define REG_MMU1_FAULT_VA 0x144 106#define REG_MMU1_INVLD_PA 0x148 107#define REG_MMU0_INT_ID 0x150 108#define REG_MMU1_INT_ID 0x154 109#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 110#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 111#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 112#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 113/* Macro for 5 bits length port ID field (default) */ 114#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 115#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 116/* Macro for 6 bits length port ID field */ 117#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) 118#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) 119 120#define MTK_PROTECT_PA_ALIGN 256 121#define MTK_IOMMU_BANK_SZ 0x1000 122 123#define PERICFG_IOMMU_1 0x714 124 125#define HAS_4GB_MODE BIT(0) 126/* HW will use the EMI clock if there isn't the "bclk". */ 127#define HAS_BCLK BIT(1) 128#define HAS_VLD_PA_RNG BIT(2) 129#define RESET_AXI BIT(3) 130#define OUT_ORDER_WR_EN BIT(4) 131#define HAS_SUB_COMM_2BITS BIT(5) 132#define HAS_SUB_COMM_3BITS BIT(6) 133#define WR_THROT_EN BIT(7) 134#define HAS_LEGACY_IVRP_PADDR BIT(8) 135#define IOVA_34_EN BIT(9) 136#define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 137#define DCM_DISABLE BIT(11) 138#define STD_AXI_MODE BIT(12) /* For non MM iommu */ 139/* 2 bits: iommu type */ 140#define MTK_IOMMU_TYPE_MM (0x0 << 13) 141#define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 142#define MTK_IOMMU_TYPE_APU (0x2 << 13) 143#define MTK_IOMMU_TYPE_MASK (0x3 << 13) 144/* PM and clock always on. e.g. infra iommu */ 145#define PM_CLK_AO BIT(15) 146#define IFA_IOMMU_PCIE_SUPPORT BIT(16) 147#define PGTABLE_PA_35_EN BIT(17) 148#define TF_PORT_TO_ADDR_MT8173 BIT(18) 149#define INT_ID_PORT_WIDTH_6 BIT(19) 150#define CFG_IFA_MASTER_IN_ATF BIT(20) 151#define DL_WITH_MULTI_LARB BIT(21) 152 153#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 154 ((((pdata)->flags) & (mask)) == (_x)) 155 156#define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 157#define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 158 MTK_IOMMU_TYPE_MASK) 159 160#define MTK_INVALID_LARBID MTK_LARB_NR_MAX 161 162#define MTK_LARB_COM_MAX 8 163#define MTK_LARB_SUBCOM_MAX 8 164 165#define MTK_IOMMU_GROUP_MAX 8 166#define MTK_IOMMU_BANK_MAX 5 167 168enum mtk_iommu_plat { 169 M4U_MT2712, 170 M4U_MT6779, 171 M4U_MT6795, 172 M4U_MT8167, 173 M4U_MT8173, 174 M4U_MT8183, 175 M4U_MT8186, 176 M4U_MT8188, 177 M4U_MT8189, 178 M4U_MT8192, 179 M4U_MT8195, 180 M4U_MT8365, 181}; 182 183struct mtk_iommu_iova_region { 184 dma_addr_t iova_base; 185 unsigned long long size; 186}; 187 188struct mtk_iommu_suspend_reg { 189 u32 misc_ctrl; 190 u32 dcm_dis; 191 u32 ctrl_reg; 192 u32 vld_pa_rng; 193 u32 wr_len_ctrl; 194 195 u32 int_control[MTK_IOMMU_BANK_MAX]; 196 u32 int_main_control[MTK_IOMMU_BANK_MAX]; 197 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 198}; 199 200struct mtk_iommu_plat_data { 201 enum mtk_iommu_plat m4u_plat; 202 u32 flags; 203 u32 inv_sel_reg; 204 205 char *pericfg_comp_str; 206 struct list_head *hw_list; 207 208 /* 209 * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges, 210 * different masters will be put in different iova ranges, for example vcodec 211 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the 212 * special IOVA range requirement, like CCU can only support the address 213 * 0x40000000-0x44000000. 214 * Here list the iova ranges this SoC supports and which larbs/ports are in 215 * which region. 216 * 217 * 16GB iova all use one pgtable, but each a region is a iommu group. 218 */ 219 struct { 220 unsigned int iova_region_nr; 221 const struct mtk_iommu_iova_region *iova_region; 222 /* 223 * Indicate the correspondance between larbs, ports and regions. 224 * 225 * The index is the same as iova_region and larb port numbers are 226 * described as bit positions. 227 * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2". 228 * [2] = { [1] = BIT(0) } 229 */ 230 const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX]; 231 }; 232 233 /* 234 * The IOMMU HW may have 5 banks. Each bank has a independent pgtable. 235 * Here list how many banks this SoC supports/enables and which ports are in which bank. 236 */ 237 struct { 238 u8 banks_num; 239 bool banks_enable[MTK_IOMMU_BANK_MAX]; 240 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 241 }; 242 243 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 244}; 245 246struct mtk_iommu_bank_data { 247 void __iomem *base; 248 int irq; 249 u8 id; 250 struct device *parent_dev; 251 struct mtk_iommu_data *parent_data; 252 spinlock_t tlb_lock; /* lock for tlb range flush */ 253 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 254}; 255 256struct mtk_iommu_data { 257 struct device *dev; 258 struct clk *bclk; 259 phys_addr_t protect_base; /* protect memory base */ 260 struct mtk_iommu_suspend_reg reg; 261 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 262 bool enable_4GB; 263 264 struct iommu_device iommu; 265 const struct mtk_iommu_plat_data *plat_data; 266 struct device *smicomm_dev; 267 268 struct mtk_iommu_bank_data *bank; 269 struct mtk_iommu_domain *share_dom; 270 271 struct regmap *pericfg; 272 struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 273 274 /* 275 * In the sharing pgtable case, list data->list to the global list like m4ulist. 276 * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 277 */ 278 struct list_head *hw_list; 279 struct list_head hw_list_head; 280 struct list_head list; 281 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 282}; 283 284struct mtk_iommu_domain { 285 struct io_pgtable_cfg cfg; 286 struct io_pgtable_ops *iop; 287 288 struct mtk_iommu_bank_data *bank; 289 struct iommu_domain domain; 290 291 struct mutex mutex; /* Protect "data" in this structure */ 292}; 293 294static int mtk_iommu_bind(struct device *dev) 295{ 296 struct mtk_iommu_data *data = dev_get_drvdata(dev); 297 298 return component_bind_all(dev, &data->larb_imu); 299} 300 301static void mtk_iommu_unbind(struct device *dev) 302{ 303 struct mtk_iommu_data *data = dev_get_drvdata(dev); 304 305 component_unbind_all(dev, &data->larb_imu); 306} 307 308static const struct iommu_ops mtk_iommu_ops; 309 310static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 311 312#define MTK_IOMMU_TLB_ADDR(iova) ({ \ 313 dma_addr_t _addr = iova; \ 314 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 315}) 316 317/* 318 * In M4U 4GB mode, the physical address is remapped as below: 319 * 320 * CPU Physical address: 321 * ==================== 322 * 323 * 0 1G 2G 3G 4G 5G 324 * |---A---|---B---|---C---|---D---|---E---| 325 * +--I/O--+------------Memory-------------+ 326 * 327 * IOMMU output physical address: 328 * ============================= 329 * 330 * 4G 5G 6G 7G 8G 331 * |---E---|---B---|---C---|---D---| 332 * +------------Memory-------------+ 333 * 334 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 335 * bit32 of the CPU physical address always is needed to set, and for Region 336 * 'E', the CPU physical address keep as is. 337 * Additionally, The iommu consumers always use the CPU phyiscal address. 338 */ 339#define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 340 341static LIST_HEAD(apulist); /* List the apu iommu HWs */ 342static LIST_HEAD(infralist); /* List the iommu_infra HW */ 343static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 344 345#define for_each_m4u(data, head) list_for_each_entry(data, head, list) 346 347#define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */ 348 349static const struct mtk_iommu_iova_region single_domain[] = { 350 {.iova_base = 0, .size = MTK_IOMMU_IOVA_SZ_4G}, 351}; 352 353#define MT8192_MULTI_REGION_NR_MAX 6 354 355#define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ 356 MT8192_MULTI_REGION_NR_MAX : 1) 357 358static const struct mtk_iommu_iova_region mt8189_multi_dom_apu[] = { 359 { .iova_base = 0x200000ULL, .size = SZ_512M}, /* APU SECURE */ 360#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 361 { .iova_base = SZ_1G, .size = 0xc0000000}, /* APU CODE */ 362 { .iova_base = 0x70000000ULL, .size = 0x12600000}, /* APU VLM */ 363 { .iova_base = SZ_4G, .size = SZ_4G * 3}, /* APU VPU */ 364#endif 365}; 366 367static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { 368 { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */ 369 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 370 { .iova_base = SZ_4G, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 4G ~ 8G */ 371 { .iova_base = SZ_4G * 2, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 8G ~ 12G */ 372 { .iova_base = SZ_4G * 3, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 12G ~ 16G */ 373 374 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 375 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 376 #endif 377}; 378 379/* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 380static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 381{ 382 return list_first_entry(hwlist, struct mtk_iommu_data, list); 383} 384 385static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 386{ 387 return container_of(dom, struct mtk_iommu_domain, domain); 388} 389 390static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 391{ 392 /* Tlb flush all always is in bank0. */ 393 struct mtk_iommu_bank_data *bank = &data->bank[0]; 394 void __iomem *base = bank->base; 395 unsigned long flags; 396 397 spin_lock_irqsave(&bank->tlb_lock, flags); 398 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 399 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 400 wmb(); /* Make sure the tlb flush all done */ 401 spin_unlock_irqrestore(&bank->tlb_lock, flags); 402} 403 404static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 405 struct mtk_iommu_bank_data *bank) 406{ 407 struct list_head *head = bank->parent_data->hw_list; 408 struct mtk_iommu_bank_data *curbank; 409 struct mtk_iommu_data *data; 410 bool check_pm_status; 411 unsigned long flags; 412 void __iomem *base; 413 int ret; 414 u32 tmp; 415 416 for_each_m4u(data, head) { 417 /* 418 * To avoid resume the iommu device frequently when the iommu device 419 * is not active, it doesn't always call pm_runtime_get here, then tlb 420 * flush depends on the tlb flush all in the runtime resume. 421 * 422 * There are 2 special cases: 423 * 424 * Case1: The iommu dev doesn't have power domain but has bclk. This case 425 * should also avoid the tlb flush while the dev is not active to mute 426 * the tlb timeout log. like mt8173. 427 * 428 * Case2: The power/clock of infra iommu is always on, and it doesn't 429 * have the device link with the master devices. This case should avoid 430 * the PM status check. 431 */ 432 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 433 434 if (check_pm_status) { 435 if (pm_runtime_get_if_in_use(data->dev) <= 0) 436 continue; 437 } 438 439 curbank = &data->bank[bank->id]; 440 base = curbank->base; 441 442 spin_lock_irqsave(&curbank->tlb_lock, flags); 443 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 444 base + data->plat_data->inv_sel_reg); 445 446 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 447 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 448 base + REG_MMU_INVLD_END_A); 449 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 450 451 /* tlb sync */ 452 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 453 tmp, tmp != 0, 10, 1000); 454 455 /* Clear the CPE status */ 456 writel_relaxed(0, base + REG_MMU_CPE_DONE); 457 spin_unlock_irqrestore(&curbank->tlb_lock, flags); 458 459 if (ret) { 460 dev_warn(data->dev, 461 "Partial TLB flush timed out, falling back to full flush\n"); 462 mtk_iommu_tlb_flush_all(data); 463 } 464 465 if (check_pm_status) 466 pm_runtime_put(data->dev); 467 } 468} 469 470static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 471{ 472 struct mtk_iommu_bank_data *bank = dev_id; 473 struct mtk_iommu_data *data = bank->parent_data; 474 struct mtk_iommu_domain *dom = bank->m4u_dom; 475 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 476 u32 int_state, regval, va34_32, pa34_32; 477 const struct mtk_iommu_plat_data *plat_data = data->plat_data; 478 void __iomem *base = bank->base; 479 u64 fault_iova, fault_pa; 480 bool layer, write; 481 482 /* Read error info from registers */ 483 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 484 if (int_state & F_REG_MMU0_FAULT_MASK) { 485 regval = readl_relaxed(base + REG_MMU0_INT_ID); 486 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 487 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 488 } else { 489 regval = readl_relaxed(base + REG_MMU1_INT_ID); 490 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 491 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 492 } 493 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 494 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 495 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 496 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 497 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 498 fault_iova |= (u64)va34_32 << 32; 499 } 500 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 501 fault_pa |= (u64)pa34_32 << 32; 502 503 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 504 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 505 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 506 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 507 fault_port = F_MMU_INT_ID_PORT_ID(regval); 508 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 509 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 510 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 511 fault_port = F_MMU_INT_ID_PORT_ID(regval); 512 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { 513 fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval); 514 fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval); 515 } else { 516 fault_port = F_MMU_INT_ID_PORT_ID(regval); 517 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 518 } 519 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 520 } 521 522 if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 523 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 524 dev_err_ratelimited( 525 bank->parent_dev, 526 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 527 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 528 layer, str_write_read(write)); 529 } 530 531 /* Interrupt clear */ 532 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 533 regval |= F_INT_CLR_BIT; 534 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 535 536 mtk_iommu_tlb_flush_all(data); 537 538 return IRQ_HANDLED; 539} 540 541static unsigned int mtk_iommu_get_bank_id(struct device *dev, 542 const struct mtk_iommu_plat_data *plat_data) 543{ 544 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 545 unsigned int i, portmsk = 0, bankid = 0; 546 547 if (plat_data->banks_num == 1) 548 return bankid; 549 550 for (i = 0; i < fwspec->num_ids; i++) 551 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 552 553 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 554 if (!plat_data->banks_enable[i]) 555 continue; 556 557 if (portmsk & plat_data->banks_portmsk[i]) { 558 bankid = i; 559 break; 560 } 561 } 562 return bankid; /* default is 0 */ 563} 564 565static int mtk_iommu_get_iova_region_id(struct device *dev, 566 const struct mtk_iommu_plat_data *plat_data) 567{ 568 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 569 unsigned int portidmsk = 0, larbid; 570 const u32 *rgn_larb_msk; 571 int i; 572 573 if (plat_data->iova_region_nr == 1) 574 return 0; 575 576 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 577 for (i = 0; i < fwspec->num_ids; i++) 578 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 579 580 for (i = 0; i < plat_data->iova_region_nr; i++) { 581 rgn_larb_msk = plat_data->iova_region_larb_msk[i]; 582 if (!rgn_larb_msk) 583 continue; 584 585 if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk) 586 return i; 587 } 588 589 dev_err(dev, "Can NOT find the region for larb(%d-%x).\n", 590 larbid, portidmsk); 591 return -EINVAL; 592} 593 594static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 595 bool enable, unsigned int regionid) 596{ 597 struct mtk_smi_larb_iommu *larb_mmu; 598 unsigned int larbid, portid; 599 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 600 const struct mtk_iommu_iova_region *region; 601 unsigned long portid_msk = 0; 602 struct arm_smccc_res res; 603 int i, ret = 0; 604 605 for (i = 0; i < fwspec->num_ids; ++i) { 606 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 607 portid_msk |= BIT(portid); 608 } 609 610 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 611 /* All ports should be in the same larb. just use 0 here */ 612 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 613 larb_mmu = &data->larb_imu[larbid]; 614 region = data->plat_data->iova_region + regionid; 615 616 for_each_set_bit(portid, &portid_msk, 32) 617 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 618 619 dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n", 620 str_enable_disable(enable), dev_name(larb_mmu->dev), 621 portid_msk, regionid, upper_32_bits(region->iova_base)); 622 623 if (enable) 624 larb_mmu->mmu |= portid_msk; 625 else 626 larb_mmu->mmu &= ~portid_msk; 627 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 628 if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 629 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, 630 IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, 631 portid_msk, enable, 0, 0, 0, 0, &res); 632 ret = res.a0; 633 } else { 634 /* PCI dev has only one output id, enable the next writing bit for PCIe */ 635 if (dev_is_pci(dev)) { 636 if (fwspec->num_ids != 1) { 637 dev_err(dev, "PCI dev can only have one port.\n"); 638 return -ENODEV; 639 } 640 portid_msk |= BIT(portid + 1); 641 } 642 643 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 644 (u32)portid_msk, enable ? (u32)portid_msk : 0); 645 } 646 if (ret) 647 dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n", 648 str_enable_disable(enable), dev_name(data->dev), 649 portid_msk, ret); 650 } 651 return ret; 652} 653 654static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 655 struct mtk_iommu_data *data, 656 unsigned int region_id) 657{ 658 struct mtk_iommu_domain *share_dom = data->share_dom; 659 const struct mtk_iommu_iova_region *region; 660 661 /* Share pgtable when 2 MM IOMMU share the pgtable or one IOMMU use multiple iova ranges */ 662 if (share_dom) { 663 dom->iop = share_dom->iop; 664 dom->cfg = share_dom->cfg; 665 dom->domain.pgsize_bitmap = share_dom->domain.pgsize_bitmap; 666 goto update_iova_region; 667 } 668 669 dom->cfg = (struct io_pgtable_cfg) { 670 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 671 IO_PGTABLE_QUIRK_NO_PERMS | 672 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 673 .pgsize_bitmap = dom->domain.pgsize_bitmap, 674 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 675 .iommu_dev = data->dev, 676 }; 677 678 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) 679 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; 680 681 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 682 dom->cfg.oas = data->enable_4GB ? 33 : 32; 683 else 684 dom->cfg.oas = 35; 685 686 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 687 if (!dom->iop) { 688 dev_err(data->dev, "Failed to alloc io pgtable\n"); 689 return -ENOMEM; 690 } 691 692 data->share_dom = dom; 693 694update_iova_region: 695 /* Update the iova region for this domain */ 696 region = data->plat_data->iova_region + region_id; 697 dom->domain.geometry.aperture_start = region->iova_base; 698 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 699 dom->domain.geometry.force_aperture = true; 700 return 0; 701} 702 703static struct iommu_domain *mtk_iommu_domain_alloc_paging(struct device *dev) 704{ 705 struct mtk_iommu_domain *dom; 706 707 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 708 if (!dom) 709 return NULL; 710 mutex_init(&dom->mutex); 711 dom->domain.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M; 712 713 return &dom->domain; 714} 715 716static void mtk_iommu_domain_free(struct iommu_domain *domain) 717{ 718 kfree(to_mtk_domain(domain)); 719} 720 721static int mtk_iommu_attach_device(struct iommu_domain *domain, 722 struct device *dev, struct iommu_domain *old) 723{ 724 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 725 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 726 struct list_head *hw_list = data->hw_list; 727 struct device *m4udev = data->dev; 728 struct mtk_iommu_bank_data *bank; 729 unsigned int bankid; 730 int ret, region_id; 731 732 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 733 if (region_id < 0) 734 return region_id; 735 736 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 737 mutex_lock(&dom->mutex); 738 if (!dom->bank) { 739 /* Data is in the frstdata in sharing pgtable case. */ 740 frstdata = mtk_iommu_get_frst_data(hw_list); 741 742 mutex_lock(&frstdata->mutex); 743 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 744 mutex_unlock(&frstdata->mutex); 745 if (ret) { 746 mutex_unlock(&dom->mutex); 747 return ret; 748 } 749 dom->bank = &data->bank[bankid]; 750 } 751 mutex_unlock(&dom->mutex); 752 753 mutex_lock(&data->mutex); 754 bank = &data->bank[bankid]; 755 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 756 ret = pm_runtime_resume_and_get(m4udev); 757 if (ret < 0) { 758 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 759 goto err_unlock; 760 } 761 762 ret = mtk_iommu_hw_init(data, bankid); 763 if (ret) { 764 pm_runtime_put(m4udev); 765 goto err_unlock; 766 } 767 bank->m4u_dom = dom; 768 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); 769 770 pm_runtime_put(m4udev); 771 } 772 mutex_unlock(&data->mutex); 773 774 if (region_id > 0) { 775 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 776 if (ret) { 777 dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret); 778 return ret; 779 } 780 } 781 782 return mtk_iommu_config(data, dev, true, region_id); 783 784err_unlock: 785 mutex_unlock(&data->mutex); 786 return ret; 787} 788 789static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, 790 struct device *dev, 791 struct iommu_domain *old) 792{ 793 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 794 795 if (old == identity_domain || !old) 796 return 0; 797 798 mtk_iommu_config(data, dev, false, 0); 799 return 0; 800} 801 802static struct iommu_domain_ops mtk_iommu_identity_ops = { 803 .attach_dev = mtk_iommu_identity_attach, 804}; 805 806static struct iommu_domain mtk_iommu_identity_domain = { 807 .type = IOMMU_DOMAIN_IDENTITY, 808 .ops = &mtk_iommu_identity_ops, 809}; 810 811static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 812 phys_addr_t paddr, size_t pgsize, size_t pgcount, 813 int prot, gfp_t gfp, size_t *mapped) 814{ 815 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 816 817 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 818 if (dom->bank->parent_data->enable_4GB) 819 paddr |= BIT_ULL(32); 820 821 /* Synchronize with the tlb_lock */ 822 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); 823} 824 825static size_t mtk_iommu_unmap(struct iommu_domain *domain, 826 unsigned long iova, size_t pgsize, size_t pgcount, 827 struct iommu_iotlb_gather *gather) 828{ 829 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 830 831 iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount); 832 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); 833} 834 835static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 836{ 837 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 838 839 if (dom->bank) 840 mtk_iommu_tlb_flush_all(dom->bank->parent_data); 841} 842 843static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 844 struct iommu_iotlb_gather *gather) 845{ 846 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 847 size_t length = gather->end - gather->start + 1; 848 849 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 850} 851 852static int mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 853 size_t size) 854{ 855 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 856 857 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 858 return 0; 859} 860 861static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 862 dma_addr_t iova) 863{ 864 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 865 phys_addr_t pa; 866 867 pa = dom->iop->iova_to_phys(dom->iop, iova); 868 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 869 dom->bank->parent_data->enable_4GB && 870 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 871 pa &= ~BIT_ULL(32); 872 873 return pa; 874} 875 876static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 877{ 878 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 879 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 880 struct device_link *link; 881 struct device *larbdev; 882 unsigned long larbid_msk = 0; 883 unsigned int larbid, larbidx, i; 884 885 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 886 return &data->iommu; 887 888 /* 889 * Link the consumer device with the smi-larb device(supplier). 890 * w/DL_WITH_MULTI_LARB: the master may connect with multi larbs, 891 * we should create device link with each larb. 892 * w/o DL_WITH_MULTI_LARB: the master must connect with one larb, 893 * otherwise fail. 894 */ 895 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 896 if (larbid >= MTK_LARB_NR_MAX) 897 return ERR_PTR(-EINVAL); 898 899 larbid_msk |= BIT(larbid); 900 901 for (i = 1; i < fwspec->num_ids; i++) { 902 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 903 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DL_WITH_MULTI_LARB)) { 904 larbid_msk |= BIT(larbidx); 905 } else if (larbid != larbidx) { 906 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 907 larbid, larbidx); 908 return ERR_PTR(-EINVAL); 909 } 910 } 911 912 for_each_set_bit(larbid, &larbid_msk, 32) { 913 larbdev = data->larb_imu[larbid].dev; 914 if (!larbdev) 915 return ERR_PTR(-EINVAL); 916 917 link = device_link_add(dev, larbdev, 918 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 919 if (!link) { 920 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 921 goto link_remove; 922 } 923 } 924 925 return &data->iommu; 926 927link_remove: 928 for_each_set_bit(i, &larbid_msk, larbid) { 929 larbdev = data->larb_imu[i].dev; 930 device_link_remove(dev, larbdev); 931 } 932 933 return ERR_PTR(-ENODEV); 934} 935 936static void mtk_iommu_release_device(struct device *dev) 937{ 938 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 939 struct mtk_iommu_data *data; 940 struct device *larbdev; 941 unsigned int larbid, i; 942 unsigned long larbid_msk = 0; 943 944 data = dev_iommu_priv_get(dev); 945 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 946 return; 947 948 for (i = 0; i < fwspec->num_ids; i++) { 949 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 950 larbid_msk |= BIT(larbid); 951 } 952 953 for_each_set_bit(larbid, &larbid_msk, 32) { 954 larbdev = data->larb_imu[larbid].dev; 955 device_link_remove(dev, larbdev); 956 } 957} 958 959static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 960{ 961 unsigned int bankid; 962 963 /* 964 * If the bank function is enabled, each bank is a iommu group/domain. 965 * Otherwise, each iova region is a iommu group/domain. 966 */ 967 bankid = mtk_iommu_get_bank_id(dev, plat_data); 968 if (bankid) 969 return bankid; 970 971 return mtk_iommu_get_iova_region_id(dev, plat_data); 972} 973 974static struct iommu_group *mtk_iommu_device_group(struct device *dev) 975{ 976 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 977 struct list_head *hw_list = c_data->hw_list; 978 struct iommu_group *group; 979 int groupid; 980 981 data = mtk_iommu_get_frst_data(hw_list); 982 if (!data) 983 return ERR_PTR(-ENODEV); 984 985 groupid = mtk_iommu_get_group_id(dev, data->plat_data); 986 if (groupid < 0) 987 return ERR_PTR(groupid); 988 989 mutex_lock(&data->mutex); 990 group = data->m4u_group[groupid]; 991 if (!group) { 992 group = iommu_group_alloc(); 993 if (!IS_ERR(group)) 994 data->m4u_group[groupid] = group; 995 } else { 996 iommu_group_ref_get(group); 997 } 998 mutex_unlock(&data->mutex); 999 return group; 1000} 1001 1002static int mtk_iommu_of_xlate(struct device *dev, 1003 const struct of_phandle_args *args) 1004{ 1005 struct platform_device *m4updev; 1006 1007 if (args->args_count != 1) { 1008 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 1009 args->args_count); 1010 return -EINVAL; 1011 } 1012 1013 if (!dev_iommu_priv_get(dev)) { 1014 /* Get the m4u device */ 1015 m4updev = of_find_device_by_node(args->np); 1016 if (WARN_ON(!m4updev)) 1017 return -EINVAL; 1018 1019 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 1020 1021 put_device(&m4updev->dev); 1022 } 1023 1024 return iommu_fwspec_add_ids(dev, args->args, 1); 1025} 1026 1027static void mtk_iommu_get_resv_regions(struct device *dev, 1028 struct list_head *head) 1029{ 1030 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 1031 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 1032 const struct mtk_iommu_iova_region *resv, *curdom; 1033 struct iommu_resv_region *region; 1034 int prot = IOMMU_WRITE | IOMMU_READ; 1035 1036 if ((int)regionid < 0) 1037 return; 1038 curdom = data->plat_data->iova_region + regionid; 1039 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 1040 resv = data->plat_data->iova_region + i; 1041 1042 /* Only reserve when the region is inside the current domain */ 1043 if (resv->iova_base <= curdom->iova_base || 1044 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 1045 continue; 1046 1047 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 1048 prot, IOMMU_RESV_RESERVED, 1049 GFP_KERNEL); 1050 if (!region) 1051 return; 1052 1053 list_add_tail(®ion->list, head); 1054 } 1055} 1056 1057static const struct iommu_ops mtk_iommu_ops = { 1058 .identity_domain = &mtk_iommu_identity_domain, 1059 .domain_alloc_paging = mtk_iommu_domain_alloc_paging, 1060 .probe_device = mtk_iommu_probe_device, 1061 .release_device = mtk_iommu_release_device, 1062 .device_group = mtk_iommu_device_group, 1063 .of_xlate = mtk_iommu_of_xlate, 1064 .get_resv_regions = mtk_iommu_get_resv_regions, 1065 .owner = THIS_MODULE, 1066 .default_domain_ops = &(const struct iommu_domain_ops) { 1067 .attach_dev = mtk_iommu_attach_device, 1068 .map_pages = mtk_iommu_map, 1069 .unmap_pages = mtk_iommu_unmap, 1070 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 1071 .iotlb_sync = mtk_iommu_iotlb_sync, 1072 .iotlb_sync_map = mtk_iommu_sync_map, 1073 .iova_to_phys = mtk_iommu_iova_to_phys, 1074 .free = mtk_iommu_domain_free, 1075 } 1076}; 1077 1078static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 1079{ 1080 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 1081 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 1082 u32 regval; 1083 1084 /* 1085 * Global control settings are in bank0. May re-init these global registers 1086 * since no sure if there is bank0 consumers. 1087 */ 1088 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { 1089 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 1090 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 1091 } else { 1092 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 1093 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 1094 } 1095 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 1096 1097 if (data->enable_4GB && 1098 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 1099 /* 1100 * If 4GB mode is enabled, the validate PA range is from 1101 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 1102 */ 1103 regval = F_MMU_VLD_PA_RNG(7, 4); 1104 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 1105 } 1106 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 1107 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 1108 else 1109 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 1110 1111 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 1112 /* write command throttling mode */ 1113 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 1114 regval &= ~F_MMU_WR_THROT_DIS_MASK; 1115 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 1116 } 1117 1118 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 1119 /* The register is called STANDARD_AXI_MODE in this case */ 1120 regval = 0; 1121 } else { 1122 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 1123 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 1124 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 1125 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 1126 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 1127 } 1128 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 1129 1130 /* Independent settings for each bank */ 1131 regval = F_L2_MULIT_HIT_EN | 1132 F_TABLE_WALK_FAULT_INT_EN | 1133 F_PREETCH_FIFO_OVERFLOW_INT_EN | 1134 F_MISS_FIFO_OVERFLOW_INT_EN | 1135 F_PREFETCH_FIFO_ERR_INT_EN | 1136 F_MISS_FIFO_ERR_INT_EN; 1137 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1138 1139 regval = F_INT_TRANSLATION_FAULT | 1140 F_INT_MAIN_MULTI_HIT_FAULT | 1141 F_INT_INVALID_PA_FAULT | 1142 F_INT_ENTRY_REPLACEMENT_FAULT | 1143 F_INT_TLB_MISS_FAULT | 1144 F_INT_MISS_TRANSACTION_FIFO_FAULT | 1145 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1146 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1147 1148 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1149 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1150 else 1151 regval = lower_32_bits(data->protect_base) | 1152 upper_32_bits(data->protect_base); 1153 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1154 1155 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1156 dev_name(bankx->parent_dev), (void *)bankx)) { 1157 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1158 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 1159 return -ENODEV; 1160 } 1161 1162 return 0; 1163} 1164 1165static const struct component_master_ops mtk_iommu_com_ops = { 1166 .bind = mtk_iommu_bind, 1167 .unbind = mtk_iommu_unbind, 1168}; 1169 1170static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1171 struct mtk_iommu_data *data) 1172{ 1173 struct device_node *larbnode, *frst_avail_smicomm_node = NULL; 1174 struct platform_device *plarbdev, *pcommdev; 1175 struct device_link *link; 1176 int i, larb_nr, ret; 1177 1178 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1179 if (larb_nr < 0) 1180 return larb_nr; 1181 if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX) 1182 return -EINVAL; 1183 1184 for (i = 0; i < larb_nr; i++) { 1185 struct device_node *smicomm_node, *smi_subcomm_node; 1186 u32 id; 1187 1188 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 1189 if (!larbnode) { 1190 ret = -EINVAL; 1191 goto err_larbdev_put; 1192 } 1193 1194 if (!of_device_is_available(larbnode)) { 1195 of_node_put(larbnode); 1196 continue; 1197 } 1198 1199 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1200 if (ret)/* The id is consecutive if there is no this property */ 1201 id = i; 1202 if (id >= MTK_LARB_NR_MAX) { 1203 of_node_put(larbnode); 1204 ret = -EINVAL; 1205 goto err_larbdev_put; 1206 } 1207 1208 plarbdev = of_find_device_by_node(larbnode); 1209 of_node_put(larbnode); 1210 if (!plarbdev) { 1211 ret = -ENODEV; 1212 goto err_larbdev_put; 1213 } 1214 if (data->larb_imu[id].dev) { 1215 platform_device_put(plarbdev); 1216 ret = -EEXIST; 1217 goto err_larbdev_put; 1218 } 1219 data->larb_imu[id].dev = &plarbdev->dev; 1220 1221 if (!plarbdev->dev.driver) { 1222 ret = -EPROBE_DEFER; 1223 goto err_larbdev_put; 1224 } 1225 1226 /* Get smi-(sub)-common dev from the last larb. */ 1227 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 1228 if (!smi_subcomm_node) { 1229 ret = -EINVAL; 1230 goto err_larbdev_put; 1231 } 1232 1233 /* 1234 * It may have two level smi-common. the node is smi-sub-common if it 1235 * has a new mediatek,smi property. otherwise it is smi-commmon. 1236 */ 1237 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1238 if (smicomm_node) 1239 of_node_put(smi_subcomm_node); 1240 else 1241 smicomm_node = smi_subcomm_node; 1242 1243 /* 1244 * All the larbs that connect to one IOMMU must connect with the same 1245 * smi-common. 1246 */ 1247 if (!frst_avail_smicomm_node) { 1248 frst_avail_smicomm_node = smicomm_node; 1249 } else if (frst_avail_smicomm_node != smicomm_node) { 1250 dev_err(dev, "mediatek,smi property is not right @larb%d.", id); 1251 of_node_put(smicomm_node); 1252 ret = -EINVAL; 1253 goto err_larbdev_put; 1254 } else { 1255 of_node_put(smicomm_node); 1256 } 1257 1258 component_match_add(dev, match, component_compare_dev, &plarbdev->dev); 1259 } 1260 1261 if (!frst_avail_smicomm_node) { 1262 ret = -EINVAL; 1263 goto err_larbdev_put; 1264 } 1265 1266 pcommdev = of_find_device_by_node(frst_avail_smicomm_node); 1267 of_node_put(frst_avail_smicomm_node); 1268 if (!pcommdev) { 1269 ret = -ENODEV; 1270 goto err_larbdev_put; 1271 } 1272 data->smicomm_dev = &pcommdev->dev; 1273 1274 link = device_link_add(data->smicomm_dev, dev, 1275 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1276 platform_device_put(pcommdev); 1277 if (!link) { 1278 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1279 ret = -EINVAL; 1280 goto err_larbdev_put; 1281 } 1282 return 0; 1283 1284err_larbdev_put: 1285 /* id mapping may not be linear, loop the whole array */ 1286 for (i = 0; i < MTK_LARB_NR_MAX; i++) 1287 put_device(data->larb_imu[i].dev); 1288 1289 return ret; 1290} 1291 1292static int mtk_iommu_probe(struct platform_device *pdev) 1293{ 1294 struct mtk_iommu_data *data; 1295 struct device *dev = &pdev->dev; 1296 struct resource *res; 1297 resource_size_t ioaddr; 1298 struct component_match *match = NULL; 1299 struct regmap *infracfg; 1300 void *protect; 1301 int ret, banks_num, i = 0; 1302 u32 val; 1303 char *p; 1304 struct mtk_iommu_bank_data *bank; 1305 void __iomem *base; 1306 1307 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 1308 if (!data) 1309 return -ENOMEM; 1310 data->dev = dev; 1311 data->plat_data = of_device_get_match_data(dev); 1312 1313 /* Protect memory. HW will access here while translation fault.*/ 1314 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, GFP_KERNEL); 1315 if (!protect) 1316 return -ENOMEM; 1317 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 1318 1319 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 1320 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); 1321 if (IS_ERR(infracfg)) { 1322 /* 1323 * Legacy devicetrees will not specify a phandle to 1324 * mediatek,infracfg: in that case, we use the older 1325 * way to retrieve a syscon to infra. 1326 * 1327 * This is for retrocompatibility purposes only, hence 1328 * no more compatibles shall be added to this. 1329 */ 1330 switch (data->plat_data->m4u_plat) { 1331 case M4U_MT2712: 1332 p = "mediatek,mt2712-infracfg"; 1333 break; 1334 case M4U_MT8173: 1335 p = "mediatek,mt8173-infracfg"; 1336 break; 1337 default: 1338 p = NULL; 1339 } 1340 1341 infracfg = syscon_regmap_lookup_by_compatible(p); 1342 if (IS_ERR(infracfg)) 1343 return PTR_ERR(infracfg); 1344 } 1345 1346 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1347 if (ret) 1348 return ret; 1349 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1350 } 1351 1352 banks_num = data->plat_data->banks_num; 1353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1354 if (!res) 1355 return -EINVAL; 1356 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 1357 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 1358 return -EINVAL; 1359 } 1360 base = devm_ioremap_resource(dev, res); 1361 if (IS_ERR(base)) 1362 return PTR_ERR(base); 1363 ioaddr = res->start; 1364 1365 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 1366 if (!data->bank) 1367 return -ENOMEM; 1368 1369 do { 1370 if (!data->plat_data->banks_enable[i]) 1371 continue; 1372 bank = &data->bank[i]; 1373 bank->id = i; 1374 bank->base = base + i * MTK_IOMMU_BANK_SZ; 1375 bank->m4u_dom = NULL; 1376 1377 bank->irq = platform_get_irq(pdev, i); 1378 if (bank->irq < 0) 1379 return bank->irq; 1380 bank->parent_dev = dev; 1381 bank->parent_data = data; 1382 spin_lock_init(&bank->tlb_lock); 1383 } while (++i < banks_num); 1384 1385 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 1386 data->bclk = devm_clk_get(dev, "bclk"); 1387 if (IS_ERR(data->bclk)) 1388 return PTR_ERR(data->bclk); 1389 } 1390 1391 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) { 1392 ret = dma_set_mask(dev, DMA_BIT_MASK(35)); 1393 if (ret) { 1394 dev_err(dev, "Failed to set dma_mask 35.\n"); 1395 return ret; 1396 } 1397 } 1398 1399 pm_runtime_enable(dev); 1400 1401 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1402 ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1403 if (ret) { 1404 dev_err_probe(dev, ret, "mm dts parse fail\n"); 1405 goto out_runtime_disable; 1406 } 1407 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1408 !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 1409 p = data->plat_data->pericfg_comp_str; 1410 data->pericfg = syscon_regmap_lookup_by_compatible(p); 1411 if (IS_ERR(data->pericfg)) { 1412 ret = PTR_ERR(data->pericfg); 1413 goto out_runtime_disable; 1414 } 1415 } 1416 1417 platform_set_drvdata(pdev, data); 1418 mutex_init(&data->mutex); 1419 1420 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 1421 list_add_tail(&data->list, data->plat_data->hw_list); 1422 data->hw_list = data->plat_data->hw_list; 1423 } else { 1424 INIT_LIST_HEAD(&data->hw_list_head); 1425 list_add_tail(&data->list, &data->hw_list_head); 1426 data->hw_list = &data->hw_list_head; 1427 } 1428 1429 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1430 "mtk-iommu.%pa", &ioaddr); 1431 if (ret) 1432 goto out_list_del; 1433 1434 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1435 if (ret) 1436 goto out_sysfs_remove; 1437 1438 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1439 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1440 if (ret) 1441 goto out_device_unregister; 1442 } 1443 return ret; 1444 1445out_device_unregister: 1446 iommu_device_unregister(&data->iommu); 1447out_sysfs_remove: 1448 iommu_device_sysfs_remove(&data->iommu); 1449out_list_del: 1450 list_del(&data->list); 1451 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1452 device_link_remove(data->smicomm_dev, dev); 1453 1454 for (i = 0; i < MTK_LARB_NR_MAX; i++) 1455 put_device(data->larb_imu[i].dev); 1456 } 1457out_runtime_disable: 1458 pm_runtime_disable(dev); 1459 return ret; 1460} 1461 1462static void mtk_iommu_remove(struct platform_device *pdev) 1463{ 1464 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 1465 struct mtk_iommu_bank_data *bank; 1466 int i; 1467 1468 iommu_device_sysfs_remove(&data->iommu); 1469 iommu_device_unregister(&data->iommu); 1470 1471 list_del(&data->list); 1472 1473 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1474 device_link_remove(data->smicomm_dev, &pdev->dev); 1475 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1476 1477 for (i = 0; i < MTK_LARB_NR_MAX; i++) 1478 put_device(data->larb_imu[i].dev); 1479 } 1480 pm_runtime_disable(&pdev->dev); 1481 for (i = 0; i < data->plat_data->banks_num; i++) { 1482 bank = &data->bank[i]; 1483 if (!bank->m4u_dom) 1484 continue; 1485 devm_free_irq(&pdev->dev, bank->irq, bank); 1486 } 1487} 1488 1489static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 1490{ 1491 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1492 struct mtk_iommu_suspend_reg *reg = &data->reg; 1493 void __iomem *base; 1494 int i = 0; 1495 1496 base = data->bank[i].base; 1497 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 1498 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 1499 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 1500 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1501 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1502 do { 1503 if (!data->plat_data->banks_enable[i]) 1504 continue; 1505 base = data->bank[i].base; 1506 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1507 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1508 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1509 } while (++i < data->plat_data->banks_num); 1510 clk_disable_unprepare(data->bclk); 1511 return 0; 1512} 1513 1514static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 1515{ 1516 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1517 struct mtk_iommu_suspend_reg *reg = &data->reg; 1518 struct mtk_iommu_domain *m4u_dom; 1519 void __iomem *base; 1520 int ret, i = 0; 1521 1522 ret = clk_prepare_enable(data->bclk); 1523 if (ret) { 1524 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 1525 return ret; 1526 } 1527 1528 /* 1529 * Uppon first resume, only enable the clk and return, since the values of the 1530 * registers are not yet set. 1531 */ 1532 if (!reg->wr_len_ctrl) 1533 return 0; 1534 1535 base = data->bank[i].base; 1536 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 1537 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 1538 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 1539 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1540 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1541 do { 1542 m4u_dom = data->bank[i].m4u_dom; 1543 if (!data->plat_data->banks_enable[i] || !m4u_dom) 1544 continue; 1545 base = data->bank[i].base; 1546 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1547 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1548 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1549 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); 1550 } while (++i < data->plat_data->banks_num); 1551 1552 /* 1553 * Users may allocate dma buffer before they call pm_runtime_get, 1554 * in which case it will lack the necessary tlb flush. 1555 * Thus, make sure to update the tlb after each PM resume. 1556 */ 1557 mtk_iommu_tlb_flush_all(data); 1558 return 0; 1559} 1560 1561static const struct dev_pm_ops mtk_iommu_pm_ops = { 1562 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 1563 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1564 pm_runtime_force_resume) 1565}; 1566 1567static const struct mtk_iommu_plat_data mt2712_data = { 1568 .m4u_plat = M4U_MT2712, 1569 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1570 MTK_IOMMU_TYPE_MM, 1571 .hw_list = &m4ulist, 1572 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1573 .iova_region = single_domain, 1574 .banks_num = 1, 1575 .banks_enable = {true}, 1576 .iova_region_nr = ARRAY_SIZE(single_domain), 1577 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1578}; 1579 1580static const struct mtk_iommu_plat_data mt6779_data = { 1581 .m4u_plat = M4U_MT6779, 1582 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1583 MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1584 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1585 .banks_num = 1, 1586 .banks_enable = {true}, 1587 .iova_region = single_domain, 1588 .iova_region_nr = ARRAY_SIZE(single_domain), 1589 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1590}; 1591 1592static const struct mtk_iommu_plat_data mt6795_data = { 1593 .m4u_plat = M4U_MT6795, 1594 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1595 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1596 TF_PORT_TO_ADDR_MT8173, 1597 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1598 .banks_num = 1, 1599 .banks_enable = {true}, 1600 .iova_region = single_domain, 1601 .iova_region_nr = ARRAY_SIZE(single_domain), 1602 .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ 1603}; 1604 1605static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1606 [0] = {~0, ~0}, /* Region0: larb0/1 */ 1607 [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ 1608 [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */ 1609 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0, 1610 ~0, ~0, ~0, ~0, ~0}, 1611 [3] = {0}, 1612 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 1613 [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */ 1614}; 1615 1616static const struct mtk_iommu_plat_data mt6893_data = { 1617 .m4u_plat = M4U_MT8192, 1618 .flags = HAS_BCLK | OUT_ORDER_WR_EN | HAS_SUB_COMM_2BITS | 1619 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1620 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1621 .banks_num = 1, 1622 .banks_enable = {true}, 1623 .iova_region = mt8192_multi_dom, 1624 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1625 .iova_region_larb_msk = mt8192_larb_region_msk, 1626 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1627 {0, 14, 16}, {0, 13, 18, 17}}, 1628}; 1629 1630static const struct mtk_iommu_plat_data mt8167_data = { 1631 .m4u_plat = M4U_MT8167, 1632 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1633 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1634 .banks_num = 1, 1635 .banks_enable = {true}, 1636 .iova_region = single_domain, 1637 .iova_region_nr = ARRAY_SIZE(single_domain), 1638 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1639}; 1640 1641static const struct mtk_iommu_plat_data mt8173_data = { 1642 .m4u_plat = M4U_MT8173, 1643 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1644 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1645 TF_PORT_TO_ADDR_MT8173, 1646 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1647 .banks_num = 1, 1648 .banks_enable = {true}, 1649 .iova_region = single_domain, 1650 .iova_region_nr = ARRAY_SIZE(single_domain), 1651 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1652}; 1653 1654static const struct mtk_iommu_plat_data mt8183_data = { 1655 .m4u_plat = M4U_MT8183, 1656 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1657 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1658 .banks_num = 1, 1659 .banks_enable = {true}, 1660 .iova_region = single_domain, 1661 .iova_region_nr = ARRAY_SIZE(single_domain), 1662 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1663}; 1664 1665static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1666 [0] = {~0, ~0, ~0}, /* Region0: all ports for larb0/1/2 */ 1667 [1] = {0, 0, 0, 0, ~0, 0, 0, ~0}, /* Region1: larb4/7 */ 1668 [2] = {0, 0, 0, 0, 0, 0, 0, 0, /* Region2: larb8/9/11/13/16/17/19/20 */ 1669 ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0, 1670 /* larb13: the other ports except port9/10 */ 1671 ~0, ~0, 0, ~0, ~0}, 1672 [3] = {0}, 1673 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 1674 [5] = {[14] = ~0}, /* larb14 */ 1675}; 1676 1677static const struct mtk_iommu_plat_data mt8186_data_mm = { 1678 .m4u_plat = M4U_MT8186, 1679 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1680 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1681 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1682 {MTK_INVALID_LARBID, 14, 16}, 1683 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1684 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1685 .banks_num = 1, 1686 .banks_enable = {true}, 1687 .iova_region = mt8192_multi_dom, 1688 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1689 .iova_region_larb_msk = mt8186_larb_region_msk, 1690}; 1691 1692static const struct mtk_iommu_plat_data mt8188_data_infra = { 1693 .m4u_plat = M4U_MT8188, 1694 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1695 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT | 1696 PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF, 1697 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1698 .banks_num = 1, 1699 .banks_enable = {true}, 1700 .iova_region = single_domain, 1701 .iova_region_nr = ARRAY_SIZE(single_domain), 1702}; 1703 1704static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1705 [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1706 [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1707 0, 0, 0, 0, 0, 0, 0, 0, 1708 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */ 1709 [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1710 ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1711 ~0, ~0, ~0, ~0, ~0, 0, 0, 0, 1712 0, ~0}, 1713 [3] = {0}, 1714 [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */ 1715 [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */ 1716}; 1717 1718static const struct mtk_iommu_plat_data mt8188_data_vdo = { 1719 .m4u_plat = M4U_MT8188, 1720 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1721 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1722 PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1723 .hw_list = &m4ulist, 1724 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1725 .banks_num = 1, 1726 .banks_enable = {true}, 1727 .iova_region = mt8192_multi_dom, 1728 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1729 .iova_region_larb_msk = mt8188_larb_region_msk, 1730 .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10, 1731 11 /* 11a */, 25 /* 11c */}, 1732 {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}}, 1733}; 1734 1735static const struct mtk_iommu_plat_data mt8188_data_vpp = { 1736 .m4u_plat = M4U_MT8188, 1737 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1738 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1739 PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1740 .hw_list = &m4ulist, 1741 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1742 .banks_num = 1, 1743 .banks_enable = {true}, 1744 .iova_region = mt8192_multi_dom, 1745 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1746 .iova_region_larb_msk = mt8188_larb_region_msk, 1747 .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID}, 1748 {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID, 1749 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID, 1750 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}}, 1751}; 1752 1753static const unsigned int mt8189_apu_region_msk[][MTK_LARB_NR_MAX] = { 1754 [0] = {[0] = BIT(2)}, /* Region0: fake larb 0 APU_SECURE */ 1755 [1] = {[0] = BIT(1)}, /* Region1: fake larb 0 APU_CODE */ 1756 [2] = {[0] = BIT(3)}, /* Region2: fake larb 0 APU_VLM */ 1757 [3] = {[0] = BIT(0)}, /* Region3: fake larb 0 APU_DATA */ 1758}; 1759 1760static const struct mtk_iommu_plat_data mt8189_data_apu = { 1761 .m4u_plat = M4U_MT8189, 1762 .flags = IOVA_34_EN | DCM_DISABLE | 1763 MTK_IOMMU_TYPE_APU | PGTABLE_PA_35_EN, 1764 .hw_list = &apulist, 1765 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1766 .banks_num = 1, 1767 .banks_enable = {true}, 1768 .iova_region = mt8189_multi_dom_apu, 1769 .iova_region_nr = ARRAY_SIZE(mt8189_multi_dom_apu), 1770 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1771 .iova_region_larb_msk = mt8189_apu_region_msk, 1772}; 1773 1774static const struct mtk_iommu_plat_data mt8189_data_infra = { 1775 .m4u_plat = M4U_MT8189, 1776 .flags = WR_THROT_EN | DCM_DISABLE | MTK_IOMMU_TYPE_INFRA | 1777 CFG_IFA_MASTER_IN_ATF | SHARE_PGTABLE | PGTABLE_PA_35_EN, 1778 .hw_list = &infralist, 1779 .banks_num = 1, 1780 .banks_enable = {true}, 1781 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1782 .iova_region = single_domain, 1783 .iova_region_nr = ARRAY_SIZE(single_domain), 1784}; 1785 1786static const u32 mt8189_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1787 [0] = {~0, ~0, ~0, [22] = BIT(0)}, /* Region0: all ports for larb0/1/2 */ 1788 [1] = {[3] = ~0, [4] = ~0}, /* Region1: all ports for larb4(3)/7(4) */ 1789 [2] = {[5] = ~0, [6] = ~0, /* Region2: all ports for larb9(5)/11(6) */ 1790 [7] = ~0, [8] = ~0, /* Region2: all ports for larb13(7)/14(8) */ 1791 [9] = ~0, [10] = ~0, /* Region2: all ports for larb16(9)/17(10) */ 1792 [11] = ~0, [12] = ~0, /* Region2: all ports for larb19(11)/20(12) */ 1793 [21] = ~0}, /* Region2: larb21 fake GCE larb */ 1794}; 1795 1796static const struct mtk_iommu_plat_data mt8189_data_mm = { 1797 .m4u_plat = M4U_MT8189, 1798 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1799 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM | 1800 PGTABLE_PA_35_EN | DL_WITH_MULTI_LARB, 1801 .hw_list = &m4ulist, 1802 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1803 .banks_num = 5, 1804 .banks_enable = {true, false, false, false, false}, 1805 .iova_region = mt8192_multi_dom, 1806 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1807 .iova_region_larb_msk = mt8189_larb_region_msk, 1808 .larbid_remap = {{0}, {1}, {21/* GCE_D */, 21/* GCE_M */, 2}, 1809 {19, 20, 9, 11}, {7}, {4}, 1810 {13, 17}, {14, 16}}, 1811}; 1812 1813static const struct mtk_iommu_plat_data mt8192_data = { 1814 .m4u_plat = M4U_MT8192, 1815 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1816 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1817 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1818 .banks_num = 1, 1819 .banks_enable = {true}, 1820 .iova_region = mt8192_multi_dom, 1821 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1822 .iova_region_larb_msk = mt8192_larb_region_msk, 1823 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1824 {0, 14, 16}, {0, 13, 18, 17}}, 1825}; 1826 1827static const struct mtk_iommu_plat_data mt8195_data_infra = { 1828 .m4u_plat = M4U_MT8195, 1829 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1830 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1831 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1832 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1833 .banks_num = 5, 1834 .banks_enable = {true, false, false, false, true}, 1835 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 1836 [4] = GENMASK(31, 20), /* USB */ 1837 }, 1838 .iova_region = single_domain, 1839 .iova_region_nr = ARRAY_SIZE(single_domain), 1840}; 1841 1842static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1843 [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1844 [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1845 0, 0, 0, 0, 0, 0, 0, 0, 1846 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */ 1847 ~0}, 1848 [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1849 ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1850 ~0, ~0, 0, 0, 0, 0, 0, 0, 1851 0, ~0, ~0, ~0, ~0}, 1852 [3] = {0}, 1853 [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */ 1854 [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */ 1855}; 1856 1857static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1858 .m4u_plat = M4U_MT8195, 1859 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1860 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1861 .hw_list = &m4ulist, 1862 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1863 .banks_num = 1, 1864 .banks_enable = {true}, 1865 .iova_region = mt8192_multi_dom, 1866 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1867 .iova_region_larb_msk = mt8195_larb_region_msk, 1868 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1869 {13, 17, 15/* 17b */, 25}, {5}}, 1870}; 1871 1872static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1873 .m4u_plat = M4U_MT8195, 1874 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1875 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1876 .hw_list = &m4ulist, 1877 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1878 .banks_num = 1, 1879 .banks_enable = {true}, 1880 .iova_region = mt8192_multi_dom, 1881 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1882 .iova_region_larb_msk = mt8195_larb_region_msk, 1883 .larbid_remap = {{1}, {3}, 1884 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1885 {8}, {20}, {12}, 1886 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1887 {14, 16, 29, 26, 30, 31, 18}, 1888 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1889}; 1890 1891static const struct mtk_iommu_plat_data mt8365_data = { 1892 .m4u_plat = M4U_MT8365, 1893 .flags = RESET_AXI | INT_ID_PORT_WIDTH_6, 1894 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1895 .banks_num = 1, 1896 .banks_enable = {true}, 1897 .iova_region = single_domain, 1898 .iova_region_nr = ARRAY_SIZE(single_domain), 1899 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1900}; 1901 1902static const struct of_device_id mtk_iommu_of_ids[] = { 1903 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1904 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1905 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, 1906 { .compatible = "mediatek,mt6893-iommu-mm", .data = &mt6893_data}, 1907 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1908 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1909 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1910 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 1911 { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra}, 1912 { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo}, 1913 { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp}, 1914 { .compatible = "mediatek,mt8189-iommu-apu", .data = &mt8189_data_apu}, 1915 { .compatible = "mediatek,mt8189-iommu-infra", .data = &mt8189_data_infra}, 1916 { .compatible = "mediatek,mt8189-iommu-mm", .data = &mt8189_data_mm}, 1917 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1918 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1919 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1920 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 1921 { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, 1922 {} 1923}; 1924MODULE_DEVICE_TABLE(of, mtk_iommu_of_ids); 1925 1926static struct platform_driver mtk_iommu_driver = { 1927 .probe = mtk_iommu_probe, 1928 .remove = mtk_iommu_remove, 1929 .driver = { 1930 .name = "mtk-iommu", 1931 .of_match_table = mtk_iommu_of_ids, 1932 .pm = &mtk_iommu_pm_ops, 1933 } 1934}; 1935module_platform_driver(mtk_iommu_driver); 1936 1937MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1938MODULE_LICENSE("GPL v2");
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