msm_iommu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  3 *
  4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
  5 */
  6
  7#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
  8#include <linux/kernel.h>
  9#include <linux/init.h>
 10#include <linux/platform_device.h>
 11#include <linux/errno.h>
 12#include <linux/io.h>
 13#include <linux/io-pgtable.h>
 14#include <linux/interrupt.h>
 15#include <linux/list.h>
 16#include <linux/spinlock.h>
 17#include <linux/slab.h>
 18#include <linux/iommu.h>
 19#include <linux/clk.h>
 20#include <linux/err.h>
 21
 22#include <asm/cacheflush.h>
 23#include <linux/sizes.h>
 24
 25#include "msm_iommu_hw-8xxx.h"
 26#include "msm_iommu.h"
 27
 28#define MRC(reg, processor, op1, crn, crm, op2)				\
 29__asm__ __volatile__ (							\
 30"   mrc   "   #processor "," #op1 ", %0,"  #crn "," #crm "," #op2 "\n"  \
 31: "=r" (reg))
 32
 33/* bitmap of the page sizes currently supported */
 34#define MSM_IOMMU_PGSIZES	(SZ_4K | SZ_64K | SZ_1M | SZ_16M)
 35
 36static DEFINE_SPINLOCK(msm_iommu_lock);
 37static LIST_HEAD(qcom_iommu_devices);
 38static struct iommu_ops msm_iommu_ops;
 39
 40struct msm_priv {
 41	struct list_head list_attached;
 42	struct iommu_domain domain;
 43	struct io_pgtable_cfg	cfg;
 44	struct io_pgtable_ops	*iop;
 45	struct device		*dev;
 46	spinlock_t		pgtlock; /* pagetable lock */
 47};
 48
 49static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
 50{
 51	return container_of(dom, struct msm_priv, domain);
 52}
 53
 54static int __enable_clocks(struct msm_iommu_dev *iommu)
 55{
 56	int ret;
 57
 58	ret = clk_enable(iommu->pclk);
 59	if (ret)
 60		goto fail;
 61
 62	if (iommu->clk) {
 63		ret = clk_enable(iommu->clk);
 64		if (ret)
 65			clk_disable(iommu->pclk);
 66	}
 67fail:
 68	return ret;
 69}
 70
 71static void __disable_clocks(struct msm_iommu_dev *iommu)
 72{
 73	if (iommu->clk)
 74		clk_disable(iommu->clk);
 75	clk_disable(iommu->pclk);
 76}
 77
 78static void msm_iommu_reset(void __iomem *base, int ncb)
 79{
 80	int ctx;
 81
 82	SET_RPUE(base, 0);
 83	SET_RPUEIE(base, 0);
 84	SET_ESRRESTORE(base, 0);
 85	SET_TBE(base, 0);
 86	SET_CR(base, 0);
 87	SET_SPDMBE(base, 0);
 88	SET_TESTBUSCR(base, 0);
 89	SET_TLBRSW(base, 0);
 90	SET_GLOBAL_TLBIALL(base, 0);
 91	SET_RPU_ACR(base, 0);
 92	SET_TLBLKCRWE(base, 1);
 93
 94	for (ctx = 0; ctx < ncb; ctx++) {
 95		SET_BPRCOSH(base, ctx, 0);
 96		SET_BPRCISH(base, ctx, 0);
 97		SET_BPRCNSH(base, ctx, 0);
 98		SET_BPSHCFG(base, ctx, 0);
 99		SET_BPMTCFG(base, ctx, 0);
100		SET_ACTLR(base, ctx, 0);
101		SET_SCTLR(base, ctx, 0);
102		SET_FSRRESTORE(base, ctx, 0);
103		SET_TTBR0(base, ctx, 0);
104		SET_TTBR1(base, ctx, 0);
105		SET_TTBCR(base, ctx, 0);
106		SET_BFBCR(base, ctx, 0);
107		SET_PAR(base, ctx, 0);
108		SET_FAR(base, ctx, 0);
109		SET_CTX_TLBIALL(base, ctx, 0);
110		SET_TLBFLPTER(base, ctx, 0);
111		SET_TLBSLPTER(base, ctx, 0);
112		SET_TLBLKCR(base, ctx, 0);
113		SET_CONTEXTIDR(base, ctx, 0);
114	}
115}
116
117static void __flush_iotlb(void *cookie)
118{
119	struct msm_priv *priv = cookie;
120	struct msm_iommu_dev *iommu = NULL;
121	struct msm_iommu_ctx_dev *master;
122	int ret = 0;
123
124	list_for_each_entry(iommu, &priv->list_attached, dom_node) {
125		ret = __enable_clocks(iommu);
126		if (ret)
127			goto fail;
128
129		list_for_each_entry(master, &iommu->ctx_list, list)
130			SET_CTX_TLBIALL(iommu->base, master->num, 0);
131
132		__disable_clocks(iommu);
133	}
134fail:
135	return;
136}
137
138static void __flush_iotlb_range(unsigned long iova, size_t size,
139				size_t granule, bool leaf, void *cookie)
140{
141	struct msm_priv *priv = cookie;
142	struct msm_iommu_dev *iommu = NULL;
143	struct msm_iommu_ctx_dev *master;
144	int ret = 0;
145	int temp_size;
146
147	list_for_each_entry(iommu, &priv->list_attached, dom_node) {
148		ret = __enable_clocks(iommu);
149		if (ret)
150			goto fail;
151
152		list_for_each_entry(master, &iommu->ctx_list, list) {
153			temp_size = size;
154			do {
155				iova &= TLBIVA_VA;
156				iova |= GET_CONTEXTIDR_ASID(iommu->base,
157							    master->num);
158				SET_TLBIVA(iommu->base, master->num, iova);
159				iova += granule;
160			} while (temp_size -= granule);
161		}
162
163		__disable_clocks(iommu);
164	}
165
166fail:
167	return;
168}
169
170static void __flush_iotlb_walk(unsigned long iova, size_t size,
171			       size_t granule, void *cookie)
172{
173	__flush_iotlb_range(iova, size, granule, false, cookie);
174}
175
176static void __flush_iotlb_page(struct iommu_iotlb_gather *gather,
177			       unsigned long iova, size_t granule, void *cookie)
178{
179	__flush_iotlb_range(iova, granule, granule, true, cookie);
180}
181
182static const struct iommu_flush_ops msm_iommu_flush_ops = {
183	.tlb_flush_all = __flush_iotlb,
184	.tlb_flush_walk = __flush_iotlb_walk,
185	.tlb_add_page = __flush_iotlb_page,
186};
187
188static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
189{
190	int idx;
191
192	do {
193		idx = find_next_zero_bit(map, end, start);
194		if (idx == end)
195			return -ENOSPC;
196	} while (test_and_set_bit(idx, map));
197
198	return idx;
199}
200
201static void msm_iommu_free_ctx(unsigned long *map, int idx)
202{
203	clear_bit(idx, map);
204}
205
206static void config_mids(struct msm_iommu_dev *iommu,
207			struct msm_iommu_ctx_dev *master)
208{
209	int mid, ctx, i;
210
211	for (i = 0; i < master->num_mids; i++) {
212		mid = master->mids[i];
213		ctx = master->num;
214
215		SET_M2VCBR_N(iommu->base, mid, 0);
216		SET_CBACR_N(iommu->base, ctx, 0);
217
218		/* Set VMID = 0 */
219		SET_VMID(iommu->base, mid, 0);
220
221		/* Set the context number for that MID to this context */
222		SET_CBNDX(iommu->base, mid, ctx);
223
224		/* Set MID associated with this context bank to 0*/
225		SET_CBVMID(iommu->base, ctx, 0);
226
227		/* Set the ASID for TLB tagging for this context */
228		SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
229
230		/* Set security bit override to be Non-secure */
231		SET_NSCFG(iommu->base, mid, 3);
232	}
233}
234
235static void __reset_context(void __iomem *base, int ctx)
236{
237	SET_BPRCOSH(base, ctx, 0);
238	SET_BPRCISH(base, ctx, 0);
239	SET_BPRCNSH(base, ctx, 0);
240	SET_BPSHCFG(base, ctx, 0);
241	SET_BPMTCFG(base, ctx, 0);
242	SET_ACTLR(base, ctx, 0);
243	SET_SCTLR(base, ctx, 0);
244	SET_FSRRESTORE(base, ctx, 0);
245	SET_TTBR0(base, ctx, 0);
246	SET_TTBR1(base, ctx, 0);
247	SET_TTBCR(base, ctx, 0);
248	SET_BFBCR(base, ctx, 0);
249	SET_PAR(base, ctx, 0);
250	SET_FAR(base, ctx, 0);
251	SET_CTX_TLBIALL(base, ctx, 0);
252	SET_TLBFLPTER(base, ctx, 0);
253	SET_TLBSLPTER(base, ctx, 0);
254	SET_TLBLKCR(base, ctx, 0);
255}
256
257static void __program_context(void __iomem *base, int ctx,
258			      struct msm_priv *priv)
259{
260	__reset_context(base, ctx);
261
262	/* Turn on TEX Remap */
263	SET_TRE(base, ctx, 1);
264	SET_AFE(base, ctx, 1);
265
266	/* Set up HTW mode */
267	/* TLB miss configuration: perform HTW on miss */
268	SET_TLBMCFG(base, ctx, 0x3);
269
270	/* V2P configuration: HTW for access */
271	SET_V2PCFG(base, ctx, 0x3);
272
273	SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
274	SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
275	SET_TTBR1(base, ctx, 0);
276
277	/* Set prrr and nmrr */
278	SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
279	SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
280
281	/* Invalidate the TLB for this context */
282	SET_CTX_TLBIALL(base, ctx, 0);
283
284	/* Set interrupt number to "secure" interrupt */
285	SET_IRPTNDX(base, ctx, 0);
286
287	/* Enable context fault interrupt */
288	SET_CFEIE(base, ctx, 1);
289
290	/* Stall access on a context fault and let the handler deal with it */
291	SET_CFCFG(base, ctx, 1);
292
293	/* Redirect all cacheable requests to L2 slave port. */
294	SET_RCISH(base, ctx, 1);
295	SET_RCOSH(base, ctx, 1);
296	SET_RCNSH(base, ctx, 1);
297
298	/* Turn on BFB prefetch */
299	SET_BFBDFE(base, ctx, 1);
300
301	/* Enable the MMU */
302	SET_M(base, ctx, 1);
303}
304
305static struct iommu_domain *msm_iommu_domain_alloc_paging(struct device *dev)
306{
307	struct msm_priv *priv;
308
309	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
310	if (!priv)
311		goto fail_nomem;
312
313	INIT_LIST_HEAD(&priv->list_attached);
314
315	priv->domain.pgsize_bitmap = MSM_IOMMU_PGSIZES;
316
317	priv->domain.geometry.aperture_start = 0;
318	priv->domain.geometry.aperture_end   = (1ULL << 32) - 1;
319	priv->domain.geometry.force_aperture = true;
320
321	return &priv->domain;
322
323fail_nomem:
324	kfree(priv);
325	return NULL;
326}
327
328static void msm_iommu_domain_free(struct iommu_domain *domain)
329{
330	struct msm_priv *priv;
331	unsigned long flags;
332
333	spin_lock_irqsave(&msm_iommu_lock, flags);
334	priv = to_msm_priv(domain);
335	kfree(priv);
336	spin_unlock_irqrestore(&msm_iommu_lock, flags);
337}
338
339static int msm_iommu_domain_config(struct msm_priv *priv)
340{
341	spin_lock_init(&priv->pgtlock);
342
343	priv->cfg = (struct io_pgtable_cfg) {
344		.pgsize_bitmap = priv->domain.pgsize_bitmap,
345		.ias = 32,
346		.oas = 32,
347		.tlb = &msm_iommu_flush_ops,
348		.iommu_dev = priv->dev,
349	};
350
351	priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
352	if (!priv->iop) {
353		dev_err(priv->dev, "Failed to allocate pgtable\n");
354		return -EINVAL;
355	}
356
357	return 0;
358}
359
360/* Must be called under msm_iommu_lock */
361static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
362{
363	struct msm_iommu_dev *iommu, *ret = NULL;
364	struct msm_iommu_ctx_dev *master;
365
366	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
367		master = list_first_entry(&iommu->ctx_list,
368					  struct msm_iommu_ctx_dev,
369					  list);
370		if (master->of_node == dev->of_node) {
371			ret = iommu;
372			break;
373		}
374	}
375
376	return ret;
377}
378
379static struct iommu_device *msm_iommu_probe_device(struct device *dev)
380{
381	struct msm_iommu_dev *iommu;
382	unsigned long flags;
383
384	spin_lock_irqsave(&msm_iommu_lock, flags);
385	iommu = find_iommu_for_dev(dev);
386	spin_unlock_irqrestore(&msm_iommu_lock, flags);
387
388	if (!iommu)
389		return ERR_PTR(-ENODEV);
390
391	return &iommu->iommu;
392}
393
394static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev,
395				struct iommu_domain *old)
396{
397	int ret = 0;
398	unsigned long flags;
399	struct msm_iommu_dev *iommu;
400	struct msm_priv *priv = to_msm_priv(domain);
401	struct msm_iommu_ctx_dev *master;
402
403	priv->dev = dev;
404	msm_iommu_domain_config(priv);
405
406	spin_lock_irqsave(&msm_iommu_lock, flags);
407	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
408		master = list_first_entry(&iommu->ctx_list,
409					  struct msm_iommu_ctx_dev,
410					  list);
411		if (master->of_node == dev->of_node) {
412			ret = __enable_clocks(iommu);
413			if (ret)
414				goto fail;
415
416			list_for_each_entry(master, &iommu->ctx_list, list) {
417				if (master->num) {
418					dev_err(dev, "domain already attached");
419					ret = -EEXIST;
420					goto fail;
421				}
422				master->num =
423					msm_iommu_alloc_ctx(iommu->context_map,
424							    0, iommu->ncb);
425				if (IS_ERR_VALUE(master->num)) {
426					ret = -ENODEV;
427					goto fail;
428				}
429				config_mids(iommu, master);
430				__program_context(iommu->base, master->num,
431						  priv);
432			}
433			__disable_clocks(iommu);
434			list_add(&iommu->dom_node, &priv->list_attached);
435		}
436	}
437
438fail:
439	spin_unlock_irqrestore(&msm_iommu_lock, flags);
440
441	return ret;
442}
443
444static int msm_iommu_identity_attach(struct iommu_domain *identity_domain,
445				     struct device *dev,
446				     struct iommu_domain *old)
447{
448	struct msm_priv *priv;
449	unsigned long flags;
450	struct msm_iommu_dev *iommu;
451	struct msm_iommu_ctx_dev *master;
452	int ret = 0;
453
454	if (old == identity_domain || !old)
455		return 0;
456
457	priv = to_msm_priv(old);
458	free_io_pgtable_ops(priv->iop);
459
460	spin_lock_irqsave(&msm_iommu_lock, flags);
461	list_for_each_entry(iommu, &priv->list_attached, dom_node) {
462		ret = __enable_clocks(iommu);
463		if (ret)
464			goto fail;
465
466		list_for_each_entry(master, &iommu->ctx_list, list) {
467			msm_iommu_free_ctx(iommu->context_map, master->num);
468			__reset_context(iommu->base, master->num);
469		}
470		__disable_clocks(iommu);
471	}
472fail:
473	spin_unlock_irqrestore(&msm_iommu_lock, flags);
474	return ret;
475}
476
477static struct iommu_domain_ops msm_iommu_identity_ops = {
478	.attach_dev = msm_iommu_identity_attach,
479};
480
481static struct iommu_domain msm_iommu_identity_domain = {
482	.type = IOMMU_DOMAIN_IDENTITY,
483	.ops = &msm_iommu_identity_ops,
484};
485
486static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
487			 phys_addr_t pa, size_t pgsize, size_t pgcount,
488			 int prot, gfp_t gfp, size_t *mapped)
489{
490	struct msm_priv *priv = to_msm_priv(domain);
491	unsigned long flags;
492	int ret;
493
494	spin_lock_irqsave(&priv->pgtlock, flags);
495	ret = priv->iop->map_pages(priv->iop, iova, pa, pgsize, pgcount, prot,
496				   GFP_ATOMIC, mapped);
497	spin_unlock_irqrestore(&priv->pgtlock, flags);
498
499	return ret;
500}
501
502static int msm_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
503			      size_t size)
504{
505	struct msm_priv *priv = to_msm_priv(domain);
506
507	__flush_iotlb_range(iova, size, SZ_4K, false, priv);
508	return 0;
509}
510
511static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
512			      size_t pgsize, size_t pgcount,
513			      struct iommu_iotlb_gather *gather)
514{
515	struct msm_priv *priv = to_msm_priv(domain);
516	unsigned long flags;
517	size_t ret;
518
519	spin_lock_irqsave(&priv->pgtlock, flags);
520	ret = priv->iop->unmap_pages(priv->iop, iova, pgsize, pgcount, gather);
521	spin_unlock_irqrestore(&priv->pgtlock, flags);
522
523	return ret;
524}
525
526static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
527					  dma_addr_t va)
528{
529	struct msm_priv *priv;
530	struct msm_iommu_dev *iommu;
531	struct msm_iommu_ctx_dev *master;
532	unsigned int par;
533	unsigned long flags;
534	phys_addr_t ret = 0;
535
536	spin_lock_irqsave(&msm_iommu_lock, flags);
537
538	priv = to_msm_priv(domain);
539	iommu = list_first_entry(&priv->list_attached,
540				 struct msm_iommu_dev, dom_node);
541
542	if (list_empty(&iommu->ctx_list))
543		goto fail;
544
545	master = list_first_entry(&iommu->ctx_list,
546				  struct msm_iommu_ctx_dev, list);
547	if (!master)
548		goto fail;
549
550	ret = __enable_clocks(iommu);
551	if (ret)
552		goto fail;
553
554	/* Invalidate context TLB */
555	SET_CTX_TLBIALL(iommu->base, master->num, 0);
556	SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
557
558	par = GET_PAR(iommu->base, master->num);
559
560	/* We are dealing with a supersection */
561	if (GET_NOFAULT_SS(iommu->base, master->num))
562		ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
563	else	/* Upper 20 bits from PAR, lower 12 from VA */
564		ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
565
566	if (GET_FAULT(iommu->base, master->num))
567		ret = 0;
568
569	__disable_clocks(iommu);
570fail:
571	spin_unlock_irqrestore(&msm_iommu_lock, flags);
572	return ret;
573}
574
575static void print_ctx_regs(void __iomem *base, int ctx)
576{
577	unsigned int fsr = GET_FSR(base, ctx);
578	pr_err("FAR    = %08x    PAR    = %08x\n",
579	       GET_FAR(base, ctx), GET_PAR(base, ctx));
580	pr_err("FSR    = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
581			(fsr & 0x02) ? "TF " : "",
582			(fsr & 0x04) ? "AFF " : "",
583			(fsr & 0x08) ? "APF " : "",
584			(fsr & 0x10) ? "TLBMF " : "",
585			(fsr & 0x20) ? "HTWDEEF " : "",
586			(fsr & 0x40) ? "HTWSEEF " : "",
587			(fsr & 0x80) ? "MHF " : "",
588			(fsr & 0x10000) ? "SL " : "",
589			(fsr & 0x40000000) ? "SS " : "",
590			(fsr & 0x80000000) ? "MULTI " : "");
591
592	pr_err("FSYNR0 = %08x    FSYNR1 = %08x\n",
593	       GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
594	pr_err("TTBR0  = %08x    TTBR1  = %08x\n",
595	       GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
596	pr_err("SCTLR  = %08x    ACTLR  = %08x\n",
597	       GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
598}
599
600static int insert_iommu_master(struct device *dev,
601				struct msm_iommu_dev **iommu,
602				const struct of_phandle_args *spec)
603{
604	struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev);
605	int sid;
606
607	if (list_empty(&(*iommu)->ctx_list)) {
608		master = kzalloc(sizeof(*master), GFP_ATOMIC);
609		if (!master) {
610			dev_err(dev, "Failed to allocate iommu_master\n");
611			return -ENOMEM;
612		}
613		master->of_node = dev->of_node;
614		list_add(&master->list, &(*iommu)->ctx_list);
615		dev_iommu_priv_set(dev, master);
616	}
617
618	for (sid = 0; sid < master->num_mids; sid++)
619		if (master->mids[sid] == spec->args[0]) {
620			dev_warn(dev, "Stream ID 0x%x repeated; ignoring\n",
621				 sid);
622			return 0;
623		}
624
625	master->mids[master->num_mids++] = spec->args[0];
626	return 0;
627}
628
629static int qcom_iommu_of_xlate(struct device *dev,
630			       const struct of_phandle_args *spec)
631{
632	struct msm_iommu_dev *iommu = NULL, *iter;
633	unsigned long flags;
634	int ret = 0;
635
636	spin_lock_irqsave(&msm_iommu_lock, flags);
637	list_for_each_entry(iter, &qcom_iommu_devices, dev_node) {
638		if (iter->dev->of_node == spec->np) {
639			iommu = iter;
640			break;
641		}
642	}
643
644	if (!iommu) {
645		ret = -ENODEV;
646		goto fail;
647	}
648
649	ret = insert_iommu_master(dev, &iommu, spec);
650fail:
651	spin_unlock_irqrestore(&msm_iommu_lock, flags);
652
653	return ret;
654}
655
656irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
657{
658	struct msm_iommu_dev *iommu = dev_id;
659	unsigned int fsr;
660	int i, ret;
661
662	spin_lock(&msm_iommu_lock);
663
664	if (!iommu) {
665		pr_err("Invalid device ID in context interrupt handler\n");
666		goto fail;
667	}
668
669	pr_err("Unexpected IOMMU page fault!\n");
670	pr_err("base = %08x\n", (unsigned int)iommu->base);
671
672	ret = __enable_clocks(iommu);
673	if (ret)
674		goto fail;
675
676	for (i = 0; i < iommu->ncb; i++) {
677		fsr = GET_FSR(iommu->base, i);
678		if (fsr) {
679			pr_err("Fault occurred in context %d.\n", i);
680			pr_err("Interesting registers:\n");
681			print_ctx_regs(iommu->base, i);
682			SET_FSR(iommu->base, i, 0x4000000F);
683		}
684	}
685	__disable_clocks(iommu);
686fail:
687	spin_unlock(&msm_iommu_lock);
688	return 0;
689}
690
691static struct iommu_ops msm_iommu_ops = {
692	.identity_domain = &msm_iommu_identity_domain,
693	.domain_alloc_paging = msm_iommu_domain_alloc_paging,
694	.probe_device = msm_iommu_probe_device,
695	.device_group = generic_device_group,
696	.of_xlate = qcom_iommu_of_xlate,
697	.default_domain_ops = &(const struct iommu_domain_ops) {
698		.attach_dev	= msm_iommu_attach_dev,
699		.map_pages	= msm_iommu_map,
700		.unmap_pages	= msm_iommu_unmap,
701		/*
702		 * Nothing is needed here, the barrier to guarantee
703		 * completion of the tlb sync operation is implicitly
704		 * taken care when the iommu client does a writel before
705		 * kick starting the other master.
706		 */
707		.iotlb_sync	= NULL,
708		.iotlb_sync_map	= msm_iommu_sync_map,
709		.iova_to_phys	= msm_iommu_iova_to_phys,
710		.free		= msm_iommu_domain_free,
711	}
712};
713
714static int msm_iommu_probe(struct platform_device *pdev)
715{
716	struct resource *r;
717	resource_size_t ioaddr;
718	struct msm_iommu_dev *iommu;
719	int ret, par, val;
720
721	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
722	if (!iommu)
723		return -ENODEV;
724
725	iommu->dev = &pdev->dev;
726	INIT_LIST_HEAD(&iommu->ctx_list);
727
728	iommu->pclk = devm_clk_get_prepared(iommu->dev, "smmu_pclk");
729	if (IS_ERR(iommu->pclk))
730		return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),
731				     "could not get smmu_pclk\n");
732
733	iommu->clk = devm_clk_get_prepared(iommu->dev, "iommu_clk");
734	if (IS_ERR(iommu->clk))
735		return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),
736				     "could not get iommu_clk\n");
737
738	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739	iommu->base = devm_ioremap_resource(iommu->dev, r);
740	if (IS_ERR(iommu->base)) {
741		ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");
742		return ret;
743	}
744	ioaddr = r->start;
745
746	iommu->irq = platform_get_irq(pdev, 0);
747	if (iommu->irq < 0)
748		return -ENODEV;
749
750	ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
751	if (ret) {
752		dev_err(iommu->dev, "could not get ncb\n");
753		return ret;
754	}
755	iommu->ncb = val;
756
757	msm_iommu_reset(iommu->base, iommu->ncb);
758	SET_M(iommu->base, 0, 1);
759	SET_PAR(iommu->base, 0, 0);
760	SET_V2PCFG(iommu->base, 0, 1);
761	SET_V2PPR(iommu->base, 0, 0);
762	par = GET_PAR(iommu->base, 0);
763	SET_V2PCFG(iommu->base, 0, 0);
764	SET_M(iommu->base, 0, 0);
765
766	if (!par) {
767		pr_err("Invalid PAR value detected\n");
768		return -ENODEV;
769	}
770
771	ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
772					msm_iommu_fault_handler,
773					IRQF_ONESHOT | IRQF_SHARED,
774					"msm_iommu_secure_irpt_handler",
775					iommu);
776	if (ret) {
777		pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
778		return ret;
779	}
780
781	list_add(&iommu->dev_node, &qcom_iommu_devices);
782
783	ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
784				     "msm-smmu.%pa", &ioaddr);
785	if (ret) {
786		pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
787		return ret;
788	}
789
790	ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);
791	if (ret) {
792		pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
793		return ret;
794	}
795
796	pr_info("device mapped at %p, irq %d with %d ctx banks\n",
797		iommu->base, iommu->irq, iommu->ncb);
798
799	return ret;
800}
801
802static const struct of_device_id msm_iommu_dt_match[] = {
803	{ .compatible = "qcom,apq8064-iommu" },
804	{}
805};
806
807static struct platform_driver msm_iommu_driver = {
808	.driver = {
809		.name	= "msm_iommu",
810		.of_match_table = msm_iommu_dt_match,
811	},
812	.probe		= msm_iommu_probe,
813};
814builtin_platform_driver(msm_iommu_driver);