irq_remapping.c

   1// SPDX-License-Identifier: GPL-2.0
   2
   3#define pr_fmt(fmt)     "DMAR-IR: " fmt
   4
   5#include <linux/interrupt.h>
   6#include <linux/dmar.h>
   7#include <linux/spinlock.h>
   8#include <linux/slab.h>
   9#include <linux/jiffies.h>
  10#include <linux/hpet.h>
  11#include <linux/pci.h>
  12#include <linux/irq.h>
  13#include <linux/irqchip/irq-msi-lib.h>
  14#include <linux/acpi.h>
  15#include <linux/irqdomain.h>
  16#include <linux/crash_dump.h>
  17#include <asm/io_apic.h>
  18#include <asm/apic.h>
  19#include <asm/smp.h>
  20#include <asm/cpu.h>
  21#include <asm/irq_remapping.h>
  22#include <asm/pci-direct.h>
  23#include <asm/posted_intr.h>
  24
  25#include "iommu.h"
  26#include "../irq_remapping.h"
  27#include "../iommu-pages.h"
  28
  29struct ioapic_scope {
  30	struct intel_iommu *iommu;
  31	unsigned int id;
  32	unsigned int bus;	/* PCI bus number */
  33	unsigned int devfn;	/* PCI devfn number */
  34};
  35
  36struct hpet_scope {
  37	struct intel_iommu *iommu;
  38	u8 id;
  39	unsigned int bus;
  40	unsigned int devfn;
  41};
  42
  43struct irq_2_iommu {
  44	struct intel_iommu *iommu;
  45	u16 irte_index;
  46	u16 sub_handle;
  47	u8  irte_mask;
  48	bool posted_msi;
  49	bool posted_vcpu;
  50};
  51
  52struct intel_ir_data {
  53	struct irq_2_iommu			irq_2_iommu;
  54	struct irte				irte_entry;
  55	union {
  56		struct msi_msg			msi_entry;
  57	};
  58};
  59
  60#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
  61#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
  62
  63static int __read_mostly eim_mode;
  64static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  65static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  66
  67/*
  68 * Lock ordering:
  69 * ->dmar_global_lock
  70 *	->irq_2_ir_lock
  71 *		->qi->q_lock
  72 *	->iommu->register_lock
  73 * Note:
  74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
  75 * in single-threaded environment with interrupt disabled, so no need to tabke
  76 * the dmar_global_lock.
  77 */
  78DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
  79static const struct irq_domain_ops intel_ir_domain_ops;
  80
  81static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
  82static int __init parse_ioapics_under_ir(void);
  83static const struct msi_parent_ops dmar_msi_parent_ops;
  84
  85static bool ir_pre_enabled(struct intel_iommu *iommu)
  86{
  87	return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
  88}
  89
  90static void clear_ir_pre_enabled(struct intel_iommu *iommu)
  91{
  92	iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
  93}
  94
  95static void init_ir_status(struct intel_iommu *iommu)
  96{
  97	u32 gsts;
  98
  99	gsts = readl(iommu->reg + DMAR_GSTS_REG);
 100	if (gsts & DMA_GSTS_IRES)
 101		iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
 102}
 103
 104static int alloc_irte(struct intel_iommu *iommu,
 105		      struct irq_2_iommu *irq_iommu, u16 count)
 106{
 107	struct ir_table *table = iommu->ir_table;
 108	unsigned int mask = 0;
 109	unsigned long flags;
 110	int index;
 111
 112	if (!count || !irq_iommu)
 113		return -1;
 114
 115	if (count > 1) {
 116		count = __roundup_pow_of_two(count);
 117		mask = ilog2(count);
 118	}
 119
 120	if (mask > ecap_max_handle_mask(iommu->ecap)) {
 121		pr_err("Requested mask %x exceeds the max invalidation handle"
 122		       " mask value %Lx\n", mask,
 123		       ecap_max_handle_mask(iommu->ecap));
 124		return -1;
 125	}
 126
 127	raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 128	index = bitmap_find_free_region(table->bitmap,
 129					INTR_REMAP_TABLE_ENTRIES, mask);
 130	if (index < 0) {
 131		pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
 132	} else {
 133		irq_iommu->iommu = iommu;
 134		irq_iommu->irte_index =  index;
 135		irq_iommu->sub_handle = 0;
 136		irq_iommu->irte_mask = mask;
 137	}
 138	raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 139
 140	return index;
 141}
 142
 143static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 144{
 145	struct qi_desc desc;
 146
 147	desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 148		   | QI_IEC_SELECTIVE;
 149	desc.qw1 = 0;
 150	desc.qw2 = 0;
 151	desc.qw3 = 0;
 152
 153	return qi_submit_sync(iommu, &desc, 1, 0);
 154}
 155
 156static int modify_irte(struct irq_2_iommu *irq_iommu,
 157		       struct irte *irte_modified)
 158{
 159	struct intel_iommu *iommu;
 160	unsigned long flags;
 161	struct irte *irte;
 162	int rc, index;
 163
 164	if (!irq_iommu)
 165		return -1;
 166
 167	raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 168
 169	iommu = irq_iommu->iommu;
 170
 171	index = irq_iommu->irte_index + irq_iommu->sub_handle;
 172	irte = &iommu->ir_table->base[index];
 173
 174	if ((irte->pst == 1) || (irte_modified->pst == 1)) {
 175		/*
 176		 * We use cmpxchg16 to atomically update the 128-bit IRTE,
 177		 * and it cannot be updated by the hardware or other processors
 178		 * behind us, so the return value of cmpxchg16 should be the
 179		 * same as the old value.
 180		 */
 181		u128 old = irte->irte;
 182		WARN_ON(!try_cmpxchg128(&irte->irte, &old, irte_modified->irte));
 183	} else {
 184		WRITE_ONCE(irte->low, irte_modified->low);
 185		WRITE_ONCE(irte->high, irte_modified->high);
 186	}
 187	__iommu_flush_cache(iommu, irte, sizeof(*irte));
 188
 189	rc = qi_flush_iec(iommu, index, 0);
 190
 191	raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 192
 193	return rc;
 194}
 195
 196static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id)
 197{
 198	int i;
 199
 200	for (i = 0; i < MAX_HPET_TBS; i++) {
 201		if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
 202			return ir_hpet[i].iommu;
 203	}
 204	return NULL;
 205}
 206
 207static struct intel_iommu *map_ioapic_to_iommu(int apic)
 208{
 209	int i;
 210
 211	for (i = 0; i < MAX_IO_APICS; i++) {
 212		if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
 213			return ir_ioapic[i].iommu;
 214	}
 215	return NULL;
 216}
 217
 218static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
 219{
 220	struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
 221
 222	return drhd ? drhd->iommu->ir_domain : NULL;
 223}
 224
 225static int clear_entries(struct irq_2_iommu *irq_iommu)
 226{
 227	struct irte *start, *entry, *end;
 228	struct intel_iommu *iommu;
 229	int index;
 230
 231	if (irq_iommu->sub_handle)
 232		return 0;
 233
 234	iommu = irq_iommu->iommu;
 235	index = irq_iommu->irte_index;
 236
 237	start = iommu->ir_table->base + index;
 238	end = start + (1 << irq_iommu->irte_mask);
 239
 240	for (entry = start; entry < end; entry++) {
 241		WRITE_ONCE(entry->low, 0);
 242		WRITE_ONCE(entry->high, 0);
 243	}
 244	bitmap_release_region(iommu->ir_table->bitmap, index,
 245			      irq_iommu->irte_mask);
 246
 247	return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 248}
 249
 250/*
 251 * source validation type
 252 */
 253#define SVT_NO_VERIFY		0x0  /* no verification is required */
 254#define SVT_VERIFY_SID_SQ	0x1  /* verify using SID and SQ fields */
 255#define SVT_VERIFY_BUS		0x2  /* verify bus of request-id */
 256
 257/*
 258 * source-id qualifier
 259 */
 260#define SQ_ALL_16	0x0  /* verify all 16 bits of request-id */
 261#define SQ_13_IGNORE_1	0x1  /* verify most significant 13 bits, ignore
 262			      * the third least significant bit
 263			      */
 264#define SQ_13_IGNORE_2	0x2  /* verify most significant 13 bits, ignore
 265			      * the second and third least significant bits
 266			      */
 267#define SQ_13_IGNORE_3	0x3  /* verify most significant 13 bits, ignore
 268			      * the least three significant bits
 269			      */
 270
 271/*
 272 * set SVT, SQ and SID fields of irte to verify
 273 * source ids of interrupt requests
 274 */
 275static void set_irte_sid(struct irte *irte, unsigned int svt,
 276			 unsigned int sq, unsigned int sid)
 277{
 278	if (disable_sourceid_checking)
 279		svt = SVT_NO_VERIFY;
 280	irte->svt = svt;
 281	irte->sq = sq;
 282	irte->sid = sid;
 283}
 284
 285/*
 286 * Set an IRTE to match only the bus number. Interrupt requests that reference
 287 * this IRTE must have a requester-id whose bus number is between or equal
 288 * to the start_bus and end_bus arguments.
 289 */
 290static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
 291				unsigned int end_bus)
 292{
 293	set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
 294		     (start_bus << 8) | end_bus);
 295}
 296
 297static int set_ioapic_sid(struct irte *irte, int apic)
 298{
 299	int i;
 300	u16 sid = 0;
 301
 302	if (!irte)
 303		return -1;
 304
 305	for (i = 0; i < MAX_IO_APICS; i++) {
 306		if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
 307			sid = PCI_DEVID(ir_ioapic[i].bus, ir_ioapic[i].devfn);
 308			break;
 309		}
 310	}
 311
 312	if (sid == 0) {
 313		pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
 314		return -1;
 315	}
 316
 317	set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
 318
 319	return 0;
 320}
 321
 322static int set_hpet_sid(struct irte *irte, u8 id)
 323{
 324	int i;
 325	u16 sid = 0;
 326
 327	if (!irte)
 328		return -1;
 329
 330	for (i = 0; i < MAX_HPET_TBS; i++) {
 331		if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
 332			sid = PCI_DEVID(ir_hpet[i].bus, ir_hpet[i].devfn);
 333			break;
 334		}
 335	}
 336
 337	if (sid == 0) {
 338		pr_warn("Failed to set source-id of HPET block (%d)\n", id);
 339		return -1;
 340	}
 341
 342	/*
 343	 * Should really use SQ_ALL_16. Some platforms are broken.
 344	 * While we figure out the right quirks for these broken platforms, use
 345	 * SQ_13_IGNORE_3 for now.
 346	 */
 347	set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
 348
 349	return 0;
 350}
 351
 352struct set_msi_sid_data {
 353	struct pci_dev *pdev;
 354	u16 alias;
 355	int count;
 356	int busmatch_count;
 357};
 358
 359static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
 360{
 361	struct set_msi_sid_data *data = opaque;
 362
 363	if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
 364		data->busmatch_count++;
 365
 366	data->pdev = pdev;
 367	data->alias = alias;
 368	data->count++;
 369
 370	return 0;
 371}
 372
 373static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 374{
 375	struct set_msi_sid_data data;
 376
 377	if (!irte || !dev)
 378		return -1;
 379
 380	data.count = 0;
 381	data.busmatch_count = 0;
 382	pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
 383
 384	/*
 385	 * DMA alias provides us with a PCI device and alias.  The only case
 386	 * where the it will return an alias on a different bus than the
 387	 * device is the case of a PCIe-to-PCI bridge, where the alias is for
 388	 * the subordinate bus.  In this case we can only verify the bus.
 389	 *
 390	 * If there are multiple aliases, all with the same bus number,
 391	 * then all we can do is verify the bus. This is typical in NTB
 392	 * hardware which use proxy IDs where the device will generate traffic
 393	 * from multiple devfn numbers on the same bus.
 394	 *
 395	 * If the alias device is on a different bus than our source device
 396	 * then we have a topology based alias, use it.
 397	 *
 398	 * Otherwise, the alias is for a device DMA quirk and we cannot
 399	 * assume that MSI uses the same requester ID.  Therefore use the
 400	 * original device.
 401	 */
 402	if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
 403		set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
 404				    dev->bus->number);
 405	else if (data.count >= 2 && data.busmatch_count == data.count)
 406		set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
 407	else if (data.pdev->bus->number != dev->bus->number)
 408		set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
 409	else
 410		set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 411			     pci_dev_id(dev));
 412
 413	return 0;
 414}
 415
 416static int iommu_load_old_irte(struct intel_iommu *iommu)
 417{
 418	struct irte *old_ir_table;
 419	phys_addr_t irt_phys;
 420	unsigned int i;
 421	size_t size;
 422	u64 irta;
 423
 424	/* Check whether the old ir-table has the same size as ours */
 425	irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
 426	if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
 427	     != INTR_REMAP_TABLE_REG_SIZE)
 428		return -EINVAL;
 429
 430	irt_phys = irta & VTD_PAGE_MASK;
 431	size     = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
 432
 433	/* Map the old IR table */
 434	old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
 435	if (!old_ir_table)
 436		return -ENOMEM;
 437
 438	/* Copy data over */
 439	memcpy(iommu->ir_table->base, old_ir_table, size);
 440
 441	__iommu_flush_cache(iommu, iommu->ir_table->base, size);
 442
 443	/*
 444	 * Now check the table for used entries and mark those as
 445	 * allocated in the bitmap
 446	 */
 447	for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
 448		if (iommu->ir_table->base[i].present)
 449			bitmap_set(iommu->ir_table->bitmap, i, 1);
 450	}
 451
 452	memunmap(old_ir_table);
 453
 454	return 0;
 455}
 456
 457
 458static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
 459{
 460	unsigned long flags;
 461	u64 addr;
 462	u32 sts;
 463
 464	addr = virt_to_phys((void *)iommu->ir_table->base);
 465
 466	raw_spin_lock_irqsave(&iommu->register_lock, flags);
 467
 468	dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 469		    (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 470
 471	/* Set interrupt-remapping table pointer */
 472	writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
 473
 474	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 475		      readl, (sts & DMA_GSTS_IRTPS), sts);
 476	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 477
 478	/*
 479	 * Global invalidation of interrupt entry cache to make sure the
 480	 * hardware uses the new irq remapping table.
 481	 */
 482	if (!cap_esirtps(iommu->cap))
 483		qi_global_iec(iommu);
 484}
 485
 486static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
 487{
 488	unsigned long flags;
 489	u32 sts;
 490
 491	raw_spin_lock_irqsave(&iommu->register_lock, flags);
 492
 493	/* Enable interrupt-remapping */
 494	iommu->gcmd |= DMA_GCMD_IRE;
 495	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 496	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 497		      readl, (sts & DMA_GSTS_IRES), sts);
 498
 499	/* Block compatibility-format MSIs */
 500	if (sts & DMA_GSTS_CFIS) {
 501		iommu->gcmd &= ~DMA_GCMD_CFI;
 502		writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 503		IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 504			      readl, !(sts & DMA_GSTS_CFIS), sts);
 505	}
 506
 507	/*
 508	 * With CFI clear in the Global Command register, we should be
 509	 * protected from dangerous (i.e. compatibility) interrupts
 510	 * regardless of x2apic status.  Check just to be sure.
 511	 */
 512	if (sts & DMA_GSTS_CFIS)
 513		WARN(1, KERN_WARNING
 514			"Compatibility-format IRQs enabled despite intr remapping;\n"
 515			"you are vulnerable to IRQ injection.\n");
 516
 517	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 518}
 519
 520static int intel_setup_irq_remapping(struct intel_iommu *iommu)
 521{
 522	struct irq_domain_info info = {
 523		.ops		= &intel_ir_domain_ops,
 524		.parent		= arch_get_ir_parent_domain(),
 525		.domain_flags	= IRQ_DOMAIN_FLAG_ISOLATED_MSI,
 526		.size		= INTR_REMAP_TABLE_ENTRIES,
 527		.host_data	= iommu,
 528	};
 529	struct ir_table *ir_table;
 530	unsigned long *bitmap;
 531	void *ir_table_base;
 532
 533	if (iommu->ir_table)
 534		return 0;
 535
 536	ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
 537	if (!ir_table)
 538		return -ENOMEM;
 539
 540	/* 1MB - maximum possible interrupt remapping table size */
 541	ir_table_base =
 542		iommu_alloc_pages_node_sz(iommu->node, GFP_KERNEL, SZ_1M);
 543	if (!ir_table_base) {
 544		pr_err("IR%d: failed to allocate 1M of pages\n", iommu->seq_id);
 545		goto out_free_table;
 546	}
 547
 548	bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_KERNEL);
 549	if (bitmap == NULL) {
 550		pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
 551		goto out_free_pages;
 552	}
 553
 554	info.fwnode = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
 555	if (!info.fwnode)
 556		goto out_free_bitmap;
 557
 558	iommu->ir_domain = msi_create_parent_irq_domain(&info, &dmar_msi_parent_ops);
 559	if (!iommu->ir_domain) {
 560		pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
 561		goto out_free_fwnode;
 562	}
 563
 564	ir_table->base = ir_table_base;
 565	ir_table->bitmap = bitmap;
 566	iommu->ir_table = ir_table;
 567
 568	/*
 569	 * If the queued invalidation is already initialized,
 570	 * shouldn't disable it.
 571	 */
 572	if (!iommu->qi) {
 573		/*
 574		 * Clear previous faults.
 575		 */
 576		dmar_fault(-1, iommu);
 577		dmar_disable_qi(iommu);
 578
 579		if (dmar_enable_qi(iommu)) {
 580			pr_err("Failed to enable queued invalidation\n");
 581			goto out_free_ir_domain;
 582		}
 583	}
 584
 585	init_ir_status(iommu);
 586
 587	if (ir_pre_enabled(iommu)) {
 588		if (!is_kdump_kernel()) {
 589			pr_info_once("IRQ remapping was enabled on %s but we are not in kdump mode\n",
 590				     iommu->name);
 591			clear_ir_pre_enabled(iommu);
 592			iommu_disable_irq_remapping(iommu);
 593		} else if (iommu_load_old_irte(iommu))
 594			pr_err("Failed to copy IR table for %s from previous kernel\n",
 595			       iommu->name);
 596		else
 597			pr_info("Copied IR table for %s from previous kernel\n",
 598				iommu->name);
 599	}
 600
 601	iommu_set_irq_remapping(iommu, eim_mode);
 602
 603	return 0;
 604
 605out_free_ir_domain:
 606	irq_domain_remove(iommu->ir_domain);
 607	iommu->ir_domain = NULL;
 608out_free_fwnode:
 609	irq_domain_free_fwnode(info.fwnode);
 610out_free_bitmap:
 611	bitmap_free(bitmap);
 612out_free_pages:
 613	iommu_free_pages(ir_table_base);
 614out_free_table:
 615	kfree(ir_table);
 616
 617	iommu->ir_table  = NULL;
 618
 619	return -ENOMEM;
 620}
 621
 622static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
 623{
 624	struct fwnode_handle *fn;
 625
 626	if (iommu && iommu->ir_table) {
 627		if (iommu->ir_domain) {
 628			fn = iommu->ir_domain->fwnode;
 629
 630			irq_domain_remove(iommu->ir_domain);
 631			irq_domain_free_fwnode(fn);
 632			iommu->ir_domain = NULL;
 633		}
 634		iommu_free_pages(iommu->ir_table->base);
 635		bitmap_free(iommu->ir_table->bitmap);
 636		kfree(iommu->ir_table);
 637		iommu->ir_table = NULL;
 638	}
 639}
 640
 641/*
 642 * Disable Interrupt Remapping.
 643 */
 644static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
 645{
 646	unsigned long flags;
 647	u32 sts;
 648
 649	if (!ecap_ir_support(iommu->ecap))
 650		return;
 651
 652	/*
 653	 * global invalidation of interrupt entry cache before disabling
 654	 * interrupt-remapping.
 655	 */
 656	if (!cap_esirtps(iommu->cap))
 657		qi_global_iec(iommu);
 658
 659	raw_spin_lock_irqsave(&iommu->register_lock, flags);
 660
 661	sts = readl(iommu->reg + DMAR_GSTS_REG);
 662	if (!(sts & DMA_GSTS_IRES))
 663		goto end;
 664
 665	iommu->gcmd &= ~DMA_GCMD_IRE;
 666	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 667
 668	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 669		      readl, !(sts & DMA_GSTS_IRES), sts);
 670
 671end:
 672	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 673}
 674
 675static int __init dmar_x2apic_optout(void)
 676{
 677	struct acpi_table_dmar *dmar;
 678	dmar = (struct acpi_table_dmar *)dmar_tbl;
 679	if (!dmar || no_x2apic_optout)
 680		return 0;
 681	return dmar->flags & DMAR_X2APIC_OPT_OUT;
 682}
 683
 684static void __init intel_cleanup_irq_remapping(void)
 685{
 686	struct dmar_drhd_unit *drhd;
 687	struct intel_iommu *iommu;
 688
 689	for_each_iommu(iommu, drhd) {
 690		if (ecap_ir_support(iommu->ecap)) {
 691			iommu_disable_irq_remapping(iommu);
 692			intel_teardown_irq_remapping(iommu);
 693		}
 694	}
 695
 696	if (x2apic_supported())
 697		pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
 698}
 699
 700static int __init intel_prepare_irq_remapping(void)
 701{
 702	struct dmar_drhd_unit *drhd;
 703	struct intel_iommu *iommu;
 704	int eim = 0;
 705
 706	if (irq_remap_broken) {
 707		pr_warn("This system BIOS has enabled interrupt remapping\n"
 708			"on a chipset that contains an erratum making that\n"
 709			"feature unstable.  To maintain system stability\n"
 710			"interrupt remapping is being disabled.  Please\n"
 711			"contact your BIOS vendor for an update\n");
 712		add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 713		return -ENODEV;
 714	}
 715
 716	if (dmar_table_init() < 0)
 717		return -ENODEV;
 718
 719	if (!dmar_ir_support())
 720		return -ENODEV;
 721
 722	if (parse_ioapics_under_ir()) {
 723		pr_info("Not enabling interrupt remapping\n");
 724		goto error;
 725	}
 726
 727	/* First make sure all IOMMUs support IRQ remapping */
 728	for_each_iommu(iommu, drhd)
 729		if (!ecap_ir_support(iommu->ecap))
 730			goto error;
 731
 732	/* Detect remapping mode: lapic or x2apic */
 733	if (x2apic_supported()) {
 734		eim = !dmar_x2apic_optout();
 735		if (!eim) {
 736			pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
 737			pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
 738		}
 739	}
 740
 741	for_each_iommu(iommu, drhd) {
 742		if (eim && !ecap_eim_support(iommu->ecap)) {
 743			pr_info("%s does not support EIM\n", iommu->name);
 744			eim = 0;
 745		}
 746	}
 747
 748	eim_mode = eim;
 749	if (eim)
 750		pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
 751
 752	/* Do the initializations early */
 753	for_each_iommu(iommu, drhd) {
 754		if (intel_setup_irq_remapping(iommu)) {
 755			pr_err("Failed to setup irq remapping for %s\n",
 756			       iommu->name);
 757			goto error;
 758		}
 759	}
 760
 761	return 0;
 762
 763error:
 764	intel_cleanup_irq_remapping();
 765	return -ENODEV;
 766}
 767
 768/*
 769 * Set Posted-Interrupts capability.
 770 */
 771static inline void set_irq_posting_cap(void)
 772{
 773	struct dmar_drhd_unit *drhd;
 774	struct intel_iommu *iommu;
 775
 776	if (!disable_irq_post) {
 777		/*
 778		 * If IRTE is in posted format, the 'pda' field goes across the
 779		 * 64-bit boundary, we need use cmpxchg16b to atomically update
 780		 * it. We only expose posted-interrupt when X86_FEATURE_CX16
 781		 * is supported. Actually, hardware platforms supporting PI
 782		 * should have X86_FEATURE_CX16 support, this has been confirmed
 783		 * with Intel hardware guys.
 784		 */
 785		if (boot_cpu_has(X86_FEATURE_CX16))
 786			intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
 787
 788		for_each_iommu(iommu, drhd)
 789			if (!cap_pi_support(iommu->cap)) {
 790				intel_irq_remap_ops.capability &=
 791						~(1 << IRQ_POSTING_CAP);
 792				break;
 793			}
 794	}
 795}
 796
 797static int __init intel_enable_irq_remapping(void)
 798{
 799	struct dmar_drhd_unit *drhd;
 800	struct intel_iommu *iommu;
 801	bool setup = false;
 802
 803	/*
 804	 * Setup Interrupt-remapping for all the DRHD's now.
 805	 */
 806	for_each_iommu(iommu, drhd) {
 807		if (!ir_pre_enabled(iommu))
 808			iommu_enable_irq_remapping(iommu);
 809		setup = true;
 810	}
 811
 812	if (!setup)
 813		goto error;
 814
 815	irq_remapping_enabled = 1;
 816
 817	set_irq_posting_cap();
 818
 819	pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
 820
 821	return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
 822
 823error:
 824	intel_cleanup_irq_remapping();
 825	return -1;
 826}
 827
 828static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
 829				   struct intel_iommu *iommu,
 830				   struct acpi_dmar_hardware_unit *drhd)
 831{
 832	struct acpi_dmar_pci_path *path;
 833	u8 bus;
 834	int count, free = -1;
 835
 836	bus = scope->bus;
 837	path = (struct acpi_dmar_pci_path *)(scope + 1);
 838	count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 839		/ sizeof(struct acpi_dmar_pci_path);
 840
 841	while (--count > 0) {
 842		/*
 843		 * Access PCI directly due to the PCI
 844		 * subsystem isn't initialized yet.
 845		 */
 846		bus = read_pci_config_byte(bus, path->device, path->function,
 847					   PCI_SECONDARY_BUS);
 848		path++;
 849	}
 850
 851	for (count = 0; count < MAX_HPET_TBS; count++) {
 852		if (ir_hpet[count].iommu == iommu &&
 853		    ir_hpet[count].id == scope->enumeration_id)
 854			return 0;
 855		else if (ir_hpet[count].iommu == NULL && free == -1)
 856			free = count;
 857	}
 858	if (free == -1) {
 859		pr_warn("Exceeded Max HPET blocks\n");
 860		return -ENOSPC;
 861	}
 862
 863	ir_hpet[free].iommu = iommu;
 864	ir_hpet[free].id    = scope->enumeration_id;
 865	ir_hpet[free].bus   = bus;
 866	ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
 867	pr_info("HPET id %d under DRHD base 0x%Lx\n",
 868		scope->enumeration_id, drhd->address);
 869
 870	return 0;
 871}
 872
 873static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 874				     struct intel_iommu *iommu,
 875				     struct acpi_dmar_hardware_unit *drhd)
 876{
 877	struct acpi_dmar_pci_path *path;
 878	u8 bus;
 879	int count, free = -1;
 880
 881	bus = scope->bus;
 882	path = (struct acpi_dmar_pci_path *)(scope + 1);
 883	count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 884		/ sizeof(struct acpi_dmar_pci_path);
 885
 886	while (--count > 0) {
 887		/*
 888		 * Access PCI directly due to the PCI
 889		 * subsystem isn't initialized yet.
 890		 */
 891		bus = read_pci_config_byte(bus, path->device, path->function,
 892					   PCI_SECONDARY_BUS);
 893		path++;
 894	}
 895
 896	for (count = 0; count < MAX_IO_APICS; count++) {
 897		if (ir_ioapic[count].iommu == iommu &&
 898		    ir_ioapic[count].id == scope->enumeration_id)
 899			return 0;
 900		else if (ir_ioapic[count].iommu == NULL && free == -1)
 901			free = count;
 902	}
 903	if (free == -1) {
 904		pr_warn("Exceeded Max IO APICS\n");
 905		return -ENOSPC;
 906	}
 907
 908	ir_ioapic[free].bus   = bus;
 909	ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
 910	ir_ioapic[free].iommu = iommu;
 911	ir_ioapic[free].id    = scope->enumeration_id;
 912	pr_info("IOAPIC id %d under DRHD base  0x%Lx IOMMU %d\n",
 913		scope->enumeration_id, drhd->address, iommu->seq_id);
 914
 915	return 0;
 916}
 917
 918static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
 919				      struct intel_iommu *iommu)
 920{
 921	int ret = 0;
 922	struct acpi_dmar_hardware_unit *drhd;
 923	struct acpi_dmar_device_scope *scope;
 924	void *start, *end;
 925
 926	drhd = (struct acpi_dmar_hardware_unit *)header;
 927	start = (void *)(drhd + 1);
 928	end = ((void *)drhd) + header->length;
 929
 930	while (start < end && ret == 0) {
 931		scope = start;
 932		if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
 933			ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
 934		else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
 935			ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
 936		start += scope->length;
 937	}
 938
 939	return ret;
 940}
 941
 942static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
 943{
 944	int i;
 945
 946	for (i = 0; i < MAX_HPET_TBS; i++)
 947		if (ir_hpet[i].iommu == iommu)
 948			ir_hpet[i].iommu = NULL;
 949
 950	for (i = 0; i < MAX_IO_APICS; i++)
 951		if (ir_ioapic[i].iommu == iommu)
 952			ir_ioapic[i].iommu = NULL;
 953}
 954
 955/*
 956 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 957 * hardware unit.
 958 */
 959static int __init parse_ioapics_under_ir(void)
 960{
 961	struct dmar_drhd_unit *drhd;
 962	struct intel_iommu *iommu;
 963	bool ir_supported = false;
 964	int ioapic_idx;
 965
 966	for_each_iommu(iommu, drhd) {
 967		int ret;
 968
 969		if (!ecap_ir_support(iommu->ecap))
 970			continue;
 971
 972		ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
 973		if (ret)
 974			return ret;
 975
 976		ir_supported = true;
 977	}
 978
 979	if (!ir_supported)
 980		return -ENODEV;
 981
 982	for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
 983		int ioapic_id = mpc_ioapic_id(ioapic_idx);
 984		if (!map_ioapic_to_iommu(ioapic_id)) {
 985			pr_err(FW_BUG "ioapic %d has no mapping iommu, "
 986			       "interrupt remapping will be disabled\n",
 987			       ioapic_id);
 988			return -1;
 989		}
 990	}
 991
 992	return 0;
 993}
 994
 995static int __init ir_dev_scope_init(void)
 996{
 997	int ret;
 998
 999	if (!irq_remapping_enabled)
1000		return 0;
1001
1002	down_write(&dmar_global_lock);
1003	ret = dmar_dev_scope_init();
1004	up_write(&dmar_global_lock);
1005
1006	return ret;
1007}
1008rootfs_initcall(ir_dev_scope_init);
1009
1010static void disable_irq_remapping(void)
1011{
1012	struct dmar_drhd_unit *drhd;
1013	struct intel_iommu *iommu = NULL;
1014
1015	/*
1016	 * Disable Interrupt-remapping for all the DRHD's now.
1017	 */
1018	for_each_iommu(iommu, drhd) {
1019		if (!ecap_ir_support(iommu->ecap))
1020			continue;
1021
1022		iommu_disable_irq_remapping(iommu);
1023	}
1024
1025	/*
1026	 * Clear Posted-Interrupts capability.
1027	 */
1028	if (!disable_irq_post)
1029		intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1030}
1031
1032static int reenable_irq_remapping(int eim)
1033{
1034	struct dmar_drhd_unit *drhd;
1035	bool setup = false;
1036	struct intel_iommu *iommu = NULL;
1037
1038	for_each_iommu(iommu, drhd)
1039		if (iommu->qi)
1040			dmar_reenable_qi(iommu);
1041
1042	/*
1043	 * Setup Interrupt-remapping for all the DRHD's now.
1044	 */
1045	for_each_iommu(iommu, drhd) {
1046		if (!ecap_ir_support(iommu->ecap))
1047			continue;
1048
1049		/* Set up interrupt remapping for iommu.*/
1050		iommu_set_irq_remapping(iommu, eim);
1051		iommu_enable_irq_remapping(iommu);
1052		setup = true;
1053	}
1054
1055	if (!setup)
1056		goto error;
1057
1058	set_irq_posting_cap();
1059
1060	return 0;
1061
1062error:
1063	/*
1064	 * handle error condition gracefully here!
1065	 */
1066	return -1;
1067}
1068
1069/*
1070 * Store the MSI remapping domain pointer in the device if enabled.
1071 *
1072 * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1073 * remapping is disabled. Only update the pointer if the device is not
1074 * already handled by a non default PCI/MSI interrupt domain. This protects
1075 * e.g. VMD devices.
1076 */
1077void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1078{
1079	if (!irq_remapping_enabled || !pci_dev_has_default_msi_parent_domain(info->dev))
1080		return;
1081
1082	dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1083}
1084
1085static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1086{
1087	memset(irte, 0, sizeof(*irte));
1088
1089	irte->present = 1;
1090	irte->dst_mode = apic->dest_mode_logical;
1091	/*
1092	 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1093	 * actual level or edge trigger will be setup in the IO-APIC
1094	 * RTE. This will help simplify level triggered irq migration.
1095	 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1096	 * irq migration in the presence of interrupt-remapping.
1097	*/
1098	irte->trigger_mode = 0;
1099	irte->dlvry_mode = APIC_DELIVERY_MODE_FIXED;
1100	irte->vector = vector;
1101	irte->dest_id = IRTE_DEST(dest);
1102	irte->redir_hint = 1;
1103}
1104
1105static void prepare_irte_posted(struct irte *irte)
1106{
1107	memset(irte, 0, sizeof(*irte));
1108
1109	irte->present = 1;
1110	irte->p_pst = 1;
1111}
1112
1113struct irq_remap_ops intel_irq_remap_ops = {
1114	.prepare		= intel_prepare_irq_remapping,
1115	.enable			= intel_enable_irq_remapping,
1116	.disable		= disable_irq_remapping,
1117	.reenable		= reenable_irq_remapping,
1118	.enable_faulting	= enable_drhd_fault_handling,
1119};
1120
1121#ifdef CONFIG_X86_POSTED_MSI
1122
1123static phys_addr_t get_pi_desc_addr(struct irq_data *irqd)
1124{
1125	int cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
1126
1127	if (WARN_ON(cpu >= nr_cpu_ids))
1128		return 0;
1129
1130	return __pa(per_cpu_ptr(&posted_msi_pi_desc, cpu));
1131}
1132
1133static void intel_ir_reconfigure_irte_posted(struct irq_data *irqd)
1134{
1135	struct intel_ir_data *ir_data = irqd->chip_data;
1136	struct irte *irte = &ir_data->irte_entry;
1137	struct irte irte_pi;
1138	u64 pid_addr;
1139
1140	pid_addr = get_pi_desc_addr(irqd);
1141
1142	if (!pid_addr) {
1143		pr_warn("Failed to setup IRQ %d for posted mode", irqd->irq);
1144		return;
1145	}
1146
1147	memset(&irte_pi, 0, sizeof(irte_pi));
1148
1149	/* The shared IRTE already be set up as posted during alloc_irte */
1150	dmar_copy_shared_irte(&irte_pi, irte);
1151
1152	irte_pi.pda_l = (pid_addr >> (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1153	irte_pi.pda_h = (pid_addr >> 32) & ~(-1UL << PDA_HIGH_BIT);
1154
1155	modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1156}
1157
1158#else
1159static inline void intel_ir_reconfigure_irte_posted(struct irq_data *irqd) {}
1160#endif
1161
1162static void __intel_ir_reconfigure_irte(struct irq_data *irqd, bool force_host)
1163{
1164	struct intel_ir_data *ir_data = irqd->chip_data;
1165
1166	/*
1167	 * Don't modify IRTEs for IRQs that are being posted to vCPUs if the
1168	 * host CPU affinity changes.
1169	 */
1170	if (ir_data->irq_2_iommu.posted_vcpu && !force_host)
1171		return;
1172
1173	ir_data->irq_2_iommu.posted_vcpu = false;
1174
1175	if (ir_data->irq_2_iommu.posted_msi)
1176		intel_ir_reconfigure_irte_posted(irqd);
1177	else
1178		modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1179}
1180
1181static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force_host)
1182{
1183	struct intel_ir_data *ir_data = irqd->chip_data;
1184	struct irte *irte = &ir_data->irte_entry;
1185	struct irq_cfg *cfg = irqd_cfg(irqd);
1186
1187	/*
1188	 * Atomically updates the IRTE with the new destination, vector
1189	 * and flushes the interrupt entry cache.
1190	 */
1191	irte->vector = cfg->vector;
1192	irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1193
1194	__intel_ir_reconfigure_irte(irqd, force_host);
1195}
1196
1197/*
1198 * Migrate the IO-APIC irq in the presence of intr-remapping.
1199 *
1200 * For both level and edge triggered, irq migration is a simple atomic
1201 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1202 *
1203 * For level triggered, we eliminate the io-apic RTE modification (with the
1204 * updated vector information), by using a virtual vector (io-apic pin number).
1205 * Real vector that is used for interrupting cpu will be coming from
1206 * the interrupt-remapping table entry.
1207 *
1208 * As the migration is a simple atomic update of IRTE, the same mechanism
1209 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1210 */
1211static int
1212intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1213		      bool force)
1214{
1215	struct irq_data *parent = data->parent_data;
1216	struct irq_cfg *cfg = irqd_cfg(data);
1217	int ret;
1218
1219	ret = parent->chip->irq_set_affinity(parent, mask, force);
1220	if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1221		return ret;
1222
1223	intel_ir_reconfigure_irte(data, false);
1224	/*
1225	 * After this point, all the interrupts will start arriving
1226	 * at the new destination. So, time to cleanup the previous
1227	 * vector allocation.
1228	 */
1229	vector_schedule_cleanup(cfg);
1230
1231	return IRQ_SET_MASK_OK_DONE;
1232}
1233
1234static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1235				     struct msi_msg *msg)
1236{
1237	struct intel_ir_data *ir_data = irq_data->chip_data;
1238
1239	*msg = ir_data->msi_entry;
1240}
1241
1242static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1243{
1244	struct intel_ir_data *ir_data = data->chip_data;
1245	struct intel_iommu_pi_data *pi_data = info;
1246
1247	/* stop posting interrupts, back to the default mode */
1248	if (!pi_data) {
1249		__intel_ir_reconfigure_irte(data, true);
1250	} else {
1251		struct irte irte_pi;
1252
1253		/*
1254		 * We are not caching the posted interrupt entry. We
1255		 * copy the data from the remapped entry and modify
1256		 * the fields which are relevant for posted mode. The
1257		 * cached remapped entry is used for switching back to
1258		 * remapped mode.
1259		 */
1260		memset(&irte_pi, 0, sizeof(irte_pi));
1261		dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1262
1263		/* Update the posted mode fields */
1264		irte_pi.p_pst = 1;
1265		irte_pi.p_urgent = 0;
1266		irte_pi.p_vector = pi_data->vector;
1267		irte_pi.pda_l = (pi_data->pi_desc_addr >>
1268				(32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1269		irte_pi.pda_h = (pi_data->pi_desc_addr >> 32) &
1270				~(-1UL << PDA_HIGH_BIT);
1271
1272		ir_data->irq_2_iommu.posted_vcpu = true;
1273		modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1274	}
1275
1276	return 0;
1277}
1278
1279static struct irq_chip intel_ir_chip = {
1280	.name			= "INTEL-IR",
1281	.irq_ack		= apic_ack_irq,
1282	.irq_set_affinity	= intel_ir_set_affinity,
1283	.irq_compose_msi_msg	= intel_ir_compose_msi_msg,
1284	.irq_set_vcpu_affinity	= intel_ir_set_vcpu_affinity,
1285};
1286
1287/*
1288 * With posted MSIs, the MSI vectors are multiplexed into a single notification
1289 * vector, and only the notification vector is sent to the APIC IRR.  Device
1290 * MSIs are then dispatched in a demux loop that harvests the MSIs from the
1291 * CPU's Posted Interrupt Request bitmap.  I.e. Posted MSIs never get sent to
1292 * the APIC IRR, and thus do not need an EOI.  The notification handler instead
1293 * performs a single EOI after processing the PIR.
1294 *
1295 * Note!  Pending SMP/CPU affinity changes, which are per MSI, must still be
1296 * honored, only the APIC EOI is omitted.
1297 *
1298 * For the example below, 3 MSIs are coalesced into one CPU notification. Only
1299 * one apic_eoi() is needed, but each MSI needs to process pending changes to
1300 * its CPU affinity.
1301 *
1302 * __sysvec_posted_msi_notification()
1303 *	irq_enter();
1304 *		handle_edge_irq()
1305 *			irq_chip_ack_parent()
1306 *				intel_ack_posted_msi_irq(); // No EOI
1307 *			handle_irq_event()
1308 *				driver_handler()
1309 *		handle_edge_irq()
1310 *			irq_chip_ack_parent()
1311 *				intel_ack_posted_msi_irq(); // No EOI
1312 *			handle_irq_event()
1313 *				driver_handler()
1314 *		handle_edge_irq()
1315 *			irq_chip_ack_parent()
1316 *				intel_ack_posted_msi_irq(); // No EOI
1317 *			handle_irq_event()
1318 *				driver_handler()
1319 *	apic_eoi()
1320 *	irq_exit()
1321 *
1322 */
1323static struct irq_chip intel_ir_chip_post_msi = {
1324	.name			= "INTEL-IR-POST",
1325	.irq_ack		= intel_ack_posted_msi_irq,
1326	.irq_set_affinity	= intel_ir_set_affinity,
1327	.irq_compose_msi_msg	= intel_ir_compose_msi_msg,
1328	.irq_set_vcpu_affinity	= intel_ir_set_vcpu_affinity,
1329};
1330
1331static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1332{
1333	memset(msg, 0, sizeof(*msg));
1334
1335	msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1336	msg->arch_addr_lo.dmar_subhandle_valid = true;
1337	msg->arch_addr_lo.dmar_format = true;
1338	msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1339	msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1340
1341	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1342
1343	msg->arch_data.dmar_subhandle = subhandle;
1344}
1345
1346static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1347					     struct irq_cfg *irq_cfg,
1348					     struct irq_alloc_info *info,
1349					     int index, int sub_handle)
1350{
1351	struct irte *irte = &data->irte_entry;
1352
1353	prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1354
1355	switch (info->type) {
1356	case X86_IRQ_ALLOC_TYPE_IOAPIC:
1357		/* Set source-id of interrupt request */
1358		set_ioapic_sid(irte, info->devid);
1359		apic_pr_verbose("IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1360				info->devid, irte->present, irte->fpd, irte->dst_mode,
1361				irte->redir_hint, irte->trigger_mode, irte->dlvry_mode,
1362				irte->avail, irte->vector, irte->dest_id, irte->sid,
1363				irte->sq, irte->svt);
1364		sub_handle = info->ioapic.pin;
1365		break;
1366	case X86_IRQ_ALLOC_TYPE_HPET:
1367		set_hpet_sid(irte, info->devid);
1368		break;
1369	case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1370	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1371		if (posted_msi_supported()) {
1372			prepare_irte_posted(irte);
1373			data->irq_2_iommu.posted_msi = 1;
1374		}
1375
1376		set_msi_sid(irte,
1377			    pci_real_dma_dev(msi_desc_to_pci_dev(info->desc)));
1378		break;
1379	default:
1380		BUG_ON(1);
1381		break;
1382	}
1383	fill_msi_msg(&data->msi_entry, index, sub_handle);
1384}
1385
1386static void intel_free_irq_resources(struct irq_domain *domain,
1387				     unsigned int virq, unsigned int nr_irqs)
1388{
1389	struct irq_data *irq_data;
1390	struct intel_ir_data *data;
1391	struct irq_2_iommu *irq_iommu;
1392	unsigned long flags;
1393	int i;
1394	for (i = 0; i < nr_irqs; i++) {
1395		irq_data = irq_domain_get_irq_data(domain, virq  + i);
1396		if (irq_data && irq_data->chip_data) {
1397			data = irq_data->chip_data;
1398			irq_iommu = &data->irq_2_iommu;
1399			raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1400			clear_entries(irq_iommu);
1401			raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1402			irq_domain_reset_irq_data(irq_data);
1403			kfree(data);
1404		}
1405	}
1406}
1407
1408static int intel_irq_remapping_alloc(struct irq_domain *domain,
1409				     unsigned int virq, unsigned int nr_irqs,
1410				     void *arg)
1411{
1412	struct intel_iommu *iommu = domain->host_data;
1413	struct irq_alloc_info *info = arg;
1414	struct intel_ir_data *data, *ird;
1415	struct irq_data *irq_data;
1416	struct irq_cfg *irq_cfg;
1417	int i, ret, index;
1418
1419	if (!info || !iommu)
1420		return -EINVAL;
1421	if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI)
1422		return -EINVAL;
1423
1424	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1425	if (ret < 0)
1426		return ret;
1427
1428	ret = -ENOMEM;
1429	data = kzalloc(sizeof(*data), GFP_KERNEL);
1430	if (!data)
1431		goto out_free_parent;
1432
1433	index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1434	if (index < 0) {
1435		pr_warn("Failed to allocate IRTE\n");
1436		kfree(data);
1437		goto out_free_parent;
1438	}
1439
1440	for (i = 0; i < nr_irqs; i++) {
1441		irq_data = irq_domain_get_irq_data(domain, virq + i);
1442		irq_cfg = irqd_cfg(irq_data);
1443		if (!irq_data || !irq_cfg) {
1444			if (!i)
1445				kfree(data);
1446			ret = -EINVAL;
1447			goto out_free_data;
1448		}
1449
1450		if (i > 0) {
1451			ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1452			if (!ird)
1453				goto out_free_data;
1454			/* Initialize the common data */
1455			ird->irq_2_iommu = data->irq_2_iommu;
1456			ird->irq_2_iommu.sub_handle = i;
1457		} else {
1458			ird = data;
1459		}
1460
1461		irq_data->hwirq = (index << 16) + i;
1462		irq_data->chip_data = ird;
1463		if (posted_msi_supported() &&
1464		    ((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||
1465		     (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))
1466			irq_data->chip = &intel_ir_chip_post_msi;
1467		else
1468			irq_data->chip = &intel_ir_chip;
1469		intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1470	}
1471	return 0;
1472
1473out_free_data:
1474	intel_free_irq_resources(domain, virq, i);
1475out_free_parent:
1476	irq_domain_free_irqs_common(domain, virq, nr_irqs);
1477	return ret;
1478}
1479
1480static void intel_irq_remapping_free(struct irq_domain *domain,
1481				     unsigned int virq, unsigned int nr_irqs)
1482{
1483	intel_free_irq_resources(domain, virq, nr_irqs);
1484	irq_domain_free_irqs_common(domain, virq, nr_irqs);
1485}
1486
1487static int intel_irq_remapping_activate(struct irq_domain *domain,
1488					struct irq_data *irq_data, bool reserve)
1489{
1490	intel_ir_reconfigure_irte(irq_data, true);
1491	return 0;
1492}
1493
1494static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1495					   struct irq_data *irq_data)
1496{
1497	struct intel_ir_data *data = irq_data->chip_data;
1498	struct irte entry;
1499
1500	WARN_ON_ONCE(data->irq_2_iommu.posted_vcpu);
1501	data->irq_2_iommu.posted_vcpu = false;
1502
1503	memset(&entry, 0, sizeof(entry));
1504	modify_irte(&data->irq_2_iommu, &entry);
1505}
1506
1507static int intel_irq_remapping_select(struct irq_domain *d,
1508				      struct irq_fwspec *fwspec,
1509				      enum irq_domain_bus_token bus_token)
1510{
1511	struct intel_iommu *iommu = NULL;
1512
1513	if (x86_fwspec_is_ioapic(fwspec))
1514		iommu = map_ioapic_to_iommu(fwspec->param[0]);
1515	else if (x86_fwspec_is_hpet(fwspec))
1516		iommu = map_hpet_to_iommu(fwspec->param[0]);
1517
1518	return iommu && d == iommu->ir_domain;
1519}
1520
1521static const struct irq_domain_ops intel_ir_domain_ops = {
1522	.select = intel_irq_remapping_select,
1523	.alloc = intel_irq_remapping_alloc,
1524	.free = intel_irq_remapping_free,
1525	.activate = intel_irq_remapping_activate,
1526	.deactivate = intel_irq_remapping_deactivate,
1527};
1528
1529static const struct msi_parent_ops dmar_msi_parent_ops = {
1530	.supported_flags	= X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI,
1531	.bus_select_token	= DOMAIN_BUS_DMAR,
1532	.bus_select_mask	= MATCH_PCI_MSI,
1533	.prefix			= "IR-",
1534	.init_dev_msi_info	= msi_parent_init_dev_msi_info,
1535};
1536
1537/*
1538 * Support of Interrupt Remapping Unit Hotplug
1539 */
1540static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1541{
1542	int ret;
1543	int eim = x2apic_enabled();
1544
1545	if (eim && !ecap_eim_support(iommu->ecap)) {
1546		pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1547			iommu->reg_phys, iommu->ecap);
1548		return -ENODEV;
1549	}
1550
1551	if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1552		pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1553			iommu->reg_phys);
1554		return -ENODEV;
1555	}
1556
1557	/* TODO: check all IOAPICs are covered by IOMMU */
1558
1559	/* Setup Interrupt-remapping now. */
1560	ret = intel_setup_irq_remapping(iommu);
1561	if (ret) {
1562		pr_err("Failed to setup irq remapping for %s\n",
1563		       iommu->name);
1564		intel_teardown_irq_remapping(iommu);
1565		ir_remove_ioapic_hpet_scope(iommu);
1566	} else {
1567		iommu_enable_irq_remapping(iommu);
1568	}
1569
1570	return ret;
1571}
1572
1573int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1574{
1575	int ret = 0;
1576	struct intel_iommu *iommu = dmaru->iommu;
1577
1578	if (!irq_remapping_enabled)
1579		return 0;
1580	if (iommu == NULL)
1581		return -EINVAL;
1582	if (!ecap_ir_support(iommu->ecap))
1583		return 0;
1584	if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1585	    !cap_pi_support(iommu->cap))
1586		return -EBUSY;
1587
1588	if (insert) {
1589		if (!iommu->ir_table)
1590			ret = dmar_ir_add(dmaru, iommu);
1591	} else {
1592		if (iommu->ir_table) {
1593			if (!bitmap_empty(iommu->ir_table->bitmap,
1594					  INTR_REMAP_TABLE_ENTRIES)) {
1595				ret = -EBUSY;
1596			} else {
1597				iommu_disable_irq_remapping(iommu);
1598				intel_teardown_irq_remapping(iommu);
1599				ir_remove_ioapic_hpet_scope(iommu);
1600			}
1601		}
1602	}
1603
1604	return ret;
1605}