debugfs.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright © 2018 Intel Corporation.
  4 *
  5 * Authors: Gayatri Kammela <gayatri.kammela@intel.com>
  6 *	    Sohil Mehta <sohil.mehta@intel.com>
  7 *	    Jacob Pan <jacob.jun.pan@linux.intel.com>
  8 *	    Lu Baolu <baolu.lu@linux.intel.com>
  9 */
 10
 11#include <linux/debugfs.h>
 12#include <linux/dmar.h>
 13#include <linux/pci.h>
 14
 15#include <asm/irq_remapping.h>
 16
 17#include "iommu.h"
 18#include "pasid.h"
 19#include "perf.h"
 20
 21struct tbl_walk {
 22	u16 bus;
 23	u16 devfn;
 24	u32 pasid;
 25	struct root_entry *rt_entry;
 26	struct context_entry *ctx_entry;
 27	struct pasid_entry *pasid_tbl_entry;
 28};
 29
 30struct iommu_regset {
 31	int offset;
 32	const char *regs;
 33};
 34
 35#define DEBUG_BUFFER_SIZE	1024
 36static char debug_buf[DEBUG_BUFFER_SIZE];
 37
 38#define IOMMU_REGSET_ENTRY(_reg_)					\
 39	{ DMAR_##_reg_##_REG, __stringify(_reg_) }
 40
 41static const struct iommu_regset iommu_regs_32[] = {
 42	IOMMU_REGSET_ENTRY(VER),
 43	IOMMU_REGSET_ENTRY(GCMD),
 44	IOMMU_REGSET_ENTRY(GSTS),
 45	IOMMU_REGSET_ENTRY(FSTS),
 46	IOMMU_REGSET_ENTRY(FECTL),
 47	IOMMU_REGSET_ENTRY(FEDATA),
 48	IOMMU_REGSET_ENTRY(FEADDR),
 49	IOMMU_REGSET_ENTRY(FEUADDR),
 50	IOMMU_REGSET_ENTRY(PMEN),
 51	IOMMU_REGSET_ENTRY(PLMBASE),
 52	IOMMU_REGSET_ENTRY(PLMLIMIT),
 53	IOMMU_REGSET_ENTRY(ICS),
 54	IOMMU_REGSET_ENTRY(PRS),
 55	IOMMU_REGSET_ENTRY(PECTL),
 56	IOMMU_REGSET_ENTRY(PEDATA),
 57	IOMMU_REGSET_ENTRY(PEADDR),
 58	IOMMU_REGSET_ENTRY(PEUADDR),
 59};
 60
 61static const struct iommu_regset iommu_regs_64[] = {
 62	IOMMU_REGSET_ENTRY(CAP),
 63	IOMMU_REGSET_ENTRY(ECAP),
 64	IOMMU_REGSET_ENTRY(RTADDR),
 65	IOMMU_REGSET_ENTRY(PHMBASE),
 66	IOMMU_REGSET_ENTRY(PHMLIMIT),
 67	IOMMU_REGSET_ENTRY(IQH),
 68	IOMMU_REGSET_ENTRY(IQT),
 69	IOMMU_REGSET_ENTRY(IQA),
 70	IOMMU_REGSET_ENTRY(IRTA),
 71	IOMMU_REGSET_ENTRY(PQH),
 72	IOMMU_REGSET_ENTRY(PQT),
 73	IOMMU_REGSET_ENTRY(PQA),
 74	IOMMU_REGSET_ENTRY(MTRRCAP),
 75	IOMMU_REGSET_ENTRY(MTRRDEF),
 76	IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
 77	IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
 78	IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
 79	IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
 80	IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
 81	IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
 82	IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
 83	IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
 84	IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
 85	IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
 86	IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
 87	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
 88	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
 89	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
 90	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
 91	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
 92	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
 93	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
 94	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
 95	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
 96	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
 97	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
 98	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
 99	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
100	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
101	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
102	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
103	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
104	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
105	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
106	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
107};
108
109static struct dentry *intel_iommu_debug;
110
111static int iommu_regset_show(struct seq_file *m, void *unused)
112{
113	struct dmar_drhd_unit *drhd;
114	struct intel_iommu *iommu;
115	unsigned long flag;
116	int i, ret = 0;
117	u64 value;
118
119	rcu_read_lock();
120	for_each_active_iommu(iommu, drhd) {
121		if (!drhd->reg_base_addr) {
122			seq_puts(m, "IOMMU: Invalid base address\n");
123			ret = -EINVAL;
124			goto out;
125		}
126
127		seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
128			   iommu->name, drhd->reg_base_addr);
129		seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
130		/*
131		 * Publish the contents of the 64-bit hardware registers
132		 * by adding the offset to the pointer (virtual address).
133		 */
134		raw_spin_lock_irqsave(&iommu->register_lock, flag);
135		for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
136			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
137			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
138				   iommu_regs_32[i].regs, iommu_regs_32[i].offset,
139				   value);
140		}
141		for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
142			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
143			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
144				   iommu_regs_64[i].regs, iommu_regs_64[i].offset,
145				   value);
146		}
147		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
148		seq_putc(m, '\n');
149	}
150out:
151	rcu_read_unlock();
152
153	return ret;
154}
155DEFINE_SHOW_ATTRIBUTE(iommu_regset);
156
157static inline void print_tbl_walk(struct seq_file *m)
158{
159	struct tbl_walk *tbl_wlk = m->private;
160
161	seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
162		   tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
163		   PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
164		   tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
165		   tbl_wlk->ctx_entry->lo);
166
167	/*
168	 * A legacy mode DMAR doesn't support PASID, hence default it to -1
169	 * indicating that it's invalid. Also, default all PASID related fields
170	 * to 0.
171	 */
172	if (!tbl_wlk->pasid_tbl_entry)
173		seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
174			   (u64)0, (u64)0, (u64)0);
175	else
176		seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
177			   tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
178			   tbl_wlk->pasid_tbl_entry->val[1],
179			   tbl_wlk->pasid_tbl_entry->val[0]);
180}
181
182static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
183			   u16 dir_idx)
184{
185	struct tbl_walk *tbl_wlk = m->private;
186	u8 tbl_idx;
187
188	for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
189		if (pasid_pte_is_present(tbl_entry)) {
190			tbl_wlk->pasid_tbl_entry = tbl_entry;
191			tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
192			print_tbl_walk(m);
193		}
194
195		tbl_entry++;
196	}
197}
198
199static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
200			   u16 pasid_dir_size)
201{
202	struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
203	struct pasid_entry *pasid_tbl;
204	u16 dir_idx;
205
206	for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
207		pasid_tbl = get_pasid_table_from_pde(dir_entry);
208		if (pasid_tbl)
209			pasid_tbl_walk(m, pasid_tbl, dir_idx);
210
211		dir_entry++;
212	}
213}
214
215static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
216{
217	struct context_entry *context;
218	u16 devfn, pasid_dir_size;
219	u64 pasid_dir_ptr;
220
221	for (devfn = 0; devfn < 256; devfn++) {
222		struct tbl_walk tbl_wlk = {0};
223
224		/*
225		 * Scalable mode root entry points to upper scalable mode
226		 * context table and lower scalable mode context table. Each
227		 * scalable mode context table has 128 context entries where as
228		 * legacy mode context table has 256 context entries. So in
229		 * scalable mode, the context entries for former 128 devices are
230		 * in the lower scalable mode context table, while the latter
231		 * 128 devices are in the upper scalable mode context table.
232		 * In scalable mode, when devfn > 127, iommu_context_addr()
233		 * automatically refers to upper scalable mode context table and
234		 * hence the caller doesn't have to worry about differences
235		 * between scalable mode and non scalable mode.
236		 */
237		context = iommu_context_addr(iommu, bus, devfn, 0);
238		if (!context)
239			return;
240
241		if (!context_present(context))
242			continue;
243
244		tbl_wlk.bus = bus;
245		tbl_wlk.devfn = devfn;
246		tbl_wlk.rt_entry = &iommu->root_entry[bus];
247		tbl_wlk.ctx_entry = context;
248		m->private = &tbl_wlk;
249
250		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
251			pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
252			pasid_dir_size = get_pasid_dir_size(context);
253			pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
254			continue;
255		}
256
257		print_tbl_walk(m);
258	}
259}
260
261static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
262{
263	u16 bus;
264
265	spin_lock(&iommu->lock);
266	seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
267		   (u64)virt_to_phys(iommu->root_entry));
268	seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
269
270	/*
271	 * No need to check if the root entry is present or not because
272	 * iommu_context_addr() performs the same check before returning
273	 * context entry.
274	 */
275	for (bus = 0; bus < 256; bus++)
276		ctx_tbl_walk(m, iommu, bus);
277	spin_unlock(&iommu->lock);
278}
279
280static int dmar_translation_struct_show(struct seq_file *m, void *unused)
281{
282	struct dmar_drhd_unit *drhd;
283	struct intel_iommu *iommu;
284	u32 sts;
285
286	rcu_read_lock();
287	for_each_active_iommu(iommu, drhd) {
288		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
289		if (!(sts & DMA_GSTS_TES)) {
290			seq_printf(m, "DMA Remapping is not enabled on %s\n",
291				   iommu->name);
292			continue;
293		}
294		root_tbl_walk(m, iommu);
295		seq_putc(m, '\n');
296	}
297	rcu_read_unlock();
298
299	return 0;
300}
301DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
302
303static inline unsigned long level_to_directory_size(int level)
304{
305	return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
306}
307
308static inline void
309dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
310{
311	seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx",
312		   iova >> VTD_PAGE_SHIFT, path[5], path[4], path[3]);
313	if (path[2]) {
314		seq_printf(m, "\t0x%016llx", path[2]);
315		if (path[1])
316			seq_printf(m, "\t0x%016llx", path[1]);
317	}
318	seq_putc(m, '\n');
319}
320
321static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
322			       int level, unsigned long start,
323			       u64 *path)
324{
325	int i;
326
327	if (level > 5 || level < 1)
328		return;
329
330	for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
331			i++, pde++, start += level_to_directory_size(level)) {
332		if (!dma_pte_present(pde))
333			continue;
334
335		path[level] = pde->val;
336		if (dma_pte_superpage(pde) || level == 1)
337			dump_page_info(m, start, path);
338		else
339			pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
340					   level - 1, start, path);
341		path[level] = 0;
342	}
343}
344
345static int domain_translation_struct_show(struct seq_file *m,
346					  struct device_domain_info *info,
347					  ioasid_t pasid)
348{
349	bool scalable, found = false;
350	struct dmar_drhd_unit *drhd;
351	struct intel_iommu *iommu;
352	u16 devfn, bus, seg;
353
354	bus = info->bus;
355	devfn = info->devfn;
356	seg = info->segment;
357
358	rcu_read_lock();
359	for_each_active_iommu(iommu, drhd) {
360		struct context_entry *context;
361		u64 pgd, path[6] = { 0 };
362		u32 sts, agaw;
363
364		if (seg != iommu->segment)
365			continue;
366
367		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
368		if (!(sts & DMA_GSTS_TES)) {
369			seq_printf(m, "DMA Remapping is not enabled on %s\n",
370				   iommu->name);
371			continue;
372		}
373		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)
374			scalable = true;
375		else
376			scalable = false;
377
378		/*
379		 * The iommu->lock is held across the callback, which will
380		 * block calls to domain_attach/domain_detach. Hence,
381		 * the domain of the device will not change during traversal.
382		 *
383		 * Traversing page table possibly races with the iommu_unmap()
384		 * interface. This could be solved by RCU-freeing the page
385		 * table pages in the iommu_unmap() path.
386		 */
387		spin_lock(&iommu->lock);
388
389		context = iommu_context_addr(iommu, bus, devfn, 0);
390		if (!context || !context_present(context))
391			goto iommu_unlock;
392
393		if (scalable) {	/* scalable mode */
394			struct pasid_entry *pasid_tbl, *pasid_tbl_entry;
395			struct pasid_dir_entry *dir_tbl, *dir_entry;
396			u16 dir_idx, tbl_idx, pgtt;
397			u64 pasid_dir_ptr;
398
399			pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
400
401			/* Dump specified device domain mappings with PASID. */
402			dir_idx = pasid >> PASID_PDE_SHIFT;
403			tbl_idx = pasid & PASID_PTE_MASK;
404
405			dir_tbl = phys_to_virt(pasid_dir_ptr);
406			dir_entry = &dir_tbl[dir_idx];
407
408			pasid_tbl = get_pasid_table_from_pde(dir_entry);
409			if (!pasid_tbl)
410				goto iommu_unlock;
411
412			pasid_tbl_entry = &pasid_tbl[tbl_idx];
413			if (!pasid_pte_is_present(pasid_tbl_entry))
414				goto iommu_unlock;
415
416			/*
417			 * According to PASID Granular Translation Type(PGTT),
418			 * get the page table pointer.
419			 */
420			pgtt = (u16)(pasid_tbl_entry->val[0] & GENMASK_ULL(8, 6)) >> 6;
421			agaw = (u8)(pasid_tbl_entry->val[0] & GENMASK_ULL(4, 2)) >> 2;
422
423			switch (pgtt) {
424			case PASID_ENTRY_PGTT_FL_ONLY:
425				pgd = pasid_tbl_entry->val[2];
426				break;
427			case PASID_ENTRY_PGTT_SL_ONLY:
428			case PASID_ENTRY_PGTT_NESTED:
429				pgd = pasid_tbl_entry->val[0];
430				break;
431			default:
432				goto iommu_unlock;
433			}
434			pgd &= VTD_PAGE_MASK;
435		} else { /* legacy mode */
436			u8 tt = (u8)(context->lo & GENMASK_ULL(3, 2)) >> 2;
437
438			/*
439			 * According to Translation Type(TT),
440			 * get the page table pointer(SSPTPTR).
441			 */
442			switch (tt) {
443			case CONTEXT_TT_MULTI_LEVEL:
444			case CONTEXT_TT_DEV_IOTLB:
445				pgd = context->lo & VTD_PAGE_MASK;
446				agaw = context->hi & 7;
447				break;
448			default:
449				goto iommu_unlock;
450			}
451		}
452
453		seq_printf(m, "Device %04x:%02x:%02x.%x ",
454			   iommu->segment, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
455
456		if (scalable)
457			seq_printf(m, "with pasid %x @0x%llx\n", pasid, pgd);
458		else
459			seq_printf(m, "@0x%llx\n", pgd);
460
461		seq_printf(m, "%-17s\t%-18s\t%-18s\t%-18s\t%-18s\t%-s\n",
462			   "IOVA_PFN", "PML5E", "PML4E", "PDPE", "PDE", "PTE");
463		pgtable_walk_level(m, phys_to_virt(pgd), agaw + 2, 0, path);
464
465		found = true;
466iommu_unlock:
467		spin_unlock(&iommu->lock);
468		if (found)
469			break;
470	}
471	rcu_read_unlock();
472
473	return 0;
474}
475
476static int dev_domain_translation_struct_show(struct seq_file *m, void *unused)
477{
478	struct device_domain_info *info = (struct device_domain_info *)m->private;
479
480	return domain_translation_struct_show(m, info, IOMMU_NO_PASID);
481}
482DEFINE_SHOW_ATTRIBUTE(dev_domain_translation_struct);
483
484static int pasid_domain_translation_struct_show(struct seq_file *m, void *unused)
485{
486	struct dev_pasid_info *dev_pasid = (struct dev_pasid_info *)m->private;
487	struct device_domain_info *info = dev_iommu_priv_get(dev_pasid->dev);
488
489	return domain_translation_struct_show(m, info, dev_pasid->pasid);
490}
491DEFINE_SHOW_ATTRIBUTE(pasid_domain_translation_struct);
492
493static void invalidation_queue_entry_show(struct seq_file *m,
494					  struct intel_iommu *iommu)
495{
496	int index, shift = qi_shift(iommu);
497	struct qi_desc *desc;
498	int offset;
499
500	if (ecap_smts(iommu->ecap))
501		seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n");
502	else
503		seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n");
504
505	for (index = 0; index < QI_LENGTH; index++) {
506		offset = index << shift;
507		desc = iommu->qi->desc + offset;
508		if (ecap_smts(iommu->ecap))
509			seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n",
510				   index, desc->qw0, desc->qw1,
511				   desc->qw2, desc->qw3,
512				   iommu->qi->desc_status[index]);
513		else
514			seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n",
515				   index, desc->qw0, desc->qw1,
516				   iommu->qi->desc_status[index]);
517	}
518}
519
520static int invalidation_queue_show(struct seq_file *m, void *unused)
521{
522	struct dmar_drhd_unit *drhd;
523	struct intel_iommu *iommu;
524	unsigned long flags;
525	struct q_inval *qi;
526	int shift;
527
528	rcu_read_lock();
529	for_each_active_iommu(iommu, drhd) {
530		qi = iommu->qi;
531		shift = qi_shift(iommu);
532
533		if (!qi || !ecap_qis(iommu->ecap))
534			continue;
535
536		seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
537
538		raw_spin_lock_irqsave(&qi->q_lock, flags);
539		seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
540			   (u64)virt_to_phys(qi->desc),
541			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
542			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
543		invalidation_queue_entry_show(m, iommu);
544		raw_spin_unlock_irqrestore(&qi->q_lock, flags);
545		seq_putc(m, '\n');
546	}
547	rcu_read_unlock();
548
549	return 0;
550}
551DEFINE_SHOW_ATTRIBUTE(invalidation_queue);
552
553#ifdef CONFIG_IRQ_REMAP
554static void ir_tbl_remap_entry_show(struct seq_file *m,
555				    struct intel_iommu *iommu)
556{
557	struct irte *ri_entry;
558	unsigned long flags;
559	int idx;
560
561	seq_puts(m, " Entry SrcID   DstID    Vct IRTE_high\t\tIRTE_low\n");
562
563	raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
564	for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
565		ri_entry = &iommu->ir_table->base[idx];
566		if (!ri_entry->present || ri_entry->p_pst)
567			continue;
568
569		seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",
570			   idx, PCI_BUS_NUM(ri_entry->sid),
571			   PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
572			   ri_entry->dest_id, ri_entry->vector,
573			   ri_entry->high, ri_entry->low);
574	}
575	raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
576}
577
578static void ir_tbl_posted_entry_show(struct seq_file *m,
579				     struct intel_iommu *iommu)
580{
581	struct irte *pi_entry;
582	unsigned long flags;
583	int idx;
584
585	seq_puts(m, " Entry SrcID   PDA_high PDA_low  Vct IRTE_high\t\tIRTE_low\n");
586
587	raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
588	for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
589		pi_entry = &iommu->ir_table->base[idx];
590		if (!pi_entry->present || !pi_entry->p_pst)
591			continue;
592
593		seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",
594			   idx, PCI_BUS_NUM(pi_entry->sid),
595			   PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
596			   pi_entry->pda_h, pi_entry->pda_l << 6,
597			   pi_entry->vector, pi_entry->high,
598			   pi_entry->low);
599	}
600	raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
601}
602
603/*
604 * For active IOMMUs go through the Interrupt remapping
605 * table and print valid entries in a table format for
606 * Remapped and Posted Interrupts.
607 */
608static int ir_translation_struct_show(struct seq_file *m, void *unused)
609{
610	struct dmar_drhd_unit *drhd;
611	struct intel_iommu *iommu;
612	u64 irta;
613	u32 sts;
614
615	rcu_read_lock();
616	for_each_active_iommu(iommu, drhd) {
617		if (!ecap_ir_support(iommu->ecap))
618			continue;
619
620		seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
621			   iommu->name);
622
623		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
624		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
625			irta = virt_to_phys(iommu->ir_table->base);
626			seq_printf(m, " IR table address:%llx\n", irta);
627			ir_tbl_remap_entry_show(m, iommu);
628		} else {
629			seq_puts(m, "Interrupt Remapping is not enabled\n");
630		}
631		seq_putc(m, '\n');
632	}
633
634	seq_puts(m, "****\n\n");
635
636	for_each_active_iommu(iommu, drhd) {
637		if (!cap_pi_support(iommu->cap))
638			continue;
639
640		seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
641			   iommu->name);
642
643		if (iommu->ir_table) {
644			irta = virt_to_phys(iommu->ir_table->base);
645			seq_printf(m, " IR table address:%llx\n", irta);
646			ir_tbl_posted_entry_show(m, iommu);
647		} else {
648			seq_puts(m, "Interrupt Remapping is not enabled\n");
649		}
650		seq_putc(m, '\n');
651	}
652	rcu_read_unlock();
653
654	return 0;
655}
656DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
657#endif
658
659static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,
660			     struct dmar_drhd_unit *drhd)
661{
662	seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
663		   iommu->name, drhd->reg_base_addr);
664
665	dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
666	seq_printf(m, "%s\n", debug_buf);
667}
668
669static int latency_show(struct seq_file *m, void *v)
670{
671	struct dmar_drhd_unit *drhd;
672	struct intel_iommu *iommu;
673
674	rcu_read_lock();
675	for_each_active_iommu(iommu, drhd)
676		latency_show_one(m, iommu, drhd);
677	rcu_read_unlock();
678
679	return 0;
680}
681
682static int dmar_perf_latency_open(struct inode *inode, struct file *filp)
683{
684	return single_open(filp, latency_show, NULL);
685}
686
687static ssize_t dmar_perf_latency_write(struct file *filp,
688				       const char __user *ubuf,
689				       size_t cnt, loff_t *ppos)
690{
691	struct dmar_drhd_unit *drhd;
692	struct intel_iommu *iommu;
693	int counting;
694	char buf[64];
695
696	if (cnt > 63)
697		cnt = 63;
698
699	if (copy_from_user(&buf, ubuf, cnt))
700		return -EFAULT;
701
702	buf[cnt] = 0;
703
704	if (kstrtoint(buf, 0, &counting))
705		return -EINVAL;
706
707	switch (counting) {
708	case 0:
709		rcu_read_lock();
710		for_each_active_iommu(iommu, drhd) {
711			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);
712			dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);
713			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);
714		}
715		rcu_read_unlock();
716		break;
717	case 1:
718		rcu_read_lock();
719		for_each_active_iommu(iommu, drhd)
720			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);
721		rcu_read_unlock();
722		break;
723	case 2:
724		rcu_read_lock();
725		for_each_active_iommu(iommu, drhd)
726			dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);
727		rcu_read_unlock();
728		break;
729	case 3:
730		rcu_read_lock();
731		for_each_active_iommu(iommu, drhd)
732			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);
733		rcu_read_unlock();
734		break;
735	default:
736		return -EINVAL;
737	}
738
739	*ppos += cnt;
740	return cnt;
741}
742
743static const struct file_operations dmar_perf_latency_fops = {
744	.open		= dmar_perf_latency_open,
745	.write		= dmar_perf_latency_write,
746	.read		= seq_read,
747	.llseek		= seq_lseek,
748	.release	= single_release,
749};
750
751void __init intel_iommu_debugfs_init(void)
752{
753	intel_iommu_debug = debugfs_create_dir("intel", iommu_debugfs_dir);
754
755	debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
756			    &iommu_regset_fops);
757	debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
758			    NULL, &dmar_translation_struct_fops);
759	debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug,
760			    NULL, &invalidation_queue_fops);
761#ifdef CONFIG_IRQ_REMAP
762	debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
763			    NULL, &ir_translation_struct_fops);
764#endif
765	debugfs_create_file("dmar_perf_latency", 0644, intel_iommu_debug,
766			    NULL, &dmar_perf_latency_fops);
767}
768
769/*
770 * Create a debugfs directory for each device, and then create a
771 * debugfs file in this directory for users to dump the page table
772 * of the default domain. e.g.
773 * /sys/kernel/debug/iommu/intel/0000:00:01.0/domain_translation_struct
774 */
775void intel_iommu_debugfs_create_dev(struct device_domain_info *info)
776{
777	info->debugfs_dentry = debugfs_create_dir(dev_name(info->dev), intel_iommu_debug);
778
779	debugfs_create_file("domain_translation_struct", 0444, info->debugfs_dentry,
780			    info, &dev_domain_translation_struct_fops);
781}
782
783/* Remove the device debugfs directory. */
784void intel_iommu_debugfs_remove_dev(struct device_domain_info *info)
785{
786	debugfs_remove_recursive(info->debugfs_dentry);
787}
788
789/*
790 * Create a debugfs directory per pair of {device, pasid}, then create the
791 * corresponding debugfs file in this directory for users to dump its page
792 * table. e.g.
793 * /sys/kernel/debug/iommu/intel/0000:00:01.0/1/domain_translation_struct
794 *
795 * The debugfs only dumps the page tables whose mappings are created and
796 * destroyed by the iommu_map/unmap() interfaces. Check the mapping type
797 * of the domain before creating debugfs directory.
798 */
799void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid)
800{
801	struct device_domain_info *info = dev_iommu_priv_get(dev_pasid->dev);
802	char dir_name[10];
803
804	sprintf(dir_name, "%x", dev_pasid->pasid);
805	dev_pasid->debugfs_dentry = debugfs_create_dir(dir_name, info->debugfs_dentry);
806
807	debugfs_create_file("domain_translation_struct", 0444, dev_pasid->debugfs_dentry,
808			    dev_pasid, &pasid_domain_translation_struct_fops);
809}
810
811/* Remove the device pasid debugfs directory. */
812void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid)
813{
814	debugfs_remove_recursive(dev_pasid->debugfs_dentry);
815}