qcom_iommu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * IOMMU API for QCOM secure IOMMUs.  Somewhat based on arm-smmu.c
  4 *
  5 * Copyright (C) 2013 ARM Limited
  6 * Copyright (C) 2017 Red Hat
  7 */
  8
  9#include <linux/atomic.h>
 10#include <linux/bitfield.h>
 11#include <linux/clk.h>
 12#include <linux/delay.h>
 13#include <linux/dma-mapping.h>
 14#include <linux/err.h>
 15#include <linux/interrupt.h>
 16#include <linux/io.h>
 17#include <linux/io-64-nonatomic-hi-lo.h>
 18#include <linux/io-pgtable.h>
 19#include <linux/iommu.h>
 20#include <linux/iopoll.h>
 21#include <linux/kconfig.h>
 22#include <linux/init.h>
 23#include <linux/mutex.h>
 24#include <linux/of.h>
 25#include <linux/of_platform.h>
 26#include <linux/platform_device.h>
 27#include <linux/pm.h>
 28#include <linux/pm_runtime.h>
 29#include <linux/firmware/qcom/qcom_scm.h>
 30#include <linux/slab.h>
 31#include <linux/spinlock.h>
 32
 33#include "arm-smmu.h"
 34
 35#define SMMU_INTR_SEL_NS     0x2000
 36
 37enum qcom_iommu_clk {
 38	CLK_IFACE,
 39	CLK_BUS,
 40	CLK_TBU,
 41	CLK_NUM,
 42};
 43
 44struct qcom_iommu_ctx;
 45
 46struct qcom_iommu_dev {
 47	/* IOMMU core code handle */
 48	struct iommu_device	 iommu;
 49	struct device		*dev;
 50	struct clk_bulk_data clks[CLK_NUM];
 51	void __iomem		*local_base;
 52	u32			 sec_id;
 53	u8			 max_asid;
 54	struct qcom_iommu_ctx	*ctxs[];   /* indexed by asid */
 55};
 56
 57struct qcom_iommu_ctx {
 58	struct device		*dev;
 59	void __iomem		*base;
 60	bool			 secure_init;
 61	bool			 secured_ctx;
 62	u8			 asid;      /* asid and ctx bank # are 1:1 */
 63	struct iommu_domain	*domain;
 64};
 65
 66struct qcom_iommu_domain {
 67	struct io_pgtable_ops	*pgtbl_ops;
 68	spinlock_t		 pgtbl_lock;
 69	struct mutex		 init_mutex; /* Protects iommu pointer */
 70	struct iommu_domain	 domain;
 71	struct qcom_iommu_dev	*iommu;
 72	struct iommu_fwspec	*fwspec;
 73};
 74
 75static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
 76{
 77	return container_of(dom, struct qcom_iommu_domain, domain);
 78}
 79
 80static const struct iommu_ops qcom_iommu_ops;
 81
 82static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid)
 83{
 84	struct qcom_iommu_dev *qcom_iommu = d->iommu;
 85	if (!qcom_iommu)
 86		return NULL;
 87	return qcom_iommu->ctxs[asid];
 88}
 89
 90static inline void
 91iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
 92{
 93	writel_relaxed(val, ctx->base + reg);
 94}
 95
 96static inline void
 97iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
 98{
 99	writeq_relaxed(val, ctx->base + reg);
100}
101
102static inline u32
103iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
104{
105	return readl_relaxed(ctx->base + reg);
106}
107
108static inline u64
109iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
110{
111	return readq_relaxed(ctx->base + reg);
112}
113
114static void qcom_iommu_tlb_sync(void *cookie)
115{
116	struct qcom_iommu_domain *qcom_domain = cookie;
117	struct iommu_fwspec *fwspec = qcom_domain->fwspec;
118	unsigned i;
119
120	for (i = 0; i < fwspec->num_ids; i++) {
121		struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
122		unsigned int val, ret;
123
124		iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
125
126		ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
127					 (val & 0x1) == 0, 0, 5000000);
128		if (ret)
129			dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
130	}
131}
132
133static void qcom_iommu_tlb_inv_context(void *cookie)
134{
135	struct qcom_iommu_domain *qcom_domain = cookie;
136	struct iommu_fwspec *fwspec = qcom_domain->fwspec;
137	unsigned i;
138
139	for (i = 0; i < fwspec->num_ids; i++) {
140		struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
141		iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
142	}
143
144	qcom_iommu_tlb_sync(cookie);
145}
146
147static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
148					    size_t granule, bool leaf, void *cookie)
149{
150	struct qcom_iommu_domain *qcom_domain = cookie;
151	struct iommu_fwspec *fwspec = qcom_domain->fwspec;
152	unsigned i, reg;
153
154	reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
155
156	for (i = 0; i < fwspec->num_ids; i++) {
157		struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
158		size_t s = size;
159
160		iova = (iova >> 12) << 12;
161		iova |= ctx->asid;
162		do {
163			iommu_writel(ctx, reg, iova);
164			iova += granule;
165		} while (s -= granule);
166	}
167}
168
169static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size,
170				      size_t granule, void *cookie)
171{
172	qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie);
173	qcom_iommu_tlb_sync(cookie);
174}
175
176static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
177				    unsigned long iova, size_t granule,
178				    void *cookie)
179{
180	qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie);
181}
182
183static const struct iommu_flush_ops qcom_flush_ops = {
184	.tlb_flush_all	= qcom_iommu_tlb_inv_context,
185	.tlb_flush_walk = qcom_iommu_tlb_flush_walk,
186	.tlb_add_page	= qcom_iommu_tlb_add_page,
187};
188
189static irqreturn_t qcom_iommu_fault(int irq, void *dev)
190{
191	struct qcom_iommu_ctx *ctx = dev;
192	u32 fsr, fsynr;
193	u64 iova;
194
195	fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
196
197	if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
198		return IRQ_NONE;
199
200	fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
201	iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
202
203	if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
204		dev_err_ratelimited(ctx->dev,
205				    "Unhandled context fault: fsr=0x%x, "
206				    "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
207				    fsr, iova, fsynr, ctx->asid);
208	}
209
210	iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
211	iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
212
213	return IRQ_HANDLED;
214}
215
216static int qcom_iommu_init_domain(struct iommu_domain *domain,
217				  struct qcom_iommu_dev *qcom_iommu,
218				  struct device *dev)
219{
220	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
221	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
222	struct io_pgtable_ops *pgtbl_ops;
223	struct io_pgtable_cfg pgtbl_cfg;
224	int i, ret = 0;
225	u32 reg;
226
227	mutex_lock(&qcom_domain->init_mutex);
228	if (qcom_domain->iommu)
229		goto out_unlock;
230
231	pgtbl_cfg = (struct io_pgtable_cfg) {
232		.pgsize_bitmap	= domain->pgsize_bitmap,
233		.ias		= 32,
234		.oas		= 40,
235		.tlb		= &qcom_flush_ops,
236		.iommu_dev	= qcom_iommu->dev,
237	};
238
239	qcom_domain->iommu = qcom_iommu;
240	qcom_domain->fwspec = fwspec;
241
242	pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain);
243	if (!pgtbl_ops) {
244		dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
245		ret = -ENOMEM;
246		goto out_clear_iommu;
247	}
248
249	domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
250	domain->geometry.force_aperture = true;
251
252	for (i = 0; i < fwspec->num_ids; i++) {
253		struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
254
255		if (!ctx->secure_init) {
256			ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
257			if (ret) {
258				dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
259				goto out_clear_iommu;
260			}
261			ctx->secure_init = true;
262		}
263
264		/* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */
265		if (ctx->secured_ctx) {
266			ctx->domain = domain;
267			continue;
268		}
269
270		/* Disable context bank before programming */
271		iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
272
273		/* Clear context bank fault address fault status registers */
274		iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
275		iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
276
277		/* TTBRs */
278		iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
279				pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
280				FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
281		iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
282
283		/* TCR */
284		iommu_writel(ctx, ARM_SMMU_CB_TCR2,
285				arm_smmu_lpae_tcr2(&pgtbl_cfg));
286		iommu_writel(ctx, ARM_SMMU_CB_TCR,
287			     arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
288
289		/* MAIRs (stage-1 only) */
290		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
291				pgtbl_cfg.arm_lpae_s1_cfg.mair);
292		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
293				pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
294
295		/* SCTLR */
296		reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
297		      ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
298		      ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
299		      ARM_SMMU_SCTLR_CFCFG;
300
301		if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
302			reg |= ARM_SMMU_SCTLR_E;
303
304		iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
305
306		ctx->domain = domain;
307	}
308
309	mutex_unlock(&qcom_domain->init_mutex);
310
311	/* Publish page table ops for map/unmap */
312	qcom_domain->pgtbl_ops = pgtbl_ops;
313
314	return 0;
315
316out_clear_iommu:
317	qcom_domain->iommu = NULL;
318out_unlock:
319	mutex_unlock(&qcom_domain->init_mutex);
320	return ret;
321}
322
323static struct iommu_domain *qcom_iommu_domain_alloc_paging(struct device *dev)
324{
325	struct qcom_iommu_domain *qcom_domain;
326
327	/*
328	 * Allocate the domain and initialise some of its data structures.
329	 * We can't really do anything meaningful until we've added a
330	 * master.
331	 */
332	qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
333	if (!qcom_domain)
334		return NULL;
335
336	mutex_init(&qcom_domain->init_mutex);
337	spin_lock_init(&qcom_domain->pgtbl_lock);
338	qcom_domain->domain.pgsize_bitmap = SZ_4K;
339
340	return &qcom_domain->domain;
341}
342
343static void qcom_iommu_domain_free(struct iommu_domain *domain)
344{
345	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
346
347	if (qcom_domain->iommu) {
348		/*
349		 * NOTE: unmap can be called after client device is powered
350		 * off, for example, with GPUs or anything involving dma-buf.
351		 * So we cannot rely on the device_link.  Make sure the IOMMU
352		 * is on to avoid unclocked accesses in the TLB inv path:
353		 */
354		pm_runtime_get_sync(qcom_domain->iommu->dev);
355		free_io_pgtable_ops(qcom_domain->pgtbl_ops);
356		pm_runtime_put_sync(qcom_domain->iommu->dev);
357	}
358
359	kfree(qcom_domain);
360}
361
362static int qcom_iommu_attach_dev(struct iommu_domain *domain,
363				 struct device *dev, struct iommu_domain *old)
364{
365	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
366	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
367	int ret;
368
369	if (!qcom_iommu) {
370		dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
371		return -ENXIO;
372	}
373
374	/* Ensure that the domain is finalized */
375	pm_runtime_get_sync(qcom_iommu->dev);
376	ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
377	pm_runtime_put_sync(qcom_iommu->dev);
378	if (ret < 0)
379		return ret;
380
381	/*
382	 * Sanity check the domain. We don't support domains across
383	 * different IOMMUs.
384	 */
385	if (qcom_domain->iommu != qcom_iommu)
386		return -EINVAL;
387
388	return 0;
389}
390
391static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain,
392				      struct device *dev,
393				      struct iommu_domain *old)
394{
395	struct qcom_iommu_domain *qcom_domain;
396	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
397	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
398	unsigned int i;
399
400	if (old == identity_domain || !old)
401		return 0;
402
403	qcom_domain = to_qcom_iommu_domain(old);
404	if (WARN_ON(!qcom_domain->iommu))
405		return -EINVAL;
406
407	pm_runtime_get_sync(qcom_iommu->dev);
408	for (i = 0; i < fwspec->num_ids; i++) {
409		struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
410
411		/* Disable the context bank: */
412		iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
413
414		ctx->domain = NULL;
415	}
416	pm_runtime_put_sync(qcom_iommu->dev);
417	return 0;
418}
419
420static struct iommu_domain_ops qcom_iommu_identity_ops = {
421	.attach_dev = qcom_iommu_identity_attach,
422};
423
424static struct iommu_domain qcom_iommu_identity_domain = {
425	.type = IOMMU_DOMAIN_IDENTITY,
426	.ops = &qcom_iommu_identity_ops,
427};
428
429static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
430			  phys_addr_t paddr, size_t pgsize, size_t pgcount,
431			  int prot, gfp_t gfp, size_t *mapped)
432{
433	int ret;
434	unsigned long flags;
435	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
436	struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
437
438	if (!ops)
439		return -ENODEV;
440
441	spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
442	ret = ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, GFP_ATOMIC, mapped);
443	spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
444	return ret;
445}
446
447static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
448			       size_t pgsize, size_t pgcount,
449			       struct iommu_iotlb_gather *gather)
450{
451	size_t ret;
452	unsigned long flags;
453	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
454	struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
455
456	if (!ops)
457		return 0;
458
459	/* NOTE: unmap can be called after client device is powered off,
460	 * for example, with GPUs or anything involving dma-buf.  So we
461	 * cannot rely on the device_link.  Make sure the IOMMU is on to
462	 * avoid unclocked accesses in the TLB inv path:
463	 */
464	pm_runtime_get_sync(qcom_domain->iommu->dev);
465	spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
466	ret = ops->unmap_pages(ops, iova, pgsize, pgcount, gather);
467	spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
468	pm_runtime_put_sync(qcom_domain->iommu->dev);
469
470	return ret;
471}
472
473static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
474{
475	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
476	struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
477						  struct io_pgtable, ops);
478	if (!qcom_domain->pgtbl_ops)
479		return;
480
481	pm_runtime_get_sync(qcom_domain->iommu->dev);
482	qcom_iommu_tlb_sync(pgtable->cookie);
483	pm_runtime_put_sync(qcom_domain->iommu->dev);
484}
485
486static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
487				  struct iommu_iotlb_gather *gather)
488{
489	qcom_iommu_flush_iotlb_all(domain);
490}
491
492static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
493					   dma_addr_t iova)
494{
495	phys_addr_t ret;
496	unsigned long flags;
497	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
498	struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
499
500	if (!ops)
501		return 0;
502
503	spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
504	ret = ops->iova_to_phys(ops, iova);
505	spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
506
507	return ret;
508}
509
510static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)
511{
512	switch (cap) {
513	case IOMMU_CAP_CACHE_COHERENCY:
514		/*
515		 * Return true here as the SMMU can always send out coherent
516		 * requests.
517		 */
518		return true;
519	case IOMMU_CAP_NOEXEC:
520		return true;
521	default:
522		return false;
523	}
524}
525
526static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
527{
528	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
529	struct device_link *link;
530
531	if (!qcom_iommu)
532		return ERR_PTR(-ENODEV);
533
534	/*
535	 * Establish the link between iommu and master, so that the
536	 * iommu gets runtime enabled/disabled as per the master's
537	 * needs.
538	 */
539	link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
540	if (!link) {
541		dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
542			dev_name(qcom_iommu->dev), dev_name(dev));
543		return ERR_PTR(-ENODEV);
544	}
545
546	return &qcom_iommu->iommu;
547}
548
549static int qcom_iommu_of_xlate(struct device *dev,
550			       const struct of_phandle_args *args)
551{
552	struct qcom_iommu_dev *qcom_iommu;
553	struct platform_device *iommu_pdev;
554	unsigned asid = args->args[0];
555
556	if (args->args_count != 1) {
557		dev_err(dev, "incorrect number of iommu params found for %s "
558			"(found %d, expected 1)\n",
559			args->np->full_name, args->args_count);
560		return -EINVAL;
561	}
562
563	iommu_pdev = of_find_device_by_node(args->np);
564	if (WARN_ON(!iommu_pdev))
565		return -EINVAL;
566
567	qcom_iommu = platform_get_drvdata(iommu_pdev);
568
569	put_device(&iommu_pdev->dev);
570
571	/* make sure the asid specified in dt is valid, so we don't have
572	 * to sanity check this elsewhere:
573	 */
574	if (WARN_ON(asid > qcom_iommu->max_asid) ||
575	    WARN_ON(qcom_iommu->ctxs[asid] == NULL))
576		return -EINVAL;
577
578	if (!dev_iommu_priv_get(dev)) {
579		dev_iommu_priv_set(dev, qcom_iommu);
580	} else {
581		/* make sure devices iommus dt node isn't referring to
582		 * multiple different iommu devices.  Multiple context
583		 * banks are ok, but multiple devices are not:
584		 */
585		if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev)))
586			return -EINVAL;
587	}
588
589	return iommu_fwspec_add_ids(dev, &asid, 1);
590}
591
592static const struct iommu_ops qcom_iommu_ops = {
593	.identity_domain = &qcom_iommu_identity_domain,
594	.capable	= qcom_iommu_capable,
595	.domain_alloc_paging = qcom_iommu_domain_alloc_paging,
596	.probe_device	= qcom_iommu_probe_device,
597	.device_group	= generic_device_group,
598	.of_xlate	= qcom_iommu_of_xlate,
599	.default_domain_ops = &(const struct iommu_domain_ops) {
600		.attach_dev	= qcom_iommu_attach_dev,
601		.map_pages	= qcom_iommu_map,
602		.unmap_pages	= qcom_iommu_unmap,
603		.flush_iotlb_all = qcom_iommu_flush_iotlb_all,
604		.iotlb_sync	= qcom_iommu_iotlb_sync,
605		.iova_to_phys	= qcom_iommu_iova_to_phys,
606		.free		= qcom_iommu_domain_free,
607	}
608};
609
610static int qcom_iommu_sec_ptbl_init(struct device *dev)
611{
612	size_t psize = 0;
613	unsigned int spare = 0;
614	void *cpu_addr;
615	dma_addr_t paddr;
616	unsigned long attrs;
617	static bool allocated = false;
618	int ret;
619
620	if (allocated)
621		return 0;
622
623	ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
624	if (ret) {
625		dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
626			ret);
627		return ret;
628	}
629
630	dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
631
632	attrs = DMA_ATTR_NO_KERNEL_MAPPING;
633
634	cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
635	if (!cpu_addr) {
636		dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
637			psize);
638		return -ENOMEM;
639	}
640
641	ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
642	if (ret) {
643		dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
644		goto free_mem;
645	}
646
647	allocated = true;
648	return 0;
649
650free_mem:
651	dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
652	return ret;
653}
654
655static int get_asid(const struct device_node *np)
656{
657	u32 reg, val;
658	int asid;
659
660	/* read the "reg" property directly to get the relative address
661	 * of the context bank, and calculate the asid from that:
662	 */
663	if (of_property_read_u32_index(np, "reg", 0, &reg))
664		return -ENODEV;
665
666	/*
667	 * Context banks are 0x1000 apart but, in some cases, the ASID
668	 * number doesn't match to this logic and needs to be passed
669	 * from the DT configuration explicitly.
670	 */
671	if (!of_property_read_u32(np, "qcom,ctx-asid", &val))
672		asid = val;
673	else
674		asid = reg / 0x1000;
675
676	return asid;
677}
678
679static int qcom_iommu_ctx_probe(struct platform_device *pdev)
680{
681	struct qcom_iommu_ctx *ctx;
682	struct device *dev = &pdev->dev;
683	struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
684	int ret, irq;
685
686	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
687	if (!ctx)
688		return -ENOMEM;
689
690	ctx->dev = dev;
691	platform_set_drvdata(pdev, ctx);
692
693	ctx->base = devm_platform_ioremap_resource(pdev, 0);
694	if (IS_ERR(ctx->base))
695		return PTR_ERR(ctx->base);
696
697	irq = platform_get_irq(pdev, 0);
698	if (irq < 0)
699		return irq;
700
701	if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec"))
702		ctx->secured_ctx = true;
703
704	/* clear IRQs before registering fault handler, just in case the
705	 * boot-loader left us a surprise:
706	 */
707	if (!ctx->secured_ctx)
708		iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
709
710	ret = devm_request_irq(dev, irq,
711			       qcom_iommu_fault,
712			       IRQF_SHARED,
713			       "qcom-iommu-fault",
714			       ctx);
715	if (ret) {
716		dev_err(dev, "failed to request IRQ %u\n", irq);
717		return ret;
718	}
719
720	ret = get_asid(dev->of_node);
721	if (ret < 0) {
722		dev_err(dev, "missing reg property\n");
723		return ret;
724	}
725
726	ctx->asid = ret;
727
728	dev_dbg(dev, "found asid %u\n", ctx->asid);
729
730	qcom_iommu->ctxs[ctx->asid] = ctx;
731
732	return 0;
733}
734
735static void qcom_iommu_ctx_remove(struct platform_device *pdev)
736{
737	struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
738	struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
739
740	platform_set_drvdata(pdev, NULL);
741
742	qcom_iommu->ctxs[ctx->asid] = NULL;
743}
744
745static const struct of_device_id ctx_of_match[] = {
746	{ .compatible = "qcom,msm-iommu-v1-ns" },
747	{ .compatible = "qcom,msm-iommu-v1-sec" },
748	{ .compatible = "qcom,msm-iommu-v2-ns" },
749	{ .compatible = "qcom,msm-iommu-v2-sec" },
750	{ /* sentinel */ }
751};
752
753static struct platform_driver qcom_iommu_ctx_driver = {
754	.driver	= {
755		.name		= "qcom-iommu-ctx",
756		.of_match_table	= ctx_of_match,
757	},
758	.probe	= qcom_iommu_ctx_probe,
759	.remove = qcom_iommu_ctx_remove,
760};
761
762static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
763{
764	struct device_node *child;
765
766	for_each_child_of_node(qcom_iommu->dev->of_node, child) {
767		if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") ||
768		    of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) {
769			of_node_put(child);
770			return true;
771		}
772	}
773
774	return false;
775}
776
777static int qcom_iommu_device_probe(struct platform_device *pdev)
778{
779	struct device_node *child;
780	struct qcom_iommu_dev *qcom_iommu;
781	struct device *dev = &pdev->dev;
782	struct resource *res;
783	struct clk *clk;
784	int ret, max_asid = 0;
785
786	/* find the max asid (which is 1:1 to ctx bank idx), so we know how
787	 * many child ctx devices we have:
788	 */
789	for_each_child_of_node(dev->of_node, child)
790		max_asid = max(max_asid, get_asid(child));
791
792	qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid + 1),
793				  GFP_KERNEL);
794	if (!qcom_iommu)
795		return -ENOMEM;
796	qcom_iommu->max_asid = max_asid;
797	qcom_iommu->dev = dev;
798
799	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
800	if (res) {
801		qcom_iommu->local_base = devm_ioremap_resource(dev, res);
802		if (IS_ERR(qcom_iommu->local_base))
803			return PTR_ERR(qcom_iommu->local_base);
804	}
805
806	clk = devm_clk_get(dev, "iface");
807	if (IS_ERR(clk)) {
808		dev_err(dev, "failed to get iface clock\n");
809		return PTR_ERR(clk);
810	}
811	qcom_iommu->clks[CLK_IFACE].clk = clk;
812
813	clk = devm_clk_get(dev, "bus");
814	if (IS_ERR(clk)) {
815		dev_err(dev, "failed to get bus clock\n");
816		return PTR_ERR(clk);
817	}
818	qcom_iommu->clks[CLK_BUS].clk = clk;
819
820	clk = devm_clk_get_optional(dev, "tbu");
821	if (IS_ERR(clk)) {
822		dev_err(dev, "failed to get tbu clock\n");
823		return PTR_ERR(clk);
824	}
825	qcom_iommu->clks[CLK_TBU].clk = clk;
826
827	if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
828				 &qcom_iommu->sec_id)) {
829		dev_err(dev, "missing qcom,iommu-secure-id property\n");
830		return -ENODEV;
831	}
832
833	if (qcom_iommu_has_secure_context(qcom_iommu)) {
834		ret = qcom_iommu_sec_ptbl_init(dev);
835		if (ret) {
836			dev_err(dev, "cannot init secure pg table(%d)\n", ret);
837			return ret;
838		}
839	}
840
841	platform_set_drvdata(pdev, qcom_iommu);
842
843	pm_runtime_enable(dev);
844
845	/* register context bank devices, which are child nodes: */
846	ret = devm_of_platform_populate(dev);
847	if (ret) {
848		dev_err(dev, "Failed to populate iommu contexts\n");
849		goto err_pm_disable;
850	}
851
852	ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
853				     dev_name(dev));
854	if (ret) {
855		dev_err(dev, "Failed to register iommu in sysfs\n");
856		goto err_pm_disable;
857	}
858
859	ret = iommu_device_register(&qcom_iommu->iommu, &qcom_iommu_ops, dev);
860	if (ret) {
861		dev_err(dev, "Failed to register iommu\n");
862		goto err_pm_disable;
863	}
864
865	if (qcom_iommu->local_base) {
866		pm_runtime_get_sync(dev);
867		writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
868		pm_runtime_put_sync(dev);
869	}
870
871	return 0;
872
873err_pm_disable:
874	pm_runtime_disable(dev);
875	return ret;
876}
877
878static void qcom_iommu_device_remove(struct platform_device *pdev)
879{
880	struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
881
882	pm_runtime_force_suspend(&pdev->dev);
883	platform_set_drvdata(pdev, NULL);
884	iommu_device_sysfs_remove(&qcom_iommu->iommu);
885	iommu_device_unregister(&qcom_iommu->iommu);
886}
887
888static int __maybe_unused qcom_iommu_resume(struct device *dev)
889{
890	struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
891	int ret;
892
893	ret = clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks);
894	if (ret < 0)
895		return ret;
896
897	if (dev->pm_domain)
898		return qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, 0);
899
900	return ret;
901}
902
903static int __maybe_unused qcom_iommu_suspend(struct device *dev)
904{
905	struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
906
907	clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks);
908
909	return 0;
910}
911
912static const struct dev_pm_ops qcom_iommu_pm_ops = {
913	SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
914	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
915				pm_runtime_force_resume)
916};
917
918static const struct of_device_id qcom_iommu_of_match[] = {
919	{ .compatible = "qcom,msm-iommu-v1" },
920	{ .compatible = "qcom,msm-iommu-v2" },
921	{ /* sentinel */ }
922};
923
924static struct platform_driver qcom_iommu_driver = {
925	.driver	= {
926		.name		= "qcom-iommu",
927		.of_match_table	= qcom_iommu_of_match,
928		.pm		= &qcom_iommu_pm_ops,
929	},
930	.probe	= qcom_iommu_device_probe,
931	.remove = qcom_iommu_device_remove,
932};
933
934static int __init qcom_iommu_init(void)
935{
936	int ret;
937
938	ret = platform_driver_register(&qcom_iommu_ctx_driver);
939	if (ret)
940		return ret;
941
942	ret = platform_driver_register(&qcom_iommu_driver);
943	if (ret)
944		platform_driver_unregister(&qcom_iommu_ctx_driver);
945
946	return ret;
947}
948device_initcall(qcom_iommu_init);