arm-smmu-qcom.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  4 */
  5
  6#include <linux/acpi.h>
  7#include <linux/adreno-smmu-priv.h>
  8#include <linux/delay.h>
  9#include <linux/of_device.h>
 10#include <linux/firmware/qcom/qcom_scm.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm_runtime.h>
 13
 14#include "arm-smmu.h"
 15#include "arm-smmu-qcom.h"
 16
 17#define QCOM_DUMMY_VAL	-1
 18
 19/*
 20 * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
 21 * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
 22 * buffer). The remaining bits are implementation defined and vary across
 23 * SoCs.
 24 */
 25
 26#define CPRE			(1 << 1)
 27#define CMTLB			(1 << 0)
 28#define PREFETCH_SHIFT		8
 29#define PREFETCH_DEFAULT	0
 30#define PREFETCH_SHALLOW	(1 << PREFETCH_SHIFT)
 31#define PREFETCH_MODERATE	(2 << PREFETCH_SHIFT)
 32#define PREFETCH_DEEP		(3 << PREFETCH_SHIFT)
 33#define GFX_ACTLR_PRR          (1 << 5)
 34
 35static const struct of_device_id qcom_smmu_actlr_client_of_match[] = {
 36	{ .compatible = "qcom,adreno",
 37			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
 38	{ .compatible = "qcom,adreno-gmu",
 39			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
 40	{ .compatible = "qcom,adreno-smmu",
 41			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
 42	{ .compatible = "qcom,fastrpc",
 43			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
 44	{ .compatible = "qcom,sc7280-mdss",
 45			.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
 46	{ .compatible = "qcom,sc7280-venus",
 47			.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
 48	{ .compatible = "qcom,sm8550-mdss",
 49			.data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
 50	{ }
 51};
 52
 53static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 54{
 55	return container_of(smmu, struct qcom_smmu, smmu);
 56}
 57
 58static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
 59				int sync, int status)
 60{
 61	unsigned int spin_cnt, delay;
 62	u32 reg;
 63
 64	arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
 65	for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
 66		for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
 67			reg = arm_smmu_readl(smmu, page, status);
 68			if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
 69				return;
 70			cpu_relax();
 71		}
 72		udelay(delay);
 73	}
 74
 75	qcom_smmu_tlb_sync_debug(smmu);
 76}
 77
 78static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
 79		u32 reg)
 80{
 81	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
 82
 83	/*
 84	 * On the GPU device we want to process subsequent transactions after a
 85	 * fault to keep the GPU from hanging
 86	 */
 87	reg |= ARM_SMMU_SCTLR_HUPCF;
 88
 89	if (qsmmu->stall_enabled & BIT(idx))
 90		reg |= ARM_SMMU_SCTLR_CFCFG;
 91
 92	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
 93}
 94
 95static void qcom_adreno_smmu_get_fault_info(const void *cookie,
 96		struct adreno_smmu_fault_info *info)
 97{
 98	struct arm_smmu_domain *smmu_domain = (void *)cookie;
 99	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
100	struct arm_smmu_device *smmu = smmu_domain->smmu;
101
102	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
103	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
104	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
105	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
106	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
107	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
108	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
109}
110
111static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
112{
113	struct arm_smmu_domain *smmu_domain = (void *)cookie;
114	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
115	struct arm_smmu_device *smmu = smmu_domain->smmu;
116	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
117	u32 mask = BIT(cfg->cbndx);
118	bool stall_changed = !!(qsmmu->stall_enabled & mask) != enabled;
119	unsigned long flags;
120
121	if (enabled)
122		qsmmu->stall_enabled |= mask;
123	else
124		qsmmu->stall_enabled &= ~mask;
125
126	/*
127	 * If the device is on and we changed the setting, update the register.
128	 * The spec pseudocode says that CFCFG is resampled after a fault, and
129	 * we believe that no implementations cache it in the TLB, so it should
130	 * be safe to change it without a TLB invalidation.
131	 */
132	if (stall_changed && pm_runtime_get_if_active(smmu->dev) > 0) {
133		u32 reg;
134
135		spin_lock_irqsave(&smmu_domain->cb_lock, flags);
136		reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR);
137
138		if (enabled)
139			reg |= ARM_SMMU_SCTLR_CFCFG;
140		else
141			reg &= ~ARM_SMMU_SCTLR_CFCFG;
142
143		arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR, reg);
144		spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
145
146		pm_runtime_put_autosuspend(smmu->dev);
147	}
148}
149
150static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set)
151{
152	struct arm_smmu_domain *smmu_domain = (void *)cookie;
153	struct arm_smmu_device *smmu = smmu_domain->smmu;
154	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
155	u32 reg = 0;
156	int ret;
157
158	ret = pm_runtime_resume_and_get(smmu->dev);
159	if (ret < 0) {
160		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
161		return;
162	}
163
164	reg =  arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
165	reg &= ~GFX_ACTLR_PRR;
166	if (set)
167		reg |= FIELD_PREP(GFX_ACTLR_PRR, 1);
168	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
169	pm_runtime_put_autosuspend(smmu->dev);
170}
171
172static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr)
173{
174	struct arm_smmu_domain *smmu_domain = (void *)cookie;
175	struct arm_smmu_device *smmu = smmu_domain->smmu;
176	int ret;
177
178	ret = pm_runtime_resume_and_get(smmu->dev);
179	if (ret < 0) {
180		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
181		return;
182	}
183
184	writel_relaxed(lower_32_bits(page_addr),
185				smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);
186	writel_relaxed(upper_32_bits(page_addr),
187				smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);
188	pm_runtime_put_autosuspend(smmu->dev);
189}
190
191#define QCOM_ADRENO_SMMU_GPU_SID 0
192
193static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
194{
195	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
196	int i;
197
198	/*
199	 * The GPU will always use SID 0 so that is a handy way to uniquely
200	 * identify it and configure it for per-instance pagetables
201	 */
202	for (i = 0; i < fwspec->num_ids; i++) {
203		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
204
205		if (sid == QCOM_ADRENO_SMMU_GPU_SID)
206			return true;
207	}
208
209	return false;
210}
211
212static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
213		const void *cookie)
214{
215	struct arm_smmu_domain *smmu_domain = (void *)cookie;
216	struct io_pgtable *pgtable =
217		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
218	return &pgtable->cfg;
219}
220
221/*
222 * Local implementation to configure TTBR0 with the specified pagetable config.
223 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
224 * are active
225 */
226
227static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
228		const struct io_pgtable_cfg *pgtbl_cfg)
229{
230	struct arm_smmu_domain *smmu_domain = (void *)cookie;
231	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
232	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
233	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
234
235	/* The domain must have split pagetables already enabled */
236	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
237		return -EINVAL;
238
239	/* If the pagetable config is NULL, disable TTBR0 */
240	if (!pgtbl_cfg) {
241		/* Do nothing if it is already disabled */
242		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
243			return -EINVAL;
244
245		/* Set TCR to the original configuration */
246		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
247		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
248	} else {
249		u32 tcr = cb->tcr[0];
250
251		/* Don't call this again if TTBR0 is already enabled */
252		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
253			return -EINVAL;
254
255		tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
256		tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
257
258		cb->tcr[0] = tcr;
259		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
260		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
261	}
262
263	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
264
265	return 0;
266}
267
268static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
269					       struct arm_smmu_device *smmu,
270					       struct device *dev, int start)
271{
272	int count;
273
274	/*
275	 * Assign context bank 0 to the GPU device so the GPU hardware can
276	 * switch pagetables
277	 */
278	if (qcom_adreno_smmu_is_gpu_device(dev)) {
279		start = 0;
280		count = 1;
281	} else {
282		start = 1;
283		count = smmu->num_context_banks;
284	}
285
286	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
287}
288
289static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
290{
291	const struct device_node *np = smmu->dev->of_node;
292
293	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
294		return false;
295
296	return true;
297}
298
299static void qcom_smmu_set_actlr_dev(struct device *dev, struct arm_smmu_device *smmu, int cbndx,
300		const struct of_device_id *client_match)
301{
302	const struct of_device_id *match =
303			of_match_device(client_match, dev);
304
305	if (!match) {
306		dev_dbg(dev, "no ACTLR settings present\n");
307		return;
308	}
309
310	arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->data);
311}
312
313static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
314		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
315{
316	const struct device_node *np = smmu_domain->smmu->dev->of_node;
317	struct arm_smmu_device *smmu = smmu_domain->smmu;
318	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
319	const struct of_device_id *client_match;
320	int cbndx = smmu_domain->cfg.cbndx;
321	struct adreno_smmu_priv *priv;
322
323	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
324
325	client_match = qsmmu->data->client_match;
326
327	if (client_match)
328		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);
329
330	/* Only enable split pagetables for the GPU device (SID 0) */
331	if (!qcom_adreno_smmu_is_gpu_device(dev))
332		return 0;
333
334	/*
335	 * All targets that use the qcom,adreno-smmu compatible string *should*
336	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
337	 * that is the case when the TTBR1 quirk is enabled
338	 */
339	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
340	    (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
341	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
342		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
343
344	/*
345	 * Initialize private interface with GPU:
346	 */
347
348	priv = dev_get_drvdata(dev);
349	priv->cookie = smmu_domain;
350	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
351	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
352	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
353	priv->set_stall = qcom_adreno_smmu_set_stall;
354	priv->set_prr_bit = NULL;
355	priv->set_prr_addr = NULL;
356
357	if (of_device_is_compatible(np, "qcom,smmu-500") &&
358	    !of_device_is_compatible(np, "qcom,sm8250-smmu-500") &&
359	    of_device_is_compatible(np, "qcom,adreno-smmu")) {
360		priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
361		priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
362	}
363
364	return 0;
365}
366
367static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
368	{ .compatible = "qcom,adreno" },
369	{ .compatible = "qcom,adreno-gmu" },
370	{ .compatible = "qcom,glymur-mdss" },
371	{ .compatible = "qcom,mdp4" },
372	{ .compatible = "qcom,mdss" },
373	{ .compatible = "qcom,qcm2290-mdss" },
374	{ .compatible = "qcom,sar2130p-mdss" },
375	{ .compatible = "qcom,sc7180-mdss" },
376	{ .compatible = "qcom,sc7180-mss-pil" },
377	{ .compatible = "qcom,sc7280-mdss" },
378	{ .compatible = "qcom,sc7280-mss-pil" },
379	{ .compatible = "qcom,sc8180x-mdss" },
380	{ .compatible = "qcom,sc8280xp-mdss" },
381	{ .compatible = "qcom,sdm670-mdss" },
382	{ .compatible = "qcom,sdm845-mdss" },
383	{ .compatible = "qcom,sdm845-mss-pil" },
384	{ .compatible = "qcom,sm6115-mdss" },
385	{ .compatible = "qcom,sm6350-mdss" },
386	{ .compatible = "qcom,sm6375-mdss" },
387	{ .compatible = "qcom,sm8150-mdss" },
388	{ .compatible = "qcom,sm8250-mdss" },
389	{ .compatible = "qcom,x1e80100-mdss" },
390	{ }
391};
392
393static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
394		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
395{
396	struct arm_smmu_device *smmu = smmu_domain->smmu;
397	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
398	const struct of_device_id *client_match;
399	int cbndx = smmu_domain->cfg.cbndx;
400
401	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
402
403	client_match = qsmmu->data->client_match;
404
405	if (client_match)
406		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);
407
408	return 0;
409}
410
411static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
412{
413	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
414	unsigned int last_s2cr;
415	u32 reg;
416	u32 smr;
417	int i;
418
419	/*
420	 * MSM8998 LPASS SMMU reports 13 context banks, but accessing
421	 * the last context bank crashes the system.
422	 */
423	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&
424	    smmu->num_context_banks == 13) {
425		smmu->num_context_banks = 12;
426	} else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {
427		if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */
428			smmu->num_context_banks = 7;
429		else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */
430			smmu->num_context_banks = 13;
431	}
432
433	/*
434	 * Some platforms support more than the Arm SMMU architected maximum of
435	 * 128 stream matching groups. The additional registers appear to have
436	 * the same behavior as the architected registers in the hardware.
437	 * However, on some firmware versions, the hypervisor does not
438	 * correctly trap and emulate accesses to the additional registers,
439	 * resulting in unexpected behavior.
440	 *
441	 * If there are more than 128 groups, use the last reliable group to
442	 * detect if we need to apply the bypass quirk.
443	 */
444	if (smmu->num_mapping_groups > 128)
445		last_s2cr = ARM_SMMU_GR0_S2CR(127);
446	else
447		last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
448
449	/*
450	 * With some firmware versions writes to S2CR of type FAULT are
451	 * ignored, and writing BYPASS will end up written as FAULT in the
452	 * register. Perform a write to S2CR to detect if this is the case and
453	 * if so reserve a context bank to emulate bypass streams.
454	 */
455	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
456	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
457	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
458	arm_smmu_gr0_write(smmu, last_s2cr, reg);
459	reg = arm_smmu_gr0_read(smmu, last_s2cr);
460	if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
461		qsmmu->bypass_quirk = true;
462		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
463
464		set_bit(qsmmu->bypass_cbndx, smmu->context_map);
465
466		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
467
468		reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
469		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
470
471		if (smmu->num_mapping_groups > 128) {
472			dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
473			smmu->num_mapping_groups = 128;
474		}
475	}
476
477	for (i = 0; i < smmu->num_mapping_groups; i++) {
478		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
479
480		if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
481			/* Ignore valid bit for SMR mask extraction. */
482			smr &= ~ARM_SMMU_SMR_VALID;
483			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
484			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
485			smmu->smrs[i].valid = true;
486
487			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
488			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
489			smmu->s2crs[i].cbndx = 0xff;
490		}
491	}
492
493	return 0;
494}
495
496static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu)
497{
498	/* Support for 16K pages is advertised on some SoCs, but it doesn't seem to work */
499	smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;
500
501	/* TZ protects several last context banks, hide them from Linux */
502	if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&
503	    smmu->num_context_banks == 5)
504		smmu->num_context_banks = 2;
505
506	return 0;
507}
508
509static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
510{
511	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
512	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
513	u32 cbndx = s2cr->cbndx;
514	u32 type = s2cr->type;
515	u32 reg;
516
517	if (qsmmu->bypass_quirk) {
518		if (type == S2CR_TYPE_BYPASS) {
519			/*
520			 * Firmware with quirky S2CR handling will substitute
521			 * BYPASS writes with FAULT, so point the stream to the
522			 * reserved context bank and ask for translation on the
523			 * stream
524			 */
525			type = S2CR_TYPE_TRANS;
526			cbndx = qsmmu->bypass_cbndx;
527		} else if (type == S2CR_TYPE_FAULT) {
528			/*
529			 * Firmware with quirky S2CR handling will ignore FAULT
530			 * writes, so trick it to write FAULT by asking for a
531			 * BYPASS.
532			 */
533			type = S2CR_TYPE_BYPASS;
534			cbndx = 0xff;
535		}
536	}
537
538	reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
539	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
540	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
541	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
542}
543
544static int qcom_smmu_def_domain_type(struct device *dev)
545{
546	const struct of_device_id *match =
547		of_match_device(qcom_smmu_client_of_match, dev);
548
549	return match ? IOMMU_DOMAIN_IDENTITY : 0;
550}
551
552static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
553{
554	int ret;
555
556	arm_mmu500_reset(smmu);
557
558	/*
559	 * To address performance degradation in non-real time clients,
560	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
561	 * such as MTP and db845, whose firmwares implement secure monitor
562	 * call handlers to turn on/off the wait-for-safe logic.
563	 */
564	ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
565	if (ret)
566		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
567
568	return ret;
569}
570
571static const struct arm_smmu_impl qcom_smmu_v2_impl = {
572	.init_context = qcom_smmu_init_context,
573	.cfg_probe = qcom_smmu_cfg_probe,
574	.def_domain_type = qcom_smmu_def_domain_type,
575	.write_s2cr = qcom_smmu_write_s2cr,
576	.tlb_sync = qcom_smmu_tlb_sync,
577};
578
579static const struct arm_smmu_impl qcom_smmu_500_impl = {
580	.init_context = qcom_smmu_init_context,
581	.cfg_probe = qcom_smmu_cfg_probe,
582	.def_domain_type = qcom_smmu_def_domain_type,
583	.reset = arm_mmu500_reset,
584	.write_s2cr = qcom_smmu_write_s2cr,
585	.tlb_sync = qcom_smmu_tlb_sync,
586#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
587	.context_fault = qcom_smmu_context_fault,
588	.context_fault_needs_threaded_irq = true,
589#endif
590};
591
592static const struct arm_smmu_impl sdm845_smmu_500_impl = {
593	.init_context = qcom_smmu_init_context,
594	.cfg_probe = qcom_smmu_cfg_probe,
595	.def_domain_type = qcom_smmu_def_domain_type,
596	.reset = qcom_sdm845_smmu500_reset,
597	.write_s2cr = qcom_smmu_write_s2cr,
598	.tlb_sync = qcom_smmu_tlb_sync,
599#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
600	.context_fault = qcom_smmu_context_fault,
601	.context_fault_needs_threaded_irq = true,
602#endif
603};
604
605static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
606	.init_context = qcom_adreno_smmu_init_context,
607	.cfg_probe = qcom_adreno_smmuv2_cfg_probe,
608	.def_domain_type = qcom_smmu_def_domain_type,
609	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
610	.write_sctlr = qcom_adreno_smmu_write_sctlr,
611	.tlb_sync = qcom_smmu_tlb_sync,
612	.context_fault_needs_threaded_irq = true,
613};
614
615static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
616	.init_context = qcom_adreno_smmu_init_context,
617	.def_domain_type = qcom_smmu_def_domain_type,
618	.reset = arm_mmu500_reset,
619	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
620	.write_sctlr = qcom_adreno_smmu_write_sctlr,
621	.tlb_sync = qcom_smmu_tlb_sync,
622	.context_fault_needs_threaded_irq = true,
623};
624
625static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
626		const struct qcom_smmu_match_data *data)
627{
628	const struct device_node *np = smmu->dev->of_node;
629	const struct arm_smmu_impl *impl;
630	struct qcom_smmu *qsmmu;
631
632	if (!data)
633		return ERR_PTR(-EINVAL);
634
635	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
636		impl = data->adreno_impl;
637	else
638		impl = data->impl;
639
640	if (!impl)
641		return smmu;
642
643	/* Check to make sure qcom_scm has finished probing */
644	if (!qcom_scm_is_available())
645		return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER,
646			"qcom_scm not ready\n"));
647
648	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
649	if (!qsmmu)
650		return ERR_PTR(-ENOMEM);
651
652	qsmmu->smmu.impl = impl;
653	qsmmu->data = data;
654
655	return &qsmmu->smmu;
656}
657
658/* Implementation Defined Register Space 0 register offsets */
659static const u32 qcom_smmu_impl0_reg_offset[] = {
660	[QCOM_SMMU_TBU_PWR_STATUS]		= 0x2204,
661	[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK]	= 0x25dc,
662	[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR]	= 0x2670,
663};
664
665static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
666	.reg_offset = qcom_smmu_impl0_reg_offset,
667};
668
669/*
670 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
671 * there are not enough context banks.
672 */
673static const struct qcom_smmu_match_data msm8996_smmu_data = {
674	.impl = NULL,
675	.adreno_impl = &qcom_adreno_smmu_v2_impl,
676};
677
678static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
679	.impl = &qcom_smmu_v2_impl,
680	.adreno_impl = &qcom_adreno_smmu_v2_impl,
681};
682
683static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
684	.impl = &sdm845_smmu_500_impl,
685	/*
686	 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
687	 * by the separate sdm845-smmu-v2 device.
688	 */
689	/* Also no debug configuration. */
690};
691
692static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
693	.impl = &qcom_smmu_500_impl,
694	.adreno_impl = &qcom_adreno_smmu_500_impl,
695	.cfg = &qcom_smmu_impl0_cfg,
696	.client_match = qcom_smmu_actlr_client_of_match,
697};
698
699/*
700 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
701 * special handling and can not be covered by the qcom,smmu-500 entry.
702 */
703static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
704	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
705	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
706	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
707	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
708	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
709	{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
710	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
711	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
712	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
713	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
714	{ .compatible = "qcom,sdm670-smmu-v2", .data = &qcom_smmu_v2_data },
715	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
716	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
717	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
718	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
719	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
720	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
721	{ .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
722	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
723	{ .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
724	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
725	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
726	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
727	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
728	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
729	{ }
730};
731
732#ifdef CONFIG_ACPI
733static struct acpi_platform_list qcom_acpi_platlist[] = {
734	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
735	{ "QCOM  ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
736	{ }
737};
738#endif
739
740static int qcom_smmu_tbu_probe(struct platform_device *pdev)
741{
742	struct device *dev = &pdev->dev;
743	int ret;
744
745	if (IS_ENABLED(CONFIG_ARM_SMMU_QCOM_DEBUG)) {
746		ret = qcom_tbu_probe(pdev);
747		if (ret)
748			return ret;
749	}
750
751	if (dev->pm_domain) {
752		pm_runtime_set_active(dev);
753		pm_runtime_enable(dev);
754	}
755
756	return 0;
757}
758
759static const struct of_device_id qcom_smmu_tbu_of_match[] = {
760	{ .compatible = "qcom,sc7280-tbu" },
761	{ .compatible = "qcom,sdm845-tbu" },
762	{ }
763};
764
765static struct platform_driver qcom_smmu_tbu_driver = {
766	.driver = {
767		.name           = "qcom_tbu",
768		.of_match_table = qcom_smmu_tbu_of_match,
769	},
770	.probe = qcom_smmu_tbu_probe,
771};
772
773struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
774{
775	const struct device_node *np = smmu->dev->of_node;
776	const struct of_device_id *match;
777
778#ifdef CONFIG_ACPI
779	if (np == NULL) {
780		/* Match platform for ACPI boot */
781		if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
782			return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
783	}
784#endif
785
786	match = of_match_node(qcom_smmu_impl_of_match, np);
787	if (match)
788		return qcom_smmu_create(smmu, match->data);
789
790	/*
791	 * If you hit this WARN_ON() you are missing an entry in the
792	 * qcom_smmu_impl_of_match[] table, and GPU per-process page-
793	 * tables will be broken.
794	 */
795	WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),
796	     "Missing qcom_smmu_impl_of_match entry for: %s",
797	     dev_name(smmu->dev));
798
799	return smmu;
800}
801
802int __init qcom_smmu_module_init(void)
803{
804	return platform_driver_register(&qcom_smmu_tbu_driver);
805}
806
807void __exit qcom_smmu_module_exit(void)
808{
809	platform_driver_unregister(&qcom_smmu_tbu_driver);
810}