sm8450.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2021, Linaro Limited
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/module.h>
  11#include <linux/mod_devicetable.h>
  12#include <linux/platform_device.h>
  13#include <linux/property.h>
  14#include <dt-bindings/interconnect/qcom,sm8450.h>
  15
  16#include "bcm-voter.h"
  17#include "icc-common.h"
  18#include "icc-rpmh.h"
  19
  20static struct qcom_icc_node qhm_qspi;
  21static struct qcom_icc_node qhm_qup1;
  22static struct qcom_icc_node qnm_a1noc_cfg;
  23static struct qcom_icc_node xm_sdc4;
  24static struct qcom_icc_node xm_ufs_mem;
  25static struct qcom_icc_node xm_usb3_0;
  26static struct qcom_icc_node qhm_qdss_bam;
  27static struct qcom_icc_node qhm_qup0;
  28static struct qcom_icc_node qhm_qup2;
  29static struct qcom_icc_node qnm_a2noc_cfg;
  30static struct qcom_icc_node qxm_crypto;
  31static struct qcom_icc_node qxm_ipa;
  32static struct qcom_icc_node qxm_sensorss_q6;
  33static struct qcom_icc_node qxm_sp;
  34static struct qcom_icc_node xm_qdss_etr_0;
  35static struct qcom_icc_node xm_qdss_etr_1;
  36static struct qcom_icc_node xm_sdc2;
  37static struct qcom_icc_node qup0_core_master;
  38static struct qcom_icc_node qup1_core_master;
  39static struct qcom_icc_node qup2_core_master;
  40static struct qcom_icc_node qnm_gemnoc_cnoc;
  41static struct qcom_icc_node qnm_gemnoc_pcie;
  42static struct qcom_icc_node alm_gpu_tcu;
  43static struct qcom_icc_node alm_sys_tcu;
  44static struct qcom_icc_node chm_apps;
  45static struct qcom_icc_node qnm_gpu;
  46static struct qcom_icc_node qnm_mdsp;
  47static struct qcom_icc_node qnm_mnoc_hf;
  48static struct qcom_icc_node qnm_mnoc_sf;
  49static struct qcom_icc_node qnm_nsp_gemnoc;
  50static struct qcom_icc_node qnm_pcie;
  51static struct qcom_icc_node qnm_snoc_gc;
  52static struct qcom_icc_node qnm_snoc_sf;
  53static struct qcom_icc_node qhm_config_noc;
  54static struct qcom_icc_node qxm_lpass_dsp;
  55static struct qcom_icc_node llcc_mc;
  56static struct qcom_icc_node qnm_camnoc_hf;
  57static struct qcom_icc_node qnm_camnoc_icp;
  58static struct qcom_icc_node qnm_camnoc_sf;
  59static struct qcom_icc_node qnm_mdp;
  60static struct qcom_icc_node qnm_mnoc_cfg;
  61static struct qcom_icc_node qnm_rot;
  62static struct qcom_icc_node qnm_vapss_hcp;
  63static struct qcom_icc_node qnm_video;
  64static struct qcom_icc_node qnm_video_cv_cpu;
  65static struct qcom_icc_node qnm_video_cvp;
  66static struct qcom_icc_node qnm_video_v_cpu;
  67static struct qcom_icc_node qhm_nsp_noc_config;
  68static struct qcom_icc_node qxm_nsp;
  69static struct qcom_icc_node qnm_pcie_anoc_cfg;
  70static struct qcom_icc_node xm_pcie3_0;
  71static struct qcom_icc_node xm_pcie3_1;
  72static struct qcom_icc_node qhm_gic;
  73static struct qcom_icc_node qnm_aggre1_noc;
  74static struct qcom_icc_node qnm_aggre2_noc;
  75static struct qcom_icc_node qnm_lpass_noc;
  76static struct qcom_icc_node qnm_snoc_cfg;
  77static struct qcom_icc_node qxm_pimem;
  78static struct qcom_icc_node xm_gic;
  79static struct qcom_icc_node qnm_mnoc_hf_disp;
  80static struct qcom_icc_node qnm_mnoc_sf_disp;
  81static struct qcom_icc_node qnm_pcie_disp;
  82static struct qcom_icc_node llcc_mc_disp;
  83static struct qcom_icc_node qnm_mdp_disp;
  84static struct qcom_icc_node qnm_rot_disp;
  85static struct qcom_icc_node qns_a1noc_snoc;
  86static struct qcom_icc_node srvc_aggre1_noc;
  87static struct qcom_icc_node qns_a2noc_snoc;
  88static struct qcom_icc_node srvc_aggre2_noc;
  89static struct qcom_icc_node qup0_core_slave;
  90static struct qcom_icc_node qup1_core_slave;
  91static struct qcom_icc_node qup2_core_slave;
  92static struct qcom_icc_node qhs_ahb2phy0;
  93static struct qcom_icc_node qhs_ahb2phy1;
  94static struct qcom_icc_node qhs_aoss;
  95static struct qcom_icc_node qhs_camera_cfg;
  96static struct qcom_icc_node qhs_clk_ctl;
  97static struct qcom_icc_node qhs_compute_cfg;
  98static struct qcom_icc_node qhs_cpr_cx;
  99static struct qcom_icc_node qhs_cpr_mmcx;
 100static struct qcom_icc_node qhs_cpr_mxa;
 101static struct qcom_icc_node qhs_cpr_mxc;
 102static struct qcom_icc_node qhs_crypto0_cfg;
 103static struct qcom_icc_node qhs_cx_rdpm;
 104static struct qcom_icc_node qhs_display_cfg;
 105static struct qcom_icc_node qhs_gpuss_cfg;
 106static struct qcom_icc_node qhs_imem_cfg;
 107static struct qcom_icc_node qhs_ipa;
 108static struct qcom_icc_node qhs_ipc_router;
 109static struct qcom_icc_node qhs_lpass_cfg;
 110static struct qcom_icc_node qhs_mss_cfg;
 111static struct qcom_icc_node qhs_mx_rdpm;
 112static struct qcom_icc_node qhs_pcie0_cfg;
 113static struct qcom_icc_node qhs_pcie1_cfg;
 114static struct qcom_icc_node qhs_pdm;
 115static struct qcom_icc_node qhs_pimem_cfg;
 116static struct qcom_icc_node qhs_prng;
 117static struct qcom_icc_node qhs_qdss_cfg;
 118static struct qcom_icc_node qhs_qspi;
 119static struct qcom_icc_node qhs_qup0;
 120static struct qcom_icc_node qhs_qup1;
 121static struct qcom_icc_node qhs_qup2;
 122static struct qcom_icc_node qhs_sdc2;
 123static struct qcom_icc_node qhs_sdc4;
 124static struct qcom_icc_node qhs_spss_cfg;
 125static struct qcom_icc_node qhs_tcsr;
 126static struct qcom_icc_node qhs_tlmm;
 127static struct qcom_icc_node qhs_tme_cfg;
 128static struct qcom_icc_node qhs_ufs_mem_cfg;
 129static struct qcom_icc_node qhs_usb3_0;
 130static struct qcom_icc_node qhs_venus_cfg;
 131static struct qcom_icc_node qhs_vsense_ctrl_cfg;
 132static struct qcom_icc_node qns_a1_noc_cfg;
 133static struct qcom_icc_node qns_a2_noc_cfg;
 134static struct qcom_icc_node qns_ddrss_cfg;
 135static struct qcom_icc_node qns_mnoc_cfg;
 136static struct qcom_icc_node qns_pcie_anoc_cfg;
 137static struct qcom_icc_node qns_snoc_cfg;
 138static struct qcom_icc_node qxs_imem;
 139static struct qcom_icc_node qxs_pimem;
 140static struct qcom_icc_node srvc_cnoc;
 141static struct qcom_icc_node xs_pcie_0;
 142static struct qcom_icc_node xs_pcie_1;
 143static struct qcom_icc_node xs_qdss_stm;
 144static struct qcom_icc_node xs_sys_tcu_cfg;
 145static struct qcom_icc_node qns_gem_noc_cnoc;
 146static struct qcom_icc_node qns_llcc;
 147static struct qcom_icc_node qns_pcie;
 148static struct qcom_icc_node qhs_lpass_core;
 149static struct qcom_icc_node qhs_lpass_lpi;
 150static struct qcom_icc_node qhs_lpass_mpu;
 151static struct qcom_icc_node qhs_lpass_top;
 152static struct qcom_icc_node qns_sysnoc;
 153static struct qcom_icc_node srvc_niu_aml_noc;
 154static struct qcom_icc_node srvc_niu_lpass_agnoc;
 155static struct qcom_icc_node ebi;
 156static struct qcom_icc_node qns_mem_noc_hf;
 157static struct qcom_icc_node qns_mem_noc_sf;
 158static struct qcom_icc_node srvc_mnoc;
 159static struct qcom_icc_node qns_nsp_gemnoc;
 160static struct qcom_icc_node service_nsp_noc;
 161static struct qcom_icc_node qns_pcie_mem_noc;
 162static struct qcom_icc_node srvc_pcie_aggre_noc;
 163static struct qcom_icc_node qns_gemnoc_gc;
 164static struct qcom_icc_node qns_gemnoc_sf;
 165static struct qcom_icc_node srvc_snoc;
 166static struct qcom_icc_node qns_llcc_disp;
 167static struct qcom_icc_node ebi_disp;
 168static struct qcom_icc_node qns_mem_noc_hf_disp;
 169static struct qcom_icc_node qns_mem_noc_sf_disp;
 170
 171static struct qcom_icc_node qhm_qspi = {
 172	.name = "qhm_qspi",
 173	.channels = 1,
 174	.buswidth = 4,
 175	.num_links = 1,
 176	.link_nodes = { &qns_a1noc_snoc },
 177};
 178
 179static struct qcom_icc_node qhm_qup1 = {
 180	.name = "qhm_qup1",
 181	.channels = 1,
 182	.buswidth = 4,
 183	.num_links = 1,
 184	.link_nodes = { &qns_a1noc_snoc },
 185};
 186
 187static struct qcom_icc_node qnm_a1noc_cfg = {
 188	.name = "qnm_a1noc_cfg",
 189	.channels = 1,
 190	.buswidth = 4,
 191	.num_links = 1,
 192	.link_nodes = { &srvc_aggre1_noc },
 193};
 194
 195static struct qcom_icc_node xm_sdc4 = {
 196	.name = "xm_sdc4",
 197	.channels = 1,
 198	.buswidth = 8,
 199	.num_links = 1,
 200	.link_nodes = { &qns_a1noc_snoc },
 201};
 202
 203static struct qcom_icc_node xm_ufs_mem = {
 204	.name = "xm_ufs_mem",
 205	.channels = 1,
 206	.buswidth = 8,
 207	.num_links = 1,
 208	.link_nodes = { &qns_a1noc_snoc },
 209};
 210
 211static struct qcom_icc_node xm_usb3_0 = {
 212	.name = "xm_usb3_0",
 213	.channels = 1,
 214	.buswidth = 8,
 215	.num_links = 1,
 216	.link_nodes = { &qns_a1noc_snoc },
 217};
 218
 219static struct qcom_icc_node qhm_qdss_bam = {
 220	.name = "qhm_qdss_bam",
 221	.channels = 1,
 222	.buswidth = 4,
 223	.num_links = 1,
 224	.link_nodes = { &qns_a2noc_snoc },
 225};
 226
 227static struct qcom_icc_node qhm_qup0 = {
 228	.name = "qhm_qup0",
 229	.channels = 1,
 230	.buswidth = 4,
 231	.num_links = 1,
 232	.link_nodes = { &qns_a2noc_snoc },
 233};
 234
 235static struct qcom_icc_node qhm_qup2 = {
 236	.name = "qhm_qup2",
 237	.channels = 1,
 238	.buswidth = 4,
 239	.num_links = 1,
 240	.link_nodes = { &qns_a2noc_snoc },
 241};
 242
 243static struct qcom_icc_node qnm_a2noc_cfg = {
 244	.name = "qnm_a2noc_cfg",
 245	.channels = 1,
 246	.buswidth = 4,
 247	.num_links = 1,
 248	.link_nodes = { &srvc_aggre2_noc },
 249};
 250
 251static struct qcom_icc_node qxm_crypto = {
 252	.name = "qxm_crypto",
 253	.channels = 1,
 254	.buswidth = 8,
 255	.num_links = 1,
 256	.link_nodes = { &qns_a2noc_snoc },
 257};
 258
 259static struct qcom_icc_node qxm_ipa = {
 260	.name = "qxm_ipa",
 261	.channels = 1,
 262	.buswidth = 8,
 263	.num_links = 1,
 264	.link_nodes = { &qns_a2noc_snoc },
 265};
 266
 267static struct qcom_icc_node qxm_sensorss_q6 = {
 268	.name = "qxm_sensorss_q6",
 269	.channels = 1,
 270	.buswidth = 8,
 271	.num_links = 1,
 272	.link_nodes = { &qns_a2noc_snoc },
 273};
 274
 275static struct qcom_icc_node qxm_sp = {
 276	.name = "qxm_sp",
 277	.channels = 1,
 278	.buswidth = 8,
 279	.num_links = 1,
 280	.link_nodes = { &qns_a2noc_snoc },
 281};
 282
 283static struct qcom_icc_node xm_qdss_etr_0 = {
 284	.name = "xm_qdss_etr_0",
 285	.channels = 1,
 286	.buswidth = 8,
 287	.num_links = 1,
 288	.link_nodes = { &qns_a2noc_snoc },
 289};
 290
 291static struct qcom_icc_node xm_qdss_etr_1 = {
 292	.name = "xm_qdss_etr_1",
 293	.channels = 1,
 294	.buswidth = 8,
 295	.num_links = 1,
 296	.link_nodes = { &qns_a2noc_snoc },
 297};
 298
 299static struct qcom_icc_node xm_sdc2 = {
 300	.name = "xm_sdc2",
 301	.channels = 1,
 302	.buswidth = 8,
 303	.num_links = 1,
 304	.link_nodes = { &qns_a2noc_snoc },
 305};
 306
 307static struct qcom_icc_node qup0_core_master = {
 308	.name = "qup0_core_master",
 309	.channels = 1,
 310	.buswidth = 4,
 311	.num_links = 1,
 312	.link_nodes = { &qup0_core_slave },
 313};
 314
 315static struct qcom_icc_node qup1_core_master = {
 316	.name = "qup1_core_master",
 317	.channels = 1,
 318	.buswidth = 4,
 319	.num_links = 1,
 320	.link_nodes = { &qup1_core_slave },
 321};
 322
 323static struct qcom_icc_node qup2_core_master = {
 324	.name = "qup2_core_master",
 325	.channels = 1,
 326	.buswidth = 4,
 327	.num_links = 1,
 328	.link_nodes = { &qup2_core_slave },
 329};
 330
 331static struct qcom_icc_node qnm_gemnoc_cnoc = {
 332	.name = "qnm_gemnoc_cnoc",
 333	.channels = 1,
 334	.buswidth = 16,
 335	.num_links = 51,
 336	.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
 337			&qhs_aoss, &qhs_camera_cfg,
 338			&qhs_clk_ctl, &qhs_compute_cfg,
 339			&qhs_cpr_cx, &qhs_cpr_mmcx,
 340			&qhs_cpr_mxa, &qhs_cpr_mxc,
 341			&qhs_crypto0_cfg, &qhs_cx_rdpm,
 342			&qhs_display_cfg, &qhs_gpuss_cfg,
 343			&qhs_imem_cfg, &qhs_ipa,
 344			&qhs_ipc_router, &qhs_lpass_cfg,
 345			&qhs_mss_cfg, &qhs_mx_rdpm,
 346			&qhs_pcie0_cfg, &qhs_pcie1_cfg,
 347			&qhs_pdm, &qhs_pimem_cfg,
 348			&qhs_prng, &qhs_qdss_cfg,
 349			&qhs_qspi, &qhs_qup0,
 350			&qhs_qup1, &qhs_qup2,
 351			&qhs_sdc2, &qhs_sdc4,
 352			&qhs_spss_cfg, &qhs_tcsr,
 353			&qhs_tlmm, &qhs_tme_cfg,
 354			&qhs_ufs_mem_cfg, &qhs_usb3_0,
 355			&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
 356			&qns_a1_noc_cfg, &qns_a2_noc_cfg,
 357			&qns_ddrss_cfg, &qns_mnoc_cfg,
 358			&qns_pcie_anoc_cfg, &qns_snoc_cfg,
 359			&qxs_imem, &qxs_pimem,
 360			&srvc_cnoc, &xs_qdss_stm,
 361			&xs_sys_tcu_cfg },
 362};
 363
 364static struct qcom_icc_node qnm_gemnoc_pcie = {
 365	.name = "qnm_gemnoc_pcie",
 366	.channels = 1,
 367	.buswidth = 8,
 368	.num_links = 2,
 369	.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
 370};
 371
 372static struct qcom_icc_node alm_gpu_tcu = {
 373	.name = "alm_gpu_tcu",
 374	.channels = 1,
 375	.buswidth = 8,
 376	.num_links = 2,
 377	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 378};
 379
 380static struct qcom_icc_node alm_sys_tcu = {
 381	.name = "alm_sys_tcu",
 382	.channels = 1,
 383	.buswidth = 8,
 384	.num_links = 2,
 385	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 386};
 387
 388static struct qcom_icc_node chm_apps = {
 389	.name = "chm_apps",
 390	.channels = 3,
 391	.buswidth = 32,
 392	.num_links = 3,
 393	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 394			&qns_pcie },
 395};
 396
 397static struct qcom_icc_node qnm_gpu = {
 398	.name = "qnm_gpu",
 399	.channels = 2,
 400	.buswidth = 32,
 401	.num_links = 2,
 402	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 403};
 404
 405static struct qcom_icc_node qnm_mdsp = {
 406	.name = "qnm_mdsp",
 407	.channels = 1,
 408	.buswidth = 16,
 409	.num_links = 3,
 410	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 411			&qns_pcie },
 412};
 413
 414static struct qcom_icc_node qnm_mnoc_hf = {
 415	.name = "qnm_mnoc_hf",
 416	.channels = 2,
 417	.buswidth = 32,
 418	.num_links = 1,
 419	.link_nodes = { &qns_llcc },
 420};
 421
 422static struct qcom_icc_node qnm_mnoc_sf = {
 423	.name = "qnm_mnoc_sf",
 424	.channels = 2,
 425	.buswidth = 32,
 426	.num_links = 2,
 427	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 428};
 429
 430static struct qcom_icc_node qnm_nsp_gemnoc = {
 431	.name = "qnm_nsp_gemnoc",
 432	.channels = 2,
 433	.buswidth = 32,
 434	.num_links = 2,
 435	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 436};
 437
 438static struct qcom_icc_node qnm_pcie = {
 439	.name = "qnm_pcie",
 440	.channels = 1,
 441	.buswidth = 16,
 442	.num_links = 2,
 443	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 444};
 445
 446static struct qcom_icc_node qnm_snoc_gc = {
 447	.name = "qnm_snoc_gc",
 448	.channels = 1,
 449	.buswidth = 8,
 450	.num_links = 1,
 451	.link_nodes = { &qns_llcc },
 452};
 453
 454static struct qcom_icc_node qnm_snoc_sf = {
 455	.name = "qnm_snoc_sf",
 456	.channels = 1,
 457	.buswidth = 16,
 458	.num_links = 3,
 459	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 460			&qns_pcie },
 461};
 462
 463static struct qcom_icc_node qhm_config_noc = {
 464	.name = "qhm_config_noc",
 465	.channels = 1,
 466	.buswidth = 4,
 467	.num_links = 6,
 468	.link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
 469			&qhs_lpass_mpu, &qhs_lpass_top,
 470			&srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
 471};
 472
 473static struct qcom_icc_node qxm_lpass_dsp = {
 474	.name = "qxm_lpass_dsp",
 475	.channels = 1,
 476	.buswidth = 8,
 477	.num_links = 4,
 478	.link_nodes = { &qhs_lpass_top, &qns_sysnoc,
 479			&srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
 480};
 481
 482static struct qcom_icc_node llcc_mc = {
 483	.name = "llcc_mc",
 484	.channels = 4,
 485	.buswidth = 4,
 486	.num_links = 1,
 487	.link_nodes = { &ebi },
 488};
 489
 490static struct qcom_icc_node qnm_camnoc_hf = {
 491	.name = "qnm_camnoc_hf",
 492	.channels = 2,
 493	.buswidth = 32,
 494	.num_links = 1,
 495	.link_nodes = { &qns_mem_noc_hf },
 496};
 497
 498static struct qcom_icc_node qnm_camnoc_icp = {
 499	.name = "qnm_camnoc_icp",
 500	.channels = 1,
 501	.buswidth = 8,
 502	.num_links = 1,
 503	.link_nodes = { &qns_mem_noc_sf },
 504};
 505
 506static struct qcom_icc_node qnm_camnoc_sf = {
 507	.name = "qnm_camnoc_sf",
 508	.channels = 2,
 509	.buswidth = 32,
 510	.num_links = 1,
 511	.link_nodes = { &qns_mem_noc_sf },
 512};
 513
 514static struct qcom_icc_node qnm_mdp = {
 515	.name = "qnm_mdp",
 516	.channels = 2,
 517	.buswidth = 32,
 518	.num_links = 1,
 519	.link_nodes = { &qns_mem_noc_hf },
 520};
 521
 522static struct qcom_icc_node qnm_mnoc_cfg = {
 523	.name = "qnm_mnoc_cfg",
 524	.channels = 1,
 525	.buswidth = 4,
 526	.num_links = 1,
 527	.link_nodes = { &srvc_mnoc },
 528};
 529
 530static struct qcom_icc_node qnm_rot = {
 531	.name = "qnm_rot",
 532	.channels = 1,
 533	.buswidth = 32,
 534	.num_links = 1,
 535	.link_nodes = { &qns_mem_noc_sf },
 536};
 537
 538static struct qcom_icc_node qnm_vapss_hcp = {
 539	.name = "qnm_vapss_hcp",
 540	.channels = 1,
 541	.buswidth = 32,
 542	.num_links = 1,
 543	.link_nodes = { &qns_mem_noc_sf },
 544};
 545
 546static struct qcom_icc_node qnm_video = {
 547	.name = "qnm_video",
 548	.channels = 2,
 549	.buswidth = 32,
 550	.num_links = 1,
 551	.link_nodes = { &qns_mem_noc_sf },
 552};
 553
 554static struct qcom_icc_node qnm_video_cv_cpu = {
 555	.name = "qnm_video_cv_cpu",
 556	.channels = 1,
 557	.buswidth = 8,
 558	.num_links = 1,
 559	.link_nodes = { &qns_mem_noc_sf },
 560};
 561
 562static struct qcom_icc_node qnm_video_cvp = {
 563	.name = "qnm_video_cvp",
 564	.channels = 1,
 565	.buswidth = 32,
 566	.num_links = 1,
 567	.link_nodes = { &qns_mem_noc_sf },
 568};
 569
 570static struct qcom_icc_node qnm_video_v_cpu = {
 571	.name = "qnm_video_v_cpu",
 572	.channels = 1,
 573	.buswidth = 8,
 574	.num_links = 1,
 575	.link_nodes = { &qns_mem_noc_sf },
 576};
 577
 578static struct qcom_icc_node qhm_nsp_noc_config = {
 579	.name = "qhm_nsp_noc_config",
 580	.channels = 1,
 581	.buswidth = 4,
 582	.num_links = 1,
 583	.link_nodes = { &service_nsp_noc },
 584};
 585
 586static struct qcom_icc_node qxm_nsp = {
 587	.name = "qxm_nsp",
 588	.channels = 2,
 589	.buswidth = 32,
 590	.num_links = 1,
 591	.link_nodes = { &qns_nsp_gemnoc },
 592};
 593
 594static struct qcom_icc_node qnm_pcie_anoc_cfg = {
 595	.name = "qnm_pcie_anoc_cfg",
 596	.channels = 1,
 597	.buswidth = 4,
 598	.num_links = 1,
 599	.link_nodes = { &srvc_pcie_aggre_noc },
 600};
 601
 602static struct qcom_icc_node xm_pcie3_0 = {
 603	.name = "xm_pcie3_0",
 604	.channels = 1,
 605	.buswidth = 8,
 606	.num_links = 1,
 607	.link_nodes = { &qns_pcie_mem_noc },
 608};
 609
 610static struct qcom_icc_node xm_pcie3_1 = {
 611	.name = "xm_pcie3_1",
 612	.channels = 1,
 613	.buswidth = 8,
 614	.num_links = 1,
 615	.link_nodes = { &qns_pcie_mem_noc },
 616};
 617
 618static struct qcom_icc_node qhm_gic = {
 619	.name = "qhm_gic",
 620	.channels = 1,
 621	.buswidth = 4,
 622	.num_links = 1,
 623	.link_nodes = { &qns_gemnoc_sf },
 624};
 625
 626static struct qcom_icc_node qnm_aggre1_noc = {
 627	.name = "qnm_aggre1_noc",
 628	.channels = 1,
 629	.buswidth = 16,
 630	.num_links = 1,
 631	.link_nodes = { &qns_gemnoc_sf },
 632};
 633
 634static struct qcom_icc_node qnm_aggre2_noc = {
 635	.name = "qnm_aggre2_noc",
 636	.channels = 1,
 637	.buswidth = 16,
 638	.num_links = 1,
 639	.link_nodes = { &qns_gemnoc_sf },
 640};
 641
 642static struct qcom_icc_node qnm_lpass_noc = {
 643	.name = "qnm_lpass_noc",
 644	.channels = 1,
 645	.buswidth = 16,
 646	.num_links = 1,
 647	.link_nodes = { &qns_gemnoc_sf },
 648};
 649
 650static struct qcom_icc_node qnm_snoc_cfg = {
 651	.name = "qnm_snoc_cfg",
 652	.channels = 1,
 653	.buswidth = 4,
 654	.num_links = 1,
 655	.link_nodes = { &srvc_snoc },
 656};
 657
 658static struct qcom_icc_node qxm_pimem = {
 659	.name = "qxm_pimem",
 660	.channels = 1,
 661	.buswidth = 8,
 662	.num_links = 1,
 663	.link_nodes = { &qns_gemnoc_gc },
 664};
 665
 666static struct qcom_icc_node xm_gic = {
 667	.name = "xm_gic",
 668	.channels = 1,
 669	.buswidth = 8,
 670	.num_links = 1,
 671	.link_nodes = { &qns_gemnoc_gc },
 672};
 673
 674static struct qcom_icc_node qnm_mnoc_hf_disp = {
 675	.name = "qnm_mnoc_hf_disp",
 676	.channels = 2,
 677	.buswidth = 32,
 678	.num_links = 1,
 679	.link_nodes = { &qns_llcc_disp },
 680};
 681
 682static struct qcom_icc_node qnm_mnoc_sf_disp = {
 683	.name = "qnm_mnoc_sf_disp",
 684	.channels = 2,
 685	.buswidth = 32,
 686	.num_links = 1,
 687	.link_nodes = { &qns_llcc_disp },
 688};
 689
 690static struct qcom_icc_node qnm_pcie_disp = {
 691	.name = "qnm_pcie_disp",
 692	.channels = 1,
 693	.buswidth = 16,
 694	.num_links = 1,
 695	.link_nodes = { &qns_llcc_disp },
 696};
 697
 698static struct qcom_icc_node llcc_mc_disp = {
 699	.name = "llcc_mc_disp",
 700	.channels = 4,
 701	.buswidth = 4,
 702	.num_links = 1,
 703	.link_nodes = { &ebi_disp },
 704};
 705
 706static struct qcom_icc_node qnm_mdp_disp = {
 707	.name = "qnm_mdp_disp",
 708	.channels = 2,
 709	.buswidth = 32,
 710	.num_links = 1,
 711	.link_nodes = { &qns_mem_noc_hf_disp },
 712};
 713
 714static struct qcom_icc_node qnm_rot_disp = {
 715	.name = "qnm_rot_disp",
 716	.channels = 1,
 717	.buswidth = 32,
 718	.num_links = 1,
 719	.link_nodes = { &qns_mem_noc_sf_disp },
 720};
 721
 722static struct qcom_icc_node qns_a1noc_snoc = {
 723	.name = "qns_a1noc_snoc",
 724	.channels = 1,
 725	.buswidth = 16,
 726	.num_links = 1,
 727	.link_nodes = { &qnm_aggre1_noc },
 728};
 729
 730static struct qcom_icc_node srvc_aggre1_noc = {
 731	.name = "srvc_aggre1_noc",
 732	.channels = 1,
 733	.buswidth = 4,
 734};
 735
 736static struct qcom_icc_node qns_a2noc_snoc = {
 737	.name = "qns_a2noc_snoc",
 738	.channels = 1,
 739	.buswidth = 16,
 740	.num_links = 1,
 741	.link_nodes = { &qnm_aggre2_noc },
 742};
 743
 744static struct qcom_icc_node srvc_aggre2_noc = {
 745	.name = "srvc_aggre2_noc",
 746	.channels = 1,
 747	.buswidth = 4,
 748};
 749
 750static struct qcom_icc_node qup0_core_slave = {
 751	.name = "qup0_core_slave",
 752	.channels = 1,
 753	.buswidth = 4,
 754};
 755
 756static struct qcom_icc_node qup1_core_slave = {
 757	.name = "qup1_core_slave",
 758	.channels = 1,
 759	.buswidth = 4,
 760};
 761
 762static struct qcom_icc_node qup2_core_slave = {
 763	.name = "qup2_core_slave",
 764	.channels = 1,
 765	.buswidth = 4,
 766};
 767
 768static struct qcom_icc_node qhs_ahb2phy0 = {
 769	.name = "qhs_ahb2phy0",
 770	.channels = 1,
 771	.buswidth = 4,
 772};
 773
 774static struct qcom_icc_node qhs_ahb2phy1 = {
 775	.name = "qhs_ahb2phy1",
 776	.channels = 1,
 777	.buswidth = 4,
 778};
 779
 780static struct qcom_icc_node qhs_aoss = {
 781	.name = "qhs_aoss",
 782	.channels = 1,
 783	.buswidth = 4,
 784};
 785
 786static struct qcom_icc_node qhs_camera_cfg = {
 787	.name = "qhs_camera_cfg",
 788	.channels = 1,
 789	.buswidth = 4,
 790};
 791
 792static struct qcom_icc_node qhs_clk_ctl = {
 793	.name = "qhs_clk_ctl",
 794	.channels = 1,
 795	.buswidth = 4,
 796};
 797
 798static struct qcom_icc_node qhs_compute_cfg = {
 799	.name = "qhs_compute_cfg",
 800	.channels = 1,
 801	.buswidth = 4,
 802	.num_links = 1,
 803	.link_nodes = { &qhm_nsp_noc_config },
 804};
 805
 806static struct qcom_icc_node qhs_cpr_cx = {
 807	.name = "qhs_cpr_cx",
 808	.channels = 1,
 809	.buswidth = 4,
 810};
 811
 812static struct qcom_icc_node qhs_cpr_mmcx = {
 813	.name = "qhs_cpr_mmcx",
 814	.channels = 1,
 815	.buswidth = 4,
 816};
 817
 818static struct qcom_icc_node qhs_cpr_mxa = {
 819	.name = "qhs_cpr_mxa",
 820	.channels = 1,
 821	.buswidth = 4,
 822};
 823
 824static struct qcom_icc_node qhs_cpr_mxc = {
 825	.name = "qhs_cpr_mxc",
 826	.channels = 1,
 827	.buswidth = 4,
 828};
 829
 830static struct qcom_icc_node qhs_crypto0_cfg = {
 831	.name = "qhs_crypto0_cfg",
 832	.channels = 1,
 833	.buswidth = 4,
 834};
 835
 836static struct qcom_icc_node qhs_cx_rdpm = {
 837	.name = "qhs_cx_rdpm",
 838	.channels = 1,
 839	.buswidth = 4,
 840};
 841
 842static struct qcom_icc_node qhs_display_cfg = {
 843	.name = "qhs_display_cfg",
 844	.channels = 1,
 845	.buswidth = 4,
 846};
 847
 848static struct qcom_icc_node qhs_gpuss_cfg = {
 849	.name = "qhs_gpuss_cfg",
 850	.channels = 1,
 851	.buswidth = 8,
 852};
 853
 854static struct qcom_icc_node qhs_imem_cfg = {
 855	.name = "qhs_imem_cfg",
 856	.channels = 1,
 857	.buswidth = 4,
 858};
 859
 860static struct qcom_icc_node qhs_ipa = {
 861	.name = "qhs_ipa",
 862	.channels = 1,
 863	.buswidth = 4,
 864};
 865
 866static struct qcom_icc_node qhs_ipc_router = {
 867	.name = "qhs_ipc_router",
 868	.channels = 1,
 869	.buswidth = 4,
 870};
 871
 872static struct qcom_icc_node qhs_lpass_cfg = {
 873	.name = "qhs_lpass_cfg",
 874	.channels = 1,
 875	.buswidth = 4,
 876	.num_links = 1,
 877	.link_nodes = { &qhm_config_noc },
 878};
 879
 880static struct qcom_icc_node qhs_mss_cfg = {
 881	.name = "qhs_mss_cfg",
 882	.channels = 1,
 883	.buswidth = 4,
 884};
 885
 886static struct qcom_icc_node qhs_mx_rdpm = {
 887	.name = "qhs_mx_rdpm",
 888	.channels = 1,
 889	.buswidth = 4,
 890};
 891
 892static struct qcom_icc_node qhs_pcie0_cfg = {
 893	.name = "qhs_pcie0_cfg",
 894	.channels = 1,
 895	.buswidth = 4,
 896};
 897
 898static struct qcom_icc_node qhs_pcie1_cfg = {
 899	.name = "qhs_pcie1_cfg",
 900	.channels = 1,
 901	.buswidth = 4,
 902};
 903
 904static struct qcom_icc_node qhs_pdm = {
 905	.name = "qhs_pdm",
 906	.channels = 1,
 907	.buswidth = 4,
 908};
 909
 910static struct qcom_icc_node qhs_pimem_cfg = {
 911	.name = "qhs_pimem_cfg",
 912	.channels = 1,
 913	.buswidth = 4,
 914};
 915
 916static struct qcom_icc_node qhs_prng = {
 917	.name = "qhs_prng",
 918	.channels = 1,
 919	.buswidth = 4,
 920};
 921
 922static struct qcom_icc_node qhs_qdss_cfg = {
 923	.name = "qhs_qdss_cfg",
 924	.channels = 1,
 925	.buswidth = 4,
 926};
 927
 928static struct qcom_icc_node qhs_qspi = {
 929	.name = "qhs_qspi",
 930	.channels = 1,
 931	.buswidth = 4,
 932};
 933
 934static struct qcom_icc_node qhs_qup0 = {
 935	.name = "qhs_qup0",
 936	.channels = 1,
 937	.buswidth = 4,
 938};
 939
 940static struct qcom_icc_node qhs_qup1 = {
 941	.name = "qhs_qup1",
 942	.channels = 1,
 943	.buswidth = 4,
 944};
 945
 946static struct qcom_icc_node qhs_qup2 = {
 947	.name = "qhs_qup2",
 948	.channels = 1,
 949	.buswidth = 4,
 950};
 951
 952static struct qcom_icc_node qhs_sdc2 = {
 953	.name = "qhs_sdc2",
 954	.channels = 1,
 955	.buswidth = 4,
 956};
 957
 958static struct qcom_icc_node qhs_sdc4 = {
 959	.name = "qhs_sdc4",
 960	.channels = 1,
 961	.buswidth = 4,
 962};
 963
 964static struct qcom_icc_node qhs_spss_cfg = {
 965	.name = "qhs_spss_cfg",
 966	.channels = 1,
 967	.buswidth = 4,
 968};
 969
 970static struct qcom_icc_node qhs_tcsr = {
 971	.name = "qhs_tcsr",
 972	.channels = 1,
 973	.buswidth = 4,
 974};
 975
 976static struct qcom_icc_node qhs_tlmm = {
 977	.name = "qhs_tlmm",
 978	.channels = 1,
 979	.buswidth = 4,
 980};
 981
 982static struct qcom_icc_node qhs_tme_cfg = {
 983	.name = "qhs_tme_cfg",
 984	.channels = 1,
 985	.buswidth = 4,
 986};
 987
 988static struct qcom_icc_node qhs_ufs_mem_cfg = {
 989	.name = "qhs_ufs_mem_cfg",
 990	.channels = 1,
 991	.buswidth = 4,
 992};
 993
 994static struct qcom_icc_node qhs_usb3_0 = {
 995	.name = "qhs_usb3_0",
 996	.channels = 1,
 997	.buswidth = 4,
 998};
 999
1000static struct qcom_icc_node qhs_venus_cfg = {
1001	.name = "qhs_venus_cfg",
1002	.channels = 1,
1003	.buswidth = 4,
1004};
1005
1006static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1007	.name = "qhs_vsense_ctrl_cfg",
1008	.channels = 1,
1009	.buswidth = 4,
1010};
1011
1012static struct qcom_icc_node qns_a1_noc_cfg = {
1013	.name = "qns_a1_noc_cfg",
1014	.channels = 1,
1015	.buswidth = 4,
1016	.num_links = 1,
1017	.link_nodes = { &qnm_a1noc_cfg },
1018};
1019
1020static struct qcom_icc_node qns_a2_noc_cfg = {
1021	.name = "qns_a2_noc_cfg",
1022	.channels = 1,
1023	.buswidth = 4,
1024	.num_links = 1,
1025	.link_nodes = { &qnm_a2noc_cfg },
1026};
1027
1028static struct qcom_icc_node qns_ddrss_cfg = {
1029	.name = "qns_ddrss_cfg",
1030	.channels = 1,
1031	.buswidth = 4,
1032	//FIXME where is link
1033};
1034
1035static struct qcom_icc_node qns_mnoc_cfg = {
1036	.name = "qns_mnoc_cfg",
1037	.channels = 1,
1038	.buswidth = 4,
1039	.num_links = 1,
1040	.link_nodes = { &qnm_mnoc_cfg },
1041};
1042
1043static struct qcom_icc_node qns_pcie_anoc_cfg = {
1044	.name = "qns_pcie_anoc_cfg",
1045	.channels = 1,
1046	.buswidth = 4,
1047	.num_links = 1,
1048	.link_nodes = { &qnm_pcie_anoc_cfg },
1049};
1050
1051static struct qcom_icc_node qns_snoc_cfg = {
1052	.name = "qns_snoc_cfg",
1053	.channels = 1,
1054	.buswidth = 4,
1055	.num_links = 1,
1056	.link_nodes = { &qnm_snoc_cfg },
1057};
1058
1059static struct qcom_icc_node qxs_imem = {
1060	.name = "qxs_imem",
1061	.channels = 1,
1062	.buswidth = 8,
1063};
1064
1065static struct qcom_icc_node qxs_pimem = {
1066	.name = "qxs_pimem",
1067	.channels = 1,
1068	.buswidth = 8,
1069};
1070
1071static struct qcom_icc_node srvc_cnoc = {
1072	.name = "srvc_cnoc",
1073	.channels = 1,
1074	.buswidth = 4,
1075};
1076
1077static struct qcom_icc_node xs_pcie_0 = {
1078	.name = "xs_pcie_0",
1079	.channels = 1,
1080	.buswidth = 8,
1081};
1082
1083static struct qcom_icc_node xs_pcie_1 = {
1084	.name = "xs_pcie_1",
1085	.channels = 1,
1086	.buswidth = 8,
1087};
1088
1089static struct qcom_icc_node xs_qdss_stm = {
1090	.name = "xs_qdss_stm",
1091	.channels = 1,
1092	.buswidth = 4,
1093};
1094
1095static struct qcom_icc_node xs_sys_tcu_cfg = {
1096	.name = "xs_sys_tcu_cfg",
1097	.channels = 1,
1098	.buswidth = 8,
1099};
1100
1101static struct qcom_icc_node qns_gem_noc_cnoc = {
1102	.name = "qns_gem_noc_cnoc",
1103	.channels = 1,
1104	.buswidth = 16,
1105	.num_links = 1,
1106	.link_nodes = { &qnm_gemnoc_cnoc },
1107};
1108
1109static struct qcom_icc_node qns_llcc = {
1110	.name = "qns_llcc",
1111	.channels = 4,
1112	.buswidth = 16,
1113	.num_links = 1,
1114	.link_nodes = { &llcc_mc },
1115};
1116
1117static struct qcom_icc_node qns_pcie = {
1118	.name = "qns_pcie",
1119	.channels = 1,
1120	.buswidth = 8,
1121	.num_links = 1,
1122	.link_nodes = { &qnm_gemnoc_pcie },
1123};
1124
1125static struct qcom_icc_node qhs_lpass_core = {
1126	.name = "qhs_lpass_core",
1127	.channels = 1,
1128	.buswidth = 4,
1129};
1130
1131static struct qcom_icc_node qhs_lpass_lpi = {
1132	.name = "qhs_lpass_lpi",
1133	.channels = 1,
1134	.buswidth = 4,
1135};
1136
1137static struct qcom_icc_node qhs_lpass_mpu = {
1138	.name = "qhs_lpass_mpu",
1139	.channels = 1,
1140	.buswidth = 4,
1141};
1142
1143static struct qcom_icc_node qhs_lpass_top = {
1144	.name = "qhs_lpass_top",
1145	.channels = 1,
1146	.buswidth = 4,
1147};
1148
1149static struct qcom_icc_node qns_sysnoc = {
1150	.name = "qns_sysnoc",
1151	.channels = 1,
1152	.buswidth = 16,
1153	.num_links = 1,
1154	.link_nodes = { &qnm_lpass_noc },
1155};
1156
1157static struct qcom_icc_node srvc_niu_aml_noc = {
1158	.name = "srvc_niu_aml_noc",
1159	.channels = 1,
1160	.buswidth = 4,
1161};
1162
1163static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1164	.name = "srvc_niu_lpass_agnoc",
1165	.channels = 1,
1166	.buswidth = 4,
1167};
1168
1169static struct qcom_icc_node ebi = {
1170	.name = "ebi",
1171	.channels = 4,
1172	.buswidth = 4,
1173};
1174
1175static struct qcom_icc_node qns_mem_noc_hf = {
1176	.name = "qns_mem_noc_hf",
1177	.channels = 2,
1178	.buswidth = 32,
1179	.num_links = 1,
1180	.link_nodes = { &qnm_mnoc_hf },
1181};
1182
1183static struct qcom_icc_node qns_mem_noc_sf = {
1184	.name = "qns_mem_noc_sf",
1185	.channels = 2,
1186	.buswidth = 32,
1187	.num_links = 1,
1188	.link_nodes = { &qnm_mnoc_sf },
1189};
1190
1191static struct qcom_icc_node srvc_mnoc = {
1192	.name = "srvc_mnoc",
1193	.channels = 1,
1194	.buswidth = 4,
1195};
1196
1197static struct qcom_icc_node qns_nsp_gemnoc = {
1198	.name = "qns_nsp_gemnoc",
1199	.channels = 2,
1200	.buswidth = 32,
1201	.num_links = 1,
1202	.link_nodes = { &qnm_nsp_gemnoc },
1203};
1204
1205static struct qcom_icc_node service_nsp_noc = {
1206	.name = "service_nsp_noc",
1207	.channels = 1,
1208	.buswidth = 4,
1209};
1210
1211static struct qcom_icc_node qns_pcie_mem_noc = {
1212	.name = "qns_pcie_mem_noc",
1213	.channels = 1,
1214	.buswidth = 16,
1215	.num_links = 1,
1216	.link_nodes = { &qnm_pcie },
1217};
1218
1219static struct qcom_icc_node srvc_pcie_aggre_noc = {
1220	.name = "srvc_pcie_aggre_noc",
1221	.channels = 1,
1222	.buswidth = 4,
1223};
1224
1225static struct qcom_icc_node qns_gemnoc_gc = {
1226	.name = "qns_gemnoc_gc",
1227	.channels = 1,
1228	.buswidth = 8,
1229	.num_links = 1,
1230	.link_nodes = { &qnm_snoc_gc },
1231};
1232
1233static struct qcom_icc_node qns_gemnoc_sf = {
1234	.name = "qns_gemnoc_sf",
1235	.channels = 1,
1236	.buswidth = 16,
1237	.num_links = 1,
1238	.link_nodes = { &qnm_snoc_sf },
1239};
1240
1241static struct qcom_icc_node srvc_snoc = {
1242	.name = "srvc_snoc",
1243	.channels = 1,
1244	.buswidth = 4,
1245};
1246
1247static struct qcom_icc_node qns_llcc_disp = {
1248	.name = "qns_llcc_disp",
1249	.channels = 4,
1250	.buswidth = 16,
1251	.num_links = 1,
1252	.link_nodes = { &llcc_mc_disp },
1253};
1254
1255static struct qcom_icc_node ebi_disp = {
1256	.name = "ebi_disp",
1257	.channels = 4,
1258	.buswidth = 4,
1259};
1260
1261static struct qcom_icc_node qns_mem_noc_hf_disp = {
1262	.name = "qns_mem_noc_hf_disp",
1263	.channels = 2,
1264	.buswidth = 32,
1265	.num_links = 1,
1266	.link_nodes = { &qnm_mnoc_hf_disp },
1267};
1268
1269static struct qcom_icc_node qns_mem_noc_sf_disp = {
1270	.name = "qns_mem_noc_sf_disp",
1271	.channels = 2,
1272	.buswidth = 32,
1273	.num_links = 1,
1274	.link_nodes = { &qnm_mnoc_sf_disp },
1275};
1276
1277static struct qcom_icc_bcm bcm_acv = {
1278	.name = "ACV",
1279	.enable_mask = 0x8,
1280	.num_nodes = 1,
1281	.nodes = { &ebi },
1282};
1283
1284static struct qcom_icc_bcm bcm_ce0 = {
1285	.name = "CE0",
1286	.num_nodes = 1,
1287	.nodes = { &qxm_crypto },
1288};
1289
1290static struct qcom_icc_bcm bcm_cn0 = {
1291	.name = "CN0",
1292	.enable_mask = 0x1,
1293	.keepalive = true,
1294	.num_nodes = 55,
1295	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1296		   &qhs_ahb2phy0, &qhs_ahb2phy1,
1297		   &qhs_aoss, &qhs_camera_cfg,
1298		   &qhs_clk_ctl, &qhs_compute_cfg,
1299		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1300		   &qhs_cpr_mxa, &qhs_cpr_mxc,
1301		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
1302		   &qhs_display_cfg, &qhs_gpuss_cfg,
1303		   &qhs_imem_cfg, &qhs_ipa,
1304		   &qhs_ipc_router, &qhs_lpass_cfg,
1305		   &qhs_mss_cfg, &qhs_mx_rdpm,
1306		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1307		   &qhs_pdm, &qhs_pimem_cfg,
1308		   &qhs_prng, &qhs_qdss_cfg,
1309		   &qhs_qspi, &qhs_qup0,
1310		   &qhs_qup1, &qhs_qup2,
1311		   &qhs_sdc2, &qhs_sdc4,
1312		   &qhs_spss_cfg, &qhs_tcsr,
1313		   &qhs_tlmm, &qhs_tme_cfg,
1314		   &qhs_ufs_mem_cfg, &qhs_usb3_0,
1315		   &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1316		   &qns_a1_noc_cfg, &qns_a2_noc_cfg,
1317		   &qns_ddrss_cfg, &qns_mnoc_cfg,
1318		   &qns_pcie_anoc_cfg, &qns_snoc_cfg,
1319		   &qxs_imem, &qxs_pimem,
1320		   &srvc_cnoc, &xs_pcie_0,
1321		   &xs_pcie_1, &xs_qdss_stm,
1322		   &xs_sys_tcu_cfg },
1323};
1324
1325static struct qcom_icc_bcm bcm_co0 = {
1326	.name = "CO0",
1327	.enable_mask = 0x1,
1328	.num_nodes = 2,
1329	.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1330};
1331
1332static struct qcom_icc_bcm bcm_mc0 = {
1333	.name = "MC0",
1334	.keepalive = true,
1335	.num_nodes = 1,
1336	.nodes = { &ebi },
1337};
1338
1339static struct qcom_icc_bcm bcm_mm0 = {
1340	.name = "MM0",
1341	.keepalive = true,
1342	.num_nodes = 1,
1343	.nodes = { &qns_mem_noc_hf },
1344};
1345
1346static struct qcom_icc_bcm bcm_mm1 = {
1347	.name = "MM1",
1348	.enable_mask = 0x1,
1349	.num_nodes = 12,
1350	.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1351		   &qnm_camnoc_sf, &qnm_mdp,
1352		   &qnm_mnoc_cfg, &qnm_rot,
1353		   &qnm_vapss_hcp, &qnm_video,
1354		   &qnm_video_cv_cpu, &qnm_video_cvp,
1355		   &qnm_video_v_cpu, &qns_mem_noc_sf },
1356};
1357
1358static struct qcom_icc_bcm bcm_qup0 = {
1359	.name = "QUP0",
1360	.keepalive = true,
1361	.vote_scale = 1,
1362	.num_nodes = 1,
1363	.nodes = { &qup0_core_slave },
1364};
1365
1366static struct qcom_icc_bcm bcm_qup1 = {
1367	.name = "QUP1",
1368	.keepalive = true,
1369	.vote_scale = 1,
1370	.num_nodes = 1,
1371	.nodes = { &qup1_core_slave },
1372};
1373
1374static struct qcom_icc_bcm bcm_qup2 = {
1375	.name = "QUP2",
1376	.keepalive = true,
1377	.vote_scale = 1,
1378	.num_nodes = 1,
1379	.nodes = { &qup2_core_slave },
1380};
1381
1382static struct qcom_icc_bcm bcm_sh0 = {
1383	.name = "SH0",
1384	.keepalive = true,
1385	.num_nodes = 1,
1386	.nodes = { &qns_llcc },
1387};
1388
1389static struct qcom_icc_bcm bcm_sh1 = {
1390	.name = "SH1",
1391	.enable_mask = 0x1,
1392	.num_nodes = 7,
1393	.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1394		   &qnm_nsp_gemnoc, &qnm_pcie,
1395		   &qnm_snoc_gc, &qns_gem_noc_cnoc,
1396		   &qns_pcie },
1397};
1398
1399static struct qcom_icc_bcm bcm_sn0 = {
1400	.name = "SN0",
1401	.keepalive = true,
1402	.num_nodes = 1,
1403	.nodes = { &qns_gemnoc_sf },
1404};
1405
1406static struct qcom_icc_bcm bcm_sn1 = {
1407	.name = "SN1",
1408	.enable_mask = 0x1,
1409	.num_nodes = 4,
1410	.nodes = { &qhm_gic, &qxm_pimem,
1411		   &xm_gic, &qns_gemnoc_gc },
1412};
1413
1414static struct qcom_icc_bcm bcm_sn2 = {
1415	.name = "SN2",
1416	.num_nodes = 1,
1417	.nodes = { &qnm_aggre1_noc },
1418};
1419
1420static struct qcom_icc_bcm bcm_sn3 = {
1421	.name = "SN3",
1422	.num_nodes = 1,
1423	.nodes = { &qnm_aggre2_noc },
1424};
1425
1426static struct qcom_icc_bcm bcm_sn4 = {
1427	.name = "SN4",
1428	.num_nodes = 1,
1429	.nodes = { &qnm_lpass_noc },
1430};
1431
1432static struct qcom_icc_bcm bcm_sn7 = {
1433	.name = "SN7",
1434	.num_nodes = 1,
1435	.nodes = { &qns_pcie_mem_noc },
1436};
1437
1438static struct qcom_icc_bcm bcm_acv_disp = {
1439	.name = "ACV",
1440	.enable_mask = 0x1,
1441	.num_nodes = 1,
1442	.nodes = { &ebi_disp },
1443};
1444
1445static struct qcom_icc_bcm bcm_mc0_disp = {
1446	.name = "MC0",
1447	.num_nodes = 1,
1448	.nodes = { &ebi_disp },
1449};
1450
1451static struct qcom_icc_bcm bcm_mm0_disp = {
1452	.name = "MM0",
1453	.num_nodes = 1,
1454	.nodes = { &qns_mem_noc_hf_disp },
1455};
1456
1457static struct qcom_icc_bcm bcm_mm1_disp = {
1458	.name = "MM1",
1459	.enable_mask = 0x1,
1460	.num_nodes = 3,
1461	.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1462		   &qns_mem_noc_sf_disp },
1463};
1464
1465static struct qcom_icc_bcm bcm_sh0_disp = {
1466	.name = "SH0",
1467	.num_nodes = 1,
1468	.nodes = { &qns_llcc_disp },
1469};
1470
1471static struct qcom_icc_bcm bcm_sh1_disp = {
1472	.name = "SH1",
1473	.enable_mask = 0x1,
1474	.num_nodes = 1,
1475	.nodes = { &qnm_pcie_disp },
1476};
1477
1478static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1479};
1480
1481static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1482	[MASTER_QSPI_0] = &qhm_qspi,
1483	[MASTER_QUP_1] = &qhm_qup1,
1484	[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1485	[MASTER_SDCC_4] = &xm_sdc4,
1486	[MASTER_UFS_MEM] = &xm_ufs_mem,
1487	[MASTER_USB3_0] = &xm_usb3_0,
1488	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1489	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1490};
1491
1492static const struct qcom_icc_desc sm8450_aggre1_noc = {
1493	.nodes = aggre1_noc_nodes,
1494	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1495	.bcms = aggre1_noc_bcms,
1496	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1497};
1498
1499static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1500	&bcm_ce0,
1501};
1502
1503static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1504	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1505	[MASTER_QUP_0] = &qhm_qup0,
1506	[MASTER_QUP_2] = &qhm_qup2,
1507	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1508	[MASTER_CRYPTO] = &qxm_crypto,
1509	[MASTER_IPA] = &qxm_ipa,
1510	[MASTER_SENSORS_PROC] = &qxm_sensorss_q6,
1511	[MASTER_SP] = &qxm_sp,
1512	[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1513	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1514	[MASTER_SDCC_2] = &xm_sdc2,
1515	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1516	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1517};
1518
1519static const struct qcom_icc_desc sm8450_aggre2_noc = {
1520	.nodes = aggre2_noc_nodes,
1521	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1522	.bcms = aggre2_noc_bcms,
1523	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1524};
1525
1526static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1527	&bcm_qup0,
1528	&bcm_qup1,
1529	&bcm_qup2,
1530};
1531
1532static struct qcom_icc_node * const clk_virt_nodes[] = {
1533	[MASTER_QUP_CORE_0] = &qup0_core_master,
1534	[MASTER_QUP_CORE_1] = &qup1_core_master,
1535	[MASTER_QUP_CORE_2] = &qup2_core_master,
1536	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1537	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1538	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1539};
1540
1541static const struct qcom_icc_desc sm8450_clk_virt = {
1542	.nodes = clk_virt_nodes,
1543	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1544	.bcms = clk_virt_bcms,
1545	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1546};
1547
1548static struct qcom_icc_bcm * const config_noc_bcms[] = {
1549	&bcm_cn0,
1550};
1551
1552static struct qcom_icc_node * const config_noc_nodes[] = {
1553	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1554	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1555	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1556	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1557	[SLAVE_AOSS] = &qhs_aoss,
1558	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1559	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1560	[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1561	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1562	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1563	[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1564	[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1565	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1566	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1567	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1568	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1569	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1570	[SLAVE_IPA_CFG] = &qhs_ipa,
1571	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1572	[SLAVE_LPASS] = &qhs_lpass_cfg,
1573	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1574	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1575	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1576	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1577	[SLAVE_PDM] = &qhs_pdm,
1578	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1579	[SLAVE_PRNG] = &qhs_prng,
1580	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1581	[SLAVE_QSPI_0] = &qhs_qspi,
1582	[SLAVE_QUP_0] = &qhs_qup0,
1583	[SLAVE_QUP_1] = &qhs_qup1,
1584	[SLAVE_QUP_2] = &qhs_qup2,
1585	[SLAVE_SDCC_2] = &qhs_sdc2,
1586	[SLAVE_SDCC_4] = &qhs_sdc4,
1587	[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1588	[SLAVE_TCSR] = &qhs_tcsr,
1589	[SLAVE_TLMM] = &qhs_tlmm,
1590	[SLAVE_TME_CFG] = &qhs_tme_cfg,
1591	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1592	[SLAVE_USB3_0] = &qhs_usb3_0,
1593	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1594	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1595	[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1596	[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1597	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1598	[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1599	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1600	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1601	[SLAVE_IMEM] = &qxs_imem,
1602	[SLAVE_PIMEM] = &qxs_pimem,
1603	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1604	[SLAVE_PCIE_0] = &xs_pcie_0,
1605	[SLAVE_PCIE_1] = &xs_pcie_1,
1606	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1607	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1608};
1609
1610static const struct qcom_icc_desc sm8450_config_noc = {
1611	.nodes = config_noc_nodes,
1612	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1613	.bcms = config_noc_bcms,
1614	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1615};
1616
1617static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1618	&bcm_sh0,
1619	&bcm_sh1,
1620	&bcm_sh0_disp,
1621	&bcm_sh1_disp,
1622};
1623
1624static struct qcom_icc_node * const gem_noc_nodes[] = {
1625	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1626	[MASTER_SYS_TCU] = &alm_sys_tcu,
1627	[MASTER_APPSS_PROC] = &chm_apps,
1628	[MASTER_GFX3D] = &qnm_gpu,
1629	[MASTER_MSS_PROC] = &qnm_mdsp,
1630	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1631	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1632	[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1633	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1634	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1635	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1636	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1637	[SLAVE_LLCC] = &qns_llcc,
1638	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1639	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1640	[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1641	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1642	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1643};
1644
1645static const struct qcom_icc_desc sm8450_gem_noc = {
1646	.nodes = gem_noc_nodes,
1647	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1648	.bcms = gem_noc_bcms,
1649	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1650};
1651
1652static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1653};
1654
1655static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1656	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1657	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1658	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1659	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1660	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1661	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1662	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
1663	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1664	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1665};
1666
1667static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
1668	.nodes = lpass_ag_noc_nodes,
1669	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1670	.bcms = lpass_ag_noc_bcms,
1671	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1672};
1673
1674static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1675	&bcm_acv,
1676	&bcm_mc0,
1677	&bcm_acv_disp,
1678	&bcm_mc0_disp,
1679};
1680
1681static struct qcom_icc_node * const mc_virt_nodes[] = {
1682	[MASTER_LLCC] = &llcc_mc,
1683	[SLAVE_EBI1] = &ebi,
1684	[MASTER_LLCC_DISP] = &llcc_mc_disp,
1685	[SLAVE_EBI1_DISP] = &ebi_disp,
1686};
1687
1688static const struct qcom_icc_desc sm8450_mc_virt = {
1689	.nodes = mc_virt_nodes,
1690	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1691	.bcms = mc_virt_bcms,
1692	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1693};
1694
1695static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1696	&bcm_mm0,
1697	&bcm_mm1,
1698	&bcm_mm0_disp,
1699	&bcm_mm1_disp,
1700};
1701
1702static struct qcom_icc_node * const mmss_noc_nodes[] = {
1703	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1704	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1705	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1706	[MASTER_MDP] = &qnm_mdp,
1707	[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1708	[MASTER_ROTATOR] = &qnm_rot,
1709	[MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1710	[MASTER_VIDEO] = &qnm_video,
1711	[MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1712	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1713	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1714	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1715	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1716	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1717	[MASTER_MDP_DISP] = &qnm_mdp_disp,
1718	[MASTER_ROTATOR_DISP] = &qnm_rot_disp,
1719	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1720	[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1721};
1722
1723static const struct qcom_icc_desc sm8450_mmss_noc = {
1724	.nodes = mmss_noc_nodes,
1725	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1726	.bcms = mmss_noc_bcms,
1727	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1728};
1729
1730static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1731	&bcm_co0,
1732};
1733
1734static struct qcom_icc_node * const nsp_noc_nodes[] = {
1735	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1736	[MASTER_CDSP_PROC] = &qxm_nsp,
1737	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1738	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1739};
1740
1741static const struct qcom_icc_desc sm8450_nsp_noc = {
1742	.nodes = nsp_noc_nodes,
1743	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1744	.bcms = nsp_noc_bcms,
1745	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1746};
1747
1748static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1749	&bcm_sn7,
1750};
1751
1752static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1753	[MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg,
1754	[MASTER_PCIE_0] = &xm_pcie3_0,
1755	[MASTER_PCIE_1] = &xm_pcie3_1,
1756	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1757	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1758};
1759
1760static const struct qcom_icc_desc sm8450_pcie_anoc = {
1761	.nodes = pcie_anoc_nodes,
1762	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1763	.bcms = pcie_anoc_bcms,
1764	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1765};
1766
1767static struct qcom_icc_bcm * const system_noc_bcms[] = {
1768	&bcm_sn0,
1769	&bcm_sn1,
1770	&bcm_sn2,
1771	&bcm_sn3,
1772	&bcm_sn4,
1773};
1774
1775static struct qcom_icc_node * const system_noc_nodes[] = {
1776	[MASTER_GIC_AHB] = &qhm_gic,
1777	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1778	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1779	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
1780	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1781	[MASTER_PIMEM] = &qxm_pimem,
1782	[MASTER_GIC] = &xm_gic,
1783	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1784	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1785	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1786};
1787
1788static const struct qcom_icc_desc sm8450_system_noc = {
1789	.nodes = system_noc_nodes,
1790	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1791	.bcms = system_noc_bcms,
1792	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1793};
1794
1795static const struct of_device_id qnoc_of_match[] = {
1796	{ .compatible = "qcom,sm8450-aggre1-noc",
1797	  .data = &sm8450_aggre1_noc},
1798	{ .compatible = "qcom,sm8450-aggre2-noc",
1799	  .data = &sm8450_aggre2_noc},
1800	{ .compatible = "qcom,sm8450-clk-virt",
1801	  .data = &sm8450_clk_virt},
1802	{ .compatible = "qcom,sm8450-config-noc",
1803	  .data = &sm8450_config_noc},
1804	{ .compatible = "qcom,sm8450-gem-noc",
1805	  .data = &sm8450_gem_noc},
1806	{ .compatible = "qcom,sm8450-lpass-ag-noc",
1807	  .data = &sm8450_lpass_ag_noc},
1808	{ .compatible = "qcom,sm8450-mc-virt",
1809	  .data = &sm8450_mc_virt},
1810	{ .compatible = "qcom,sm8450-mmss-noc",
1811	  .data = &sm8450_mmss_noc},
1812	{ .compatible = "qcom,sm8450-nsp-noc",
1813	  .data = &sm8450_nsp_noc},
1814	{ .compatible = "qcom,sm8450-pcie-anoc",
1815	  .data = &sm8450_pcie_anoc},
1816	{ .compatible = "qcom,sm8450-system-noc",
1817	  .data = &sm8450_system_noc},
1818	{ }
1819};
1820MODULE_DEVICE_TABLE(of, qnoc_of_match);
1821
1822static struct platform_driver qnoc_driver = {
1823	.probe = qcom_icc_rpmh_probe,
1824	.remove = qcom_icc_rpmh_remove,
1825	.driver = {
1826		.name = "qnoc-sm8450",
1827		.of_match_table = qnoc_of_match,
1828		.sync_state = icc_sync_state,
1829	},
1830};
1831
1832static int __init qnoc_driver_init(void)
1833{
1834	return platform_driver_register(&qnoc_driver);
1835}
1836core_initcall(qnoc_driver_init);
1837
1838static void __exit qnoc_driver_exit(void)
1839{
1840	platform_driver_unregister(&qnoc_driver);
1841}
1842module_exit(qnoc_driver_exit);
1843
1844MODULE_DESCRIPTION("sm8450 NoC driver");
1845MODULE_LICENSE("GPL v2");