FILE
sm6350.c
File preview with syntax highlighting.
linux-6.19.14/drivers/interconnect/qcom/sm6350.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6#include <linux/device.h> 7#include <linux/interconnect.h> 8#include <linux/interconnect-provider.h> 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <dt-bindings/interconnect/qcom,sm6350.h> 13 14#include "bcm-voter.h" 15#include "icc-rpmh.h" 16 17static struct qcom_icc_node qhm_a1noc_cfg; 18static struct qcom_icc_node qhm_qup_0; 19static struct qcom_icc_node xm_emmc; 20static struct qcom_icc_node xm_ufs_mem; 21static struct qcom_icc_node qhm_a2noc_cfg; 22static struct qcom_icc_node qhm_qdss_bam; 23static struct qcom_icc_node qhm_qup_1; 24static struct qcom_icc_node qxm_crypto; 25static struct qcom_icc_node qxm_ipa; 26static struct qcom_icc_node xm_qdss_etr; 27static struct qcom_icc_node xm_sdc2; 28static struct qcom_icc_node xm_usb3_0; 29static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 30static struct qcom_icc_node qxm_camnoc_icp_uncomp; 31static struct qcom_icc_node qxm_camnoc_sf_uncomp; 32static struct qcom_icc_node qup0_core_master; 33static struct qcom_icc_node qup1_core_master; 34static struct qcom_icc_node qnm_npu; 35static struct qcom_icc_node qxm_npu_dsp; 36static struct qcom_icc_node qnm_snoc; 37static struct qcom_icc_node xm_qdss_dap; 38static struct qcom_icc_node qhm_cnoc_dc_noc; 39static struct qcom_icc_node acm_apps; 40static struct qcom_icc_node acm_sys_tcu; 41static struct qcom_icc_node qhm_gemnoc_cfg; 42static struct qcom_icc_node qnm_cmpnoc; 43static struct qcom_icc_node qnm_mnoc_hf; 44static struct qcom_icc_node qnm_mnoc_sf; 45static struct qcom_icc_node qnm_snoc_gc; 46static struct qcom_icc_node qnm_snoc_sf; 47static struct qcom_icc_node qxm_gpu; 48static struct qcom_icc_node llcc_mc; 49static struct qcom_icc_node qhm_mnoc_cfg; 50static struct qcom_icc_node qnm_video0; 51static struct qcom_icc_node qnm_video_cvp; 52static struct qcom_icc_node qxm_camnoc_hf; 53static struct qcom_icc_node qxm_camnoc_icp; 54static struct qcom_icc_node qxm_camnoc_sf; 55static struct qcom_icc_node qxm_mdp0; 56static struct qcom_icc_node amm_npu_sys; 57static struct qcom_icc_node qhm_npu_cfg; 58static struct qcom_icc_node qhm_snoc_cfg; 59static struct qcom_icc_node qnm_aggre1_noc; 60static struct qcom_icc_node qnm_aggre2_noc; 61static struct qcom_icc_node qnm_gemnoc; 62static struct qcom_icc_node qxm_pimem; 63static struct qcom_icc_node xm_gic; 64static struct qcom_icc_node qns_a1noc_snoc; 65static struct qcom_icc_node srvc_aggre1_noc; 66static struct qcom_icc_node qns_a2noc_snoc; 67static struct qcom_icc_node srvc_aggre2_noc; 68static struct qcom_icc_node qns_camnoc_uncomp; 69static struct qcom_icc_node qup0_core_slave; 70static struct qcom_icc_node qup1_core_slave; 71static struct qcom_icc_node qns_cdsp_gemnoc; 72static struct qcom_icc_node qhs_a1_noc_cfg; 73static struct qcom_icc_node qhs_a2_noc_cfg; 74static struct qcom_icc_node qhs_ahb2phy0; 75static struct qcom_icc_node qhs_ahb2phy2; 76static struct qcom_icc_node qhs_aoss; 77static struct qcom_icc_node qhs_boot_rom; 78static struct qcom_icc_node qhs_camera_cfg; 79static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; 80static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 81static struct qcom_icc_node qhs_clk_ctl; 82static struct qcom_icc_node qhs_cpr_cx; 83static struct qcom_icc_node qhs_cpr_mx; 84static struct qcom_icc_node qhs_crypto0_cfg; 85static struct qcom_icc_node qhs_dcc_cfg; 86static struct qcom_icc_node qhs_ddrss_cfg; 87static struct qcom_icc_node qhs_display_cfg; 88static struct qcom_icc_node qhs_display_throttle_cfg; 89static struct qcom_icc_node qhs_emmc_cfg; 90static struct qcom_icc_node qhs_glm; 91static struct qcom_icc_node qhs_gpuss_cfg; 92static struct qcom_icc_node qhs_imem_cfg; 93static struct qcom_icc_node qhs_ipa; 94static struct qcom_icc_node qhs_mnoc_cfg; 95static struct qcom_icc_node qhs_mss_cfg; 96static struct qcom_icc_node qhs_npu_cfg; 97static struct qcom_icc_node qhs_pdm; 98static struct qcom_icc_node qhs_pimem_cfg; 99static struct qcom_icc_node qhs_prng; 100static struct qcom_icc_node qhs_qdss_cfg; 101static struct qcom_icc_node qhs_qm_cfg; 102static struct qcom_icc_node qhs_qm_mpu_cfg; 103static struct qcom_icc_node qhs_qup0; 104static struct qcom_icc_node qhs_qup1; 105static struct qcom_icc_node qhs_sdc2; 106static struct qcom_icc_node qhs_security; 107static struct qcom_icc_node qhs_snoc_cfg; 108static struct qcom_icc_node qhs_tcsr; 109static struct qcom_icc_node qhs_ufs_mem_cfg; 110static struct qcom_icc_node qhs_usb3_0; 111static struct qcom_icc_node qhs_venus_cfg; 112static struct qcom_icc_node qhs_venus_throttle_cfg; 113static struct qcom_icc_node qhs_vsense_ctrl_cfg; 114static struct qcom_icc_node srvc_cnoc; 115static struct qcom_icc_node qhs_gemnoc; 116static struct qcom_icc_node qhs_llcc; 117static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg; 118static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 119static struct qcom_icc_node qns_gem_noc_snoc; 120static struct qcom_icc_node qns_llcc; 121static struct qcom_icc_node srvc_gemnoc; 122static struct qcom_icc_node ebi; 123static struct qcom_icc_node qns_mem_noc_hf; 124static struct qcom_icc_node qns_mem_noc_sf; 125static struct qcom_icc_node srvc_mnoc; 126static struct qcom_icc_node qhs_cal_dp0; 127static struct qcom_icc_node qhs_cp; 128static struct qcom_icc_node qhs_dma_bwmon; 129static struct qcom_icc_node qhs_dpm; 130static struct qcom_icc_node qhs_isense; 131static struct qcom_icc_node qhs_llm; 132static struct qcom_icc_node qhs_tcm; 133static struct qcom_icc_node qns_npu_sys; 134static struct qcom_icc_node srvc_noc; 135static struct qcom_icc_node qhs_apss; 136static struct qcom_icc_node qns_cnoc; 137static struct qcom_icc_node qns_gemnoc_gc; 138static struct qcom_icc_node qns_gemnoc_sf; 139static struct qcom_icc_node qxs_imem; 140static struct qcom_icc_node qxs_pimem; 141static struct qcom_icc_node srvc_snoc; 142static struct qcom_icc_node xs_qdss_stm; 143static struct qcom_icc_node xs_sys_tcu_cfg; 144 145static struct qcom_icc_node qhm_a1noc_cfg = { 146 .name = "qhm_a1noc_cfg", 147 .channels = 1, 148 .buswidth = 4, 149 .num_links = 1, 150 .link_nodes = { &srvc_aggre1_noc }, 151}; 152 153static struct qcom_icc_qosbox qhm_qup_0_qos = { 154 .num_ports = 1, 155 .port_offsets = { 0xa000 }, 156 .prio = 2, 157 .urg_fwd = 0, 158}; 159 160static struct qcom_icc_node qhm_qup_0 = { 161 .name = "qhm_qup_0", 162 .channels = 1, 163 .buswidth = 4, 164 .qosbox = &qhm_qup_0_qos, 165 .num_links = 1, 166 .link_nodes = { &qns_a1noc_snoc }, 167}; 168 169static struct qcom_icc_qosbox xm_emmc_qos = { 170 .num_ports = 1, 171 .port_offsets = { 0x7000 }, 172 .prio = 2, 173 .urg_fwd = 0, 174}; 175 176static struct qcom_icc_node xm_emmc = { 177 .name = "xm_emmc", 178 .channels = 1, 179 .buswidth = 8, 180 .qosbox = &xm_emmc_qos, 181 .num_links = 1, 182 .link_nodes = { &qns_a1noc_snoc }, 183}; 184 185static struct qcom_icc_qosbox xm_ufs_mem_qos = { 186 .num_ports = 1, 187 .port_offsets = { 0x8000 }, 188 .prio = 4, 189 .urg_fwd = 0, 190}; 191 192static struct qcom_icc_node xm_ufs_mem = { 193 .name = "xm_ufs_mem", 194 .channels = 1, 195 .buswidth = 8, 196 .qosbox = &xm_ufs_mem_qos, 197 .num_links = 1, 198 .link_nodes = { &qns_a1noc_snoc }, 199}; 200 201static struct qcom_icc_node qhm_a2noc_cfg = { 202 .name = "qhm_a2noc_cfg", 203 .channels = 1, 204 .buswidth = 4, 205 .num_links = 1, 206 .link_nodes = { &srvc_aggre2_noc }, 207}; 208 209static struct qcom_icc_qosbox qhm_qdss_bam_qos = { 210 .num_ports = 1, 211 .port_offsets = { 0xb000 }, 212 .prio = 2, 213 .urg_fwd = 0, 214}; 215 216static struct qcom_icc_node qhm_qdss_bam = { 217 .name = "qhm_qdss_bam", 218 .channels = 1, 219 .buswidth = 4, 220 .qosbox = &qhm_qdss_bam_qos, 221 .num_links = 1, 222 .link_nodes = { &qns_a2noc_snoc }, 223}; 224 225static struct qcom_icc_qosbox qhm_qup_1_qos = { 226 .num_ports = 1, 227 .port_offsets = { 0x9000 }, 228 .prio = 2, 229 .urg_fwd = 0, 230}; 231static struct qcom_icc_node qhm_qup_1 = { 232 .name = "qhm_qup_1", 233 .channels = 1, 234 .buswidth = 4, 235 .qosbox = &qhm_qup_1_qos, 236 .num_links = 1, 237 .link_nodes = { &qns_a2noc_snoc }, 238}; 239 240static struct qcom_icc_qosbox qxm_crypto_qos = { 241 .num_ports = 1, 242 .port_offsets = { 0x6000 }, 243 .prio = 2, 244 .urg_fwd = 0, 245}; 246 247static struct qcom_icc_node qxm_crypto = { 248 .name = "qxm_crypto", 249 .channels = 1, 250 .buswidth = 8, 251 .qosbox = &qxm_crypto_qos, 252 .num_links = 1, 253 .link_nodes = { &qns_a2noc_snoc }, 254}; 255 256static struct qcom_icc_qosbox qxm_ipa_qos = { 257 .num_ports = 1, 258 .port_offsets = { 0x7000 }, 259 .prio = 2, 260 .urg_fwd = 0, 261}; 262 263static struct qcom_icc_node qxm_ipa = { 264 .name = "qxm_ipa", 265 .channels = 1, 266 .buswidth = 8, 267 .qosbox = &qxm_ipa_qos, 268 .num_links = 1, 269 .link_nodes = { &qns_a2noc_snoc }, 270}; 271 272static struct qcom_icc_qosbox xm_qdss_etr_qos = { 273 .num_ports = 1, 274 .port_offsets = { 0xc000 }, 275 .prio = 2, 276 .urg_fwd = 0, 277}; 278 279static struct qcom_icc_node xm_qdss_etr = { 280 .name = "xm_qdss_etr", 281 .channels = 1, 282 .buswidth = 8, 283 .qosbox = &xm_qdss_etr_qos, 284 .num_links = 1, 285 .link_nodes = { &qns_a2noc_snoc }, 286}; 287 288static struct qcom_icc_qosbox xm_sdc2_qos = { 289 .num_ports = 1, 290 .port_offsets = { 0x18000 }, 291 .prio = 2, 292 .urg_fwd = 0, 293}; 294 295static struct qcom_icc_node xm_sdc2 = { 296 .name = "xm_sdc2", 297 .channels = 1, 298 .buswidth = 8, 299 .qosbox = &xm_sdc2_qos, 300 .num_links = 1, 301 .link_nodes = { &qns_a2noc_snoc }, 302}; 303 304static struct qcom_icc_qosbox xm_usb3_0_qos = { 305 .num_ports = 1, 306 .port_offsets = { 0xd000 }, 307 .prio = 2, 308 .urg_fwd = 0, 309}; 310 311static struct qcom_icc_node xm_usb3_0 = { 312 .name = "xm_usb3_0", 313 .channels = 1, 314 .buswidth = 8, 315 .qosbox = &xm_usb3_0_qos, 316 .num_links = 1, 317 .link_nodes = { &qns_a2noc_snoc }, 318}; 319 320static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 321 .name = "qxm_camnoc_hf0_uncomp", 322 .channels = 2, 323 .buswidth = 32, 324 .num_links = 1, 325 .link_nodes = { &qns_camnoc_uncomp }, 326}; 327 328static struct qcom_icc_node qxm_camnoc_icp_uncomp = { 329 .name = "qxm_camnoc_icp_uncomp", 330 .channels = 1, 331 .buswidth = 32, 332 .num_links = 1, 333 .link_nodes = { &qns_camnoc_uncomp }, 334}; 335 336static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 337 .name = "qxm_camnoc_sf_uncomp", 338 .channels = 1, 339 .buswidth = 32, 340 .num_links = 1, 341 .link_nodes = { &qns_camnoc_uncomp }, 342}; 343 344static struct qcom_icc_node qup0_core_master = { 345 .name = "qup0_core_master", 346 .channels = 1, 347 .buswidth = 4, 348 .num_links = 1, 349 .link_nodes = { &qup0_core_slave }, 350}; 351 352static struct qcom_icc_node qup1_core_master = { 353 .name = "qup1_core_master", 354 .channels = 1, 355 .buswidth = 4, 356 .num_links = 1, 357 .link_nodes = { &qup1_core_slave }, 358}; 359 360static struct qcom_icc_qosbox qnm_npu_qos = { 361 .num_ports = 2, 362 .port_offsets = { 0xf000, 0x11000 }, 363 .prio = 0, 364 .urg_fwd = 1, 365}; 366 367static struct qcom_icc_node qnm_npu = { 368 .name = "qnm_npu", 369 .channels = 2, 370 .buswidth = 32, 371 .qosbox = &qnm_npu_qos, 372 .num_links = 1, 373 .link_nodes = { &qns_cdsp_gemnoc }, 374}; 375 376static struct qcom_icc_qosbox qxm_npu_dsp_qos = { 377 .num_ports = 1, 378 .port_offsets = { 0x13000 }, 379 .prio = 0, 380 .urg_fwd = 1, 381}; 382 383static struct qcom_icc_node qxm_npu_dsp = { 384 .name = "qxm_npu_dsp", 385 .channels = 1, 386 .buswidth = 8, 387 .qosbox = &qxm_npu_dsp_qos, 388 .num_links = 1, 389 .link_nodes = { &qns_cdsp_gemnoc }, 390}; 391 392static struct qcom_icc_node qnm_snoc = { 393 .name = "qnm_snoc", 394 .channels = 1, 395 .buswidth = 8, 396 .num_links = 42, 397 .link_nodes = { &qhs_camera_cfg, 398 &qhs_sdc2, 399 &qhs_mnoc_cfg, 400 &qhs_ufs_mem_cfg, 401 &qhs_qm_cfg, 402 &qhs_snoc_cfg, 403 &qhs_qm_mpu_cfg, 404 &qhs_glm, 405 &qhs_pdm, 406 &qhs_camera_nrt_thrott_cfg, 407 &qhs_a2_noc_cfg, 408 &qhs_qdss_cfg, 409 &qhs_vsense_ctrl_cfg, 410 &qhs_camera_rt_throttle_cfg, 411 &qhs_display_cfg, 412 &qhs_tcsr, 413 &qhs_dcc_cfg, 414 &qhs_ddrss_cfg, 415 &qhs_display_throttle_cfg, 416 &qhs_npu_cfg, 417 &qhs_ahb2phy0, 418 &qhs_gpuss_cfg, 419 &qhs_boot_rom, 420 &qhs_venus_cfg, 421 &qhs_ipa, 422 &qhs_security, 423 &qhs_imem_cfg, 424 &qhs_mss_cfg, 425 &srvc_cnoc, 426 &qhs_usb3_0, 427 &qhs_venus_throttle_cfg, 428 &qhs_cpr_cx, 429 &qhs_a1_noc_cfg, 430 &qhs_aoss, 431 &qhs_prng, 432 &qhs_emmc_cfg, 433 &qhs_crypto0_cfg, 434 &qhs_pimem_cfg, 435 &qhs_cpr_mx, 436 &qhs_qup0, 437 &qhs_qup1, 438 &qhs_clk_ctl }, 439}; 440 441static struct qcom_icc_node xm_qdss_dap = { 442 .name = "xm_qdss_dap", 443 .channels = 1, 444 .buswidth = 8, 445 .num_links = 42, 446 .link_nodes = { &qhs_camera_cfg, 447 &qhs_sdc2, 448 &qhs_mnoc_cfg, 449 &qhs_ufs_mem_cfg, 450 &qhs_qm_cfg, 451 &qhs_snoc_cfg, 452 &qhs_qm_mpu_cfg, 453 &qhs_glm, 454 &qhs_pdm, 455 &qhs_camera_nrt_thrott_cfg, 456 &qhs_a2_noc_cfg, 457 &qhs_qdss_cfg, 458 &qhs_vsense_ctrl_cfg, 459 &qhs_camera_rt_throttle_cfg, 460 &qhs_display_cfg, 461 &qhs_tcsr, 462 &qhs_dcc_cfg, 463 &qhs_ddrss_cfg, 464 &qhs_display_throttle_cfg, 465 &qhs_npu_cfg, 466 &qhs_ahb2phy0, 467 &qhs_gpuss_cfg, 468 &qhs_boot_rom, 469 &qhs_venus_cfg, 470 &qhs_ipa, 471 &qhs_security, 472 &qhs_imem_cfg, 473 &qhs_mss_cfg, 474 &srvc_cnoc, 475 &qhs_usb3_0, 476 &qhs_venus_throttle_cfg, 477 &qhs_cpr_cx, 478 &qhs_a1_noc_cfg, 479 &qhs_aoss, 480 &qhs_prng, 481 &qhs_emmc_cfg, 482 &qhs_crypto0_cfg, 483 &qhs_pimem_cfg, 484 &qhs_cpr_mx, 485 &qhs_qup0, 486 &qhs_qup1, 487 &qhs_clk_ctl }, 488}; 489 490static struct qcom_icc_node qhm_cnoc_dc_noc = { 491 .name = "qhm_cnoc_dc_noc", 492 .channels = 1, 493 .buswidth = 4, 494 .num_links = 2, 495 .link_nodes = { &qhs_llcc, 496 &qhs_gemnoc }, 497}; 498 499static struct qcom_icc_qosbox acm_apps_qos = { 500 .num_ports = 2, 501 .port_offsets = { 0x2f100, 0x2f000 }, 502 .prio = 0, 503 .urg_fwd = 0, 504}; 505 506static struct qcom_icc_node acm_apps = { 507 .name = "acm_apps", 508 .channels = 1, 509 .buswidth = 16, 510 .qosbox = &acm_apps_qos, 511 .num_links = 2, 512 .link_nodes = { &qns_llcc, 513 &qns_gem_noc_snoc }, 514}; 515 516static struct qcom_icc_qosbox acm_sys_tcu_qos = { 517 .num_ports = 1, 518 .port_offsets = { 0x35000 }, 519 .prio = 6, 520 .urg_fwd = 0, 521}; 522 523static struct qcom_icc_node acm_sys_tcu = { 524 .name = "acm_sys_tcu", 525 .channels = 1, 526 .buswidth = 8, 527 .qosbox = &acm_sys_tcu_qos, 528 .num_links = 2, 529 .link_nodes = { &qns_llcc, 530 &qns_gem_noc_snoc }, 531}; 532 533static struct qcom_icc_node qhm_gemnoc_cfg = { 534 .name = "qhm_gemnoc_cfg", 535 .channels = 1, 536 .buswidth = 4, 537 .num_links = 3, 538 .link_nodes = { &qhs_mcdma_ms_mpu_cfg, 539 &srvc_gemnoc, 540 &qhs_mdsp_ms_mpu_cfg }, 541}; 542 543static struct qcom_icc_qosbox qnm_cmpnoc_qos = { 544 .num_ports = 1, 545 .port_offsets = { 0x2e000 }, 546 .prio = 0, 547 .urg_fwd = 1, 548}; 549 550static struct qcom_icc_node qnm_cmpnoc = { 551 .name = "qnm_cmpnoc", 552 .channels = 1, 553 .buswidth = 32, 554 .qosbox = &qnm_cmpnoc_qos, 555 .num_links = 2, 556 .link_nodes = { &qns_llcc, 557 &qns_gem_noc_snoc }, 558}; 559 560static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 561 .num_ports = 1, 562 .port_offsets = { 0x30000 }, 563 .prio = 0, 564 .urg_fwd = 1, 565}; 566 567static struct qcom_icc_node qnm_mnoc_hf = { 568 .name = "qnm_mnoc_hf", 569 .channels = 1, 570 .buswidth = 32, 571 .qosbox = &qnm_mnoc_hf_qos, 572 .num_links = 2, 573 .link_nodes = { &qns_llcc, 574 &qns_gem_noc_snoc }, 575}; 576 577static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 578 .num_ports = 1, 579 .port_offsets = { 0x34000 }, 580 .prio = 0, 581 .urg_fwd = 1, 582}; 583 584static struct qcom_icc_node qnm_mnoc_sf = { 585 .name = "qnm_mnoc_sf", 586 .channels = 1, 587 .buswidth = 32, 588 .qosbox = &qnm_mnoc_sf_qos, 589 .num_links = 2, 590 .link_nodes = { &qns_llcc, 591 &qns_gem_noc_snoc }, 592}; 593 594static struct qcom_icc_qosbox qnm_snoc_gc_qos = { 595 .num_ports = 1, 596 .port_offsets = { 0x32000 }, 597 .prio = 0, 598 .urg_fwd = 1, 599}; 600 601static struct qcom_icc_node qnm_snoc_gc = { 602 .name = "qnm_snoc_gc", 603 .channels = 1, 604 .buswidth = 8, 605 .qosbox = &qnm_snoc_gc_qos, 606 .num_links = 1, 607 .link_nodes = { &qns_llcc }, 608}; 609 610static struct qcom_icc_qosbox qnm_snoc_sf_qos = { 611 .num_ports = 1, 612 .port_offsets = { 0x31000 }, 613 .prio = 0, 614 .urg_fwd = 1, 615}; 616 617static struct qcom_icc_node qnm_snoc_sf = { 618 .name = "qnm_snoc_sf", 619 .channels = 1, 620 .buswidth = 16, 621 .qosbox = &qnm_snoc_sf_qos, 622 .num_links = 1, 623 .link_nodes = { &qns_llcc }, 624}; 625 626static struct qcom_icc_qosbox qxm_gpu_qos = { 627 .num_ports = 2, 628 .port_offsets = { 0x33000, 0x33080 }, 629 .prio = 0, 630 .urg_fwd = 0, 631}; 632 633static struct qcom_icc_node qxm_gpu = { 634 .name = "qxm_gpu", 635 .channels = 2, 636 .buswidth = 32, 637 .qosbox = &qxm_gpu_qos, 638 .num_links = 2, 639 .link_nodes = { &qns_llcc, 640 &qns_gem_noc_snoc }, 641}; 642 643static struct qcom_icc_node llcc_mc = { 644 .name = "llcc_mc", 645 .channels = 2, 646 .buswidth = 4, 647 .num_links = 1, 648 .link_nodes = { &ebi }, 649}; 650 651static struct qcom_icc_node qhm_mnoc_cfg = { 652 .name = "qhm_mnoc_cfg", 653 .channels = 1, 654 .buswidth = 4, 655 .num_links = 1, 656 .link_nodes = { &srvc_mnoc }, 657}; 658 659static struct qcom_icc_qosbox qnm_video0_qos = { 660 .num_ports = 1, 661 .port_offsets = { 0xf000 }, 662 .prio = 2, 663 .urg_fwd = 1, 664}; 665 666static struct qcom_icc_node qnm_video0 = { 667 .name = "qnm_video0", 668 .channels = 1, 669 .buswidth = 32, 670 .qosbox = &qnm_video0_qos, 671 .num_links = 1, 672 .link_nodes = { &qns_mem_noc_sf }, 673}; 674 675static struct qcom_icc_qosbox qnm_video_cvp_qos = { 676 .num_ports = 1, 677 .port_offsets = { 0xe000 }, 678 .prio = 5, 679 .urg_fwd = 1, 680}; 681 682static struct qcom_icc_node qnm_video_cvp = { 683 .name = "qnm_video_cvp", 684 .channels = 1, 685 .buswidth = 8, 686 .qosbox = &qnm_video_cvp_qos, 687 .num_links = 1, 688 .link_nodes = { &qns_mem_noc_sf }, 689}; 690 691static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { 692 .num_ports = 2, 693 .port_offsets = { 0xa000, 0xb000 }, 694 .prio = 3, 695 .urg_fwd = 1, 696}; 697 698static struct qcom_icc_node qxm_camnoc_hf = { 699 .name = "qxm_camnoc_hf", 700 .channels = 2, 701 .buswidth = 32, 702 .qosbox = &qxm_camnoc_hf_qos, 703 .num_links = 1, 704 .link_nodes = { &qns_mem_noc_hf }, 705}; 706 707static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { 708 .num_ports = 1, 709 .port_offsets = { 0xd000 }, 710 .prio = 5, 711 .urg_fwd = 0, 712}; 713 714static struct qcom_icc_node qxm_camnoc_icp = { 715 .name = "qxm_camnoc_icp", 716 .channels = 1, 717 .buswidth = 8, 718 .qosbox = &qxm_camnoc_icp_qos, 719 .num_links = 1, 720 .link_nodes = { &qns_mem_noc_sf }, 721}; 722 723static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { 724 .num_ports = 1, 725 .port_offsets = { 0x9000 }, 726 .prio = 3, 727 .urg_fwd = 1, 728}; 729 730static struct qcom_icc_node qxm_camnoc_sf = { 731 .name = "qxm_camnoc_sf", 732 .channels = 1, 733 .buswidth = 32, 734 .qosbox = &qxm_camnoc_sf_qos, 735 .num_links = 1, 736 .link_nodes = { &qns_mem_noc_sf }, 737}; 738 739static struct qcom_icc_qosbox qxm_mdp0_qos = { 740 .num_ports = 1, 741 .port_offsets = { 0xc000 }, 742 .prio = 3, 743 .urg_fwd = 1, 744}; 745 746static struct qcom_icc_node qxm_mdp0 = { 747 .name = "qxm_mdp0", 748 .channels = 1, 749 .buswidth = 32, 750 .qosbox = &qxm_mdp0_qos, 751 .num_links = 1, 752 .link_nodes = { &qns_mem_noc_hf }, 753}; 754 755static struct qcom_icc_node amm_npu_sys = { 756 .name = "amm_npu_sys", 757 .channels = 2, 758 .buswidth = 32, 759 .num_links = 1, 760 .link_nodes = { &qns_npu_sys }, 761}; 762 763static struct qcom_icc_node qhm_npu_cfg = { 764 .name = "qhm_npu_cfg", 765 .channels = 1, 766 .buswidth = 4, 767 .num_links = 8, 768 .link_nodes = { &srvc_noc, 769 &qhs_isense, 770 &qhs_llm, 771 &qhs_dma_bwmon, 772 &qhs_cp, 773 &qhs_tcm, 774 &qhs_cal_dp0, 775 &qhs_dpm }, 776}; 777 778static struct qcom_icc_node qhm_snoc_cfg = { 779 .name = "qhm_snoc_cfg", 780 .channels = 1, 781 .buswidth = 4, 782 .num_links = 1, 783 .link_nodes = { &srvc_snoc }, 784}; 785 786static struct qcom_icc_node qnm_aggre1_noc = { 787 .name = "qnm_aggre1_noc", 788 .channels = 1, 789 .buswidth = 16, 790 .num_links = 6, 791 .link_nodes = { &qns_gemnoc_sf, 792 &qxs_pimem, 793 &qxs_imem, 794 &qhs_apss, 795 &qns_cnoc, 796 &xs_qdss_stm }, 797}; 798 799static struct qcom_icc_node qnm_aggre2_noc = { 800 .name = "qnm_aggre2_noc", 801 .channels = 1, 802 .buswidth = 16, 803 .num_links = 7, 804 .link_nodes = { &qns_gemnoc_sf, 805 &qxs_pimem, 806 &qxs_imem, 807 &qhs_apss, 808 &qns_cnoc, 809 &xs_sys_tcu_cfg, 810 &xs_qdss_stm }, 811}; 812 813static struct qcom_icc_node qnm_gemnoc = { 814 .name = "qnm_gemnoc", 815 .channels = 1, 816 .buswidth = 8, 817 .num_links = 6, 818 .link_nodes = { &qxs_pimem, 819 &qxs_imem, 820 &qhs_apss, 821 &qns_cnoc, 822 &xs_sys_tcu_cfg, 823 &xs_qdss_stm }, 824}; 825 826static struct qcom_icc_qosbox qxm_pimem_qos = { 827 .num_ports = 1, 828 .port_offsets = { 0xd000 }, 829 .prio = 2, 830 .urg_fwd = 0, 831}; 832 833static struct qcom_icc_node qxm_pimem = { 834 .name = "qxm_pimem", 835 .channels = 1, 836 .buswidth = 8, 837 .qosbox = &qxm_pimem_qos, 838 .num_links = 2, 839 .link_nodes = { &qns_gemnoc_gc, 840 &qxs_imem }, 841}; 842 843static struct qcom_icc_qosbox xm_gic_qos = { 844 .num_ports = 1, 845 .port_offsets = { 0xb000 }, 846 .prio = 3, 847 .urg_fwd = 0, 848}; 849 850static struct qcom_icc_node xm_gic = { 851 .name = "xm_gic", 852 .channels = 1, 853 .buswidth = 8, 854 .qosbox = &xm_gic_qos, 855 .num_links = 1, 856 .link_nodes = { &qns_gemnoc_gc }, 857}; 858 859static struct qcom_icc_node qns_a1noc_snoc = { 860 .name = "qns_a1noc_snoc", 861 .channels = 1, 862 .buswidth = 16, 863 .num_links = 1, 864 .link_nodes = { &qnm_aggre1_noc }, 865}; 866 867static struct qcom_icc_node srvc_aggre1_noc = { 868 .name = "srvc_aggre1_noc", 869 .channels = 1, 870 .buswidth = 4, 871}; 872 873static struct qcom_icc_node qns_a2noc_snoc = { 874 .name = "qns_a2noc_snoc", 875 .channels = 1, 876 .buswidth = 16, 877 .num_links = 1, 878 .link_nodes = { &qnm_aggre2_noc }, 879}; 880 881static struct qcom_icc_node srvc_aggre2_noc = { 882 .name = "srvc_aggre2_noc", 883 .channels = 1, 884 .buswidth = 4, 885}; 886 887static struct qcom_icc_node qns_camnoc_uncomp = { 888 .name = "qns_camnoc_uncomp", 889 .channels = 1, 890 .buswidth = 32, 891}; 892 893static struct qcom_icc_node qup0_core_slave = { 894 .name = "qup0_core_slave", 895 .channels = 1, 896 .buswidth = 4, 897}; 898 899static struct qcom_icc_node qup1_core_slave = { 900 .name = "qup1_core_slave", 901 .channels = 1, 902 .buswidth = 4, 903}; 904 905static struct qcom_icc_node qns_cdsp_gemnoc = { 906 .name = "qns_cdsp_gemnoc", 907 .channels = 1, 908 .buswidth = 32, 909 .num_links = 1, 910 .link_nodes = { &qnm_cmpnoc }, 911}; 912 913static struct qcom_icc_node qhs_a1_noc_cfg = { 914 .name = "qhs_a1_noc_cfg", 915 .channels = 1, 916 .buswidth = 4, 917 .num_links = 1, 918 .link_nodes = { &qhm_a1noc_cfg }, 919}; 920 921static struct qcom_icc_node qhs_a2_noc_cfg = { 922 .name = "qhs_a2_noc_cfg", 923 .channels = 1, 924 .buswidth = 4, 925 .num_links = 1, 926 .link_nodes = { &qhm_a2noc_cfg }, 927}; 928 929static struct qcom_icc_node qhs_ahb2phy0 = { 930 .name = "qhs_ahb2phy0", 931 .channels = 1, 932 .buswidth = 4, 933}; 934 935static struct qcom_icc_node qhs_ahb2phy2 = { 936 .name = "qhs_ahb2phy2", 937 .channels = 1, 938 .buswidth = 4, 939}; 940 941static struct qcom_icc_node qhs_aoss = { 942 .name = "qhs_aoss", 943 .channels = 1, 944 .buswidth = 4, 945}; 946 947static struct qcom_icc_node qhs_boot_rom = { 948 .name = "qhs_boot_rom", 949 .channels = 1, 950 .buswidth = 4, 951}; 952 953static struct qcom_icc_node qhs_camera_cfg = { 954 .name = "qhs_camera_cfg", 955 .channels = 1, 956 .buswidth = 4, 957}; 958 959static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { 960 .name = "qhs_camera_nrt_thrott_cfg", 961 .channels = 1, 962 .buswidth = 4, 963}; 964 965static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 966 .name = "qhs_camera_rt_throttle_cfg", 967 .channels = 1, 968 .buswidth = 4, 969}; 970 971static struct qcom_icc_node qhs_clk_ctl = { 972 .name = "qhs_clk_ctl", 973 .channels = 1, 974 .buswidth = 4, 975}; 976 977static struct qcom_icc_node qhs_cpr_cx = { 978 .name = "qhs_cpr_cx", 979 .channels = 1, 980 .buswidth = 4, 981}; 982 983static struct qcom_icc_node qhs_cpr_mx = { 984 .name = "qhs_cpr_mx", 985 .channels = 1, 986 .buswidth = 4, 987}; 988 989static struct qcom_icc_node qhs_crypto0_cfg = { 990 .name = "qhs_crypto0_cfg", 991 .channels = 1, 992 .buswidth = 4, 993}; 994 995static struct qcom_icc_node qhs_dcc_cfg = { 996 .name = "qhs_dcc_cfg", 997 .channels = 1, 998 .buswidth = 4, 999}; 1000 1001static struct qcom_icc_node qhs_ddrss_cfg = { 1002 .name = "qhs_ddrss_cfg", 1003 .channels = 1, 1004 .buswidth = 4, 1005 .num_links = 1, 1006 .link_nodes = { &qhm_cnoc_dc_noc }, 1007}; 1008 1009static struct qcom_icc_node qhs_display_cfg = { 1010 .name = "qhs_display_cfg", 1011 .channels = 1, 1012 .buswidth = 4, 1013}; 1014 1015static struct qcom_icc_node qhs_display_throttle_cfg = { 1016 .name = "qhs_display_throttle_cfg", 1017 .channels = 1, 1018 .buswidth = 4, 1019}; 1020 1021static struct qcom_icc_node qhs_emmc_cfg = { 1022 .name = "qhs_emmc_cfg", 1023 .channels = 1, 1024 .buswidth = 4, 1025}; 1026 1027static struct qcom_icc_node qhs_glm = { 1028 .name = "qhs_glm", 1029 .channels = 1, 1030 .buswidth = 4, 1031}; 1032 1033static struct qcom_icc_node qhs_gpuss_cfg = { 1034 .name = "qhs_gpuss_cfg", 1035 .channels = 1, 1036 .buswidth = 8, 1037}; 1038 1039static struct qcom_icc_node qhs_imem_cfg = { 1040 .name = "qhs_imem_cfg", 1041 .channels = 1, 1042 .buswidth = 4, 1043}; 1044 1045static struct qcom_icc_node qhs_ipa = { 1046 .name = "qhs_ipa", 1047 .channels = 1, 1048 .buswidth = 4, 1049}; 1050 1051static struct qcom_icc_node qhs_mnoc_cfg = { 1052 .name = "qhs_mnoc_cfg", 1053 .channels = 1, 1054 .buswidth = 4, 1055 .num_links = 1, 1056 .link_nodes = { &qhm_mnoc_cfg }, 1057}; 1058 1059static struct qcom_icc_node qhs_mss_cfg = { 1060 .name = "qhs_mss_cfg", 1061 .channels = 1, 1062 .buswidth = 4, 1063}; 1064 1065static struct qcom_icc_node qhs_npu_cfg = { 1066 .name = "qhs_npu_cfg", 1067 .channels = 1, 1068 .buswidth = 4, 1069 .num_links = 1, 1070 .link_nodes = { &qhm_npu_cfg }, 1071}; 1072 1073static struct qcom_icc_node qhs_pdm = { 1074 .name = "qhs_pdm", 1075 .channels = 1, 1076 .buswidth = 4, 1077}; 1078 1079static struct qcom_icc_node qhs_pimem_cfg = { 1080 .name = "qhs_pimem_cfg", 1081 .channels = 1, 1082 .buswidth = 4, 1083}; 1084 1085static struct qcom_icc_node qhs_prng = { 1086 .name = "qhs_prng", 1087 .channels = 1, 1088 .buswidth = 4, 1089}; 1090 1091static struct qcom_icc_node qhs_qdss_cfg = { 1092 .name = "qhs_qdss_cfg", 1093 .channels = 1, 1094 .buswidth = 4, 1095}; 1096 1097static struct qcom_icc_node qhs_qm_cfg = { 1098 .name = "qhs_qm_cfg", 1099 .channels = 1, 1100 .buswidth = 4, 1101}; 1102 1103static struct qcom_icc_node qhs_qm_mpu_cfg = { 1104 .name = "qhs_qm_mpu_cfg", 1105 .channels = 1, 1106 .buswidth = 4, 1107}; 1108 1109static struct qcom_icc_node qhs_qup0 = { 1110 .name = "qhs_qup0", 1111 .channels = 1, 1112 .buswidth = 4, 1113}; 1114 1115static struct qcom_icc_node qhs_qup1 = { 1116 .name = "qhs_qup1", 1117 .channels = 1, 1118 .buswidth = 4, 1119}; 1120 1121static struct qcom_icc_node qhs_sdc2 = { 1122 .name = "qhs_sdc2", 1123 .channels = 1, 1124 .buswidth = 4, 1125}; 1126 1127static struct qcom_icc_node qhs_security = { 1128 .name = "qhs_security", 1129 .channels = 1, 1130 .buswidth = 4, 1131}; 1132 1133static struct qcom_icc_node qhs_snoc_cfg = { 1134 .name = "qhs_snoc_cfg", 1135 .channels = 1, 1136 .buswidth = 4, 1137 .num_links = 1, 1138 .link_nodes = { &qhm_snoc_cfg }, 1139}; 1140 1141static struct qcom_icc_node qhs_tcsr = { 1142 .name = "qhs_tcsr", 1143 .channels = 1, 1144 .buswidth = 4, 1145}; 1146 1147static struct qcom_icc_node qhs_ufs_mem_cfg = { 1148 .name = "qhs_ufs_mem_cfg", 1149 .channels = 1, 1150 .buswidth = 4, 1151}; 1152 1153static struct qcom_icc_node qhs_usb3_0 = { 1154 .name = "qhs_usb3_0", 1155 .channels = 1, 1156 .buswidth = 4, 1157}; 1158 1159static struct qcom_icc_node qhs_venus_cfg = { 1160 .name = "qhs_venus_cfg", 1161 .channels = 1, 1162 .buswidth = 4, 1163}; 1164 1165static struct qcom_icc_node qhs_venus_throttle_cfg = { 1166 .name = "qhs_venus_throttle_cfg", 1167 .channels = 1, 1168 .buswidth = 4, 1169}; 1170 1171static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1172 .name = "qhs_vsense_ctrl_cfg", 1173 .channels = 1, 1174 .buswidth = 4, 1175}; 1176 1177static struct qcom_icc_node srvc_cnoc = { 1178 .name = "srvc_cnoc", 1179 .channels = 1, 1180 .buswidth = 4, 1181}; 1182 1183static struct qcom_icc_node qhs_gemnoc = { 1184 .name = "qhs_gemnoc", 1185 .channels = 1, 1186 .buswidth = 4, 1187 .num_links = 1, 1188 .link_nodes = { &qhm_gemnoc_cfg }, 1189}; 1190 1191static struct qcom_icc_node qhs_llcc = { 1192 .name = "qhs_llcc", 1193 .channels = 1, 1194 .buswidth = 4, 1195}; 1196 1197static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { 1198 .name = "qhs_mcdma_ms_mpu_cfg", 1199 .channels = 1, 1200 .buswidth = 4, 1201}; 1202 1203static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1204 .name = "qhs_mdsp_ms_mpu_cfg", 1205 .channels = 1, 1206 .buswidth = 4, 1207}; 1208 1209static struct qcom_icc_node qns_gem_noc_snoc = { 1210 .name = "qns_gem_noc_snoc", 1211 .channels = 1, 1212 .buswidth = 8, 1213 .num_links = 1, 1214 .link_nodes = { &qnm_gemnoc }, 1215}; 1216 1217static struct qcom_icc_node qns_llcc = { 1218 .name = "qns_llcc", 1219 .channels = 1, 1220 .buswidth = 16, 1221 .num_links = 1, 1222 .link_nodes = { &llcc_mc }, 1223}; 1224 1225static struct qcom_icc_node srvc_gemnoc = { 1226 .name = "srvc_gemnoc", 1227 .channels = 1, 1228 .buswidth = 4, 1229}; 1230 1231static struct qcom_icc_node ebi = { 1232 .name = "ebi", 1233 .channels = 2, 1234 .buswidth = 4, 1235}; 1236 1237static struct qcom_icc_node qns_mem_noc_hf = { 1238 .name = "qns_mem_noc_hf", 1239 .channels = 1, 1240 .buswidth = 32, 1241 .num_links = 1, 1242 .link_nodes = { &qnm_mnoc_hf }, 1243}; 1244 1245static struct qcom_icc_node qns_mem_noc_sf = { 1246 .name = "qns_mem_noc_sf", 1247 .channels = 1, 1248 .buswidth = 32, 1249 .num_links = 1, 1250 .link_nodes = { &qnm_mnoc_sf }, 1251}; 1252 1253static struct qcom_icc_node srvc_mnoc = { 1254 .name = "srvc_mnoc", 1255 .channels = 1, 1256 .buswidth = 4, 1257}; 1258 1259static struct qcom_icc_node qhs_cal_dp0 = { 1260 .name = "qhs_cal_dp0", 1261 .channels = 1, 1262 .buswidth = 4, 1263}; 1264 1265static struct qcom_icc_node qhs_cp = { 1266 .name = "qhs_cp", 1267 .channels = 1, 1268 .buswidth = 4, 1269}; 1270 1271static struct qcom_icc_node qhs_dma_bwmon = { 1272 .name = "qhs_dma_bwmon", 1273 .channels = 1, 1274 .buswidth = 4, 1275}; 1276 1277static struct qcom_icc_node qhs_dpm = { 1278 .name = "qhs_dpm", 1279 .channels = 1, 1280 .buswidth = 4, 1281}; 1282 1283static struct qcom_icc_node qhs_isense = { 1284 .name = "qhs_isense", 1285 .channels = 1, 1286 .buswidth = 4, 1287}; 1288 1289static struct qcom_icc_node qhs_llm = { 1290 .name = "qhs_llm", 1291 .channels = 1, 1292 .buswidth = 4, 1293}; 1294 1295static struct qcom_icc_node qhs_tcm = { 1296 .name = "qhs_tcm", 1297 .channels = 1, 1298 .buswidth = 4, 1299}; 1300 1301static struct qcom_icc_node qns_npu_sys = { 1302 .name = "qns_npu_sys", 1303 .channels = 2, 1304 .buswidth = 32, 1305}; 1306 1307static struct qcom_icc_node srvc_noc = { 1308 .name = "srvc_noc", 1309 .channels = 1, 1310 .buswidth = 4, 1311}; 1312 1313static struct qcom_icc_node qhs_apss = { 1314 .name = "qhs_apss", 1315 .channels = 1, 1316 .buswidth = 8, 1317}; 1318 1319static struct qcom_icc_node qns_cnoc = { 1320 .name = "qns_cnoc", 1321 .channels = 1, 1322 .buswidth = 8, 1323 .num_links = 1, 1324 .link_nodes = { &qnm_snoc }, 1325}; 1326 1327static struct qcom_icc_node qns_gemnoc_gc = { 1328 .name = "qns_gemnoc_gc", 1329 .channels = 1, 1330 .buswidth = 8, 1331 .num_links = 1, 1332 .link_nodes = { &qnm_snoc_gc }, 1333}; 1334 1335static struct qcom_icc_node qns_gemnoc_sf = { 1336 .name = "qns_gemnoc_sf", 1337 .channels = 1, 1338 .buswidth = 16, 1339 .num_links = 1, 1340 .link_nodes = { &qnm_snoc_sf }, 1341}; 1342 1343static struct qcom_icc_node qxs_imem = { 1344 .name = "qxs_imem", 1345 .channels = 1, 1346 .buswidth = 8, 1347}; 1348 1349static struct qcom_icc_node qxs_pimem = { 1350 .name = "qxs_pimem", 1351 .channels = 1, 1352 .buswidth = 8, 1353}; 1354 1355static struct qcom_icc_node srvc_snoc = { 1356 .name = "srvc_snoc", 1357 .channels = 1, 1358 .buswidth = 4, 1359}; 1360 1361static struct qcom_icc_node xs_qdss_stm = { 1362 .name = "xs_qdss_stm", 1363 .channels = 1, 1364 .buswidth = 4, 1365}; 1366 1367static struct qcom_icc_node xs_sys_tcu_cfg = { 1368 .name = "xs_sys_tcu_cfg", 1369 .channels = 1, 1370 .buswidth = 8, 1371}; 1372 1373static struct qcom_icc_bcm bcm_acv = { 1374 .name = "ACV", 1375 .enable_mask = BIT(3), 1376 .keepalive = false, 1377 .num_nodes = 1, 1378 .nodes = { &ebi }, 1379}; 1380 1381static struct qcom_icc_bcm bcm_ce0 = { 1382 .name = "CE0", 1383 .keepalive = false, 1384 .num_nodes = 1, 1385 .nodes = { &qxm_crypto }, 1386}; 1387 1388static struct qcom_icc_bcm bcm_cn0 = { 1389 .name = "CN0", 1390 .keepalive = true, 1391 .num_nodes = 41, 1392 .nodes = { &qnm_snoc, 1393 &xm_qdss_dap, 1394 &qhs_a1_noc_cfg, 1395 &qhs_a2_noc_cfg, 1396 &qhs_ahb2phy0, 1397 &qhs_aoss, 1398 &qhs_boot_rom, 1399 &qhs_camera_cfg, 1400 &qhs_camera_nrt_thrott_cfg, 1401 &qhs_camera_rt_throttle_cfg, 1402 &qhs_clk_ctl, 1403 &qhs_cpr_cx, 1404 &qhs_cpr_mx, 1405 &qhs_crypto0_cfg, 1406 &qhs_dcc_cfg, 1407 &qhs_ddrss_cfg, 1408 &qhs_display_cfg, 1409 &qhs_display_throttle_cfg, 1410 &qhs_glm, 1411 &qhs_gpuss_cfg, 1412 &qhs_imem_cfg, 1413 &qhs_ipa, 1414 &qhs_mnoc_cfg, 1415 &qhs_mss_cfg, 1416 &qhs_npu_cfg, 1417 &qhs_pimem_cfg, 1418 &qhs_prng, 1419 &qhs_qdss_cfg, 1420 &qhs_qm_cfg, 1421 &qhs_qm_mpu_cfg, 1422 &qhs_qup0, 1423 &qhs_qup1, 1424 &qhs_security, 1425 &qhs_snoc_cfg, 1426 &qhs_tcsr, 1427 &qhs_ufs_mem_cfg, 1428 &qhs_usb3_0, 1429 &qhs_venus_cfg, 1430 &qhs_venus_throttle_cfg, 1431 &qhs_vsense_ctrl_cfg, 1432 &srvc_cnoc 1433 }, 1434}; 1435 1436static struct qcom_icc_bcm bcm_cn1 = { 1437 .name = "CN1", 1438 .keepalive = false, 1439 .num_nodes = 6, 1440 .nodes = { &xm_emmc, 1441 &xm_sdc2, 1442 &qhs_ahb2phy2, 1443 &qhs_emmc_cfg, 1444 &qhs_pdm, 1445 &qhs_sdc2 1446 }, 1447}; 1448 1449static struct qcom_icc_bcm bcm_co0 = { 1450 .name = "CO0", 1451 .keepalive = false, 1452 .num_nodes = 1, 1453 .nodes = { &qns_cdsp_gemnoc }, 1454}; 1455 1456static struct qcom_icc_bcm bcm_co2 = { 1457 .name = "CO2", 1458 .keepalive = false, 1459 .num_nodes = 1, 1460 .nodes = { &qnm_npu }, 1461}; 1462 1463static struct qcom_icc_bcm bcm_co3 = { 1464 .name = "CO3", 1465 .keepalive = false, 1466 .num_nodes = 1, 1467 .nodes = { &qxm_npu_dsp }, 1468}; 1469 1470static struct qcom_icc_bcm bcm_mc0 = { 1471 .name = "MC0", 1472 .keepalive = true, 1473 .num_nodes = 1, 1474 .nodes = { &ebi }, 1475}; 1476 1477static struct qcom_icc_bcm bcm_mm0 = { 1478 .name = "MM0", 1479 .keepalive = true, 1480 .num_nodes = 1, 1481 .nodes = { &qns_mem_noc_hf }, 1482}; 1483 1484static struct qcom_icc_bcm bcm_mm1 = { 1485 .name = "MM1", 1486 .keepalive = true, 1487 .num_nodes = 5, 1488 .nodes = { &qxm_camnoc_hf0_uncomp, 1489 &qxm_camnoc_icp_uncomp, 1490 &qxm_camnoc_sf_uncomp, 1491 &qxm_camnoc_hf, 1492 &qxm_mdp0 1493 }, 1494}; 1495 1496static struct qcom_icc_bcm bcm_mm2 = { 1497 .name = "MM2", 1498 .keepalive = false, 1499 .num_nodes = 1, 1500 .nodes = { &qns_mem_noc_sf }, 1501}; 1502 1503static struct qcom_icc_bcm bcm_mm3 = { 1504 .name = "MM3", 1505 .keepalive = false, 1506 .num_nodes = 4, 1507 .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf }, 1508}; 1509 1510static struct qcom_icc_bcm bcm_qup0 = { 1511 .name = "QUP0", 1512 .keepalive = false, 1513 .num_nodes = 4, 1514 .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave }, 1515}; 1516 1517static struct qcom_icc_bcm bcm_sh0 = { 1518 .name = "SH0", 1519 .keepalive = true, 1520 .num_nodes = 1, 1521 .nodes = { &qns_llcc }, 1522}; 1523 1524static struct qcom_icc_bcm bcm_sh2 = { 1525 .name = "SH2", 1526 .keepalive = false, 1527 .num_nodes = 1, 1528 .nodes = { &acm_sys_tcu }, 1529}; 1530 1531static struct qcom_icc_bcm bcm_sh3 = { 1532 .name = "SH3", 1533 .keepalive = false, 1534 .num_nodes = 1, 1535 .nodes = { &qnm_cmpnoc }, 1536}; 1537 1538static struct qcom_icc_bcm bcm_sh4 = { 1539 .name = "SH4", 1540 .keepalive = false, 1541 .num_nodes = 1, 1542 .nodes = { &acm_apps }, 1543}; 1544 1545static struct qcom_icc_bcm bcm_sn0 = { 1546 .name = "SN0", 1547 .keepalive = true, 1548 .num_nodes = 1, 1549 .nodes = { &qns_gemnoc_sf }, 1550}; 1551 1552static struct qcom_icc_bcm bcm_sn1 = { 1553 .name = "SN1", 1554 .keepalive = false, 1555 .num_nodes = 1, 1556 .nodes = { &qxs_imem }, 1557}; 1558 1559static struct qcom_icc_bcm bcm_sn2 = { 1560 .name = "SN2", 1561 .keepalive = false, 1562 .num_nodes = 1, 1563 .nodes = { &qns_gemnoc_gc }, 1564}; 1565 1566static struct qcom_icc_bcm bcm_sn3 = { 1567 .name = "SN3", 1568 .keepalive = false, 1569 .num_nodes = 1, 1570 .nodes = { &qxs_pimem }, 1571}; 1572 1573static struct qcom_icc_bcm bcm_sn4 = { 1574 .name = "SN4", 1575 .keepalive = false, 1576 .num_nodes = 1, 1577 .nodes = { &xs_qdss_stm }, 1578}; 1579 1580static struct qcom_icc_bcm bcm_sn5 = { 1581 .name = "SN5", 1582 .keepalive = false, 1583 .num_nodes = 1, 1584 .nodes = { &qnm_aggre1_noc }, 1585}; 1586 1587static struct qcom_icc_bcm bcm_sn6 = { 1588 .name = "SN6", 1589 .keepalive = false, 1590 .num_nodes = 1, 1591 .nodes = { &qnm_aggre2_noc }, 1592}; 1593 1594static struct qcom_icc_bcm bcm_sn10 = { 1595 .name = "SN10", 1596 .keepalive = false, 1597 .num_nodes = 1, 1598 .nodes = { &qnm_gemnoc }, 1599}; 1600 1601static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1602 &bcm_cn1, 1603}; 1604 1605static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1606 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1607 [MASTER_QUP_0] = &qhm_qup_0, 1608 [MASTER_EMMC] = &xm_emmc, 1609 [MASTER_UFS_MEM] = &xm_ufs_mem, 1610 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1611 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1612}; 1613 1614static const struct regmap_config sm6350_aggre1_noc_regmap_config = { 1615 .reg_bits = 32, 1616 .reg_stride = 4, 1617 .val_bits = 32, 1618 .max_register = 0x15080, 1619 .fast_io = true, 1620}; 1621 1622static const struct qcom_icc_desc sm6350_aggre1_noc = { 1623 .config = &sm6350_aggre1_noc_regmap_config, 1624 .nodes = aggre1_noc_nodes, 1625 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1626 .bcms = aggre1_noc_bcms, 1627 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1628 .qos_requires_clocks = true, 1629}; 1630 1631static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1632 &bcm_ce0, 1633 &bcm_cn1, 1634}; 1635 1636static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1637 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1638 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1639 [MASTER_QUP_1] = &qhm_qup_1, 1640 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1641 [MASTER_IPA] = &qxm_ipa, 1642 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1643 [MASTER_SDCC_2] = &xm_sdc2, 1644 [MASTER_USB3] = &xm_usb3_0, 1645 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1646 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1647}; 1648 1649static const struct regmap_config sm6350_aggre2_noc_regmap_config = { 1650 .reg_bits = 32, 1651 .reg_stride = 4, 1652 .val_bits = 32, 1653 .max_register = 0x1f880, 1654 .fast_io = true, 1655}; 1656 1657static const struct qcom_icc_desc sm6350_aggre2_noc = { 1658 .config = &sm6350_aggre2_noc_regmap_config, 1659 .nodes = aggre2_noc_nodes, 1660 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1661 .bcms = aggre2_noc_bcms, 1662 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1663 .qos_requires_clocks = true, 1664}; 1665 1666static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1667 &bcm_acv, 1668 &bcm_mc0, 1669 &bcm_mm1, 1670 &bcm_qup0, 1671}; 1672 1673static struct qcom_icc_node * const clk_virt_nodes[] = { 1674 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1675 [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp, 1676 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1677 [MASTER_QUP_CORE_0] = &qup0_core_master, 1678 [MASTER_QUP_CORE_1] = &qup1_core_master, 1679 [MASTER_LLCC] = &llcc_mc, 1680 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1681 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1682 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1683 [SLAVE_EBI_CH0] = &ebi, 1684}; 1685 1686static const struct qcom_icc_desc sm6350_clk_virt = { 1687 .nodes = clk_virt_nodes, 1688 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1689 .bcms = clk_virt_bcms, 1690 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1691}; 1692 1693static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1694 &bcm_co0, 1695 &bcm_co2, 1696 &bcm_co3, 1697}; 1698 1699static struct qcom_icc_node * const compute_noc_nodes[] = { 1700 [MASTER_NPU] = &qnm_npu, 1701 [MASTER_NPU_PROC] = &qxm_npu_dsp, 1702 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1703}; 1704 1705static const struct regmap_config sm6350_compute_noc_regmap_config = { 1706 .reg_bits = 32, 1707 .reg_stride = 4, 1708 .val_bits = 32, 1709 .max_register = 0x1f880, 1710 .fast_io = true, 1711}; 1712 1713static const struct qcom_icc_desc sm6350_compute_noc = { 1714 .config = &sm6350_compute_noc_regmap_config, 1715 .nodes = compute_noc_nodes, 1716 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1717 .bcms = compute_noc_bcms, 1718 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1719}; 1720 1721static struct qcom_icc_bcm * const config_noc_bcms[] = { 1722 &bcm_cn0, 1723 &bcm_cn1, 1724}; 1725 1726static struct qcom_icc_node * const config_noc_nodes[] = { 1727 [SNOC_CNOC_MAS] = &qnm_snoc, 1728 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1729 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1730 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1731 [SLAVE_AHB2PHY] = &qhs_ahb2phy0, 1732 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1733 [SLAVE_AOSS] = &qhs_aoss, 1734 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1735 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1736 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, 1737 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1738 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1739 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1740 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1741 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1742 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1743 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1744 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1745 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1746 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1747 [SLAVE_GLM] = &qhs_glm, 1748 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1749 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1750 [SLAVE_IPA_CFG] = &qhs_ipa, 1751 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1752 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1753 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1754 [SLAVE_PDM] = &qhs_pdm, 1755 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1756 [SLAVE_PRNG] = &qhs_prng, 1757 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1758 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1759 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1760 [SLAVE_QUP_0] = &qhs_qup0, 1761 [SLAVE_QUP_1] = &qhs_qup1, 1762 [SLAVE_SDCC_2] = &qhs_sdc2, 1763 [SLAVE_SECURITY] = &qhs_security, 1764 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1765 [SLAVE_TCSR] = &qhs_tcsr, 1766 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1767 [SLAVE_USB3] = &qhs_usb3_0, 1768 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1769 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1770 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1771 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1772}; 1773 1774static const struct qcom_icc_desc sm6350_config_noc = { 1775 .nodes = config_noc_nodes, 1776 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1777 .bcms = config_noc_bcms, 1778 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1779}; 1780 1781static struct qcom_icc_node * const dc_noc_nodes[] = { 1782 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1783 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1784 [SLAVE_LLCC_CFG] = &qhs_llcc, 1785}; 1786 1787static const struct regmap_config sm6350_dc_noc_regmap_config = { 1788 .reg_bits = 32, 1789 .reg_stride = 4, 1790 .val_bits = 32, 1791 .max_register = 0x3200, 1792 .fast_io = true, 1793}; 1794 1795static const struct qcom_icc_desc sm6350_dc_noc = { 1796 .config = &sm6350_dc_noc_regmap_config, 1797 .nodes = dc_noc_nodes, 1798 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1799}; 1800 1801static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1802 &bcm_sh0, 1803 &bcm_sh2, 1804 &bcm_sh3, 1805 &bcm_sh4, 1806}; 1807 1808static struct qcom_icc_node * const gem_noc_nodes[] = { 1809 [MASTER_AMPSS_M0] = &acm_apps, 1810 [MASTER_SYS_TCU] = &acm_sys_tcu, 1811 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1812 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1813 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1814 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1815 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1816 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1817 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1818 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg, 1819 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1820 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1821 [SLAVE_LLCC] = &qns_llcc, 1822 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1823}; 1824 1825static const struct regmap_config sm6350_gem_noc_regmap_config = { 1826 .reg_bits = 32, 1827 .reg_stride = 4, 1828 .val_bits = 32, 1829 .max_register = 0x3e200, 1830 .fast_io = true, 1831}; 1832 1833static const struct qcom_icc_desc sm6350_gem_noc = { 1834 .config = &sm6350_gem_noc_regmap_config, 1835 .nodes = gem_noc_nodes, 1836 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1837 .bcms = gem_noc_bcms, 1838 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1839}; 1840 1841static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1842 &bcm_mm0, 1843 &bcm_mm1, 1844 &bcm_mm2, 1845 &bcm_mm3, 1846}; 1847 1848static struct qcom_icc_node * const mmss_noc_nodes[] = { 1849 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1850 [MASTER_VIDEO_P0] = &qnm_video0, 1851 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1852 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 1853 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 1854 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1855 [MASTER_MDP_PORT0] = &qxm_mdp0, 1856 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1857 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1858 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1859}; 1860 1861static const struct regmap_config sm6350_mmss_noc_regmap_config = { 1862 .reg_bits = 32, 1863 .reg_stride = 4, 1864 .val_bits = 32, 1865 .max_register = 0x1c100, 1866 .fast_io = true, 1867}; 1868 1869static const struct qcom_icc_desc sm6350_mmss_noc = { 1870 .config = &sm6350_mmss_noc_regmap_config, 1871 .nodes = mmss_noc_nodes, 1872 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1873 .bcms = mmss_noc_bcms, 1874 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1875}; 1876 1877static struct qcom_icc_node * const npu_noc_nodes[] = { 1878 [MASTER_NPU_SYS] = &amm_npu_sys, 1879 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, 1880 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1881 [SLAVE_NPU_CP] = &qhs_cp, 1882 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1883 [SLAVE_NPU_DPM] = &qhs_dpm, 1884 [SLAVE_ISENSE_CFG] = &qhs_isense, 1885 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1886 [SLAVE_NPU_TCM] = &qhs_tcm, 1887 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1888 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1889}; 1890 1891static const struct qcom_icc_desc sm6350_npu_noc = { 1892 .nodes = npu_noc_nodes, 1893 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1894}; 1895 1896static struct qcom_icc_bcm * const system_noc_bcms[] = { 1897 &bcm_sn0, 1898 &bcm_sn1, 1899 &bcm_sn10, 1900 &bcm_sn2, 1901 &bcm_sn3, 1902 &bcm_sn4, 1903 &bcm_sn5, 1904 &bcm_sn6, 1905}; 1906 1907static struct qcom_icc_node * const system_noc_nodes[] = { 1908 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1909 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1910 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1911 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1912 [MASTER_PIMEM] = &qxm_pimem, 1913 [MASTER_GIC] = &xm_gic, 1914 [SLAVE_APPSS] = &qhs_apss, 1915 [SNOC_CNOC_SLV] = &qns_cnoc, 1916 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1917 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1918 [SLAVE_OCIMEM] = &qxs_imem, 1919 [SLAVE_PIMEM] = &qxs_pimem, 1920 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1921 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1922 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1923}; 1924 1925static const struct regmap_config sm6350_system_noc_regmap_config = { 1926 .reg_bits = 32, 1927 .reg_stride = 4, 1928 .val_bits = 32, 1929 .max_register = 0x17080, 1930 .fast_io = true, 1931}; 1932 1933static const struct qcom_icc_desc sm6350_system_noc = { 1934 .config = &sm6350_system_noc_regmap_config, 1935 .nodes = system_noc_nodes, 1936 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1937 .bcms = system_noc_bcms, 1938 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1939}; 1940 1941static const struct of_device_id qnoc_of_match[] = { 1942 { .compatible = "qcom,sm6350-aggre1-noc", 1943 .data = &sm6350_aggre1_noc}, 1944 { .compatible = "qcom,sm6350-aggre2-noc", 1945 .data = &sm6350_aggre2_noc}, 1946 { .compatible = "qcom,sm6350-clk-virt", 1947 .data = &sm6350_clk_virt}, 1948 { .compatible = "qcom,sm6350-compute-noc", 1949 .data = &sm6350_compute_noc}, 1950 { .compatible = "qcom,sm6350-config-noc", 1951 .data = &sm6350_config_noc}, 1952 { .compatible = "qcom,sm6350-dc-noc", 1953 .data = &sm6350_dc_noc}, 1954 { .compatible = "qcom,sm6350-gem-noc", 1955 .data = &sm6350_gem_noc}, 1956 { .compatible = "qcom,sm6350-mmss-noc", 1957 .data = &sm6350_mmss_noc}, 1958 { .compatible = "qcom,sm6350-npu-noc", 1959 .data = &sm6350_npu_noc}, 1960 { .compatible = "qcom,sm6350-system-noc", 1961 .data = &sm6350_system_noc}, 1962 { } 1963}; 1964MODULE_DEVICE_TABLE(of, qnoc_of_match); 1965 1966static struct platform_driver qnoc_driver = { 1967 .probe = qcom_icc_rpmh_probe, 1968 .remove = qcom_icc_rpmh_remove, 1969 .driver = { 1970 .name = "qnoc-sm6350", 1971 .of_match_table = qnoc_of_match, 1972 .sync_state = icc_sync_state, 1973 }, 1974}; 1975module_platform_driver(qnoc_driver); 1976 1977MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver"); 1978MODULE_LICENSE("GPL v2");
~/
Read-only file preview.