sdx75.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4 *
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/module.h>
  11#include <linux/of_platform.h>
  12#include <dt-bindings/interconnect/qcom,sdx75.h>
  13
  14#include "bcm-voter.h"
  15#include "icc-common.h"
  16#include "icc-rpmh.h"
  17
  18static struct qcom_icc_node qup0_core_master;
  19static struct qcom_icc_node qnm_cnoc;
  20static struct qcom_icc_node alm_sys_tcu;
  21static struct qcom_icc_node chm_apps;
  22static struct qcom_icc_node qnm_gemnoc_cfg;
  23static struct qcom_icc_node qnm_mdsp;
  24static struct qcom_icc_node qnm_pcie;
  25static struct qcom_icc_node qnm_snoc_sf;
  26static struct qcom_icc_node xm_gic;
  27static struct qcom_icc_node xm_ipa2pcie;
  28static struct qcom_icc_node llcc_mc;
  29static struct qcom_icc_node xm_pcie3_0;
  30static struct qcom_icc_node xm_pcie3_1;
  31static struct qcom_icc_node xm_pcie3_2;
  32static struct qcom_icc_node qhm_audio;
  33static struct qcom_icc_node qhm_gic;
  34static struct qcom_icc_node qhm_pcie_rscc;
  35static struct qcom_icc_node qhm_qdss_bam;
  36static struct qcom_icc_node qhm_qpic;
  37static struct qcom_icc_node qhm_qup0;
  38static struct qcom_icc_node qnm_aggre_noc;
  39static struct qcom_icc_node qnm_gemnoc_cnoc;
  40static struct qcom_icc_node qnm_gemnoc_pcie;
  41static struct qcom_icc_node qnm_system_noc_cfg;
  42static struct qcom_icc_node qnm_system_noc_pcie_cfg;
  43static struct qcom_icc_node qxm_crypto;
  44static struct qcom_icc_node qxm_ipa;
  45static struct qcom_icc_node qxm_mvmss;
  46static struct qcom_icc_node xm_emac_0;
  47static struct qcom_icc_node xm_emac_1;
  48static struct qcom_icc_node xm_qdss_etr0;
  49static struct qcom_icc_node xm_qdss_etr1;
  50static struct qcom_icc_node xm_sdc1;
  51static struct qcom_icc_node xm_sdc4;
  52static struct qcom_icc_node xm_usb3;
  53static struct qcom_icc_node qup0_core_slave;
  54static struct qcom_icc_node qhs_lagg;
  55static struct qcom_icc_node qhs_mccc_master;
  56static struct qcom_icc_node qns_gemnoc;
  57static struct qcom_icc_node qss_snoop_bwmon;
  58static struct qcom_icc_node qns_gemnoc_cnoc;
  59static struct qcom_icc_node qns_llcc;
  60static struct qcom_icc_node qns_pcie;
  61static struct qcom_icc_node srvc_gemnoc;
  62static struct qcom_icc_node ebi;
  63static struct qcom_icc_node qns_pcie_gemnoc;
  64static struct qcom_icc_node ps_eth0_cfg;
  65static struct qcom_icc_node ps_eth1_cfg;
  66static struct qcom_icc_node qhs_audio;
  67static struct qcom_icc_node qhs_clk_ctl;
  68static struct qcom_icc_node qhs_crypto_cfg;
  69static struct qcom_icc_node qhs_imem_cfg;
  70static struct qcom_icc_node qhs_ipa;
  71static struct qcom_icc_node qhs_ipc_router;
  72static struct qcom_icc_node qhs_mss_cfg;
  73static struct qcom_icc_node qhs_mvmss_cfg;
  74static struct qcom_icc_node qhs_pcie0_cfg;
  75static struct qcom_icc_node qhs_pcie1_cfg;
  76static struct qcom_icc_node qhs_pcie2_cfg;
  77static struct qcom_icc_node qhs_pcie_rscc;
  78static struct qcom_icc_node qhs_pdm;
  79static struct qcom_icc_node qhs_prng;
  80static struct qcom_icc_node qhs_qdss_cfg;
  81static struct qcom_icc_node qhs_qpic;
  82static struct qcom_icc_node qhs_qup0;
  83static struct qcom_icc_node qhs_sdc1;
  84static struct qcom_icc_node qhs_sdc4;
  85static struct qcom_icc_node qhs_spmi_vgi_coex;
  86static struct qcom_icc_node qhs_tcsr;
  87static struct qcom_icc_node qhs_tlmm;
  88static struct qcom_icc_node qhs_usb3;
  89static struct qcom_icc_node qhs_usb3_phy;
  90static struct qcom_icc_node qns_a1noc;
  91static struct qcom_icc_node qns_ddrss_cfg;
  92static struct qcom_icc_node qns_gemnoc_sf;
  93static struct qcom_icc_node qns_system_noc_cfg;
  94static struct qcom_icc_node qns_system_noc_pcie_cfg;
  95static struct qcom_icc_node qxs_imem;
  96static struct qcom_icc_node srvc_pcie_system_noc;
  97static struct qcom_icc_node srvc_system_noc;
  98static struct qcom_icc_node xs_pcie_0;
  99static struct qcom_icc_node xs_pcie_1;
 100static struct qcom_icc_node xs_pcie_2;
 101static struct qcom_icc_node xs_qdss_stm;
 102static struct qcom_icc_node xs_sys_tcu_cfg;
 103
 104static struct qcom_icc_node qup0_core_master = {
 105	.name = "qup0_core_master",
 106	.channels = 1,
 107	.buswidth = 4,
 108	.num_links = 1,
 109	.link_nodes = { &qup0_core_slave },
 110};
 111
 112static struct qcom_icc_node qnm_cnoc = {
 113	.name = "qnm_cnoc",
 114	.channels = 1,
 115	.buswidth = 4,
 116	.num_links = 4,
 117	.link_nodes = { &qhs_lagg, &qhs_mccc_master,
 118			&qns_gemnoc, &qss_snoop_bwmon },
 119};
 120
 121static struct qcom_icc_node alm_sys_tcu = {
 122	.name = "alm_sys_tcu",
 123	.channels = 1,
 124	.buswidth = 8,
 125	.num_links = 2,
 126	.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc },
 127};
 128
 129static struct qcom_icc_node chm_apps = {
 130	.name = "chm_apps",
 131	.channels = 1,
 132	.buswidth = 16,
 133	.num_links = 3,
 134	.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
 135			&qns_pcie },
 136};
 137
 138static struct qcom_icc_node qnm_gemnoc_cfg = {
 139	.name = "qnm_gemnoc_cfg",
 140	.channels = 1,
 141	.buswidth = 4,
 142	.num_links = 1,
 143	.link_nodes = { &srvc_gemnoc },
 144};
 145
 146static struct qcom_icc_node qnm_mdsp = {
 147	.name = "qnm_mdsp",
 148	.channels = 1,
 149	.buswidth = 16,
 150	.num_links = 3,
 151	.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
 152			&qns_pcie },
 153};
 154
 155static struct qcom_icc_node qnm_pcie = {
 156	.name = "qnm_pcie",
 157	.channels = 1,
 158	.buswidth = 16,
 159	.num_links = 2,
 160	.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc },
 161};
 162
 163static struct qcom_icc_node qnm_snoc_sf = {
 164	.name = "qnm_snoc_sf",
 165	.channels = 1,
 166	.buswidth = 16,
 167	.num_links = 3,
 168	.link_nodes = { &qns_gemnoc_cnoc, &qns_llcc,
 169			&qns_pcie },
 170};
 171
 172static struct qcom_icc_node xm_gic = {
 173	.name = "xm_gic",
 174	.channels = 1,
 175	.buswidth = 8,
 176	.num_links = 1,
 177	.link_nodes = { &qns_llcc },
 178};
 179
 180static struct qcom_icc_node xm_ipa2pcie = {
 181	.name = "xm_ipa2pcie",
 182	.channels = 1,
 183	.buswidth = 8,
 184	.num_links = 1,
 185	.link_nodes = { &qns_pcie },
 186};
 187
 188static struct qcom_icc_node llcc_mc = {
 189	.name = "llcc_mc",
 190	.channels = 1,
 191	.buswidth = 4,
 192	.num_links = 1,
 193	.link_nodes = { &ebi },
 194};
 195
 196static struct qcom_icc_node xm_pcie3_0 = {
 197	.name = "xm_pcie3_0",
 198	.channels = 1,
 199	.buswidth = 8,
 200	.num_links = 1,
 201	.link_nodes = { &qns_pcie_gemnoc },
 202};
 203
 204static struct qcom_icc_node xm_pcie3_1 = {
 205	.name = "xm_pcie3_1",
 206	.channels = 1,
 207	.buswidth = 8,
 208	.num_links = 1,
 209	.link_nodes = { &qns_pcie_gemnoc },
 210};
 211
 212static struct qcom_icc_node xm_pcie3_2 = {
 213	.name = "xm_pcie3_2",
 214	.channels = 1,
 215	.buswidth = 8,
 216	.num_links = 1,
 217	.link_nodes = { &qns_pcie_gemnoc },
 218};
 219
 220static struct qcom_icc_node qhm_audio = {
 221	.name = "qhm_audio",
 222	.channels = 1,
 223	.buswidth = 4,
 224	.num_links = 1,
 225	.link_nodes = { &qns_gemnoc_sf },
 226};
 227
 228static struct qcom_icc_node qhm_gic = {
 229	.name = "qhm_gic",
 230	.channels = 1,
 231	.buswidth = 4,
 232	.num_links = 1,
 233	.link_nodes = { &qns_gemnoc_sf },
 234};
 235
 236static struct qcom_icc_node qhm_pcie_rscc = {
 237	.name = "qhm_pcie_rscc",
 238	.channels = 1,
 239	.buswidth = 4,
 240	.num_links = 31,
 241	.link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
 242			&qhs_audio, &qhs_clk_ctl,
 243			&qhs_crypto_cfg, &qhs_imem_cfg,
 244			&qhs_ipa, &qhs_ipc_router,
 245			&qhs_mss_cfg, &qhs_mvmss_cfg,
 246			&qhs_pcie0_cfg, &qhs_pcie1_cfg,
 247			&qhs_pcie2_cfg, &qhs_pdm,
 248			&qhs_prng, &qhs_qdss_cfg,
 249			&qhs_qpic, &qhs_qup0,
 250			&qhs_sdc1, &qhs_sdc4,
 251			&qhs_spmi_vgi_coex, &qhs_tcsr,
 252			&qhs_tlmm, &qhs_usb3,
 253			&qhs_usb3_phy, &qns_ddrss_cfg,
 254			&qns_system_noc_cfg, &qns_system_noc_pcie_cfg,
 255			&qxs_imem, &xs_qdss_stm,
 256			&xs_sys_tcu_cfg },
 257};
 258
 259static struct qcom_icc_node qhm_qdss_bam = {
 260	.name = "qhm_qdss_bam",
 261	.channels = 1,
 262	.buswidth = 4,
 263	.num_links = 1,
 264	.link_nodes = { &qns_a1noc },
 265};
 266
 267static struct qcom_icc_node qhm_qpic = {
 268	.name = "qhm_qpic",
 269	.channels = 1,
 270	.buswidth = 4,
 271	.num_links = 1,
 272	.link_nodes = { &qns_a1noc },
 273};
 274
 275static struct qcom_icc_node qhm_qup0 = {
 276	.name = "qhm_qup0",
 277	.channels = 1,
 278	.buswidth = 4,
 279	.num_links = 1,
 280	.link_nodes = { &qns_a1noc },
 281};
 282
 283static struct qcom_icc_node qnm_aggre_noc = {
 284	.name = "qnm_aggre_noc",
 285	.channels = 1,
 286	.buswidth = 8,
 287	.num_links = 1,
 288	.link_nodes = { &qns_gemnoc_sf },
 289};
 290
 291static struct qcom_icc_node qnm_gemnoc_cnoc = {
 292	.name = "qnm_gemnoc_cnoc",
 293	.channels = 1,
 294	.buswidth = 8,
 295	.num_links = 32,
 296	.link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg,
 297			&qhs_audio, &qhs_clk_ctl,
 298			&qhs_crypto_cfg, &qhs_imem_cfg,
 299			&qhs_ipa, &qhs_ipc_router,
 300			&qhs_mss_cfg, &qhs_mvmss_cfg,
 301			&qhs_pcie0_cfg, &qhs_pcie1_cfg,
 302			&qhs_pcie2_cfg, &qhs_pcie_rscc,
 303			&qhs_pdm, &qhs_prng,
 304			&qhs_qdss_cfg, &qhs_qpic,
 305			&qhs_qup0, &qhs_sdc1,
 306			&qhs_sdc4, &qhs_spmi_vgi_coex,
 307			&qhs_tcsr, &qhs_tlmm,
 308			&qhs_usb3, &qhs_usb3_phy,
 309			&qns_ddrss_cfg, &qns_system_noc_cfg,
 310			&qns_system_noc_pcie_cfg, &qxs_imem,
 311			&xs_qdss_stm, &xs_sys_tcu_cfg },
 312};
 313
 314static struct qcom_icc_node qnm_gemnoc_pcie = {
 315	.name = "qnm_gemnoc_pcie",
 316	.channels = 1,
 317	.buswidth = 16,
 318	.num_links = 3,
 319	.link_nodes = { &xs_pcie_0, &xs_pcie_1,
 320			&xs_pcie_2 },
 321};
 322
 323static struct qcom_icc_node qnm_system_noc_cfg = {
 324	.name = "qnm_system_noc_cfg",
 325	.channels = 1,
 326	.buswidth = 4,
 327	.num_links = 1,
 328	.link_nodes = { &srvc_system_noc },
 329};
 330
 331static struct qcom_icc_node qnm_system_noc_pcie_cfg = {
 332	.name = "qnm_system_noc_pcie_cfg",
 333	.channels = 1,
 334	.buswidth = 4,
 335	.num_links = 1,
 336	.link_nodes = { &srvc_pcie_system_noc },
 337};
 338
 339static struct qcom_icc_node qxm_crypto = {
 340	.name = "qxm_crypto",
 341	.channels = 1,
 342	.buswidth = 8,
 343	.num_links = 1,
 344	.link_nodes = { &qns_a1noc },
 345};
 346
 347static struct qcom_icc_node qxm_ipa = {
 348	.name = "qxm_ipa",
 349	.channels = 1,
 350	.buswidth = 8,
 351	.num_links = 1,
 352	.link_nodes = { &qns_gemnoc_sf },
 353};
 354
 355static struct qcom_icc_node qxm_mvmss = {
 356	.name = "qxm_mvmss",
 357	.channels = 1,
 358	.buswidth = 8,
 359	.num_links = 1,
 360	.link_nodes = { &qns_a1noc },
 361};
 362
 363static struct qcom_icc_node xm_emac_0 = {
 364	.name = "xm_emac_0",
 365	.channels = 1,
 366	.buswidth = 8,
 367	.num_links = 1,
 368	.link_nodes = { &qns_a1noc },
 369};
 370
 371static struct qcom_icc_node xm_emac_1 = {
 372	.name = "xm_emac_1",
 373	.channels = 1,
 374	.buswidth = 8,
 375	.num_links = 1,
 376	.link_nodes = { &qns_a1noc },
 377};
 378
 379static struct qcom_icc_node xm_qdss_etr0 = {
 380	.name = "xm_qdss_etr0",
 381	.channels = 1,
 382	.buswidth = 8,
 383	.num_links = 1,
 384	.link_nodes = { &qns_a1noc },
 385};
 386
 387static struct qcom_icc_node xm_qdss_etr1 = {
 388	.name = "xm_qdss_etr1",
 389	.channels = 1,
 390	.buswidth = 8,
 391	.num_links = 1,
 392	.link_nodes = { &qns_a1noc },
 393};
 394
 395static struct qcom_icc_node xm_sdc1 = {
 396	.name = "xm_sdc1",
 397	.channels = 1,
 398	.buswidth = 8,
 399	.num_links = 1,
 400	.link_nodes = { &qns_a1noc },
 401};
 402
 403static struct qcom_icc_node xm_sdc4 = {
 404	.name = "xm_sdc4",
 405	.channels = 1,
 406	.buswidth = 8,
 407	.num_links = 1,
 408	.link_nodes = { &qns_a1noc },
 409};
 410
 411static struct qcom_icc_node xm_usb3 = {
 412	.name = "xm_usb3",
 413	.channels = 1,
 414	.buswidth = 8,
 415	.num_links = 1,
 416	.link_nodes = { &qns_a1noc },
 417};
 418
 419static struct qcom_icc_node qup0_core_slave = {
 420	.name = "qup0_core_slave",
 421	.channels = 1,
 422	.buswidth = 4,
 423};
 424
 425static struct qcom_icc_node qhs_lagg = {
 426	.name = "qhs_lagg",
 427	.channels = 1,
 428	.buswidth = 4,
 429};
 430
 431static struct qcom_icc_node qhs_mccc_master = {
 432	.name = "qhs_mccc_master",
 433	.channels = 1,
 434	.buswidth = 4,
 435};
 436
 437static struct qcom_icc_node qns_gemnoc = {
 438	.name = "qns_gemnoc",
 439	.channels = 1,
 440	.buswidth = 4,
 441};
 442
 443static struct qcom_icc_node qss_snoop_bwmon = {
 444	.name = "qss_snoop_bwmon",
 445	.channels = 1,
 446	.buswidth = 4,
 447};
 448
 449static struct qcom_icc_node qns_gemnoc_cnoc = {
 450	.name = "qns_gemnoc_cnoc",
 451	.channels = 1,
 452	.buswidth = 8,
 453	.num_links = 1,
 454	.link_nodes = { &qnm_gemnoc_cnoc },
 455};
 456
 457static struct qcom_icc_node qns_llcc = {
 458	.name = "qns_llcc",
 459	.channels = 1,
 460	.buswidth = 16,
 461	.num_links = 1,
 462	.link_nodes = { &llcc_mc },
 463};
 464
 465static struct qcom_icc_node qns_pcie = {
 466	.name = "qns_pcie",
 467	.channels = 1,
 468	.buswidth = 16,
 469	.num_links = 1,
 470	.link_nodes = { &qnm_gemnoc_pcie },
 471};
 472
 473static struct qcom_icc_node srvc_gemnoc = {
 474	.name = "srvc_gemnoc",
 475	.channels = 1,
 476	.buswidth = 4,
 477};
 478
 479static struct qcom_icc_node ebi = {
 480	.name = "ebi",
 481	.channels = 1,
 482	.buswidth = 4,
 483};
 484
 485static struct qcom_icc_node qns_pcie_gemnoc = {
 486	.name = "qns_pcie_gemnoc",
 487	.channels = 1,
 488	.buswidth = 16,
 489	.num_links = 1,
 490	.link_nodes = { &qnm_pcie },
 491};
 492
 493static struct qcom_icc_node ps_eth0_cfg = {
 494	.name = "ps_eth0_cfg",
 495	.channels = 1,
 496	.buswidth = 4,
 497};
 498
 499static struct qcom_icc_node ps_eth1_cfg = {
 500	.name = "ps_eth1_cfg",
 501	.channels = 1,
 502	.buswidth = 4,
 503};
 504
 505static struct qcom_icc_node qhs_audio = {
 506	.name = "qhs_audio",
 507	.channels = 1,
 508	.buswidth = 4,
 509};
 510
 511static struct qcom_icc_node qhs_clk_ctl = {
 512	.name = "qhs_clk_ctl",
 513	.channels = 1,
 514	.buswidth = 4,
 515};
 516
 517static struct qcom_icc_node qhs_crypto_cfg = {
 518	.name = "qhs_crypto_cfg",
 519	.channels = 1,
 520	.buswidth = 4,
 521};
 522
 523static struct qcom_icc_node qhs_imem_cfg = {
 524	.name = "qhs_imem_cfg",
 525	.channels = 1,
 526	.buswidth = 4,
 527};
 528
 529static struct qcom_icc_node qhs_ipa = {
 530	.name = "qhs_ipa",
 531	.channels = 1,
 532	.buswidth = 4,
 533};
 534
 535static struct qcom_icc_node qhs_ipc_router = {
 536	.name = "qhs_ipc_router",
 537	.channels = 1,
 538	.buswidth = 4,
 539};
 540
 541static struct qcom_icc_node qhs_mss_cfg = {
 542	.name = "qhs_mss_cfg",
 543	.channels = 1,
 544	.buswidth = 4,
 545};
 546
 547static struct qcom_icc_node qhs_mvmss_cfg = {
 548	.name = "qhs_mvmss_cfg",
 549	.channels = 1,
 550	.buswidth = 4,
 551};
 552
 553static struct qcom_icc_node qhs_pcie0_cfg = {
 554	.name = "qhs_pcie0_cfg",
 555	.channels = 1,
 556	.buswidth = 4,
 557};
 558
 559static struct qcom_icc_node qhs_pcie1_cfg = {
 560	.name = "qhs_pcie1_cfg",
 561	.channels = 1,
 562	.buswidth = 4,
 563};
 564
 565static struct qcom_icc_node qhs_pcie2_cfg = {
 566	.name = "qhs_pcie2_cfg",
 567	.channels = 1,
 568	.buswidth = 4,
 569};
 570
 571static struct qcom_icc_node qhs_pcie_rscc = {
 572	.name = "qhs_pcie_rscc",
 573	.channels = 1,
 574	.buswidth = 4,
 575};
 576
 577static struct qcom_icc_node qhs_pdm = {
 578	.name = "qhs_pdm",
 579	.channels = 1,
 580	.buswidth = 4,
 581};
 582
 583static struct qcom_icc_node qhs_prng = {
 584	.name = "qhs_prng",
 585	.channels = 1,
 586	.buswidth = 4,
 587};
 588
 589static struct qcom_icc_node qhs_qdss_cfg = {
 590	.name = "qhs_qdss_cfg",
 591	.channels = 1,
 592	.buswidth = 4,
 593};
 594
 595static struct qcom_icc_node qhs_qpic = {
 596	.name = "qhs_qpic",
 597	.channels = 1,
 598	.buswidth = 4,
 599};
 600
 601static struct qcom_icc_node qhs_qup0 = {
 602	.name = "qhs_qup0",
 603	.channels = 1,
 604	.buswidth = 4,
 605};
 606
 607static struct qcom_icc_node qhs_sdc1 = {
 608	.name = "qhs_sdc1",
 609	.channels = 1,
 610	.buswidth = 4,
 611};
 612
 613static struct qcom_icc_node qhs_sdc4 = {
 614	.name = "qhs_sdc4",
 615	.channels = 1,
 616	.buswidth = 4,
 617};
 618
 619static struct qcom_icc_node qhs_spmi_vgi_coex = {
 620	.name = "qhs_spmi_vgi_coex",
 621	.channels = 1,
 622	.buswidth = 4,
 623};
 624
 625static struct qcom_icc_node qhs_tcsr = {
 626	.name = "qhs_tcsr",
 627	.channels = 1,
 628	.buswidth = 4,
 629};
 630
 631static struct qcom_icc_node qhs_tlmm = {
 632	.name = "qhs_tlmm",
 633	.channels = 1,
 634	.buswidth = 4,
 635};
 636
 637static struct qcom_icc_node qhs_usb3 = {
 638	.name = "qhs_usb3",
 639	.channels = 1,
 640	.buswidth = 4,
 641};
 642
 643static struct qcom_icc_node qhs_usb3_phy = {
 644	.name = "qhs_usb3_phy",
 645	.channels = 1,
 646	.buswidth = 4,
 647};
 648
 649static struct qcom_icc_node qns_a1noc = {
 650	.name = "qns_a1noc",
 651	.channels = 1,
 652	.buswidth = 8,
 653	.num_links = 1,
 654	.link_nodes = { &qnm_aggre_noc },
 655};
 656
 657static struct qcom_icc_node qns_ddrss_cfg = {
 658	.name = "qns_ddrss_cfg",
 659	.channels = 1,
 660	.buswidth = 4,
 661	.num_links = 1,
 662	.link_nodes = { &qnm_cnoc },
 663};
 664
 665static struct qcom_icc_node qns_gemnoc_sf = {
 666	.name = "qns_gemnoc_sf",
 667	.channels = 1,
 668	.buswidth = 16,
 669	.num_links = 1,
 670	.link_nodes = { &qnm_snoc_sf },
 671};
 672
 673static struct qcom_icc_node qns_system_noc_cfg = {
 674	.name = "qns_system_noc_cfg",
 675	.channels = 1,
 676	.buswidth = 4,
 677	.num_links = 1,
 678	.link_nodes = { &qnm_system_noc_cfg },
 679};
 680
 681static struct qcom_icc_node qns_system_noc_pcie_cfg = {
 682	.name = "qns_system_noc_pcie_cfg",
 683	.channels = 1,
 684	.buswidth = 4,
 685	.num_links = 1,
 686	.link_nodes = { &qnm_system_noc_pcie_cfg },
 687};
 688
 689static struct qcom_icc_node qxs_imem = {
 690	.name = "qxs_imem",
 691	.channels = 1,
 692	.buswidth = 8,
 693};
 694
 695static struct qcom_icc_node srvc_pcie_system_noc = {
 696	.name = "srvc_pcie_system_noc",
 697	.channels = 1,
 698	.buswidth = 4,
 699};
 700
 701static struct qcom_icc_node srvc_system_noc = {
 702	.name = "srvc_system_noc",
 703	.channels = 1,
 704	.buswidth = 4,
 705};
 706
 707static struct qcom_icc_node xs_pcie_0 = {
 708	.name = "xs_pcie_0",
 709	.channels = 1,
 710	.buswidth = 8,
 711};
 712
 713static struct qcom_icc_node xs_pcie_1 = {
 714	.name = "xs_pcie_1",
 715	.channels = 1,
 716	.buswidth = 8,
 717};
 718
 719static struct qcom_icc_node xs_pcie_2 = {
 720	.name = "xs_pcie_2",
 721	.channels = 1,
 722	.buswidth = 8,
 723};
 724
 725static struct qcom_icc_node xs_qdss_stm = {
 726	.name = "xs_qdss_stm",
 727	.channels = 1,
 728	.buswidth = 4,
 729};
 730
 731static struct qcom_icc_node xs_sys_tcu_cfg = {
 732	.name = "xs_sys_tcu_cfg",
 733	.channels = 1,
 734	.buswidth = 8,
 735};
 736
 737static struct qcom_icc_bcm bcm_ce0 = {
 738	.name = "CE0",
 739	.num_nodes = 1,
 740	.nodes = { &qxm_crypto },
 741};
 742
 743static struct qcom_icc_bcm bcm_cn0 = {
 744	.name = "CN0",
 745	.keepalive = true,
 746	.num_nodes = 39,
 747	.nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc,
 748		   &ps_eth0_cfg, &ps_eth1_cfg,
 749		   &qhs_audio, &qhs_clk_ctl,
 750		   &qhs_crypto_cfg, &qhs_imem_cfg,
 751		   &qhs_ipa, &qhs_ipc_router,
 752		   &qhs_mss_cfg, &qhs_mvmss_cfg,
 753		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
 754		   &qhs_pcie2_cfg, &qhs_pcie_rscc,
 755		   &qhs_pdm, &qhs_prng,
 756		   &qhs_qdss_cfg, &qhs_qpic,
 757		   &qhs_qup0, &qhs_sdc1,
 758		   &qhs_sdc4, &qhs_spmi_vgi_coex,
 759		   &qhs_tcsr, &qhs_tlmm,
 760		   &qhs_usb3, &qhs_usb3_phy,
 761		   &qns_ddrss_cfg, &qns_system_noc_cfg,
 762		   &qns_system_noc_pcie_cfg, &qxs_imem,
 763		   &srvc_pcie_system_noc, &srvc_system_noc,
 764		   &xs_pcie_0, &xs_pcie_1,
 765		   &xs_pcie_2, &xs_qdss_stm,
 766		   &xs_sys_tcu_cfg },
 767};
 768
 769static struct qcom_icc_bcm bcm_mc0 = {
 770	.name = "MC0",
 771	.keepalive = true,
 772	.num_nodes = 1,
 773	.nodes = { &ebi },
 774};
 775
 776static struct qcom_icc_bcm bcm_qup0 = {
 777	.name = "QUP0",
 778	.keepalive = true,
 779	.vote_scale = 1,
 780	.num_nodes = 1,
 781	.nodes = { &qup0_core_slave },
 782};
 783
 784static struct qcom_icc_bcm bcm_sh0 = {
 785	.name = "SH0",
 786	.keepalive = true,
 787	.num_nodes = 1,
 788	.nodes = { &qns_llcc },
 789};
 790
 791static struct qcom_icc_bcm bcm_sh1 = {
 792	.name = "SH1",
 793	.num_nodes = 10,
 794	.nodes = { &alm_sys_tcu, &chm_apps,
 795		   &qnm_gemnoc_cfg, &qnm_mdsp,
 796		   &qnm_snoc_sf, &xm_gic,
 797		   &xm_ipa2pcie, &qns_gemnoc_cnoc,
 798		   &qns_pcie, &srvc_gemnoc },
 799};
 800
 801static struct qcom_icc_bcm bcm_sn0 = {
 802	.name = "SN0",
 803	.keepalive = true,
 804	.num_nodes = 1,
 805	.nodes = { &qns_gemnoc_sf },
 806};
 807
 808static struct qcom_icc_bcm bcm_sn1 = {
 809	.name = "SN1",
 810	.num_nodes = 21,
 811	.nodes = { &xm_pcie3_0, &xm_pcie3_1,
 812		   &xm_pcie3_2, &qhm_audio,
 813		   &qhm_gic, &qhm_qdss_bam,
 814		   &qhm_qpic, &qhm_qup0,
 815		   &qnm_gemnoc_pcie, &qnm_system_noc_cfg,
 816		   &qnm_system_noc_pcie_cfg, &qxm_crypto,
 817		   &qxm_ipa, &qxm_mvmss,
 818		   &xm_emac_0, &xm_emac_1,
 819		   &xm_qdss_etr0, &xm_qdss_etr1,
 820		   &xm_sdc1, &xm_sdc4,
 821		   &xm_usb3 },
 822};
 823
 824static struct qcom_icc_bcm bcm_sn2 = {
 825	.name = "SN2",
 826	.num_nodes = 2,
 827	.nodes = { &qnm_aggre_noc, &qns_a1noc },
 828};
 829
 830static struct qcom_icc_bcm bcm_sn4 = {
 831	.name = "SN4",
 832	.num_nodes = 2,
 833	.nodes = { &qnm_pcie, &qns_pcie_gemnoc },
 834};
 835
 836static struct qcom_icc_bcm * const clk_virt_bcms[] = {
 837	&bcm_qup0,
 838};
 839
 840static struct qcom_icc_node * const clk_virt_nodes[] = {
 841	[MASTER_QUP_CORE_0] = &qup0_core_master,
 842	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
 843};
 844
 845static const struct qcom_icc_desc sdx75_clk_virt = {
 846	.nodes = clk_virt_nodes,
 847	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
 848	.bcms = clk_virt_bcms,
 849	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
 850};
 851
 852static struct qcom_icc_node * const dc_noc_nodes[] = {
 853	[MASTER_CNOC_DC_NOC] = &qnm_cnoc,
 854	[SLAVE_LAGG_CFG] = &qhs_lagg,
 855	[SLAVE_MCCC_MASTER] = &qhs_mccc_master,
 856	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
 857	[SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon,
 858};
 859
 860static const struct qcom_icc_desc sdx75_dc_noc = {
 861	.nodes = dc_noc_nodes,
 862	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
 863};
 864
 865static struct qcom_icc_bcm * const gem_noc_bcms[] = {
 866	&bcm_sh0,
 867	&bcm_sh1,
 868	&bcm_sn4,
 869};
 870
 871static struct qcom_icc_node * const gem_noc_nodes[] = {
 872	[MASTER_SYS_TCU] = &alm_sys_tcu,
 873	[MASTER_APPSS_PROC] = &chm_apps,
 874	[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
 875	[MASTER_MSS_PROC] = &qnm_mdsp,
 876	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
 877	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 878	[MASTER_GIC] = &xm_gic,
 879	[MASTER_IPA_PCIE] = &xm_ipa2pcie,
 880	[SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc,
 881	[SLAVE_LLCC] = &qns_llcc,
 882	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
 883	[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
 884};
 885
 886static const struct qcom_icc_desc sdx75_gem_noc = {
 887	.nodes = gem_noc_nodes,
 888	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
 889	.bcms = gem_noc_bcms,
 890	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
 891};
 892
 893static struct qcom_icc_bcm * const mc_virt_bcms[] = {
 894	&bcm_mc0,
 895};
 896
 897static struct qcom_icc_node * const mc_virt_nodes[] = {
 898	[MASTER_LLCC] = &llcc_mc,
 899	[SLAVE_EBI1] = &ebi,
 900};
 901
 902static const struct qcom_icc_desc sdx75_mc_virt = {
 903	.nodes = mc_virt_nodes,
 904	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
 905	.bcms = mc_virt_bcms,
 906	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
 907};
 908
 909static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
 910	&bcm_sn1,
 911	&bcm_sn4,
 912};
 913
 914static struct qcom_icc_node * const pcie_anoc_nodes[] = {
 915	[MASTER_PCIE_0] = &xm_pcie3_0,
 916	[MASTER_PCIE_1] = &xm_pcie3_1,
 917	[MASTER_PCIE_2] = &xm_pcie3_2,
 918	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
 919};
 920
 921static const struct qcom_icc_desc sdx75_pcie_anoc = {
 922	.nodes = pcie_anoc_nodes,
 923	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
 924	.bcms = pcie_anoc_bcms,
 925	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
 926};
 927
 928static struct qcom_icc_bcm * const system_noc_bcms[] = {
 929	&bcm_ce0,
 930	&bcm_cn0,
 931	&bcm_sn0,
 932	&bcm_sn1,
 933	&bcm_sn2,
 934};
 935
 936static struct qcom_icc_node * const system_noc_nodes[] = {
 937	[MASTER_AUDIO] = &qhm_audio,
 938	[MASTER_GIC_AHB] = &qhm_gic,
 939	[MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
 940	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
 941	[MASTER_QPIC] = &qhm_qpic,
 942	[MASTER_QUP_0] = &qhm_qup0,
 943	[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
 944	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
 945	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
 946	[MASTER_SNOC_CFG] = &qnm_system_noc_cfg,
 947	[MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg,
 948	[MASTER_CRYPTO] = &qxm_crypto,
 949	[MASTER_IPA] = &qxm_ipa,
 950	[MASTER_MVMSS] = &qxm_mvmss,
 951	[MASTER_EMAC_0] = &xm_emac_0,
 952	[MASTER_EMAC_1] = &xm_emac_1,
 953	[MASTER_QDSS_ETR] = &xm_qdss_etr0,
 954	[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
 955	[MASTER_SDCC_1] = &xm_sdc1,
 956	[MASTER_SDCC_4] = &xm_sdc4,
 957	[MASTER_USB3_0] = &xm_usb3,
 958	[SLAVE_ETH0_CFG] = &ps_eth0_cfg,
 959	[SLAVE_ETH1_CFG] = &ps_eth1_cfg,
 960	[SLAVE_AUDIO] = &qhs_audio,
 961	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
 962	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
 963	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 964	[SLAVE_IPA_CFG] = &qhs_ipa,
 965	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
 966	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
 967	[SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg,
 968	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
 969	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
 970	[SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
 971	[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
 972	[SLAVE_PDM] = &qhs_pdm,
 973	[SLAVE_PRNG] = &qhs_prng,
 974	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 975	[SLAVE_QPIC] = &qhs_qpic,
 976	[SLAVE_QUP_0] = &qhs_qup0,
 977	[SLAVE_SDCC_1] = &qhs_sdc1,
 978	[SLAVE_SDCC_4] = &qhs_sdc4,
 979	[SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
 980	[SLAVE_TCSR] = &qhs_tcsr,
 981	[SLAVE_TLMM] = &qhs_tlmm,
 982	[SLAVE_USB3] = &qhs_usb3,
 983	[SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
 984	[SLAVE_A1NOC_CFG] = &qns_a1noc,
 985	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
 986	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 987	[SLAVE_SNOC_CFG] = &qns_system_noc_cfg,
 988	[SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg,
 989	[SLAVE_IMEM] = &qxs_imem,
 990	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc,
 991	[SLAVE_SERVICE_SNOC] = &srvc_system_noc,
 992	[SLAVE_PCIE_0] = &xs_pcie_0,
 993	[SLAVE_PCIE_1] = &xs_pcie_1,
 994	[SLAVE_PCIE_2] = &xs_pcie_2,
 995	[SLAVE_QDSS_STM] = &xs_qdss_stm,
 996	[SLAVE_TCU] = &xs_sys_tcu_cfg,
 997};
 998
 999static const struct qcom_icc_desc sdx75_system_noc = {
1000	.nodes = system_noc_nodes,
1001	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1002	.bcms = system_noc_bcms,
1003	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1004};
1005
1006static const struct of_device_id qnoc_of_match[] = {
1007	{ .compatible = "qcom,sdx75-clk-virt", .data = &sdx75_clk_virt },
1008	{ .compatible = "qcom,sdx75-dc-noc", .data = &sdx75_dc_noc },
1009	{ .compatible = "qcom,sdx75-gem-noc", .data = &sdx75_gem_noc },
1010	{ .compatible = "qcom,sdx75-mc-virt", .data = &sdx75_mc_virt },
1011	{ .compatible = "qcom,sdx75-pcie-anoc", .data = &sdx75_pcie_anoc },
1012	{ .compatible = "qcom,sdx75-system-noc", .data = &sdx75_system_noc },
1013	{ }
1014};
1015MODULE_DEVICE_TABLE(of, qnoc_of_match);
1016
1017static struct platform_driver qnoc_driver = {
1018	.probe = qcom_icc_rpmh_probe,
1019	.remove = qcom_icc_rpmh_remove,
1020	.driver = {
1021		.name = "qnoc-sdx75",
1022		.of_match_table = qnoc_of_match,
1023		.sync_state = icc_sync_state,
1024	},
1025};
1026
1027static int __init qnoc_driver_init(void)
1028{
1029	return platform_driver_register(&qnoc_driver);
1030}
1031core_initcall(qnoc_driver_init);
1032
1033static void __exit qnoc_driver_exit(void)
1034{
1035	platform_driver_unregister(&qnoc_driver);
1036}
1037module_exit(qnoc_driver_exit);
1038
1039MODULE_DESCRIPTION("SDX75 NoC driver");
1040MODULE_LICENSE("GPL");