sdx55.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm SDX55 interconnect driver
  4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  5 *
  6 * Copyright (c) 2021, Linaro Ltd.
  7 *
  8 */
  9
 10#include <linux/device.h>
 11#include <linux/interconnect.h>
 12#include <linux/interconnect-provider.h>
 13#include <linux/mod_devicetable.h>
 14#include <linux/module.h>
 15#include <linux/platform_device.h>
 16#include <dt-bindings/interconnect/qcom,sdx55.h>
 17
 18#include "bcm-voter.h"
 19#include "icc-rpmh.h"
 20
 21static struct qcom_icc_node llcc_mc;
 22static struct qcom_icc_node acm_tcu;
 23static struct qcom_icc_node qnm_snoc_gc;
 24static struct qcom_icc_node xm_apps_rdwr;
 25static struct qcom_icc_node qhm_audio;
 26static struct qcom_icc_node qhm_blsp1;
 27static struct qcom_icc_node qhm_qdss_bam;
 28static struct qcom_icc_node qhm_qpic;
 29static struct qcom_icc_node qhm_snoc_cfg;
 30static struct qcom_icc_node qhm_spmi_fetcher1;
 31static struct qcom_icc_node qnm_aggre_noc;
 32static struct qcom_icc_node qnm_ipa;
 33static struct qcom_icc_node qnm_memnoc;
 34static struct qcom_icc_node qnm_memnoc_pcie;
 35static struct qcom_icc_node qxm_crypto;
 36static struct qcom_icc_node xm_emac;
 37static struct qcom_icc_node xm_ipa2pcie_slv;
 38static struct qcom_icc_node xm_pcie;
 39static struct qcom_icc_node xm_qdss_etr;
 40static struct qcom_icc_node xm_sdc1;
 41static struct qcom_icc_node xm_usb3;
 42static struct qcom_icc_node ebi;
 43static struct qcom_icc_node qns_llcc;
 44static struct qcom_icc_node qns_memnoc_snoc;
 45static struct qcom_icc_node qns_sys_pcie;
 46static struct qcom_icc_node qhs_aop;
 47static struct qcom_icc_node qhs_aoss;
 48static struct qcom_icc_node qhs_apss;
 49static struct qcom_icc_node qhs_audio;
 50static struct qcom_icc_node qhs_blsp1;
 51static struct qcom_icc_node qhs_clk_ctl;
 52static struct qcom_icc_node qhs_crypto0_cfg;
 53static struct qcom_icc_node qhs_ddrss_cfg;
 54static struct qcom_icc_node qhs_ecc_cfg;
 55static struct qcom_icc_node qhs_emac_cfg;
 56static struct qcom_icc_node qhs_imem_cfg;
 57static struct qcom_icc_node qhs_ipa;
 58static struct qcom_icc_node qhs_mss_cfg;
 59static struct qcom_icc_node qhs_pcie_parf;
 60static struct qcom_icc_node qhs_pdm;
 61static struct qcom_icc_node qhs_prng;
 62static struct qcom_icc_node qhs_qdss_cfg;
 63static struct qcom_icc_node qhs_qpic;
 64static struct qcom_icc_node qhs_sdc1;
 65static struct qcom_icc_node qhs_snoc_cfg;
 66static struct qcom_icc_node qhs_spmi_fetcher;
 67static struct qcom_icc_node qhs_spmi_vgi_coex;
 68static struct qcom_icc_node qhs_tcsr;
 69static struct qcom_icc_node qhs_tlmm;
 70static struct qcom_icc_node qhs_usb3;
 71static struct qcom_icc_node qhs_usb3_phy;
 72static struct qcom_icc_node qns_aggre_noc;
 73static struct qcom_icc_node qns_snoc_memnoc;
 74static struct qcom_icc_node qxs_imem;
 75static struct qcom_icc_node srvc_snoc;
 76static struct qcom_icc_node xs_pcie;
 77static struct qcom_icc_node xs_qdss_stm;
 78static struct qcom_icc_node xs_sys_tcu_cfg;
 79
 80static struct qcom_icc_node llcc_mc = {
 81	.name = "llcc_mc",
 82	.channels = 4,
 83	.buswidth = 4,
 84	.num_links = 1,
 85	.link_nodes = { &ebi },
 86};
 87
 88static struct qcom_icc_node acm_tcu = {
 89	.name = "acm_tcu",
 90	.channels = 1,
 91	.buswidth = 8,
 92	.num_links = 3,
 93	.link_nodes = { &qns_llcc,
 94			&qns_memnoc_snoc,
 95			&qns_sys_pcie },
 96};
 97
 98static struct qcom_icc_node qnm_snoc_gc = {
 99	.name = "qnm_snoc_gc",
100	.channels = 1,
101	.buswidth = 8,
102	.num_links = 1,
103	.link_nodes = { &qns_llcc },
104};
105
106static struct qcom_icc_node xm_apps_rdwr = {
107	.name = "xm_apps_rdwr",
108	.channels = 1,
109	.buswidth = 16,
110	.num_links = 3,
111	.link_nodes = { &qns_llcc,
112			&qns_memnoc_snoc,
113			&qns_sys_pcie },
114};
115
116static struct qcom_icc_node qhm_audio = {
117	.name = "qhm_audio",
118	.channels = 1,
119	.buswidth = 4,
120	.num_links = 1,
121	.link_nodes = { &qns_aggre_noc },
122};
123
124static struct qcom_icc_node qhm_blsp1 = {
125	.name = "qhm_blsp1",
126	.channels = 1,
127	.buswidth = 4,
128	.num_links = 1,
129	.link_nodes = { &qns_aggre_noc },
130};
131
132static struct qcom_icc_node qhm_qdss_bam = {
133	.name = "qhm_qdss_bam",
134	.channels = 1,
135	.buswidth = 4,
136	.num_links = 28,
137	.link_nodes = { &qhs_snoc_cfg,
138			&qhs_emac_cfg,
139			&qhs_usb3,
140			&qhs_tlmm,
141			&qhs_spmi_fetcher,
142			&qhs_qdss_cfg,
143			&qhs_pdm,
144			&qns_snoc_memnoc,
145			&qhs_tcsr,
146			&qhs_ddrss_cfg,
147			&qhs_spmi_vgi_coex,
148			&qhs_qpic,
149			&qxs_imem,
150			&qhs_ipa,
151			&qhs_usb3_phy,
152			&qhs_aop,
153			&qhs_blsp1,
154			&qhs_sdc1,
155			&qhs_mss_cfg,
156			&qhs_pcie_parf,
157			&qhs_ecc_cfg,
158			&qhs_audio,
159			&qhs_aoss,
160			&qhs_prng,
161			&qhs_crypto0_cfg,
162			&xs_sys_tcu_cfg,
163			&qhs_clk_ctl,
164			&qhs_imem_cfg },
165};
166
167static struct qcom_icc_node qhm_qpic = {
168	.name = "qhm_qpic",
169	.channels = 1,
170	.buswidth = 4,
171	.num_links = 5,
172	.link_nodes = { &qhs_aoss,
173			&qhs_ipa,
174			&qns_aggre_noc,
175			&qhs_aop,
176			&qhs_audio },
177};
178
179static struct qcom_icc_node qhm_snoc_cfg = {
180	.name = "qhm_snoc_cfg",
181	.channels = 1,
182	.buswidth = 4,
183	.num_links = 1,
184	.link_nodes = { &srvc_snoc },
185};
186
187static struct qcom_icc_node qhm_spmi_fetcher1 = {
188	.name = "qhm_spmi_fetcher1",
189	.channels = 1,
190	.buswidth = 4,
191	.num_links = 3,
192	.link_nodes = { &qhs_aoss,
193			&qns_aggre_noc,
194			&qhs_aop },
195};
196
197static struct qcom_icc_node qnm_aggre_noc = {
198	.name = "qnm_aggre_noc",
199	.channels = 1,
200	.buswidth = 8,
201	.num_links = 30,
202	.link_nodes = { &xs_pcie,
203			&qhs_snoc_cfg,
204			&qhs_sdc1,
205			&qhs_tlmm,
206			&qhs_spmi_fetcher,
207			&qhs_qdss_cfg,
208			&qhs_pdm,
209			&qns_snoc_memnoc,
210			&qhs_tcsr,
211			&qhs_ddrss_cfg,
212			&qhs_spmi_vgi_coex,
213			&xs_qdss_stm,
214			&qhs_qpic,
215			&qxs_imem,
216			&qhs_ipa,
217			&qhs_usb3_phy,
218			&qhs_aop,
219			&qhs_blsp1,
220			&qhs_usb3,
221			&qhs_mss_cfg,
222			&qhs_pcie_parf,
223			&qhs_ecc_cfg,
224			&qhs_apss,
225			&qhs_audio,
226			&qhs_aoss,
227			&qhs_prng,
228			&qhs_crypto0_cfg,
229			&xs_sys_tcu_cfg,
230			&qhs_clk_ctl,
231			&qhs_imem_cfg },
232};
233
234static struct qcom_icc_node qnm_ipa = {
235	.name = "qnm_ipa",
236	.channels = 1,
237	.buswidth = 8,
238	.num_links = 27,
239	.link_nodes = { &qhs_snoc_cfg,
240			&qhs_emac_cfg,
241			&qhs_usb3,
242			&qhs_aoss,
243			&qhs_spmi_fetcher,
244			&qhs_qdss_cfg,
245			&qhs_pdm,
246			&qns_snoc_memnoc,
247			&qhs_tcsr,
248			&qhs_ddrss_cfg,
249			&xs_qdss_stm,
250			&qhs_qpic,
251			&qxs_imem,
252			&qhs_ipa,
253			&qhs_usb3_phy,
254			&qhs_aop,
255			&qhs_blsp1,
256			&qhs_sdc1,
257			&qhs_mss_cfg,
258			&qhs_pcie_parf,
259			&qhs_ecc_cfg,
260			&qhs_audio,
261			&qhs_tlmm,
262			&qhs_prng,
263			&qhs_crypto0_cfg,
264			&qhs_clk_ctl,
265			&qhs_imem_cfg },
266};
267
268static struct qcom_icc_node qnm_memnoc = {
269	.name = "qnm_memnoc",
270	.channels = 1,
271	.buswidth = 8,
272	.num_links = 29,
273	.link_nodes = { &qhs_snoc_cfg,
274			&qhs_emac_cfg,
275			&qhs_usb3,
276			&qhs_tlmm,
277			&qhs_spmi_fetcher,
278			&qhs_qdss_cfg,
279			&qhs_pdm,
280			&qhs_tcsr,
281			&qhs_ddrss_cfg,
282			&qhs_spmi_vgi_coex,
283			&xs_qdss_stm,
284			&qhs_qpic,
285			&qxs_imem,
286			&qhs_ipa,
287			&qhs_usb3_phy,
288			&qhs_aop,
289			&qhs_blsp1,
290			&qhs_sdc1,
291			&qhs_mss_cfg,
292			&qhs_pcie_parf,
293			&qhs_ecc_cfg,
294			&qhs_apss,
295			&qhs_audio,
296			&qhs_aoss,
297			&qhs_prng,
298			&qhs_crypto0_cfg,
299			&xs_sys_tcu_cfg,
300			&qhs_clk_ctl,
301			&qhs_imem_cfg },
302};
303
304static struct qcom_icc_node qnm_memnoc_pcie = {
305	.name = "qnm_memnoc_pcie",
306	.channels = 1,
307	.buswidth = 8,
308	.num_links = 1,
309	.link_nodes = { &xs_pcie },
310};
311
312static struct qcom_icc_node qxm_crypto = {
313	.name = "qxm_crypto",
314	.channels = 1,
315	.buswidth = 8,
316	.num_links = 3,
317	.link_nodes = { &qhs_aoss,
318			&qns_aggre_noc,
319			&qhs_aop },
320};
321
322static struct qcom_icc_node xm_emac = {
323	.name = "xm_emac",
324	.channels = 1,
325	.buswidth = 8,
326	.num_links = 1,
327	.link_nodes = { &qns_aggre_noc },
328};
329
330static struct qcom_icc_node xm_ipa2pcie_slv = {
331	.name = "xm_ipa2pcie_slv",
332	.channels = 1,
333	.buswidth = 8,
334	.num_links = 1,
335	.link_nodes = { &xs_pcie },
336};
337
338static struct qcom_icc_node xm_pcie = {
339	.name = "xm_pcie",
340	.channels = 1,
341	.buswidth = 8,
342	.num_links = 1,
343	.link_nodes = { &qns_aggre_noc },
344};
345
346static struct qcom_icc_node xm_qdss_etr = {
347	.name = "xm_qdss_etr",
348	.channels = 1,
349	.buswidth = 8,
350	.num_links = 28,
351	.link_nodes = { &qhs_snoc_cfg,
352			&qhs_emac_cfg,
353			&qhs_usb3,
354			&qhs_aoss,
355			&qhs_spmi_fetcher,
356			&qhs_qdss_cfg,
357			&qhs_pdm,
358			&qns_snoc_memnoc,
359			&qhs_tcsr,
360			&qhs_ddrss_cfg,
361			&qhs_spmi_vgi_coex,
362			&qhs_qpic,
363			&qxs_imem,
364			&qhs_ipa,
365			&qhs_usb3_phy,
366			&qhs_aop,
367			&qhs_blsp1,
368			&qhs_sdc1,
369			&qhs_mss_cfg,
370			&qhs_pcie_parf,
371			&qhs_ecc_cfg,
372			&qhs_audio,
373			&qhs_aoss,
374			&qhs_prng,
375			&qhs_crypto0_cfg,
376			&xs_sys_tcu_cfg,
377			&qhs_clk_ctl,
378			&qhs_imem_cfg },
379};
380
381static struct qcom_icc_node xm_sdc1 = {
382	.name = "xm_sdc1",
383	.channels = 1,
384	.buswidth = 8,
385	.num_links = 5,
386	.link_nodes = { &qhs_aoss,
387			&qhs_ipa,
388			&qns_aggre_noc,
389			&qhs_aop,
390			&qhs_audio },
391};
392
393static struct qcom_icc_node xm_usb3 = {
394	.name = "xm_usb3",
395	.channels = 1,
396	.buswidth = 8,
397	.num_links = 1,
398	.link_nodes = { &qns_aggre_noc },
399};
400
401static struct qcom_icc_node ebi = {
402	.name = "ebi",
403	.channels = 1,
404	.buswidth = 4,
405};
406
407static struct qcom_icc_node qns_llcc = {
408	.name = "qns_llcc",
409	.channels = 1,
410	.buswidth = 16,
411	.num_links = 1,
412	.link_nodes = { &ebi },
413};
414
415static struct qcom_icc_node qns_memnoc_snoc = {
416	.name = "qns_memnoc_snoc",
417	.channels = 1,
418	.buswidth = 8,
419	.num_links = 1,
420	.link_nodes = { &qnm_memnoc },
421};
422
423static struct qcom_icc_node qns_sys_pcie = {
424	.name = "qns_sys_pcie",
425	.channels = 1,
426	.buswidth = 8,
427	.num_links = 1,
428	.link_nodes = { &qnm_memnoc_pcie },
429};
430
431static struct qcom_icc_node qhs_aop = {
432	.name = "qhs_aop",
433	.channels = 1,
434	.buswidth = 4,
435};
436
437static struct qcom_icc_node qhs_aoss = {
438	.name = "qhs_aoss",
439	.channels = 1,
440	.buswidth = 4,
441};
442
443static struct qcom_icc_node qhs_apss = {
444	.name = "qhs_apss",
445	.channels = 1,
446	.buswidth = 4,
447};
448
449static struct qcom_icc_node qhs_audio = {
450	.name = "qhs_audio",
451	.channels = 1,
452	.buswidth = 4,
453};
454
455static struct qcom_icc_node qhs_blsp1 = {
456	.name = "qhs_blsp1",
457	.channels = 1,
458	.buswidth = 4,
459};
460
461static struct qcom_icc_node qhs_clk_ctl = {
462	.name = "qhs_clk_ctl",
463	.channels = 1,
464	.buswidth = 4,
465};
466
467static struct qcom_icc_node qhs_crypto0_cfg = {
468	.name = "qhs_crypto0_cfg",
469	.channels = 1,
470	.buswidth = 4,
471};
472
473static struct qcom_icc_node qhs_ddrss_cfg = {
474	.name = "qhs_ddrss_cfg",
475	.channels = 1,
476	.buswidth = 4,
477};
478
479static struct qcom_icc_node qhs_ecc_cfg = {
480	.name = "qhs_ecc_cfg",
481	.channels = 1,
482	.buswidth = 4,
483};
484
485static struct qcom_icc_node qhs_emac_cfg = {
486	.name = "qhs_emac_cfg",
487	.channels = 1,
488	.buswidth = 4,
489};
490
491static struct qcom_icc_node qhs_imem_cfg = {
492	.name = "qhs_imem_cfg",
493	.channels = 1,
494	.buswidth = 4,
495};
496
497static struct qcom_icc_node qhs_ipa = {
498	.name = "qhs_ipa",
499	.channels = 1,
500	.buswidth = 4,
501};
502
503static struct qcom_icc_node qhs_mss_cfg = {
504	.name = "qhs_mss_cfg",
505	.channels = 1,
506	.buswidth = 4,
507};
508
509static struct qcom_icc_node qhs_pcie_parf = {
510	.name = "qhs_pcie_parf",
511	.channels = 1,
512	.buswidth = 4,
513};
514
515static struct qcom_icc_node qhs_pdm = {
516	.name = "qhs_pdm",
517	.channels = 1,
518	.buswidth = 4,
519};
520
521static struct qcom_icc_node qhs_prng = {
522	.name = "qhs_prng",
523	.channels = 1,
524	.buswidth = 4,
525};
526
527static struct qcom_icc_node qhs_qdss_cfg = {
528	.name = "qhs_qdss_cfg",
529	.channels = 1,
530	.buswidth = 4,
531};
532
533static struct qcom_icc_node qhs_qpic = {
534	.name = "qhs_qpic",
535	.channels = 1,
536	.buswidth = 4,
537};
538
539static struct qcom_icc_node qhs_sdc1 = {
540	.name = "qhs_sdc1",
541	.channels = 1,
542	.buswidth = 4,
543};
544
545static struct qcom_icc_node qhs_snoc_cfg = {
546	.name = "qhs_snoc_cfg",
547	.channels = 1,
548	.buswidth = 4,
549	.num_links = 1,
550	.link_nodes = { &qhm_snoc_cfg },
551};
552
553static struct qcom_icc_node qhs_spmi_fetcher = {
554	.name = "qhs_spmi_fetcher",
555	.channels = 1,
556	.buswidth = 4,
557};
558
559static struct qcom_icc_node qhs_spmi_vgi_coex = {
560	.name = "qhs_spmi_vgi_coex",
561	.channels = 1,
562	.buswidth = 4,
563};
564
565static struct qcom_icc_node qhs_tcsr = {
566	.name = "qhs_tcsr",
567	.channels = 1,
568	.buswidth = 4,
569};
570
571static struct qcom_icc_node qhs_tlmm = {
572	.name = "qhs_tlmm",
573	.channels = 1,
574	.buswidth = 4,
575};
576
577static struct qcom_icc_node qhs_usb3 = {
578	.name = "qhs_usb3",
579	.channels = 1,
580	.buswidth = 4,
581};
582
583static struct qcom_icc_node qhs_usb3_phy = {
584	.name = "qhs_usb3_phy",
585	.channels = 1,
586	.buswidth = 4,
587};
588
589static struct qcom_icc_node qns_aggre_noc = {
590	.name = "qns_aggre_noc",
591	.channels = 1,
592	.buswidth = 8,
593	.num_links = 1,
594	.link_nodes = { &qnm_aggre_noc },
595};
596
597static struct qcom_icc_node qns_snoc_memnoc = {
598	.name = "qns_snoc_memnoc",
599	.channels = 1,
600	.buswidth = 8,
601	.num_links = 1,
602	.link_nodes = { &qnm_snoc_gc },
603};
604
605static struct qcom_icc_node qxs_imem = {
606	.name = "qxs_imem",
607	.channels = 1,
608	.buswidth = 8,
609};
610
611static struct qcom_icc_node srvc_snoc = {
612	.name = "srvc_snoc",
613	.channels = 1,
614	.buswidth = 4,
615};
616
617static struct qcom_icc_node xs_pcie = {
618	.name = "xs_pcie",
619	.channels = 1,
620	.buswidth = 8,
621};
622
623static struct qcom_icc_node xs_qdss_stm = {
624	.name = "xs_qdss_stm",
625	.channels = 1,
626	.buswidth = 4,
627};
628
629static struct qcom_icc_node xs_sys_tcu_cfg = {
630	.name = "xs_sys_tcu_cfg",
631	.channels = 1,
632	.buswidth = 8,
633};
634
635static struct qcom_icc_bcm bcm_mc0 = {
636	.name = "MC0",
637	.keepalive = true,
638	.num_nodes = 1,
639	.nodes = { &ebi },
640};
641
642static struct qcom_icc_bcm bcm_sh0 = {
643	.name = "SH0",
644	.keepalive = true,
645	.num_nodes = 1,
646	.nodes = { &qns_llcc },
647};
648
649static struct qcom_icc_bcm bcm_ce0 = {
650	.name = "CE0",
651	.keepalive = false,
652	.num_nodes = 1,
653	.nodes = { &qxm_crypto },
654};
655
656static struct qcom_icc_bcm bcm_pn0 = {
657	.name = "PN0",
658	.keepalive = false,
659	.num_nodes = 1,
660	.nodes = { &qhm_snoc_cfg },
661};
662
663static struct qcom_icc_bcm bcm_sh3 = {
664	.name = "SH3",
665	.keepalive = false,
666	.num_nodes = 1,
667	.nodes = { &xm_apps_rdwr },
668};
669
670static struct qcom_icc_bcm bcm_sh4 = {
671	.name = "SH4",
672	.keepalive = false,
673	.num_nodes = 2,
674	.nodes = { &qns_memnoc_snoc, &qns_sys_pcie },
675};
676
677static struct qcom_icc_bcm bcm_sn0 = {
678	.name = "SN0",
679	.keepalive = true,
680	.num_nodes = 1,
681	.nodes = { &qns_snoc_memnoc },
682};
683
684static struct qcom_icc_bcm bcm_sn1 = {
685	.name = "SN1",
686	.keepalive = false,
687	.num_nodes = 1,
688	.nodes = { &qxs_imem },
689};
690
691static struct qcom_icc_bcm bcm_pn1 = {
692	.name = "PN1",
693	.keepalive = false,
694	.num_nodes = 1,
695	.nodes = { &xm_sdc1 },
696};
697
698static struct qcom_icc_bcm bcm_pn2 = {
699	.name = "PN2",
700	.keepalive = false,
701	.num_nodes = 2,
702	.nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
703};
704
705static struct qcom_icc_bcm bcm_sn3 = {
706	.name = "SN3",
707	.keepalive = false,
708	.num_nodes = 1,
709	.nodes = { &xs_qdss_stm },
710};
711
712static struct qcom_icc_bcm bcm_pn3 = {
713	.name = "PN3",
714	.keepalive = false,
715	.num_nodes = 2,
716	.nodes = { &qhm_blsp1, &qhm_qpic },
717};
718
719static struct qcom_icc_bcm bcm_sn4 = {
720	.name = "SN4",
721	.keepalive = false,
722	.num_nodes = 1,
723	.nodes = { &xs_sys_tcu_cfg },
724};
725
726static struct qcom_icc_bcm bcm_pn5 = {
727	.name = "PN5",
728	.keepalive = false,
729	.num_nodes = 1,
730	.nodes = { &qxm_crypto },
731};
732
733static struct qcom_icc_bcm bcm_sn6 = {
734	.name = "SN6",
735	.keepalive = false,
736	.num_nodes = 1,
737	.nodes = { &xs_pcie },
738};
739
740static struct qcom_icc_bcm bcm_sn7 = {
741	.name = "SN7",
742	.keepalive = false,
743	.num_nodes = 5,
744	.nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc },
745};
746
747static struct qcom_icc_bcm bcm_sn8 = {
748	.name = "SN8",
749	.keepalive = false,
750	.num_nodes = 2,
751	.nodes = { &qhm_qdss_bam, &xm_qdss_etr },
752};
753
754static struct qcom_icc_bcm bcm_sn9 = {
755	.name = "SN9",
756	.keepalive = false,
757	.num_nodes = 1,
758	.nodes = { &qnm_memnoc },
759};
760
761static struct qcom_icc_bcm bcm_sn10 = {
762	.name = "SN10",
763	.keepalive = false,
764	.num_nodes = 1,
765	.nodes = { &qnm_memnoc_pcie },
766};
767
768static struct qcom_icc_bcm bcm_sn11 = {
769	.name = "SN11",
770	.keepalive = false,
771	.num_nodes = 2,
772	.nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
773};
774
775static struct qcom_icc_bcm * const mc_virt_bcms[] = {
776	&bcm_mc0,
777};
778
779static struct qcom_icc_node * const mc_virt_nodes[] = {
780	[MASTER_LLCC] = &llcc_mc,
781	[SLAVE_EBI_CH0] = &ebi,
782};
783
784static const struct qcom_icc_desc sdx55_mc_virt = {
785	.nodes = mc_virt_nodes,
786	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
787	.bcms = mc_virt_bcms,
788	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
789};
790
791static struct qcom_icc_bcm * const mem_noc_bcms[] = {
792	&bcm_sh0,
793	&bcm_sh3,
794	&bcm_sh4,
795};
796
797static struct qcom_icc_node * const mem_noc_nodes[] = {
798	[MASTER_TCU_0] = &acm_tcu,
799	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
800	[MASTER_AMPSS_M0] = &xm_apps_rdwr,
801	[SLAVE_LLCC] = &qns_llcc,
802	[SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
803	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
804};
805
806static const struct qcom_icc_desc sdx55_mem_noc = {
807	.nodes = mem_noc_nodes,
808	.num_nodes = ARRAY_SIZE(mem_noc_nodes),
809	.bcms = mem_noc_bcms,
810	.num_bcms = ARRAY_SIZE(mem_noc_bcms),
811};
812
813static struct qcom_icc_bcm * const system_noc_bcms[] = {
814	&bcm_ce0,
815	&bcm_pn0,
816	&bcm_pn1,
817	&bcm_pn2,
818	&bcm_pn3,
819	&bcm_pn5,
820	&bcm_sn0,
821	&bcm_sn1,
822	&bcm_sn3,
823	&bcm_sn4,
824	&bcm_sn6,
825	&bcm_sn7,
826	&bcm_sn8,
827	&bcm_sn9,
828	&bcm_sn10,
829	&bcm_sn11,
830};
831
832static struct qcom_icc_node * const system_noc_nodes[] = {
833	[MASTER_AUDIO] = &qhm_audio,
834	[MASTER_BLSP_1] = &qhm_blsp1,
835	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
836	[MASTER_QPIC] = &qhm_qpic,
837	[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
838	[MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
839	[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
840	[MASTER_IPA] = &qnm_ipa,
841	[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
842	[MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
843	[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
844	[MASTER_EMAC] = &xm_emac,
845	[MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
846	[MASTER_PCIE] = &xm_pcie,
847	[MASTER_QDSS_ETR] = &xm_qdss_etr,
848	[MASTER_SDCC_1] = &xm_sdc1,
849	[MASTER_USB3] = &xm_usb3,
850	[SLAVE_AOP] = &qhs_aop,
851	[SLAVE_AOSS] = &qhs_aoss,
852	[SLAVE_APPSS] = &qhs_apss,
853	[SLAVE_AUDIO] = &qhs_audio,
854	[SLAVE_BLSP_1] = &qhs_blsp1,
855	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
856	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
857	[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
858	[SLAVE_ECC_CFG] = &qhs_ecc_cfg,
859	[SLAVE_EMAC_CFG] = &qhs_emac_cfg,
860	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
861	[SLAVE_IPA_CFG] = &qhs_ipa,
862	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
863	[SLAVE_PCIE_PARF] = &qhs_pcie_parf,
864	[SLAVE_PDM] = &qhs_pdm,
865	[SLAVE_PRNG] = &qhs_prng,
866	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
867	[SLAVE_QPIC] = &qhs_qpic,
868	[SLAVE_SDCC_1] = &qhs_sdc1,
869	[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
870	[SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
871	[SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
872	[SLAVE_TCSR] = &qhs_tcsr,
873	[SLAVE_TLMM] = &qhs_tlmm,
874	[SLAVE_USB3] = &qhs_usb3,
875	[SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
876	[SLAVE_ANOC_SNOC] = &qns_aggre_noc,
877	[SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
878	[SLAVE_OCIMEM] = &qxs_imem,
879	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
880	[SLAVE_PCIE_0] = &xs_pcie,
881	[SLAVE_QDSS_STM] = &xs_qdss_stm,
882	[SLAVE_TCU] = &xs_sys_tcu_cfg,
883};
884
885static const struct qcom_icc_desc sdx55_system_noc = {
886	.nodes = system_noc_nodes,
887	.num_nodes = ARRAY_SIZE(system_noc_nodes),
888	.bcms = system_noc_bcms,
889	.num_bcms = ARRAY_SIZE(system_noc_bcms),
890};
891
892static const struct of_device_id qnoc_of_match[] = {
893	{ .compatible = "qcom,sdx55-mc-virt",
894	  .data = &sdx55_mc_virt},
895	{ .compatible = "qcom,sdx55-mem-noc",
896	  .data = &sdx55_mem_noc},
897	{ .compatible = "qcom,sdx55-system-noc",
898	  .data = &sdx55_system_noc},
899	{ }
900};
901MODULE_DEVICE_TABLE(of, qnoc_of_match);
902
903static struct platform_driver qnoc_driver = {
904	.probe = qcom_icc_rpmh_probe,
905	.remove = qcom_icc_rpmh_remove,
906	.driver = {
907		.name = "qnoc-sdx55",
908		.of_match_table = qnoc_of_match,
909		.sync_state = icc_sync_state,
910	},
911};
912module_platform_driver(qnoc_driver);
913
914MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver");
915MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
916MODULE_LICENSE("GPL v2");