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sdm845.c
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linux-6.19.14/drivers/interconnect/qcom/sdm845.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/device.h> 7#include <linux/interconnect.h> 8#include <linux/interconnect-provider.h> 9#include <linux/module.h> 10#include <linux/mod_devicetable.h> 11#include <linux/platform_device.h> 12 13#include <dt-bindings/interconnect/qcom,sdm845.h> 14 15#include "bcm-voter.h" 16#include "icc-rpmh.h" 17 18static struct qcom_icc_node qhm_a1noc_cfg; 19static struct qcom_icc_node qhm_qup1; 20static struct qcom_icc_node qhm_tsif; 21static struct qcom_icc_node xm_sdc2; 22static struct qcom_icc_node xm_sdc4; 23static struct qcom_icc_node xm_ufs_card; 24static struct qcom_icc_node xm_ufs_mem; 25static struct qcom_icc_node xm_pcie_0; 26static struct qcom_icc_node qhm_a2noc_cfg; 27static struct qcom_icc_node qhm_qdss_bam; 28static struct qcom_icc_node qhm_qup2; 29static struct qcom_icc_node qnm_cnoc; 30static struct qcom_icc_node qxm_crypto; 31static struct qcom_icc_node qxm_ipa; 32static struct qcom_icc_node xm_pcie3_1; 33static struct qcom_icc_node xm_qdss_etr; 34static struct qcom_icc_node xm_usb3_0; 35static struct qcom_icc_node xm_usb3_1; 36static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 37static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 38static struct qcom_icc_node qxm_camnoc_sf_uncomp; 39static struct qcom_icc_node qhm_spdm; 40static struct qcom_icc_node qhm_tic; 41static struct qcom_icc_node qnm_snoc; 42static struct qcom_icc_node xm_qdss_dap; 43static struct qcom_icc_node qhm_cnoc; 44static struct qcom_icc_node acm_l3; 45static struct qcom_icc_node pm_gnoc_cfg; 46static struct qcom_icc_node llcc_mc; 47static struct qcom_icc_node acm_tcu; 48static struct qcom_icc_node qhm_memnoc_cfg; 49static struct qcom_icc_node qnm_apps; 50static struct qcom_icc_node qnm_mnoc_hf; 51static struct qcom_icc_node qnm_mnoc_sf; 52static struct qcom_icc_node qnm_snoc_gc; 53static struct qcom_icc_node qnm_snoc_sf; 54static struct qcom_icc_node qxm_gpu; 55static struct qcom_icc_node qhm_mnoc_cfg; 56static struct qcom_icc_node qxm_camnoc_hf0; 57static struct qcom_icc_node qxm_camnoc_hf1; 58static struct qcom_icc_node qxm_camnoc_sf; 59static struct qcom_icc_node qxm_mdp0; 60static struct qcom_icc_node qxm_mdp1; 61static struct qcom_icc_node qxm_rot; 62static struct qcom_icc_node qxm_venus0; 63static struct qcom_icc_node qxm_venus1; 64static struct qcom_icc_node qxm_venus_arm9; 65static struct qcom_icc_node qhm_snoc_cfg; 66static struct qcom_icc_node qnm_aggre1_noc; 67static struct qcom_icc_node qnm_aggre2_noc; 68static struct qcom_icc_node qnm_gladiator_sodv; 69static struct qcom_icc_node qnm_memnoc; 70static struct qcom_icc_node qnm_pcie_anoc; 71static struct qcom_icc_node qxm_pimem; 72static struct qcom_icc_node xm_gic; 73static struct qcom_icc_node qns_a1noc_snoc; 74static struct qcom_icc_node srvc_aggre1_noc; 75static struct qcom_icc_node qns_pcie_a1noc_snoc; 76static struct qcom_icc_node qns_a2noc_snoc; 77static struct qcom_icc_node qns_pcie_snoc; 78static struct qcom_icc_node srvc_aggre2_noc; 79static struct qcom_icc_node qns_camnoc_uncomp; 80static struct qcom_icc_node qhs_a1_noc_cfg; 81static struct qcom_icc_node qhs_a2_noc_cfg; 82static struct qcom_icc_node qhs_aop; 83static struct qcom_icc_node qhs_aoss; 84static struct qcom_icc_node qhs_camera_cfg; 85static struct qcom_icc_node qhs_clk_ctl; 86static struct qcom_icc_node qhs_compute_dsp_cfg; 87static struct qcom_icc_node qhs_cpr_cx; 88static struct qcom_icc_node qhs_crypto0_cfg; 89static struct qcom_icc_node qhs_dcc_cfg; 90static struct qcom_icc_node qhs_ddrss_cfg; 91static struct qcom_icc_node qhs_display_cfg; 92static struct qcom_icc_node qhs_glm; 93static struct qcom_icc_node qhs_gpuss_cfg; 94static struct qcom_icc_node qhs_imem_cfg; 95static struct qcom_icc_node qhs_ipa; 96static struct qcom_icc_node qhs_mnoc_cfg; 97static struct qcom_icc_node qhs_pcie0_cfg; 98static struct qcom_icc_node qhs_pcie_gen3_cfg; 99static struct qcom_icc_node qhs_pdm; 100static struct qcom_icc_node qhs_phy_refgen_south; 101static struct qcom_icc_node qhs_pimem_cfg; 102static struct qcom_icc_node qhs_prng; 103static struct qcom_icc_node qhs_qdss_cfg; 104static struct qcom_icc_node qhs_qupv3_north; 105static struct qcom_icc_node qhs_qupv3_south; 106static struct qcom_icc_node qhs_sdc2; 107static struct qcom_icc_node qhs_sdc4; 108static struct qcom_icc_node qhs_snoc_cfg; 109static struct qcom_icc_node qhs_spdm; 110static struct qcom_icc_node qhs_spss_cfg; 111static struct qcom_icc_node qhs_tcsr; 112static struct qcom_icc_node qhs_tlmm_north; 113static struct qcom_icc_node qhs_tlmm_south; 114static struct qcom_icc_node qhs_tsif; 115static struct qcom_icc_node qhs_ufs_card_cfg; 116static struct qcom_icc_node qhs_ufs_mem_cfg; 117static struct qcom_icc_node qhs_usb3_0; 118static struct qcom_icc_node qhs_usb3_1; 119static struct qcom_icc_node qhs_venus_cfg; 120static struct qcom_icc_node qhs_vsense_ctrl_cfg; 121static struct qcom_icc_node qns_cnoc_a2noc; 122static struct qcom_icc_node srvc_cnoc; 123static struct qcom_icc_node qhs_llcc; 124static struct qcom_icc_node qhs_memnoc; 125static struct qcom_icc_node qns_gladiator_sodv; 126static struct qcom_icc_node qns_gnoc_memnoc; 127static struct qcom_icc_node srvc_gnoc; 128static struct qcom_icc_node ebi; 129static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 130static struct qcom_icc_node qns_apps_io; 131static struct qcom_icc_node qns_llcc; 132static struct qcom_icc_node qns_memnoc_snoc; 133static struct qcom_icc_node srvc_memnoc; 134static struct qcom_icc_node qns2_mem_noc; 135static struct qcom_icc_node qns_mem_noc_hf; 136static struct qcom_icc_node srvc_mnoc; 137static struct qcom_icc_node qhs_apss; 138static struct qcom_icc_node qns_cnoc; 139static struct qcom_icc_node qns_memnoc_gc; 140static struct qcom_icc_node qns_memnoc_sf; 141static struct qcom_icc_node qxs_imem; 142static struct qcom_icc_node qxs_pcie; 143static struct qcom_icc_node qxs_pcie_gen3; 144static struct qcom_icc_node qxs_pimem; 145static struct qcom_icc_node srvc_snoc; 146static struct qcom_icc_node xs_qdss_stm; 147static struct qcom_icc_node xs_sys_tcu_cfg; 148 149static struct qcom_icc_node qhm_a1noc_cfg = { 150 .name = "qhm_a1noc_cfg", 151 .channels = 1, 152 .buswidth = 4, 153 .num_links = 1, 154 .link_nodes = { &srvc_aggre1_noc }, 155}; 156 157static struct qcom_icc_node qhm_qup1 = { 158 .name = "qhm_qup1", 159 .channels = 1, 160 .buswidth = 4, 161 .num_links = 1, 162 .link_nodes = { &qns_a1noc_snoc }, 163}; 164 165static struct qcom_icc_node qhm_tsif = { 166 .name = "qhm_tsif", 167 .channels = 1, 168 .buswidth = 4, 169 .num_links = 1, 170 .link_nodes = { &qns_a1noc_snoc }, 171}; 172 173static struct qcom_icc_node xm_sdc2 = { 174 .name = "xm_sdc2", 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .link_nodes = { &qns_a1noc_snoc }, 179}; 180 181static struct qcom_icc_node xm_sdc4 = { 182 .name = "xm_sdc4", 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187}; 188 189static struct qcom_icc_node xm_ufs_card = { 190 .name = "xm_ufs_card", 191 .channels = 1, 192 .buswidth = 8, 193 .num_links = 1, 194 .link_nodes = { &qns_a1noc_snoc }, 195}; 196 197static struct qcom_icc_node xm_ufs_mem = { 198 .name = "xm_ufs_mem", 199 .channels = 1, 200 .buswidth = 8, 201 .num_links = 1, 202 .link_nodes = { &qns_a1noc_snoc }, 203}; 204 205static struct qcom_icc_node xm_pcie_0 = { 206 .name = "xm_pcie_0", 207 .channels = 1, 208 .buswidth = 8, 209 .num_links = 1, 210 .link_nodes = { &qns_pcie_a1noc_snoc }, 211}; 212 213static struct qcom_icc_node qhm_a2noc_cfg = { 214 .name = "qhm_a2noc_cfg", 215 .channels = 1, 216 .buswidth = 4, 217 .num_links = 1, 218 .link_nodes = { &srvc_aggre2_noc }, 219}; 220 221static struct qcom_icc_node qhm_qdss_bam = { 222 .name = "qhm_qdss_bam", 223 .channels = 1, 224 .buswidth = 4, 225 .num_links = 1, 226 .link_nodes = { &qns_a2noc_snoc }, 227}; 228 229static struct qcom_icc_node qhm_qup2 = { 230 .name = "qhm_qup2", 231 .channels = 1, 232 .buswidth = 4, 233 .num_links = 1, 234 .link_nodes = { &qns_a2noc_snoc }, 235}; 236 237static struct qcom_icc_node qnm_cnoc = { 238 .name = "qnm_cnoc", 239 .channels = 1, 240 .buswidth = 8, 241 .num_links = 1, 242 .link_nodes = { &qns_a2noc_snoc }, 243}; 244 245static struct qcom_icc_node qxm_crypto = { 246 .name = "qxm_crypto", 247 .channels = 1, 248 .buswidth = 8, 249 .num_links = 1, 250 .link_nodes = { &qns_a2noc_snoc }, 251}; 252 253static struct qcom_icc_node qxm_ipa = { 254 .name = "qxm_ipa", 255 .channels = 1, 256 .buswidth = 8, 257 .num_links = 1, 258 .link_nodes = { &qns_a2noc_snoc }, 259}; 260 261static struct qcom_icc_node xm_pcie3_1 = { 262 .name = "xm_pcie3_1", 263 .channels = 1, 264 .buswidth = 8, 265 .num_links = 1, 266 .link_nodes = { &qns_pcie_snoc }, 267}; 268 269static struct qcom_icc_node xm_qdss_etr = { 270 .name = "xm_qdss_etr", 271 .channels = 1, 272 .buswidth = 8, 273 .num_links = 1, 274 .link_nodes = { &qns_a2noc_snoc }, 275}; 276 277static struct qcom_icc_node xm_usb3_0 = { 278 .name = "xm_usb3_0", 279 .channels = 1, 280 .buswidth = 8, 281 .num_links = 1, 282 .link_nodes = { &qns_a2noc_snoc }, 283}; 284 285static struct qcom_icc_node xm_usb3_1 = { 286 .name = "xm_usb3_1", 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 1, 290 .link_nodes = { &qns_a2noc_snoc }, 291}; 292 293static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 294 .name = "qxm_camnoc_hf0_uncomp", 295 .channels = 1, 296 .buswidth = 32, 297 .num_links = 1, 298 .link_nodes = { &qns_camnoc_uncomp }, 299}; 300 301static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 302 .name = "qxm_camnoc_hf1_uncomp", 303 .channels = 1, 304 .buswidth = 32, 305 .num_links = 1, 306 .link_nodes = { &qns_camnoc_uncomp }, 307}; 308 309static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 310 .name = "qxm_camnoc_sf_uncomp", 311 .channels = 1, 312 .buswidth = 32, 313 .num_links = 1, 314 .link_nodes = { &qns_camnoc_uncomp }, 315}; 316 317static struct qcom_icc_node qhm_spdm = { 318 .name = "qhm_spdm", 319 .channels = 1, 320 .buswidth = 4, 321 .num_links = 1, 322 .link_nodes = { &qns_cnoc_a2noc }, 323}; 324 325static struct qcom_icc_node qhm_tic = { 326 .name = "qhm_tic", 327 .channels = 1, 328 .buswidth = 4, 329 .num_links = 43, 330 .link_nodes = { &qhs_a1_noc_cfg, 331 &qhs_a2_noc_cfg, 332 &qhs_aop, 333 &qhs_aoss, 334 &qhs_camera_cfg, 335 &qhs_clk_ctl, 336 &qhs_compute_dsp_cfg, 337 &qhs_cpr_cx, 338 &qhs_crypto0_cfg, 339 &qhs_dcc_cfg, 340 &qhs_ddrss_cfg, 341 &qhs_display_cfg, 342 &qhs_glm, 343 &qhs_gpuss_cfg, 344 &qhs_imem_cfg, 345 &qhs_ipa, 346 &qhs_mnoc_cfg, 347 &qhs_pcie0_cfg, 348 &qhs_pcie_gen3_cfg, 349 &qhs_pdm, 350 &qhs_phy_refgen_south, 351 &qhs_pimem_cfg, 352 &qhs_prng, 353 &qhs_qdss_cfg, 354 &qhs_qupv3_north, 355 &qhs_qupv3_south, 356 &qhs_sdc2, 357 &qhs_sdc4, 358 &qhs_snoc_cfg, 359 &qhs_spdm, 360 &qhs_spss_cfg, 361 &qhs_tcsr, 362 &qhs_tlmm_north, 363 &qhs_tlmm_south, 364 &qhs_tsif, 365 &qhs_ufs_card_cfg, 366 &qhs_ufs_mem_cfg, 367 &qhs_usb3_0, 368 &qhs_usb3_1, 369 &qhs_venus_cfg, 370 &qhs_vsense_ctrl_cfg, 371 &qns_cnoc_a2noc, 372 &srvc_cnoc }, 373}; 374 375static struct qcom_icc_node qnm_snoc = { 376 .name = "qnm_snoc", 377 .channels = 1, 378 .buswidth = 8, 379 .num_links = 42, 380 .link_nodes = { &qhs_a1_noc_cfg, 381 &qhs_a2_noc_cfg, 382 &qhs_aop, 383 &qhs_aoss, 384 &qhs_camera_cfg, 385 &qhs_clk_ctl, 386 &qhs_compute_dsp_cfg, 387 &qhs_cpr_cx, 388 &qhs_crypto0_cfg, 389 &qhs_dcc_cfg, 390 &qhs_ddrss_cfg, 391 &qhs_display_cfg, 392 &qhs_glm, 393 &qhs_gpuss_cfg, 394 &qhs_imem_cfg, 395 &qhs_ipa, 396 &qhs_mnoc_cfg, 397 &qhs_pcie0_cfg, 398 &qhs_pcie_gen3_cfg, 399 &qhs_pdm, 400 &qhs_phy_refgen_south, 401 &qhs_pimem_cfg, 402 &qhs_prng, 403 &qhs_qdss_cfg, 404 &qhs_qupv3_north, 405 &qhs_qupv3_south, 406 &qhs_sdc2, 407 &qhs_sdc4, 408 &qhs_snoc_cfg, 409 &qhs_spdm, 410 &qhs_spss_cfg, 411 &qhs_tcsr, 412 &qhs_tlmm_north, 413 &qhs_tlmm_south, 414 &qhs_tsif, 415 &qhs_ufs_card_cfg, 416 &qhs_ufs_mem_cfg, 417 &qhs_usb3_0, 418 &qhs_usb3_1, 419 &qhs_venus_cfg, 420 &qhs_vsense_ctrl_cfg, 421 &srvc_cnoc }, 422}; 423 424static struct qcom_icc_node xm_qdss_dap = { 425 .name = "xm_qdss_dap", 426 .channels = 1, 427 .buswidth = 8, 428 .num_links = 43, 429 .link_nodes = { &qhs_a1_noc_cfg, 430 &qhs_a2_noc_cfg, 431 &qhs_aop, 432 &qhs_aoss, 433 &qhs_camera_cfg, 434 &qhs_clk_ctl, 435 &qhs_compute_dsp_cfg, 436 &qhs_cpr_cx, 437 &qhs_crypto0_cfg, 438 &qhs_dcc_cfg, 439 &qhs_ddrss_cfg, 440 &qhs_display_cfg, 441 &qhs_glm, 442 &qhs_gpuss_cfg, 443 &qhs_imem_cfg, 444 &qhs_ipa, 445 &qhs_mnoc_cfg, 446 &qhs_pcie0_cfg, 447 &qhs_pcie_gen3_cfg, 448 &qhs_pdm, 449 &qhs_phy_refgen_south, 450 &qhs_pimem_cfg, 451 &qhs_prng, 452 &qhs_qdss_cfg, 453 &qhs_qupv3_north, 454 &qhs_qupv3_south, 455 &qhs_sdc2, 456 &qhs_sdc4, 457 &qhs_snoc_cfg, 458 &qhs_spdm, 459 &qhs_spss_cfg, 460 &qhs_tcsr, 461 &qhs_tlmm_north, 462 &qhs_tlmm_south, 463 &qhs_tsif, 464 &qhs_ufs_card_cfg, 465 &qhs_ufs_mem_cfg, 466 &qhs_usb3_0, 467 &qhs_usb3_1, 468 &qhs_venus_cfg, 469 &qhs_vsense_ctrl_cfg, 470 &qns_cnoc_a2noc, 471 &srvc_cnoc }, 472}; 473 474static struct qcom_icc_node qhm_cnoc = { 475 .name = "qhm_cnoc", 476 .channels = 1, 477 .buswidth = 4, 478 .num_links = 2, 479 .link_nodes = { &qhs_llcc, 480 &qhs_memnoc }, 481}; 482 483static struct qcom_icc_node acm_l3 = { 484 .name = "acm_l3", 485 .channels = 1, 486 .buswidth = 16, 487 .num_links = 3, 488 .link_nodes = { &qns_gladiator_sodv, 489 &qns_gnoc_memnoc, 490 &srvc_gnoc }, 491}; 492 493static struct qcom_icc_node pm_gnoc_cfg = { 494 .name = "pm_gnoc_cfg", 495 .channels = 1, 496 .buswidth = 4, 497 .num_links = 1, 498 .link_nodes = { &srvc_gnoc }, 499}; 500 501static struct qcom_icc_node llcc_mc = { 502 .name = "llcc_mc", 503 .channels = 4, 504 .buswidth = 4, 505 .num_links = 1, 506 .link_nodes = { &ebi }, 507}; 508 509static struct qcom_icc_node acm_tcu = { 510 .name = "acm_tcu", 511 .channels = 1, 512 .buswidth = 8, 513 .num_links = 3, 514 .link_nodes = { &qns_apps_io, 515 &qns_llcc, 516 &qns_memnoc_snoc }, 517}; 518 519static struct qcom_icc_node qhm_memnoc_cfg = { 520 .name = "qhm_memnoc_cfg", 521 .channels = 1, 522 .buswidth = 4, 523 .num_links = 2, 524 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, 525 &srvc_memnoc }, 526}; 527 528static struct qcom_icc_node qnm_apps = { 529 .name = "qnm_apps", 530 .channels = 2, 531 .buswidth = 32, 532 .num_links = 1, 533 .link_nodes = { &qns_llcc }, 534}; 535 536static struct qcom_icc_node qnm_mnoc_hf = { 537 .name = "qnm_mnoc_hf", 538 .channels = 2, 539 .buswidth = 32, 540 .num_links = 2, 541 .link_nodes = { &qns_apps_io, 542 &qns_llcc }, 543}; 544 545static struct qcom_icc_node qnm_mnoc_sf = { 546 .name = "qnm_mnoc_sf", 547 .channels = 1, 548 .buswidth = 32, 549 .num_links = 3, 550 .link_nodes = { &qns_apps_io, 551 &qns_llcc, 552 &qns_memnoc_snoc }, 553}; 554 555static struct qcom_icc_node qnm_snoc_gc = { 556 .name = "qnm_snoc_gc", 557 .channels = 1, 558 .buswidth = 8, 559 .num_links = 1, 560 .link_nodes = { &qns_llcc }, 561}; 562 563static struct qcom_icc_node qnm_snoc_sf = { 564 .name = "qnm_snoc_sf", 565 .channels = 1, 566 .buswidth = 16, 567 .num_links = 2, 568 .link_nodes = { &qns_apps_io, 569 &qns_llcc }, 570}; 571 572static struct qcom_icc_node qxm_gpu = { 573 .name = "qxm_gpu", 574 .channels = 2, 575 .buswidth = 32, 576 .num_links = 3, 577 .link_nodes = { &qns_apps_io, 578 &qns_llcc, 579 &qns_memnoc_snoc }, 580}; 581 582static struct qcom_icc_node qhm_mnoc_cfg = { 583 .name = "qhm_mnoc_cfg", 584 .channels = 1, 585 .buswidth = 4, 586 .num_links = 1, 587 .link_nodes = { &srvc_mnoc }, 588}; 589 590static struct qcom_icc_node qxm_camnoc_hf0 = { 591 .name = "qxm_camnoc_hf0", 592 .channels = 1, 593 .buswidth = 32, 594 .num_links = 1, 595 .link_nodes = { &qns_mem_noc_hf }, 596}; 597 598static struct qcom_icc_node qxm_camnoc_hf1 = { 599 .name = "qxm_camnoc_hf1", 600 .channels = 1, 601 .buswidth = 32, 602 .num_links = 1, 603 .link_nodes = { &qns_mem_noc_hf }, 604}; 605 606static struct qcom_icc_node qxm_camnoc_sf = { 607 .name = "qxm_camnoc_sf", 608 .channels = 1, 609 .buswidth = 32, 610 .num_links = 1, 611 .link_nodes = { &qns2_mem_noc }, 612}; 613 614static struct qcom_icc_node qxm_mdp0 = { 615 .name = "qxm_mdp0", 616 .channels = 1, 617 .buswidth = 32, 618 .num_links = 1, 619 .link_nodes = { &qns_mem_noc_hf }, 620}; 621 622static struct qcom_icc_node qxm_mdp1 = { 623 .name = "qxm_mdp1", 624 .channels = 1, 625 .buswidth = 32, 626 .num_links = 1, 627 .link_nodes = { &qns_mem_noc_hf }, 628}; 629 630static struct qcom_icc_node qxm_rot = { 631 .name = "qxm_rot", 632 .channels = 1, 633 .buswidth = 32, 634 .num_links = 1, 635 .link_nodes = { &qns2_mem_noc }, 636}; 637 638static struct qcom_icc_node qxm_venus0 = { 639 .name = "qxm_venus0", 640 .channels = 1, 641 .buswidth = 32, 642 .num_links = 1, 643 .link_nodes = { &qns2_mem_noc }, 644}; 645 646static struct qcom_icc_node qxm_venus1 = { 647 .name = "qxm_venus1", 648 .channels = 1, 649 .buswidth = 32, 650 .num_links = 1, 651 .link_nodes = { &qns2_mem_noc }, 652}; 653 654static struct qcom_icc_node qxm_venus_arm9 = { 655 .name = "qxm_venus_arm9", 656 .channels = 1, 657 .buswidth = 8, 658 .num_links = 1, 659 .link_nodes = { &qns2_mem_noc }, 660}; 661 662static struct qcom_icc_node qhm_snoc_cfg = { 663 .name = "qhm_snoc_cfg", 664 .channels = 1, 665 .buswidth = 4, 666 .num_links = 1, 667 .link_nodes = { &srvc_snoc }, 668}; 669 670static struct qcom_icc_node qnm_aggre1_noc = { 671 .name = "qnm_aggre1_noc", 672 .channels = 1, 673 .buswidth = 16, 674 .num_links = 6, 675 .link_nodes = { &qhs_apss, 676 &qns_cnoc, 677 &qns_memnoc_sf, 678 &qxs_imem, 679 &qxs_pimem, 680 &xs_qdss_stm }, 681}; 682 683static struct qcom_icc_node qnm_aggre2_noc = { 684 .name = "qnm_aggre2_noc", 685 .channels = 1, 686 .buswidth = 16, 687 .num_links = 9, 688 .link_nodes = { &qhs_apss, 689 &qns_cnoc, 690 &qns_memnoc_sf, 691 &qxs_imem, 692 &qxs_pcie, 693 &qxs_pcie_gen3, 694 &qxs_pimem, 695 &xs_qdss_stm, 696 &xs_sys_tcu_cfg }, 697}; 698 699static struct qcom_icc_node qnm_gladiator_sodv = { 700 .name = "qnm_gladiator_sodv", 701 .channels = 1, 702 .buswidth = 8, 703 .num_links = 8, 704 .link_nodes = { &qhs_apss, 705 &qns_cnoc, 706 &qxs_imem, 707 &qxs_pcie, 708 &qxs_pcie_gen3, 709 &qxs_pimem, 710 &xs_qdss_stm, 711 &xs_sys_tcu_cfg }, 712}; 713 714static struct qcom_icc_node qnm_memnoc = { 715 .name = "qnm_memnoc", 716 .channels = 1, 717 .buswidth = 8, 718 .num_links = 5, 719 .link_nodes = { &qhs_apss, 720 &qns_cnoc, 721 &qxs_imem, 722 &qxs_pimem, 723 &xs_qdss_stm }, 724}; 725 726static struct qcom_icc_node qnm_pcie_anoc = { 727 .name = "qnm_pcie_anoc", 728 .channels = 1, 729 .buswidth = 16, 730 .num_links = 5, 731 .link_nodes = { &qhs_apss, 732 &qns_cnoc, 733 &qns_memnoc_sf, 734 &qxs_imem, 735 &xs_qdss_stm }, 736}; 737 738static struct qcom_icc_node qxm_pimem = { 739 .name = "qxm_pimem", 740 .channels = 1, 741 .buswidth = 8, 742 .num_links = 2, 743 .link_nodes = { &qns_memnoc_gc, 744 &qxs_imem }, 745}; 746 747static struct qcom_icc_node xm_gic = { 748 .name = "xm_gic", 749 .channels = 1, 750 .buswidth = 8, 751 .num_links = 2, 752 .link_nodes = { &qns_memnoc_gc, 753 &qxs_imem }, 754}; 755 756static struct qcom_icc_node qns_a1noc_snoc = { 757 .name = "qns_a1noc_snoc", 758 .channels = 1, 759 .buswidth = 16, 760 .num_links = 1, 761 .link_nodes = { &qnm_aggre1_noc }, 762}; 763 764static struct qcom_icc_node srvc_aggre1_noc = { 765 .name = "srvc_aggre1_noc", 766 .channels = 1, 767 .buswidth = 4, 768}; 769 770static struct qcom_icc_node qns_pcie_a1noc_snoc = { 771 .name = "qns_pcie_a1noc_snoc", 772 .channels = 1, 773 .buswidth = 16, 774 .num_links = 1, 775 .link_nodes = { &qnm_pcie_anoc }, 776}; 777 778static struct qcom_icc_node qns_a2noc_snoc = { 779 .name = "qns_a2noc_snoc", 780 .channels = 1, 781 .buswidth = 16, 782 .num_links = 1, 783 .link_nodes = { &qnm_aggre2_noc }, 784}; 785 786static struct qcom_icc_node qns_pcie_snoc = { 787 .name = "qns_pcie_snoc", 788 .channels = 1, 789 .buswidth = 16, 790 .num_links = 1, 791 .link_nodes = { &qnm_pcie_anoc }, 792}; 793 794static struct qcom_icc_node srvc_aggre2_noc = { 795 .name = "srvc_aggre2_noc", 796 .channels = 1, 797 .buswidth = 4, 798}; 799 800static struct qcom_icc_node qns_camnoc_uncomp = { 801 .name = "qns_camnoc_uncomp", 802 .channels = 1, 803 .buswidth = 32, 804}; 805 806static struct qcom_icc_node qhs_a1_noc_cfg = { 807 .name = "qhs_a1_noc_cfg", 808 .channels = 1, 809 .buswidth = 4, 810 .num_links = 1, 811 .link_nodes = { &qhm_a1noc_cfg }, 812}; 813 814static struct qcom_icc_node qhs_a2_noc_cfg = { 815 .name = "qhs_a2_noc_cfg", 816 .channels = 1, 817 .buswidth = 4, 818 .num_links = 1, 819 .link_nodes = { &qhm_a2noc_cfg }, 820}; 821 822static struct qcom_icc_node qhs_aop = { 823 .name = "qhs_aop", 824 .channels = 1, 825 .buswidth = 4, 826}; 827 828static struct qcom_icc_node qhs_aoss = { 829 .name = "qhs_aoss", 830 .channels = 1, 831 .buswidth = 4, 832}; 833 834static struct qcom_icc_node qhs_camera_cfg = { 835 .name = "qhs_camera_cfg", 836 .channels = 1, 837 .buswidth = 4, 838}; 839 840static struct qcom_icc_node qhs_clk_ctl = { 841 .name = "qhs_clk_ctl", 842 .channels = 1, 843 .buswidth = 4, 844}; 845 846static struct qcom_icc_node qhs_compute_dsp_cfg = { 847 .name = "qhs_compute_dsp_cfg", 848 .channels = 1, 849 .buswidth = 4, 850}; 851 852static struct qcom_icc_node qhs_cpr_cx = { 853 .name = "qhs_cpr_cx", 854 .channels = 1, 855 .buswidth = 4, 856}; 857 858static struct qcom_icc_node qhs_crypto0_cfg = { 859 .name = "qhs_crypto0_cfg", 860 .channels = 1, 861 .buswidth = 4, 862}; 863 864static struct qcom_icc_node qhs_dcc_cfg = { 865 .name = "qhs_dcc_cfg", 866 .channels = 1, 867 .buswidth = 4, 868 .num_links = 1, 869 .link_nodes = { &qhm_cnoc }, 870}; 871 872static struct qcom_icc_node qhs_ddrss_cfg = { 873 .name = "qhs_ddrss_cfg", 874 .channels = 1, 875 .buswidth = 4, 876}; 877 878static struct qcom_icc_node qhs_display_cfg = { 879 .name = "qhs_display_cfg", 880 .channels = 1, 881 .buswidth = 4, 882}; 883 884static struct qcom_icc_node qhs_glm = { 885 .name = "qhs_glm", 886 .channels = 1, 887 .buswidth = 4, 888}; 889 890static struct qcom_icc_node qhs_gpuss_cfg = { 891 .name = "qhs_gpuss_cfg", 892 .channels = 1, 893 .buswidth = 8, 894}; 895 896static struct qcom_icc_node qhs_imem_cfg = { 897 .name = "qhs_imem_cfg", 898 .channels = 1, 899 .buswidth = 4, 900}; 901 902static struct qcom_icc_node qhs_ipa = { 903 .name = "qhs_ipa", 904 .channels = 1, 905 .buswidth = 4, 906}; 907 908static struct qcom_icc_node qhs_mnoc_cfg = { 909 .name = "qhs_mnoc_cfg", 910 .channels = 1, 911 .buswidth = 4, 912 .num_links = 1, 913 .link_nodes = { &qhm_mnoc_cfg }, 914}; 915 916static struct qcom_icc_node qhs_pcie0_cfg = { 917 .name = "qhs_pcie0_cfg", 918 .channels = 1, 919 .buswidth = 4, 920}; 921 922static struct qcom_icc_node qhs_pcie_gen3_cfg = { 923 .name = "qhs_pcie_gen3_cfg", 924 .channels = 1, 925 .buswidth = 4, 926}; 927 928static struct qcom_icc_node qhs_pdm = { 929 .name = "qhs_pdm", 930 .channels = 1, 931 .buswidth = 4, 932}; 933 934static struct qcom_icc_node qhs_phy_refgen_south = { 935 .name = "qhs_phy_refgen_south", 936 .channels = 1, 937 .buswidth = 4, 938}; 939 940static struct qcom_icc_node qhs_pimem_cfg = { 941 .name = "qhs_pimem_cfg", 942 .channels = 1, 943 .buswidth = 4, 944}; 945 946static struct qcom_icc_node qhs_prng = { 947 .name = "qhs_prng", 948 .channels = 1, 949 .buswidth = 4, 950}; 951 952static struct qcom_icc_node qhs_qdss_cfg = { 953 .name = "qhs_qdss_cfg", 954 .channels = 1, 955 .buswidth = 4, 956}; 957 958static struct qcom_icc_node qhs_qupv3_north = { 959 .name = "qhs_qupv3_north", 960 .channels = 1, 961 .buswidth = 4, 962}; 963 964static struct qcom_icc_node qhs_qupv3_south = { 965 .name = "qhs_qupv3_south", 966 .channels = 1, 967 .buswidth = 4, 968}; 969 970static struct qcom_icc_node qhs_sdc2 = { 971 .name = "qhs_sdc2", 972 .channels = 1, 973 .buswidth = 4, 974}; 975 976static struct qcom_icc_node qhs_sdc4 = { 977 .name = "qhs_sdc4", 978 .channels = 1, 979 .buswidth = 4, 980}; 981 982static struct qcom_icc_node qhs_snoc_cfg = { 983 .name = "qhs_snoc_cfg", 984 .channels = 1, 985 .buswidth = 4, 986 .num_links = 1, 987 .link_nodes = { &qhm_snoc_cfg }, 988}; 989 990static struct qcom_icc_node qhs_spdm = { 991 .name = "qhs_spdm", 992 .channels = 1, 993 .buswidth = 4, 994}; 995 996static struct qcom_icc_node qhs_spss_cfg = { 997 .name = "qhs_spss_cfg", 998 .channels = 1, 999 .buswidth = 4, 1000}; 1001 1002static struct qcom_icc_node qhs_tcsr = { 1003 .name = "qhs_tcsr", 1004 .channels = 1, 1005 .buswidth = 4, 1006}; 1007 1008static struct qcom_icc_node qhs_tlmm_north = { 1009 .name = "qhs_tlmm_north", 1010 .channels = 1, 1011 .buswidth = 4, 1012}; 1013 1014static struct qcom_icc_node qhs_tlmm_south = { 1015 .name = "qhs_tlmm_south", 1016 .channels = 1, 1017 .buswidth = 4, 1018}; 1019 1020static struct qcom_icc_node qhs_tsif = { 1021 .name = "qhs_tsif", 1022 .channels = 1, 1023 .buswidth = 4, 1024}; 1025 1026static struct qcom_icc_node qhs_ufs_card_cfg = { 1027 .name = "qhs_ufs_card_cfg", 1028 .channels = 1, 1029 .buswidth = 4, 1030}; 1031 1032static struct qcom_icc_node qhs_ufs_mem_cfg = { 1033 .name = "qhs_ufs_mem_cfg", 1034 .channels = 1, 1035 .buswidth = 4, 1036}; 1037 1038static struct qcom_icc_node qhs_usb3_0 = { 1039 .name = "qhs_usb3_0", 1040 .channels = 1, 1041 .buswidth = 4, 1042}; 1043 1044static struct qcom_icc_node qhs_usb3_1 = { 1045 .name = "qhs_usb3_1", 1046 .channels = 1, 1047 .buswidth = 4, 1048}; 1049 1050static struct qcom_icc_node qhs_venus_cfg = { 1051 .name = "qhs_venus_cfg", 1052 .channels = 1, 1053 .buswidth = 4, 1054}; 1055 1056static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1057 .name = "qhs_vsense_ctrl_cfg", 1058 .channels = 1, 1059 .buswidth = 4, 1060}; 1061 1062static struct qcom_icc_node qns_cnoc_a2noc = { 1063 .name = "qns_cnoc_a2noc", 1064 .channels = 1, 1065 .buswidth = 8, 1066 .num_links = 1, 1067 .link_nodes = { &qnm_cnoc }, 1068}; 1069 1070static struct qcom_icc_node srvc_cnoc = { 1071 .name = "srvc_cnoc", 1072 .channels = 1, 1073 .buswidth = 4, 1074}; 1075 1076static struct qcom_icc_node qhs_llcc = { 1077 .name = "qhs_llcc", 1078 .channels = 1, 1079 .buswidth = 4, 1080}; 1081 1082static struct qcom_icc_node qhs_memnoc = { 1083 .name = "qhs_memnoc", 1084 .channels = 1, 1085 .buswidth = 4, 1086 .num_links = 1, 1087 .link_nodes = { &qhm_memnoc_cfg }, 1088}; 1089 1090static struct qcom_icc_node qns_gladiator_sodv = { 1091 .name = "qns_gladiator_sodv", 1092 .channels = 1, 1093 .buswidth = 8, 1094 .num_links = 1, 1095 .link_nodes = { &qnm_gladiator_sodv }, 1096}; 1097 1098static struct qcom_icc_node qns_gnoc_memnoc = { 1099 .name = "qns_gnoc_memnoc", 1100 .channels = 2, 1101 .buswidth = 32, 1102 .num_links = 1, 1103 .link_nodes = { &qnm_apps }, 1104}; 1105 1106static struct qcom_icc_node srvc_gnoc = { 1107 .name = "srvc_gnoc", 1108 .channels = 1, 1109 .buswidth = 4, 1110}; 1111 1112static struct qcom_icc_node ebi = { 1113 .name = "ebi", 1114 .channels = 4, 1115 .buswidth = 4, 1116}; 1117 1118static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1119 .name = "qhs_mdsp_ms_mpu_cfg", 1120 .channels = 1, 1121 .buswidth = 4, 1122}; 1123 1124static struct qcom_icc_node qns_apps_io = { 1125 .name = "qns_apps_io", 1126 .channels = 1, 1127 .buswidth = 32, 1128}; 1129 1130static struct qcom_icc_node qns_llcc = { 1131 .name = "qns_llcc", 1132 .channels = 4, 1133 .buswidth = 16, 1134 .num_links = 1, 1135 .link_nodes = { &llcc_mc }, 1136}; 1137 1138static struct qcom_icc_node qns_memnoc_snoc = { 1139 .name = "qns_memnoc_snoc", 1140 .channels = 1, 1141 .buswidth = 8, 1142 .num_links = 1, 1143 .link_nodes = { &qnm_memnoc }, 1144}; 1145 1146static struct qcom_icc_node srvc_memnoc = { 1147 .name = "srvc_memnoc", 1148 .channels = 1, 1149 .buswidth = 4, 1150}; 1151 1152static struct qcom_icc_node qns2_mem_noc = { 1153 .name = "qns2_mem_noc", 1154 .channels = 1, 1155 .buswidth = 32, 1156 .num_links = 1, 1157 .link_nodes = { &qnm_mnoc_sf }, 1158}; 1159 1160static struct qcom_icc_node qns_mem_noc_hf = { 1161 .name = "qns_mem_noc_hf", 1162 .channels = 2, 1163 .buswidth = 32, 1164 .num_links = 1, 1165 .link_nodes = { &qnm_mnoc_hf }, 1166}; 1167 1168static struct qcom_icc_node srvc_mnoc = { 1169 .name = "srvc_mnoc", 1170 .channels = 1, 1171 .buswidth = 4, 1172}; 1173 1174static struct qcom_icc_node qhs_apss = { 1175 .name = "qhs_apss", 1176 .channels = 1, 1177 .buswidth = 8, 1178}; 1179 1180static struct qcom_icc_node qns_cnoc = { 1181 .name = "qns_cnoc", 1182 .channels = 1, 1183 .buswidth = 8, 1184 .num_links = 1, 1185 .link_nodes = { &qnm_snoc }, 1186}; 1187 1188static struct qcom_icc_node qns_memnoc_gc = { 1189 .name = "qns_memnoc_gc", 1190 .channels = 1, 1191 .buswidth = 8, 1192 .num_links = 1, 1193 .link_nodes = { &qnm_snoc_gc }, 1194}; 1195 1196static struct qcom_icc_node qns_memnoc_sf = { 1197 .name = "qns_memnoc_sf", 1198 .channels = 1, 1199 .buswidth = 16, 1200 .num_links = 1, 1201 .link_nodes = { &qnm_snoc_sf }, 1202}; 1203 1204static struct qcom_icc_node qxs_imem = { 1205 .name = "qxs_imem", 1206 .channels = 1, 1207 .buswidth = 8, 1208}; 1209 1210static struct qcom_icc_node qxs_pcie = { 1211 .name = "qxs_pcie", 1212 .channels = 1, 1213 .buswidth = 8, 1214}; 1215 1216static struct qcom_icc_node qxs_pcie_gen3 = { 1217 .name = "qxs_pcie_gen3", 1218 .channels = 1, 1219 .buswidth = 8, 1220}; 1221 1222static struct qcom_icc_node qxs_pimem = { 1223 .name = "qxs_pimem", 1224 .channels = 1, 1225 .buswidth = 8, 1226}; 1227 1228static struct qcom_icc_node srvc_snoc = { 1229 .name = "srvc_snoc", 1230 .channels = 1, 1231 .buswidth = 4, 1232}; 1233 1234static struct qcom_icc_node xs_qdss_stm = { 1235 .name = "xs_qdss_stm", 1236 .channels = 1, 1237 .buswidth = 4, 1238}; 1239 1240static struct qcom_icc_node xs_sys_tcu_cfg = { 1241 .name = "xs_sys_tcu_cfg", 1242 .channels = 1, 1243 .buswidth = 8, 1244}; 1245 1246static struct qcom_icc_bcm bcm_acv = { 1247 .name = "ACV", 1248 .enable_mask = BIT(3), 1249 .keepalive = false, 1250 .num_nodes = 1, 1251 .nodes = { &ebi }, 1252}; 1253 1254static struct qcom_icc_bcm bcm_mc0 = { 1255 .name = "MC0", 1256 .keepalive = true, 1257 .num_nodes = 1, 1258 .nodes = { &ebi }, 1259}; 1260 1261static struct qcom_icc_bcm bcm_sh0 = { 1262 .name = "SH0", 1263 .keepalive = true, 1264 .num_nodes = 1, 1265 .nodes = { &qns_llcc }, 1266}; 1267 1268static struct qcom_icc_bcm bcm_mm0 = { 1269 .name = "MM0", 1270 .keepalive = false, 1271 .num_nodes = 1, 1272 .nodes = { &qns_mem_noc_hf }, 1273}; 1274 1275static struct qcom_icc_bcm bcm_sh1 = { 1276 .name = "SH1", 1277 .keepalive = false, 1278 .num_nodes = 1, 1279 .nodes = { &qns_apps_io }, 1280}; 1281 1282static struct qcom_icc_bcm bcm_mm1 = { 1283 .name = "MM1", 1284 .keepalive = true, 1285 .num_nodes = 7, 1286 .nodes = { &qxm_camnoc_hf0_uncomp, 1287 &qxm_camnoc_hf1_uncomp, 1288 &qxm_camnoc_sf_uncomp, 1289 &qxm_camnoc_hf0, 1290 &qxm_camnoc_hf1, 1291 &qxm_mdp0, 1292 &qxm_mdp1 1293 }, 1294}; 1295 1296static struct qcom_icc_bcm bcm_sh2 = { 1297 .name = "SH2", 1298 .keepalive = false, 1299 .num_nodes = 1, 1300 .nodes = { &qns_memnoc_snoc }, 1301}; 1302 1303static struct qcom_icc_bcm bcm_mm2 = { 1304 .name = "MM2", 1305 .keepalive = false, 1306 .num_nodes = 1, 1307 .nodes = { &qns2_mem_noc }, 1308}; 1309 1310static struct qcom_icc_bcm bcm_sh3 = { 1311 .name = "SH3", 1312 .keepalive = false, 1313 .num_nodes = 1, 1314 .nodes = { &acm_tcu }, 1315}; 1316 1317static struct qcom_icc_bcm bcm_mm3 = { 1318 .name = "MM3", 1319 .keepalive = false, 1320 .num_nodes = 5, 1321 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1322}; 1323 1324static struct qcom_icc_bcm bcm_sh5 = { 1325 .name = "SH5", 1326 .keepalive = false, 1327 .num_nodes = 1, 1328 .nodes = { &qnm_apps }, 1329}; 1330 1331static struct qcom_icc_bcm bcm_sn0 = { 1332 .name = "SN0", 1333 .keepalive = true, 1334 .num_nodes = 1, 1335 .nodes = { &qns_memnoc_sf }, 1336}; 1337 1338static struct qcom_icc_bcm bcm_ce0 = { 1339 .name = "CE0", 1340 .keepalive = false, 1341 .num_nodes = 1, 1342 .nodes = { &qxm_crypto }, 1343}; 1344 1345static struct qcom_icc_bcm bcm_cn0 = { 1346 .name = "CN0", 1347 .keepalive = false, 1348 .num_nodes = 47, 1349 .nodes = { &qhm_spdm, 1350 &qhm_tic, 1351 &qnm_snoc, 1352 &xm_qdss_dap, 1353 &qhs_a1_noc_cfg, 1354 &qhs_a2_noc_cfg, 1355 &qhs_aop, 1356 &qhs_aoss, 1357 &qhs_camera_cfg, 1358 &qhs_clk_ctl, 1359 &qhs_compute_dsp_cfg, 1360 &qhs_cpr_cx, 1361 &qhs_crypto0_cfg, 1362 &qhs_dcc_cfg, 1363 &qhs_ddrss_cfg, 1364 &qhs_display_cfg, 1365 &qhs_glm, 1366 &qhs_gpuss_cfg, 1367 &qhs_imem_cfg, 1368 &qhs_ipa, 1369 &qhs_mnoc_cfg, 1370 &qhs_pcie0_cfg, 1371 &qhs_pcie_gen3_cfg, 1372 &qhs_pdm, 1373 &qhs_phy_refgen_south, 1374 &qhs_pimem_cfg, 1375 &qhs_prng, 1376 &qhs_qdss_cfg, 1377 &qhs_qupv3_north, 1378 &qhs_qupv3_south, 1379 &qhs_sdc2, 1380 &qhs_sdc4, 1381 &qhs_snoc_cfg, 1382 &qhs_spdm, 1383 &qhs_spss_cfg, 1384 &qhs_tcsr, 1385 &qhs_tlmm_north, 1386 &qhs_tlmm_south, 1387 &qhs_tsif, 1388 &qhs_ufs_card_cfg, 1389 &qhs_ufs_mem_cfg, 1390 &qhs_usb3_0, 1391 &qhs_usb3_1, 1392 &qhs_venus_cfg, 1393 &qhs_vsense_ctrl_cfg, 1394 &qns_cnoc_a2noc, 1395 &srvc_cnoc 1396 }, 1397}; 1398 1399static struct qcom_icc_bcm bcm_qup0 = { 1400 .name = "QUP0", 1401 .keepalive = false, 1402 .num_nodes = 2, 1403 .nodes = { &qhm_qup1, &qhm_qup2 }, 1404}; 1405 1406static struct qcom_icc_bcm bcm_sn1 = { 1407 .name = "SN1", 1408 .keepalive = false, 1409 .num_nodes = 1, 1410 .nodes = { &qxs_imem }, 1411}; 1412 1413static struct qcom_icc_bcm bcm_sn2 = { 1414 .name = "SN2", 1415 .keepalive = false, 1416 .num_nodes = 1, 1417 .nodes = { &qns_memnoc_gc }, 1418}; 1419 1420static struct qcom_icc_bcm bcm_sn3 = { 1421 .name = "SN3", 1422 .keepalive = false, 1423 .num_nodes = 1, 1424 .nodes = { &qns_cnoc }, 1425}; 1426 1427static struct qcom_icc_bcm bcm_sn4 = { 1428 .name = "SN4", 1429 .keepalive = false, 1430 .num_nodes = 1, 1431 .nodes = { &qxm_pimem }, 1432}; 1433 1434static struct qcom_icc_bcm bcm_sn5 = { 1435 .name = "SN5", 1436 .keepalive = false, 1437 .num_nodes = 1, 1438 .nodes = { &xs_qdss_stm }, 1439}; 1440 1441static struct qcom_icc_bcm bcm_sn6 = { 1442 .name = "SN6", 1443 .keepalive = false, 1444 .num_nodes = 3, 1445 .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg }, 1446}; 1447 1448static struct qcom_icc_bcm bcm_sn7 = { 1449 .name = "SN7", 1450 .keepalive = false, 1451 .num_nodes = 1, 1452 .nodes = { &qxs_pcie }, 1453}; 1454 1455static struct qcom_icc_bcm bcm_sn8 = { 1456 .name = "SN8", 1457 .keepalive = false, 1458 .num_nodes = 1, 1459 .nodes = { &qxs_pcie_gen3 }, 1460}; 1461 1462static struct qcom_icc_bcm bcm_sn9 = { 1463 .name = "SN9", 1464 .keepalive = false, 1465 .num_nodes = 2, 1466 .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc }, 1467}; 1468 1469static struct qcom_icc_bcm bcm_sn11 = { 1470 .name = "SN11", 1471 .keepalive = false, 1472 .num_nodes = 2, 1473 .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc }, 1474}; 1475 1476static struct qcom_icc_bcm bcm_sn12 = { 1477 .name = "SN12", 1478 .keepalive = false, 1479 .num_nodes = 2, 1480 .nodes = { &qnm_gladiator_sodv, &xm_gic }, 1481}; 1482 1483static struct qcom_icc_bcm bcm_sn14 = { 1484 .name = "SN14", 1485 .keepalive = false, 1486 .num_nodes = 1, 1487 .nodes = { &qnm_pcie_anoc }, 1488}; 1489 1490static struct qcom_icc_bcm bcm_sn15 = { 1491 .name = "SN15", 1492 .keepalive = false, 1493 .num_nodes = 1, 1494 .nodes = { &qnm_memnoc }, 1495}; 1496 1497static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1498 &bcm_sn9, 1499 &bcm_qup0, 1500}; 1501 1502static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1503 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1504 [MASTER_TSIF] = &qhm_tsif, 1505 [MASTER_SDCC_2] = &xm_sdc2, 1506 [MASTER_SDCC_4] = &xm_sdc4, 1507 [MASTER_UFS_CARD] = &xm_ufs_card, 1508 [MASTER_UFS_MEM] = &xm_ufs_mem, 1509 [MASTER_PCIE_0] = &xm_pcie_0, 1510 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1511 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1512 [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, 1513 [MASTER_QUP_1] = &qhm_qup1, 1514}; 1515 1516static const struct qcom_icc_desc sdm845_aggre1_noc = { 1517 .nodes = aggre1_noc_nodes, 1518 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1519 .bcms = aggre1_noc_bcms, 1520 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1521}; 1522 1523static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1524 &bcm_ce0, 1525 &bcm_sn11, 1526 &bcm_qup0, 1527}; 1528 1529static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1530 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1531 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1532 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1533 [MASTER_CRYPTO] = &qxm_crypto, 1534 [MASTER_IPA] = &qxm_ipa, 1535 [MASTER_PCIE_1] = &xm_pcie3_1, 1536 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1537 [MASTER_USB3_0] = &xm_usb3_0, 1538 [MASTER_USB3_1] = &xm_usb3_1, 1539 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1540 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, 1541 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1542 [MASTER_QUP_2] = &qhm_qup2, 1543}; 1544 1545static const struct qcom_icc_desc sdm845_aggre2_noc = { 1546 .nodes = aggre2_noc_nodes, 1547 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1548 .bcms = aggre2_noc_bcms, 1549 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1550}; 1551 1552static struct qcom_icc_bcm * const config_noc_bcms[] = { 1553 &bcm_cn0, 1554}; 1555 1556static struct qcom_icc_node * const config_noc_nodes[] = { 1557 [MASTER_SPDM] = &qhm_spdm, 1558 [MASTER_TIC] = &qhm_tic, 1559 [MASTER_SNOC_CNOC] = &qnm_snoc, 1560 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1561 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1562 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1563 [SLAVE_AOP] = &qhs_aop, 1564 [SLAVE_AOSS] = &qhs_aoss, 1565 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1566 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1567 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1568 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1569 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1570 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1571 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1572 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1573 [SLAVE_GLM] = &qhs_glm, 1574 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1575 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1576 [SLAVE_IPA_CFG] = &qhs_ipa, 1577 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1578 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1579 [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg, 1580 [SLAVE_PDM] = &qhs_pdm, 1581 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, 1582 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1583 [SLAVE_PRNG] = &qhs_prng, 1584 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1585 [SLAVE_BLSP_2] = &qhs_qupv3_north, 1586 [SLAVE_BLSP_1] = &qhs_qupv3_south, 1587 [SLAVE_SDCC_2] = &qhs_sdc2, 1588 [SLAVE_SDCC_4] = &qhs_sdc4, 1589 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1590 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1591 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1592 [SLAVE_TCSR] = &qhs_tcsr, 1593 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1594 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1595 [SLAVE_TSIF] = &qhs_tsif, 1596 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1597 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1598 [SLAVE_USB3_0] = &qhs_usb3_0, 1599 [SLAVE_USB3_1] = &qhs_usb3_1, 1600 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1601 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1602 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1603 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1604}; 1605 1606static const struct qcom_icc_desc sdm845_config_noc = { 1607 .nodes = config_noc_nodes, 1608 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1609 .bcms = config_noc_bcms, 1610 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1611}; 1612 1613static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1614}; 1615 1616static struct qcom_icc_node * const dc_noc_nodes[] = { 1617 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1618 [SLAVE_LLCC_CFG] = &qhs_llcc, 1619 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, 1620}; 1621 1622static const struct qcom_icc_desc sdm845_dc_noc = { 1623 .nodes = dc_noc_nodes, 1624 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1625 .bcms = dc_noc_bcms, 1626 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1627}; 1628 1629static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { 1630}; 1631 1632static struct qcom_icc_node * const gladiator_noc_nodes[] = { 1633 [MASTER_APPSS_PROC] = &acm_l3, 1634 [MASTER_GNOC_CFG] = &pm_gnoc_cfg, 1635 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, 1636 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, 1637 [SLAVE_SERVICE_GNOC] = &srvc_gnoc, 1638}; 1639 1640static const struct qcom_icc_desc sdm845_gladiator_noc = { 1641 .nodes = gladiator_noc_nodes, 1642 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), 1643 .bcms = gladiator_noc_bcms, 1644 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), 1645}; 1646 1647static struct qcom_icc_bcm * const mem_noc_bcms[] = { 1648 &bcm_mc0, 1649 &bcm_acv, 1650 &bcm_sh0, 1651 &bcm_sh1, 1652 &bcm_sh2, 1653 &bcm_sh3, 1654 &bcm_sh5, 1655}; 1656 1657static struct qcom_icc_node * const mem_noc_nodes[] = { 1658 [MASTER_TCU_0] = &acm_tcu, 1659 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, 1660 [MASTER_GNOC_MEM_NOC] = &qnm_apps, 1661 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1662 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1663 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1664 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1665 [MASTER_GFX3D] = &qxm_gpu, 1666 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1667 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, 1668 [SLAVE_LLCC] = &qns_llcc, 1669 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 1670 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, 1671 [MASTER_LLCC] = &llcc_mc, 1672 [SLAVE_EBI1] = &ebi, 1673}; 1674 1675static const struct qcom_icc_desc sdm845_mem_noc = { 1676 .nodes = mem_noc_nodes, 1677 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 1678 .bcms = mem_noc_bcms, 1679 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 1680}; 1681 1682static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1683 &bcm_mm0, 1684 &bcm_mm1, 1685 &bcm_mm2, 1686 &bcm_mm3, 1687}; 1688 1689static struct qcom_icc_node * const mmss_noc_nodes[] = { 1690 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1691 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1692 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1693 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1694 [MASTER_MDP0] = &qxm_mdp0, 1695 [MASTER_MDP1] = &qxm_mdp1, 1696 [MASTER_ROTATOR] = &qxm_rot, 1697 [MASTER_VIDEO_P0] = &qxm_venus0, 1698 [MASTER_VIDEO_P1] = &qxm_venus1, 1699 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1700 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1701 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1702 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1703 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1704 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1705 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1706 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1707}; 1708 1709static const struct qcom_icc_desc sdm845_mmss_noc = { 1710 .nodes = mmss_noc_nodes, 1711 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1712 .bcms = mmss_noc_bcms, 1713 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1714}; 1715 1716static struct qcom_icc_bcm * const system_noc_bcms[] = { 1717 &bcm_sn0, 1718 &bcm_sn1, 1719 &bcm_sn2, 1720 &bcm_sn3, 1721 &bcm_sn4, 1722 &bcm_sn5, 1723 &bcm_sn6, 1724 &bcm_sn7, 1725 &bcm_sn8, 1726 &bcm_sn9, 1727 &bcm_sn11, 1728 &bcm_sn12, 1729 &bcm_sn14, 1730 &bcm_sn15, 1731}; 1732 1733static struct qcom_icc_node * const system_noc_nodes[] = { 1734 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1735 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1736 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1737 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, 1738 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 1739 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, 1740 [MASTER_PIMEM] = &qxm_pimem, 1741 [MASTER_GIC] = &xm_gic, 1742 [SLAVE_APPSS] = &qhs_apss, 1743 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1744 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1745 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, 1746 [SLAVE_IMEM] = &qxs_imem, 1747 [SLAVE_PCIE_0] = &qxs_pcie, 1748 [SLAVE_PCIE_1] = &qxs_pcie_gen3, 1749 [SLAVE_PIMEM] = &qxs_pimem, 1750 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1751 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1752 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1753}; 1754 1755static const struct qcom_icc_desc sdm845_system_noc = { 1756 .nodes = system_noc_nodes, 1757 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1758 .bcms = system_noc_bcms, 1759 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1760}; 1761 1762static const struct of_device_id qnoc_of_match[] = { 1763 { .compatible = "qcom,sdm845-aggre1-noc", 1764 .data = &sdm845_aggre1_noc}, 1765 { .compatible = "qcom,sdm845-aggre2-noc", 1766 .data = &sdm845_aggre2_noc}, 1767 { .compatible = "qcom,sdm845-config-noc", 1768 .data = &sdm845_config_noc}, 1769 { .compatible = "qcom,sdm845-dc-noc", 1770 .data = &sdm845_dc_noc}, 1771 { .compatible = "qcom,sdm845-gladiator-noc", 1772 .data = &sdm845_gladiator_noc}, 1773 { .compatible = "qcom,sdm845-mem-noc", 1774 .data = &sdm845_mem_noc}, 1775 { .compatible = "qcom,sdm845-mmss-noc", 1776 .data = &sdm845_mmss_noc}, 1777 { .compatible = "qcom,sdm845-system-noc", 1778 .data = &sdm845_system_noc}, 1779 { } 1780}; 1781MODULE_DEVICE_TABLE(of, qnoc_of_match); 1782 1783static struct platform_driver qnoc_driver = { 1784 .probe = qcom_icc_rpmh_probe, 1785 .remove = qcom_icc_rpmh_remove, 1786 .driver = { 1787 .name = "qnoc-sdm845", 1788 .of_match_table = qnoc_of_match, 1789 .sync_state = icc_sync_state, 1790 }, 1791}; 1792module_platform_driver(qnoc_driver); 1793 1794MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>"); 1795MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver"); 1796MODULE_LICENSE("GPL v2");
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