sdm670.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/device.h>
   7#include <linux/interconnect.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/mod_devicetable.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
  13
  14#include "bcm-voter.h"
  15#include "icc-rpmh.h"
  16
  17static struct qcom_icc_node qhm_a1noc_cfg;
  18static struct qcom_icc_node qhm_qup1;
  19static struct qcom_icc_node qhm_tsif;
  20static struct qcom_icc_node xm_emmc;
  21static struct qcom_icc_node xm_sdc2;
  22static struct qcom_icc_node xm_sdc4;
  23static struct qcom_icc_node xm_ufs_mem;
  24static struct qcom_icc_node qhm_a2noc_cfg;
  25static struct qcom_icc_node qhm_qdss_bam;
  26static struct qcom_icc_node qhm_qup2;
  27static struct qcom_icc_node qnm_cnoc;
  28static struct qcom_icc_node qxm_crypto;
  29static struct qcom_icc_node qxm_ipa;
  30static struct qcom_icc_node xm_qdss_etr;
  31static struct qcom_icc_node xm_usb3_0;
  32static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
  33static struct qcom_icc_node qxm_camnoc_hf1_uncomp;
  34static struct qcom_icc_node qxm_camnoc_sf_uncomp;
  35static struct qcom_icc_node qhm_spdm;
  36static struct qcom_icc_node qnm_snoc;
  37static struct qcom_icc_node qhm_cnoc;
  38static struct qcom_icc_node acm_l3;
  39static struct qcom_icc_node pm_gnoc_cfg;
  40static struct qcom_icc_node llcc_mc;
  41static struct qcom_icc_node acm_tcu;
  42static struct qcom_icc_node qhm_memnoc_cfg;
  43static struct qcom_icc_node qnm_apps;
  44static struct qcom_icc_node qnm_mnoc_hf;
  45static struct qcom_icc_node qnm_mnoc_sf;
  46static struct qcom_icc_node qnm_snoc_gc;
  47static struct qcom_icc_node qnm_snoc_sf;
  48static struct qcom_icc_node qxm_gpu;
  49static struct qcom_icc_node qhm_mnoc_cfg;
  50static struct qcom_icc_node qxm_camnoc_hf0;
  51static struct qcom_icc_node qxm_camnoc_hf1;
  52static struct qcom_icc_node qxm_camnoc_sf;
  53static struct qcom_icc_node qxm_mdp0;
  54static struct qcom_icc_node qxm_mdp1;
  55static struct qcom_icc_node qxm_rot;
  56static struct qcom_icc_node qxm_venus0;
  57static struct qcom_icc_node qxm_venus1;
  58static struct qcom_icc_node qxm_venus_arm9;
  59static struct qcom_icc_node qhm_snoc_cfg;
  60static struct qcom_icc_node qnm_aggre1_noc;
  61static struct qcom_icc_node qnm_aggre2_noc;
  62static struct qcom_icc_node qnm_gladiator_sodv;
  63static struct qcom_icc_node qnm_memnoc;
  64static struct qcom_icc_node qxm_pimem;
  65static struct qcom_icc_node xm_gic;
  66static struct qcom_icc_node qns_a1noc_snoc;
  67static struct qcom_icc_node srvc_aggre1_noc;
  68static struct qcom_icc_node qns_a2noc_snoc;
  69static struct qcom_icc_node srvc_aggre2_noc;
  70static struct qcom_icc_node qns_camnoc_uncomp;
  71static struct qcom_icc_node qhs_a1_noc_cfg;
  72static struct qcom_icc_node qhs_a2_noc_cfg;
  73static struct qcom_icc_node qhs_aop;
  74static struct qcom_icc_node qhs_aoss;
  75static struct qcom_icc_node qhs_camera_cfg;
  76static struct qcom_icc_node qhs_clk_ctl;
  77static struct qcom_icc_node qhs_compute_dsp_cfg;
  78static struct qcom_icc_node qhs_cpr_cx;
  79static struct qcom_icc_node qhs_crypto0_cfg;
  80static struct qcom_icc_node qhs_dcc_cfg;
  81static struct qcom_icc_node qhs_ddrss_cfg;
  82static struct qcom_icc_node qhs_display_cfg;
  83static struct qcom_icc_node qhs_emmc_cfg;
  84static struct qcom_icc_node qhs_glm;
  85static struct qcom_icc_node qhs_gpuss_cfg;
  86static struct qcom_icc_node qhs_imem_cfg;
  87static struct qcom_icc_node qhs_ipa;
  88static struct qcom_icc_node qhs_mnoc_cfg;
  89static struct qcom_icc_node qhs_pdm;
  90static struct qcom_icc_node qhs_phy_refgen_south;
  91static struct qcom_icc_node qhs_pimem_cfg;
  92static struct qcom_icc_node qhs_prng;
  93static struct qcom_icc_node qhs_qdss_cfg;
  94static struct qcom_icc_node qhs_qupv3_north;
  95static struct qcom_icc_node qhs_qupv3_south;
  96static struct qcom_icc_node qhs_sdc2;
  97static struct qcom_icc_node qhs_sdc4;
  98static struct qcom_icc_node qhs_snoc_cfg;
  99static struct qcom_icc_node qhs_spdm;
 100static struct qcom_icc_node qhs_tcsr;
 101static struct qcom_icc_node qhs_tlmm_north;
 102static struct qcom_icc_node qhs_tlmm_south;
 103static struct qcom_icc_node qhs_tsif;
 104static struct qcom_icc_node qhs_ufs_mem_cfg;
 105static struct qcom_icc_node qhs_usb3_0;
 106static struct qcom_icc_node qhs_venus_cfg;
 107static struct qcom_icc_node qhs_vsense_ctrl_cfg;
 108static struct qcom_icc_node qns_cnoc_a2noc;
 109static struct qcom_icc_node srvc_cnoc;
 110static struct qcom_icc_node qhs_llcc;
 111static struct qcom_icc_node qhs_memnoc;
 112static struct qcom_icc_node qns_gladiator_sodv;
 113static struct qcom_icc_node qns_gnoc_memnoc;
 114static struct qcom_icc_node srvc_gnoc;
 115static struct qcom_icc_node ebi;
 116static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
 117static struct qcom_icc_node qns_apps_io;
 118static struct qcom_icc_node qns_llcc;
 119static struct qcom_icc_node qns_memnoc_snoc;
 120static struct qcom_icc_node srvc_memnoc;
 121static struct qcom_icc_node qns2_mem_noc;
 122static struct qcom_icc_node qns_mem_noc_hf;
 123static struct qcom_icc_node srvc_mnoc;
 124static struct qcom_icc_node qhs_apss;
 125static struct qcom_icc_node qns_cnoc;
 126static struct qcom_icc_node qns_memnoc_gc;
 127static struct qcom_icc_node qns_memnoc_sf;
 128static struct qcom_icc_node qxs_imem;
 129static struct qcom_icc_node qxs_pimem;
 130static struct qcom_icc_node srvc_snoc;
 131static struct qcom_icc_node xs_qdss_stm;
 132static struct qcom_icc_node xs_sys_tcu_cfg;
 133
 134static struct qcom_icc_node qhm_a1noc_cfg = {
 135	.name = "qhm_a1noc_cfg",
 136	.channels = 1,
 137	.buswidth = 4,
 138	.num_links = 1,
 139	.link_nodes = { &srvc_aggre1_noc },
 140};
 141
 142static struct qcom_icc_node qhm_qup1 = {
 143	.name = "qhm_qup1",
 144	.channels = 1,
 145	.buswidth = 4,
 146	.num_links = 1,
 147	.link_nodes = { &qns_a1noc_snoc },
 148};
 149
 150static struct qcom_icc_node qhm_tsif = {
 151	.name = "qhm_tsif",
 152	.channels = 1,
 153	.buswidth = 4,
 154	.num_links = 1,
 155	.link_nodes = { &qns_a1noc_snoc },
 156};
 157
 158static struct qcom_icc_node xm_emmc = {
 159	.name = "xm_emmc",
 160	.channels = 1,
 161	.buswidth = 8,
 162	.num_links = 1,
 163	.link_nodes = { &qns_a1noc_snoc },
 164};
 165
 166static struct qcom_icc_node xm_sdc2 = {
 167	.name = "xm_sdc2",
 168	.channels = 1,
 169	.buswidth = 8,
 170	.num_links = 1,
 171	.link_nodes = { &qns_a1noc_snoc },
 172};
 173
 174static struct qcom_icc_node xm_sdc4 = {
 175	.name = "xm_sdc4",
 176	.channels = 1,
 177	.buswidth = 8,
 178	.num_links = 1,
 179	.link_nodes = { &qns_a1noc_snoc },
 180};
 181
 182static struct qcom_icc_node xm_ufs_mem = {
 183	.name = "xm_ufs_mem",
 184	.channels = 1,
 185	.buswidth = 8,
 186	.num_links = 1,
 187	.link_nodes = { &qns_a1noc_snoc },
 188};
 189
 190static struct qcom_icc_node qhm_a2noc_cfg = {
 191	.name = "qhm_a2noc_cfg",
 192	.channels = 1,
 193	.buswidth = 4,
 194	.num_links = 1,
 195	.link_nodes = { &srvc_aggre2_noc },
 196};
 197
 198static struct qcom_icc_node qhm_qdss_bam = {
 199	.name = "qhm_qdss_bam",
 200	.channels = 1,
 201	.buswidth = 4,
 202	.num_links = 1,
 203	.link_nodes = { &qns_a2noc_snoc },
 204};
 205
 206static struct qcom_icc_node qhm_qup2 = {
 207	.name = "qhm_qup2",
 208	.channels = 1,
 209	.buswidth = 4,
 210	.num_links = 1,
 211	.link_nodes = { &qns_a2noc_snoc },
 212};
 213
 214static struct qcom_icc_node qnm_cnoc = {
 215	.name = "qnm_cnoc",
 216	.channels = 1,
 217	.buswidth = 8,
 218	.num_links = 1,
 219	.link_nodes = { &qns_a2noc_snoc },
 220};
 221
 222static struct qcom_icc_node qxm_crypto = {
 223	.name = "qxm_crypto",
 224	.channels = 1,
 225	.buswidth = 8,
 226	.num_links = 1,
 227	.link_nodes = { &qns_a2noc_snoc },
 228};
 229
 230static struct qcom_icc_node qxm_ipa = {
 231	.name = "qxm_ipa",
 232	.channels = 1,
 233	.buswidth = 8,
 234	.num_links = 1,
 235	.link_nodes = { &qns_a2noc_snoc },
 236};
 237
 238static struct qcom_icc_node xm_qdss_etr = {
 239	.name = "xm_qdss_etr",
 240	.channels = 1,
 241	.buswidth = 8,
 242	.num_links = 1,
 243	.link_nodes = { &qns_a2noc_snoc },
 244};
 245
 246static struct qcom_icc_node xm_usb3_0 = {
 247	.name = "xm_usb3_0",
 248	.channels = 1,
 249	.buswidth = 8,
 250	.num_links = 1,
 251	.link_nodes = { &qns_a2noc_snoc },
 252};
 253
 254static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
 255	.name = "qxm_camnoc_hf0_uncomp",
 256	.channels = 1,
 257	.buswidth = 32,
 258	.num_links = 1,
 259	.link_nodes = { &qns_camnoc_uncomp },
 260};
 261
 262static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
 263	.name = "qxm_camnoc_hf1_uncomp",
 264	.channels = 1,
 265	.buswidth = 32,
 266	.num_links = 1,
 267	.link_nodes = { &qns_camnoc_uncomp },
 268};
 269
 270static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
 271	.name = "qxm_camnoc_sf_uncomp",
 272	.channels = 1,
 273	.buswidth = 32,
 274	.num_links = 1,
 275	.link_nodes = { &qns_camnoc_uncomp },
 276};
 277
 278static struct qcom_icc_node qhm_spdm = {
 279	.name = "qhm_spdm",
 280	.channels = 1,
 281	.buswidth = 4,
 282	.num_links = 1,
 283	.link_nodes = { &qns_cnoc_a2noc },
 284};
 285
 286static struct qcom_icc_node qnm_snoc = {
 287	.name = "qnm_snoc",
 288	.channels = 1,
 289	.buswidth = 8,
 290	.num_links = 38,
 291	.link_nodes = { &qhs_tlmm_south,
 292			&qhs_camera_cfg,
 293			&qhs_sdc4,
 294			&qhs_sdc2,
 295			&qhs_mnoc_cfg,
 296			&qhs_ufs_mem_cfg,
 297			&qhs_glm,
 298			&qhs_pdm,
 299			&qhs_a2_noc_cfg,
 300			&qhs_qdss_cfg,
 301			&qhs_display_cfg,
 302			&qhs_tcsr,
 303			&qhs_dcc_cfg,
 304			&qhs_ddrss_cfg,
 305			&qhs_snoc_cfg,
 306			&qhs_phy_refgen_south,
 307			&qhs_gpuss_cfg,
 308			&qhs_venus_cfg,
 309			&qhs_tsif,
 310			&qhs_compute_dsp_cfg,
 311			&qhs_aop,
 312			&qhs_qupv3_north,
 313			&srvc_cnoc,
 314			&qhs_usb3_0,
 315			&qhs_ipa,
 316			&qhs_cpr_cx,
 317			&qhs_a1_noc_cfg,
 318			&qhs_aoss,
 319			&qhs_prng,
 320			&qhs_vsense_ctrl_cfg,
 321			&qhs_emmc_cfg,
 322			&qhs_qupv3_south,
 323			&qhs_spdm,
 324			&qhs_crypto0_cfg,
 325			&qhs_pimem_cfg,
 326			&qhs_tlmm_north,
 327			&qhs_clk_ctl,
 328			&qhs_imem_cfg },
 329};
 330
 331static struct qcom_icc_node qhm_cnoc = {
 332	.name = "qhm_cnoc",
 333	.channels = 1,
 334	.buswidth = 4,
 335	.num_links = 2,
 336	.link_nodes = { &qhs_memnoc,
 337			&qhs_llcc },
 338};
 339
 340static struct qcom_icc_node acm_l3 = {
 341	.name = "acm_l3",
 342	.channels = 1,
 343	.buswidth = 16,
 344	.num_links = 3,
 345	.link_nodes = { &srvc_gnoc,
 346			&qns_gladiator_sodv,
 347			&qns_gnoc_memnoc },
 348};
 349
 350static struct qcom_icc_node pm_gnoc_cfg = {
 351	.name = "pm_gnoc_cfg",
 352	.channels = 1,
 353	.buswidth = 4,
 354	.num_links = 1,
 355	.link_nodes = { &srvc_gnoc },
 356};
 357
 358static struct qcom_icc_node llcc_mc = {
 359	.name = "llcc_mc",
 360	.channels = 2,
 361	.buswidth = 4,
 362	.num_links = 1,
 363	.link_nodes = { &ebi },
 364};
 365
 366static struct qcom_icc_node acm_tcu = {
 367	.name = "acm_tcu",
 368	.channels = 1,
 369	.buswidth = 8,
 370	.num_links = 3,
 371	.link_nodes = { &qns_apps_io,
 372			&qns_llcc,
 373			&qns_memnoc_snoc },
 374};
 375
 376static struct qcom_icc_node qhm_memnoc_cfg = {
 377	.name = "qhm_memnoc_cfg",
 378	.channels = 1,
 379	.buswidth = 4,
 380	.num_links = 2,
 381	.link_nodes = { &srvc_memnoc,
 382			&qhs_mdsp_ms_mpu_cfg },
 383};
 384
 385static struct qcom_icc_node qnm_apps = {
 386	.name = "qnm_apps",
 387	.channels = 2,
 388	.buswidth = 32,
 389	.num_links = 1,
 390	.link_nodes = { &qns_llcc },
 391};
 392
 393static struct qcom_icc_node qnm_mnoc_hf = {
 394	.name = "qnm_mnoc_hf",
 395	.channels = 2,
 396	.buswidth = 32,
 397	.num_links = 1,
 398	.link_nodes = { &qns_llcc },
 399};
 400
 401static struct qcom_icc_node qnm_mnoc_sf = {
 402	.name = "qnm_mnoc_sf",
 403	.channels = 1,
 404	.buswidth = 32,
 405	.num_links = 3,
 406	.link_nodes = { &qns_apps_io,
 407			&qns_llcc,
 408			&qns_memnoc_snoc },
 409};
 410
 411static struct qcom_icc_node qnm_snoc_gc = {
 412	.name = "qnm_snoc_gc",
 413	.channels = 1,
 414	.buswidth = 8,
 415	.num_links = 1,
 416	.link_nodes = { &qns_llcc },
 417};
 418
 419static struct qcom_icc_node qnm_snoc_sf = {
 420	.name = "qnm_snoc_sf",
 421	.channels = 1,
 422	.buswidth = 16,
 423	.num_links = 2,
 424	.link_nodes = { &qns_apps_io,
 425			&qns_llcc },
 426};
 427
 428static struct qcom_icc_node qxm_gpu = {
 429	.name = "qxm_gpu",
 430	.channels = 2,
 431	.buswidth = 32,
 432	.num_links = 3,
 433	.link_nodes = { &qns_apps_io,
 434			&qns_llcc,
 435			&qns_memnoc_snoc },
 436};
 437
 438static struct qcom_icc_node qhm_mnoc_cfg = {
 439	.name = "qhm_mnoc_cfg",
 440	.channels = 1,
 441	.buswidth = 4,
 442	.num_links = 1,
 443	.link_nodes = { &srvc_mnoc },
 444};
 445
 446static struct qcom_icc_node qxm_camnoc_hf0 = {
 447	.name = "qxm_camnoc_hf0",
 448	.channels = 1,
 449	.buswidth = 32,
 450	.num_links = 1,
 451	.link_nodes = { &qns_mem_noc_hf },
 452};
 453
 454static struct qcom_icc_node qxm_camnoc_hf1 = {
 455	.name = "qxm_camnoc_hf1",
 456	.channels = 1,
 457	.buswidth = 32,
 458	.num_links = 1,
 459	.link_nodes = { &qns_mem_noc_hf },
 460};
 461
 462static struct qcom_icc_node qxm_camnoc_sf = {
 463	.name = "qxm_camnoc_sf",
 464	.channels = 1,
 465	.buswidth = 32,
 466	.num_links = 1,
 467	.link_nodes = { &qns2_mem_noc },
 468};
 469
 470static struct qcom_icc_node qxm_mdp0 = {
 471	.name = "qxm_mdp0",
 472	.channels = 1,
 473	.buswidth = 32,
 474	.num_links = 1,
 475	.link_nodes = { &qns_mem_noc_hf },
 476};
 477
 478static struct qcom_icc_node qxm_mdp1 = {
 479	.name = "qxm_mdp1",
 480	.channels = 1,
 481	.buswidth = 32,
 482	.num_links = 1,
 483	.link_nodes = { &qns_mem_noc_hf },
 484};
 485
 486static struct qcom_icc_node qxm_rot = {
 487	.name = "qxm_rot",
 488	.channels = 1,
 489	.buswidth = 32,
 490	.num_links = 1,
 491	.link_nodes = { &qns2_mem_noc },
 492};
 493
 494static struct qcom_icc_node qxm_venus0 = {
 495	.name = "qxm_venus0",
 496	.channels = 1,
 497	.buswidth = 32,
 498	.num_links = 1,
 499	.link_nodes = { &qns2_mem_noc },
 500};
 501
 502static struct qcom_icc_node qxm_venus1 = {
 503	.name = "qxm_venus1",
 504	.channels = 1,
 505	.buswidth = 32,
 506	.num_links = 1,
 507	.link_nodes = { &qns2_mem_noc },
 508};
 509
 510static struct qcom_icc_node qxm_venus_arm9 = {
 511	.name = "qxm_venus_arm9",
 512	.channels = 1,
 513	.buswidth = 8,
 514	.num_links = 1,
 515	.link_nodes = { &qns2_mem_noc },
 516};
 517
 518static struct qcom_icc_node qhm_snoc_cfg = {
 519	.name = "qhm_snoc_cfg",
 520	.channels = 1,
 521	.buswidth = 4,
 522	.num_links = 1,
 523	.link_nodes = { &srvc_snoc },
 524};
 525
 526static struct qcom_icc_node qnm_aggre1_noc = {
 527	.name = "qnm_aggre1_noc",
 528	.channels = 1,
 529	.buswidth = 16,
 530	.num_links = 6,
 531	.link_nodes = { &qxs_pimem,
 532			&qns_memnoc_sf,
 533			&qxs_imem,
 534			&qhs_apss,
 535			&qns_cnoc,
 536			&xs_qdss_stm },
 537};
 538
 539static struct qcom_icc_node qnm_aggre2_noc = {
 540	.name = "qnm_aggre2_noc",
 541	.channels = 1,
 542	.buswidth = 16,
 543	.num_links = 7,
 544	.link_nodes = { &qxs_pimem,
 545			&qns_memnoc_sf,
 546			&qxs_imem,
 547			&qhs_apss,
 548			&qns_cnoc,
 549			&xs_sys_tcu_cfg,
 550			&xs_qdss_stm },
 551};
 552
 553static struct qcom_icc_node qnm_gladiator_sodv = {
 554	.name = "qnm_gladiator_sodv",
 555	.channels = 1,
 556	.buswidth = 8,
 557	.num_links = 6,
 558	.link_nodes = { &qxs_pimem,
 559			&qxs_imem,
 560			&qhs_apss,
 561			&qns_cnoc,
 562			&xs_sys_tcu_cfg,
 563			&xs_qdss_stm },
 564};
 565
 566static struct qcom_icc_node qnm_memnoc = {
 567	.name = "qnm_memnoc",
 568	.channels = 1,
 569	.buswidth = 8,
 570	.num_links = 5,
 571	.link_nodes = { &qxs_imem,
 572			&qhs_apss,
 573			&qxs_pimem,
 574			&qns_cnoc,
 575			&xs_qdss_stm },
 576};
 577
 578static struct qcom_icc_node qxm_pimem = {
 579	.name = "qxm_pimem",
 580	.channels = 1,
 581	.buswidth = 8,
 582	.num_links = 2,
 583	.link_nodes = { &qxs_imem,
 584			&qns_memnoc_gc },
 585};
 586
 587static struct qcom_icc_node xm_gic = {
 588	.name = "xm_gic",
 589	.channels = 1,
 590	.buswidth = 8,
 591	.num_links = 2,
 592	.link_nodes = { &qxs_imem,
 593			&qns_memnoc_gc },
 594};
 595
 596static struct qcom_icc_node qns_a1noc_snoc = {
 597	.name = "qns_a1noc_snoc",
 598	.channels = 1,
 599	.buswidth = 16,
 600	.num_links = 1,
 601	.link_nodes = { &qnm_aggre1_noc },
 602};
 603
 604static struct qcom_icc_node srvc_aggre1_noc = {
 605	.name = "srvc_aggre1_noc",
 606	.channels = 1,
 607	.buswidth = 4,
 608};
 609
 610static struct qcom_icc_node qns_a2noc_snoc = {
 611	.name = "qns_a2noc_snoc",
 612	.channels = 1,
 613	.buswidth = 16,
 614	.num_links = 1,
 615	.link_nodes = { &qnm_aggre2_noc },
 616};
 617
 618static struct qcom_icc_node srvc_aggre2_noc = {
 619	.name = "srvc_aggre2_noc",
 620	.channels = 1,
 621	.buswidth = 4,
 622};
 623
 624static struct qcom_icc_node qns_camnoc_uncomp = {
 625	.name = "qns_camnoc_uncomp",
 626	.channels = 1,
 627	.buswidth = 32,
 628};
 629
 630static struct qcom_icc_node qhs_a1_noc_cfg = {
 631	.name = "qhs_a1_noc_cfg",
 632	.channels = 1,
 633	.buswidth = 4,
 634	.num_links = 1,
 635	.link_nodes = { &qhm_a1noc_cfg },
 636};
 637
 638static struct qcom_icc_node qhs_a2_noc_cfg = {
 639	.name = "qhs_a2_noc_cfg",
 640	.channels = 1,
 641	.buswidth = 4,
 642	.num_links = 1,
 643	.link_nodes = { &qhm_a2noc_cfg },
 644};
 645
 646static struct qcom_icc_node qhs_aop = {
 647	.name = "qhs_aop",
 648	.channels = 1,
 649	.buswidth = 4,
 650};
 651
 652static struct qcom_icc_node qhs_aoss = {
 653	.name = "qhs_aoss",
 654	.channels = 1,
 655	.buswidth = 4,
 656};
 657
 658static struct qcom_icc_node qhs_camera_cfg = {
 659	.name = "qhs_camera_cfg",
 660	.channels = 1,
 661	.buswidth = 4,
 662};
 663
 664static struct qcom_icc_node qhs_clk_ctl = {
 665	.name = "qhs_clk_ctl",
 666	.channels = 1,
 667	.buswidth = 4,
 668};
 669
 670static struct qcom_icc_node qhs_compute_dsp_cfg = {
 671	.name = "qhs_compute_dsp_cfg",
 672	.channels = 1,
 673	.buswidth = 4,
 674};
 675
 676static struct qcom_icc_node qhs_cpr_cx = {
 677	.name = "qhs_cpr_cx",
 678	.channels = 1,
 679	.buswidth = 4,
 680};
 681
 682static struct qcom_icc_node qhs_crypto0_cfg = {
 683	.name = "qhs_crypto0_cfg",
 684	.channels = 1,
 685	.buswidth = 4,
 686};
 687
 688static struct qcom_icc_node qhs_dcc_cfg = {
 689	.name = "qhs_dcc_cfg",
 690	.channels = 1,
 691	.buswidth = 4,
 692	.num_links = 1,
 693	.link_nodes = { &qhm_cnoc },
 694};
 695
 696static struct qcom_icc_node qhs_ddrss_cfg = {
 697	.name = "qhs_ddrss_cfg",
 698	.channels = 1,
 699	.buswidth = 4,
 700};
 701
 702static struct qcom_icc_node qhs_display_cfg = {
 703	.name = "qhs_display_cfg",
 704	.channels = 1,
 705	.buswidth = 4,
 706};
 707
 708static struct qcom_icc_node qhs_emmc_cfg = {
 709	.name = "qhs_emmc_cfg",
 710	.channels = 1,
 711	.buswidth = 4,
 712};
 713
 714static struct qcom_icc_node qhs_glm = {
 715	.name = "qhs_glm",
 716	.channels = 1,
 717	.buswidth = 4,
 718};
 719
 720static struct qcom_icc_node qhs_gpuss_cfg = {
 721	.name = "qhs_gpuss_cfg",
 722	.channels = 1,
 723	.buswidth = 8,
 724};
 725
 726static struct qcom_icc_node qhs_imem_cfg = {
 727	.name = "qhs_imem_cfg",
 728	.channels = 1,
 729	.buswidth = 4,
 730};
 731
 732static struct qcom_icc_node qhs_ipa = {
 733	.name = "qhs_ipa",
 734	.channels = 1,
 735	.buswidth = 4,
 736};
 737
 738static struct qcom_icc_node qhs_mnoc_cfg = {
 739	.name = "qhs_mnoc_cfg",
 740	.channels = 1,
 741	.buswidth = 4,
 742	.num_links = 1,
 743	.link_nodes = { &qhm_mnoc_cfg },
 744};
 745
 746static struct qcom_icc_node qhs_pdm = {
 747	.name = "qhs_pdm",
 748	.channels = 1,
 749	.buswidth = 4,
 750};
 751
 752static struct qcom_icc_node qhs_phy_refgen_south = {
 753	.name = "qhs_phy_refgen_south",
 754	.channels = 1,
 755	.buswidth = 4,
 756};
 757
 758static struct qcom_icc_node qhs_pimem_cfg = {
 759	.name = "qhs_pimem_cfg",
 760	.channels = 1,
 761	.buswidth = 4,
 762};
 763
 764static struct qcom_icc_node qhs_prng = {
 765	.name = "qhs_prng",
 766	.channels = 1,
 767	.buswidth = 4,
 768};
 769
 770static struct qcom_icc_node qhs_qdss_cfg = {
 771	.name = "qhs_qdss_cfg",
 772	.channels = 1,
 773	.buswidth = 4,
 774};
 775
 776static struct qcom_icc_node qhs_qupv3_north = {
 777	.name = "qhs_qupv3_north",
 778	.channels = 1,
 779	.buswidth = 4,
 780};
 781
 782static struct qcom_icc_node qhs_qupv3_south = {
 783	.name = "qhs_qupv3_south",
 784	.channels = 1,
 785	.buswidth = 4,
 786};
 787
 788static struct qcom_icc_node qhs_sdc2 = {
 789	.name = "qhs_sdc2",
 790	.channels = 1,
 791	.buswidth = 4,
 792};
 793
 794static struct qcom_icc_node qhs_sdc4 = {
 795	.name = "qhs_sdc4",
 796	.channels = 1,
 797	.buswidth = 4,
 798};
 799
 800static struct qcom_icc_node qhs_snoc_cfg = {
 801	.name = "qhs_snoc_cfg",
 802	.channels = 1,
 803	.buswidth = 4,
 804	.num_links = 1,
 805	.link_nodes = { &qhm_snoc_cfg },
 806};
 807
 808static struct qcom_icc_node qhs_spdm = {
 809	.name = "qhs_spdm",
 810	.channels = 1,
 811	.buswidth = 4,
 812};
 813
 814static struct qcom_icc_node qhs_tcsr = {
 815	.name = "qhs_tcsr",
 816	.channels = 1,
 817	.buswidth = 4,
 818};
 819
 820static struct qcom_icc_node qhs_tlmm_north = {
 821	.name = "qhs_tlmm_north",
 822	.channels = 1,
 823	.buswidth = 4,
 824};
 825
 826static struct qcom_icc_node qhs_tlmm_south = {
 827	.name = "qhs_tlmm_south",
 828	.channels = 1,
 829	.buswidth = 4,
 830};
 831
 832static struct qcom_icc_node qhs_tsif = {
 833	.name = "qhs_tsif",
 834	.channels = 1,
 835	.buswidth = 4,
 836};
 837
 838static struct qcom_icc_node qhs_ufs_mem_cfg = {
 839	.name = "qhs_ufs_mem_cfg",
 840	.channels = 1,
 841	.buswidth = 4,
 842};
 843
 844static struct qcom_icc_node qhs_usb3_0 = {
 845	.name = "qhs_usb3_0",
 846	.channels = 1,
 847	.buswidth = 4,
 848};
 849
 850static struct qcom_icc_node qhs_venus_cfg = {
 851	.name = "qhs_venus_cfg",
 852	.channels = 1,
 853	.buswidth = 4,
 854};
 855
 856static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
 857	.name = "qhs_vsense_ctrl_cfg",
 858	.channels = 1,
 859	.buswidth = 4,
 860};
 861
 862static struct qcom_icc_node qns_cnoc_a2noc = {
 863	.name = "qns_cnoc_a2noc",
 864	.channels = 1,
 865	.buswidth = 8,
 866	.num_links = 1,
 867	.link_nodes = { &qnm_cnoc },
 868};
 869
 870static struct qcom_icc_node srvc_cnoc = {
 871	.name = "srvc_cnoc",
 872	.channels = 1,
 873	.buswidth = 4,
 874};
 875
 876static struct qcom_icc_node qhs_llcc = {
 877	.name = "qhs_llcc",
 878	.channels = 1,
 879	.buswidth = 4,
 880};
 881
 882static struct qcom_icc_node qhs_memnoc = {
 883	.name = "qhs_memnoc",
 884	.channels = 1,
 885	.buswidth = 4,
 886	.num_links = 1,
 887	.link_nodes = { &qhm_memnoc_cfg },
 888};
 889
 890static struct qcom_icc_node qns_gladiator_sodv = {
 891	.name = "qns_gladiator_sodv",
 892	.channels = 1,
 893	.buswidth = 8,
 894	.num_links = 1,
 895	.link_nodes = { &qnm_gladiator_sodv },
 896};
 897
 898static struct qcom_icc_node qns_gnoc_memnoc = {
 899	.name = "qns_gnoc_memnoc",
 900	.channels = 2,
 901	.buswidth = 32,
 902	.num_links = 1,
 903	.link_nodes = { &qnm_apps },
 904};
 905
 906static struct qcom_icc_node srvc_gnoc = {
 907	.name = "srvc_gnoc",
 908	.channels = 1,
 909	.buswidth = 4,
 910};
 911
 912static struct qcom_icc_node ebi = {
 913	.name = "ebi",
 914	.channels = 2,
 915	.buswidth = 4,
 916};
 917
 918static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
 919	.name = "qhs_mdsp_ms_mpu_cfg",
 920	.channels = 1,
 921	.buswidth = 4,
 922};
 923
 924static struct qcom_icc_node qns_apps_io = {
 925	.name = "qns_apps_io",
 926	.channels = 1,
 927	.buswidth = 32,
 928};
 929
 930static struct qcom_icc_node qns_llcc = {
 931	.name = "qns_llcc",
 932	.channels = 2,
 933	.buswidth = 16,
 934	.num_links = 1,
 935	.link_nodes = { &llcc_mc },
 936};
 937
 938static struct qcom_icc_node qns_memnoc_snoc = {
 939	.name = "qns_memnoc_snoc",
 940	.channels = 1,
 941	.buswidth = 8,
 942	.num_links = 1,
 943	.link_nodes = { &qnm_memnoc },
 944};
 945
 946static struct qcom_icc_node srvc_memnoc = {
 947	.name = "srvc_memnoc",
 948	.channels = 1,
 949	.buswidth = 4,
 950};
 951
 952static struct qcom_icc_node qns2_mem_noc = {
 953	.name = "qns2_mem_noc",
 954	.channels = 1,
 955	.buswidth = 32,
 956	.num_links = 1,
 957	.link_nodes = { &qnm_mnoc_sf },
 958};
 959
 960static struct qcom_icc_node qns_mem_noc_hf = {
 961	.name = "qns_mem_noc_hf",
 962	.channels = 2,
 963	.buswidth = 32,
 964	.num_links = 1,
 965	.link_nodes = { &qnm_mnoc_hf },
 966};
 967
 968static struct qcom_icc_node srvc_mnoc = {
 969	.name = "srvc_mnoc",
 970	.channels = 1,
 971	.buswidth = 4,
 972};
 973
 974static struct qcom_icc_node qhs_apss = {
 975	.name = "qhs_apss",
 976	.channels = 1,
 977	.buswidth = 8,
 978};
 979
 980static struct qcom_icc_node qns_cnoc = {
 981	.name = "qns_cnoc",
 982	.channels = 1,
 983	.buswidth = 8,
 984	.num_links = 1,
 985	.link_nodes = { &qnm_snoc },
 986};
 987
 988static struct qcom_icc_node qns_memnoc_gc = {
 989	.name = "qns_memnoc_gc",
 990	.channels = 1,
 991	.buswidth = 8,
 992	.num_links = 1,
 993	.link_nodes = { &qnm_snoc_gc },
 994};
 995
 996static struct qcom_icc_node qns_memnoc_sf = {
 997	.name = "qns_memnoc_sf",
 998	.channels = 1,
 999	.buswidth = 16,
1000	.num_links = 1,
1001	.link_nodes = { &qnm_snoc_sf },
1002};
1003
1004static struct qcom_icc_node qxs_imem = {
1005	.name = "qxs_imem",
1006	.channels = 1,
1007	.buswidth = 8,
1008};
1009
1010static struct qcom_icc_node qxs_pimem = {
1011	.name = "qxs_pimem",
1012	.channels = 1,
1013	.buswidth = 8,
1014};
1015
1016static struct qcom_icc_node srvc_snoc = {
1017	.name = "srvc_snoc",
1018	.channels = 1,
1019	.buswidth = 4,
1020};
1021
1022static struct qcom_icc_node xs_qdss_stm = {
1023	.name = "xs_qdss_stm",
1024	.channels = 1,
1025	.buswidth = 4,
1026};
1027
1028static struct qcom_icc_node xs_sys_tcu_cfg = {
1029	.name = "xs_sys_tcu_cfg",
1030	.channels = 1,
1031	.buswidth = 8,
1032};
1033
1034static struct qcom_icc_bcm bcm_acv = {
1035	.name = "ACV",
1036	.enable_mask = BIT(3),
1037	.keepalive = false,
1038	.num_nodes = 1,
1039	.nodes = { &ebi },
1040};
1041
1042static struct qcom_icc_bcm bcm_mc0 = {
1043	.name = "MC0",
1044	.keepalive = true,
1045	.num_nodes = 1,
1046	.nodes = { &ebi },
1047};
1048
1049static struct qcom_icc_bcm bcm_sh0 = {
1050	.name = "SH0",
1051	.keepalive = true,
1052	.num_nodes = 1,
1053	.nodes = { &qns_llcc },
1054};
1055
1056static struct qcom_icc_bcm bcm_mm0 = {
1057	.name = "MM0",
1058	.keepalive = true,
1059	.num_nodes = 1,
1060	.nodes = { &qns_mem_noc_hf },
1061};
1062
1063static struct qcom_icc_bcm bcm_sh1 = {
1064	.name = "SH1",
1065	.keepalive = false,
1066	.num_nodes = 1,
1067	.nodes = { &qns_apps_io },
1068};
1069
1070static struct qcom_icc_bcm bcm_mm1 = {
1071	.name = "MM1",
1072	.keepalive = true,
1073	.num_nodes = 7,
1074	.nodes = { &qxm_camnoc_hf0_uncomp,
1075		   &qxm_camnoc_hf1_uncomp,
1076		   &qxm_camnoc_sf_uncomp,
1077		   &qxm_camnoc_hf0,
1078		   &qxm_camnoc_hf1,
1079		   &qxm_mdp0,
1080		   &qxm_mdp1
1081	},
1082};
1083
1084static struct qcom_icc_bcm bcm_sh2 = {
1085	.name = "SH2",
1086	.keepalive = false,
1087	.num_nodes = 1,
1088	.nodes = { &qns_memnoc_snoc },
1089};
1090
1091static struct qcom_icc_bcm bcm_mm2 = {
1092	.name = "MM2",
1093	.keepalive = false,
1094	.num_nodes = 1,
1095	.nodes = { &qns2_mem_noc },
1096};
1097
1098static struct qcom_icc_bcm bcm_sh3 = {
1099	.name = "SH3",
1100	.keepalive = false,
1101	.num_nodes = 1,
1102	.nodes = { &acm_tcu },
1103};
1104
1105static struct qcom_icc_bcm bcm_mm3 = {
1106	.name = "MM3",
1107	.keepalive = false,
1108	.num_nodes = 5,
1109	.nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
1110};
1111
1112static struct qcom_icc_bcm bcm_sh5 = {
1113	.name = "SH5",
1114	.keepalive = false,
1115	.num_nodes = 1,
1116	.nodes = { &qnm_apps },
1117};
1118
1119static struct qcom_icc_bcm bcm_sn0 = {
1120	.name = "SN0",
1121	.keepalive = true,
1122	.num_nodes = 1,
1123	.nodes = { &qns_memnoc_sf },
1124};
1125
1126static struct qcom_icc_bcm bcm_ce0 = {
1127	.name = "CE0",
1128	.keepalive = false,
1129	.num_nodes = 1,
1130	.nodes = { &qxm_crypto },
1131};
1132
1133static struct qcom_icc_bcm bcm_cn0 = {
1134	.name = "CN0",
1135	.keepalive = true,
1136	.num_nodes = 41,
1137	.nodes = { &qhm_spdm,
1138		   &qnm_snoc,
1139		   &qhs_a1_noc_cfg,
1140		   &qhs_a2_noc_cfg,
1141		   &qhs_aop,
1142		   &qhs_aoss,
1143		   &qhs_camera_cfg,
1144		   &qhs_clk_ctl,
1145		   &qhs_compute_dsp_cfg,
1146		   &qhs_cpr_cx,
1147		   &qhs_crypto0_cfg,
1148		   &qhs_dcc_cfg,
1149		   &qhs_ddrss_cfg,
1150		   &qhs_display_cfg,
1151		   &qhs_emmc_cfg,
1152		   &qhs_glm,
1153		   &qhs_gpuss_cfg,
1154		   &qhs_imem_cfg,
1155		   &qhs_ipa,
1156		   &qhs_mnoc_cfg,
1157		   &qhs_pdm,
1158		   &qhs_phy_refgen_south,
1159		   &qhs_pimem_cfg,
1160		   &qhs_prng,
1161		   &qhs_qdss_cfg,
1162		   &qhs_qupv3_north,
1163		   &qhs_qupv3_south,
1164		   &qhs_sdc2,
1165		   &qhs_sdc4,
1166		   &qhs_snoc_cfg,
1167		   &qhs_spdm,
1168		   &qhs_tcsr,
1169		   &qhs_tlmm_north,
1170		   &qhs_tlmm_south,
1171		   &qhs_tsif,
1172		   &qhs_ufs_mem_cfg,
1173		   &qhs_usb3_0,
1174		   &qhs_venus_cfg,
1175		   &qhs_vsense_ctrl_cfg,
1176		   &qns_cnoc_a2noc,
1177		   &srvc_cnoc
1178	},
1179};
1180
1181static struct qcom_icc_bcm bcm_qup0 = {
1182	.name = "QUP0",
1183	.keepalive = false,
1184	.num_nodes = 2,
1185	.nodes = { &qhm_qup1, &qhm_qup2 },
1186};
1187
1188static struct qcom_icc_bcm bcm_sn1 = {
1189	.name = "SN1",
1190	.keepalive = false,
1191	.num_nodes = 1,
1192	.nodes = { &qxs_imem },
1193};
1194
1195static struct qcom_icc_bcm bcm_sn2 = {
1196	.name = "SN2",
1197	.keepalive = false,
1198	.num_nodes = 1,
1199	.nodes = { &qns_memnoc_gc },
1200};
1201
1202static struct qcom_icc_bcm bcm_sn3 = {
1203	.name = "SN3",
1204	.keepalive = false,
1205	.num_nodes = 1,
1206	.nodes = { &qns_cnoc },
1207};
1208
1209static struct qcom_icc_bcm bcm_sn4 = {
1210	.name = "SN4",
1211	.keepalive = false,
1212	.num_nodes = 2,
1213	.nodes = { &qxm_pimem, &qxs_pimem },
1214};
1215
1216static struct qcom_icc_bcm bcm_sn5 = {
1217	.name = "SN5",
1218	.keepalive = false,
1219	.num_nodes = 1,
1220	.nodes = { &xs_qdss_stm },
1221};
1222
1223static struct qcom_icc_bcm bcm_sn8 = {
1224	.name = "SN8",
1225	.keepalive = false,
1226	.num_nodes = 2,
1227	.nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc },
1228};
1229
1230static struct qcom_icc_bcm bcm_sn10 = {
1231	.name = "SN10",
1232	.keepalive = false,
1233	.num_nodes = 2,
1234	.nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc },
1235};
1236
1237static struct qcom_icc_bcm bcm_sn11 = {
1238	.name = "SN11",
1239	.keepalive = false,
1240	.num_nodes = 2,
1241	.nodes = { &qnm_gladiator_sodv, &xm_gic },
1242};
1243
1244static struct qcom_icc_bcm bcm_sn13 = {
1245	.name = "SN13",
1246	.keepalive = false,
1247	.num_nodes = 1,
1248	.nodes = { &qnm_memnoc },
1249};
1250
1251static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1252	&bcm_qup0,
1253	&bcm_sn8,
1254};
1255
1256static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1257	[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1258	[MASTER_BLSP_1] = &qhm_qup1,
1259	[MASTER_TSIF] = &qhm_tsif,
1260	[MASTER_EMMC] = &xm_emmc,
1261	[MASTER_SDCC_2] = &xm_sdc2,
1262	[MASTER_SDCC_4] = &xm_sdc4,
1263	[MASTER_UFS_MEM] = &xm_ufs_mem,
1264	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1265	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1266};
1267
1268static const struct qcom_icc_desc sdm670_aggre1_noc = {
1269	.nodes = aggre1_noc_nodes,
1270	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1271	.bcms = aggre1_noc_bcms,
1272	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1273};
1274
1275static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1276	&bcm_ce0,
1277	&bcm_qup0,
1278	&bcm_sn10,
1279};
1280
1281static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1282	[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1283	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1284	[MASTER_BLSP_2] = &qhm_qup2,
1285	[MASTER_CNOC_A2NOC] = &qnm_cnoc,
1286	[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
1287	[MASTER_IPA] = &qxm_ipa,
1288	[MASTER_QDSS_ETR] = &xm_qdss_etr,
1289	[MASTER_USB3] = &xm_usb3_0,
1290	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1291	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1292};
1293
1294static const struct qcom_icc_desc sdm670_aggre2_noc = {
1295	.nodes = aggre2_noc_nodes,
1296	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1297	.bcms = aggre2_noc_bcms,
1298	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1299};
1300
1301static struct qcom_icc_bcm * const config_noc_bcms[] = {
1302	&bcm_cn0,
1303};
1304
1305static struct qcom_icc_node * const config_noc_nodes[] = {
1306	[MASTER_SPDM] = &qhm_spdm,
1307	[MASTER_SNOC_CNOC] = &qnm_snoc,
1308	[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1309	[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1310	[SLAVE_AOP] = &qhs_aop,
1311	[SLAVE_AOSS] = &qhs_aoss,
1312	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1313	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1314	[SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
1315	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1316	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1317	[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1318	[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1319	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1320	[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1321	[SLAVE_GLM] = &qhs_glm,
1322	[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
1323	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1324	[SLAVE_IPA_CFG] = &qhs_ipa,
1325	[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1326	[SLAVE_PDM] = &qhs_pdm,
1327	[SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
1328	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1329	[SLAVE_PRNG] = &qhs_prng,
1330	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1331	[SLAVE_BLSP_2] = &qhs_qupv3_north,
1332	[SLAVE_BLSP_1] = &qhs_qupv3_south,
1333	[SLAVE_SDCC_2] = &qhs_sdc2,
1334	[SLAVE_SDCC_4] = &qhs_sdc4,
1335	[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1336	[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1337	[SLAVE_TCSR] = &qhs_tcsr,
1338	[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
1339	[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1340	[SLAVE_TSIF] = &qhs_tsif,
1341	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1342	[SLAVE_USB3] = &qhs_usb3_0,
1343	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1344	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1345	[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1346	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1347};
1348
1349static const struct qcom_icc_desc sdm670_config_noc = {
1350	.nodes = config_noc_nodes,
1351	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1352	.bcms = config_noc_bcms,
1353	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1354};
1355
1356static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1357};
1358
1359static struct qcom_icc_node * const dc_noc_nodes[] = {
1360	[MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1361	[SLAVE_LLCC_CFG] = &qhs_llcc,
1362	[SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
1363};
1364
1365static const struct qcom_icc_desc sdm670_dc_noc = {
1366	.nodes = dc_noc_nodes,
1367	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1368	.bcms = dc_noc_bcms,
1369	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
1370};
1371
1372static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
1373};
1374
1375static struct qcom_icc_node * const gladiator_noc_nodes[] = {
1376	[MASTER_AMPSS_M0] = &acm_l3,
1377	[MASTER_GNOC_CFG] = &pm_gnoc_cfg,
1378	[SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
1379	[SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
1380	[SLAVE_SERVICE_GNOC] = &srvc_gnoc,
1381};
1382
1383static const struct qcom_icc_desc sdm670_gladiator_noc = {
1384	.nodes = gladiator_noc_nodes,
1385	.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
1386	.bcms = gladiator_noc_bcms,
1387	.num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
1388};
1389
1390static struct qcom_icc_bcm * const mem_noc_bcms[] = {
1391	&bcm_acv,
1392	&bcm_mc0,
1393	&bcm_sh0,
1394	&bcm_sh1,
1395	&bcm_sh2,
1396	&bcm_sh3,
1397	&bcm_sh5,
1398};
1399
1400static struct qcom_icc_node * const mem_noc_nodes[] = {
1401	[MASTER_TCU_0] = &acm_tcu,
1402	[MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
1403	[MASTER_GNOC_MEM_NOC] = &qnm_apps,
1404	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1405	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1406	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1407	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1408	[MASTER_GRAPHICS_3D] = &qxm_gpu,
1409	[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1410	[SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
1411	[SLAVE_LLCC] = &qns_llcc,
1412	[SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
1413	[SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
1414	[MASTER_LLCC] = &llcc_mc,
1415	[SLAVE_EBI_CH0] = &ebi,
1416};
1417
1418static const struct qcom_icc_desc sdm670_mem_noc = {
1419	.nodes = mem_noc_nodes,
1420	.num_nodes = ARRAY_SIZE(mem_noc_nodes),
1421	.bcms = mem_noc_bcms,
1422	.num_bcms = ARRAY_SIZE(mem_noc_bcms),
1423};
1424
1425static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1426	&bcm_mm0,
1427	&bcm_mm1,
1428	&bcm_mm2,
1429	&bcm_mm3,
1430};
1431
1432static struct qcom_icc_node * const mmss_noc_nodes[] = {
1433	[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1434	[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1435	[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1436	[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1437	[MASTER_MDP_PORT0] = &qxm_mdp0,
1438	[MASTER_MDP_PORT1] = &qxm_mdp1,
1439	[MASTER_ROTATOR] = &qxm_rot,
1440	[MASTER_VIDEO_P0] = &qxm_venus0,
1441	[MASTER_VIDEO_P1] = &qxm_venus1,
1442	[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1443	[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1444	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1445	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1446};
1447
1448static const struct qcom_icc_desc sdm670_mmss_noc = {
1449	.nodes = mmss_noc_nodes,
1450	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1451	.bcms = mmss_noc_bcms,
1452	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1453};
1454
1455static struct qcom_icc_bcm * const system_noc_bcms[] = {
1456	&bcm_mm1,
1457	&bcm_sn0,
1458	&bcm_sn1,
1459	&bcm_sn10,
1460	&bcm_sn11,
1461	&bcm_sn13,
1462	&bcm_sn2,
1463	&bcm_sn3,
1464	&bcm_sn4,
1465	&bcm_sn5,
1466	&bcm_sn8,
1467};
1468
1469static struct qcom_icc_node * const system_noc_nodes[] = {
1470	[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1471	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1472	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1473	[MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
1474	[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
1475	[MASTER_PIMEM] = &qxm_pimem,
1476	[MASTER_GIC] = &xm_gic,
1477	[SLAVE_APPSS] = &qhs_apss,
1478	[SLAVE_SNOC_CNOC] = &qns_cnoc,
1479	[SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1480	[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
1481	[SLAVE_OCIMEM] = &qxs_imem,
1482	[SLAVE_PIMEM] = &qxs_pimem,
1483	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1484	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1485	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1486	[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1487	[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1488	[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1489	[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1490};
1491
1492static const struct qcom_icc_desc sdm670_system_noc = {
1493	.nodes = system_noc_nodes,
1494	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1495	.bcms = system_noc_bcms,
1496	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1497};
1498
1499static const struct of_device_id qnoc_of_match[] = {
1500	{ .compatible = "qcom,sdm670-aggre1-noc",
1501	  .data = &sdm670_aggre1_noc},
1502	{ .compatible = "qcom,sdm670-aggre2-noc",
1503	  .data = &sdm670_aggre2_noc},
1504	{ .compatible = "qcom,sdm670-config-noc",
1505	  .data = &sdm670_config_noc},
1506	{ .compatible = "qcom,sdm670-dc-noc",
1507	  .data = &sdm670_dc_noc},
1508	{ .compatible = "qcom,sdm670-gladiator-noc",
1509	  .data = &sdm670_gladiator_noc},
1510	{ .compatible = "qcom,sdm670-mem-noc",
1511	  .data = &sdm670_mem_noc},
1512	{ .compatible = "qcom,sdm670-mmss-noc",
1513	  .data = &sdm670_mmss_noc},
1514	{ .compatible = "qcom,sdm670-system-noc",
1515	  .data = &sdm670_system_noc},
1516	{ }
1517};
1518MODULE_DEVICE_TABLE(of, qnoc_of_match);
1519
1520static struct platform_driver qnoc_driver = {
1521	.probe = qcom_icc_rpmh_probe,
1522	.remove = qcom_icc_rpmh_remove,
1523	.driver = {
1524		.name = "qnoc-sdm670",
1525		.of_match_table = qnoc_of_match,
1526		.sync_state = icc_sync_state,
1527	},
1528};
1529module_platform_driver(qnoc_driver);
1530
1531MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver");
1532MODULE_LICENSE("GPL");