sc8180x.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2021, Linaro Ltd.
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/module.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/platform_device.h>
  12
  13#include <dt-bindings/interconnect/qcom,sc8180x.h>
  14
  15#include "bcm-voter.h"
  16#include "icc-rpmh.h"
  17
  18static struct qcom_icc_node mas_qhm_a1noc_cfg;
  19static struct qcom_icc_node mas_xm_ufs_card;
  20static struct qcom_icc_node mas_xm_ufs_g4;
  21static struct qcom_icc_node mas_xm_ufs_mem;
  22static struct qcom_icc_node mas_xm_usb3_0;
  23static struct qcom_icc_node mas_xm_usb3_1;
  24static struct qcom_icc_node mas_xm_usb3_2;
  25static struct qcom_icc_node mas_qhm_a2noc_cfg;
  26static struct qcom_icc_node mas_qhm_qdss_bam;
  27static struct qcom_icc_node mas_qhm_qspi;
  28static struct qcom_icc_node mas_qhm_qspi1;
  29static struct qcom_icc_node mas_qhm_qup0;
  30static struct qcom_icc_node mas_qhm_qup1;
  31static struct qcom_icc_node mas_qhm_qup2;
  32static struct qcom_icc_node mas_qhm_sensorss_ahb;
  33static struct qcom_icc_node mas_qxm_crypto;
  34static struct qcom_icc_node mas_qxm_ipa;
  35static struct qcom_icc_node mas_xm_emac;
  36static struct qcom_icc_node mas_xm_pcie3_0;
  37static struct qcom_icc_node mas_xm_pcie3_1;
  38static struct qcom_icc_node mas_xm_pcie3_2;
  39static struct qcom_icc_node mas_xm_pcie3_3;
  40static struct qcom_icc_node mas_xm_qdss_etr;
  41static struct qcom_icc_node mas_xm_sdc2;
  42static struct qcom_icc_node mas_xm_sdc4;
  43static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp;
  44static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp;
  45static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp;
  46static struct qcom_icc_node mas_qnm_npu;
  47static struct qcom_icc_node mas_qnm_snoc;
  48static struct qcom_icc_node mas_qhm_cnoc_dc_noc;
  49static struct qcom_icc_node mas_acm_apps;
  50static struct qcom_icc_node mas_acm_gpu_tcu;
  51static struct qcom_icc_node mas_acm_sys_tcu;
  52static struct qcom_icc_node mas_qhm_gemnoc_cfg;
  53static struct qcom_icc_node mas_qnm_cmpnoc;
  54static struct qcom_icc_node mas_qnm_gpu;
  55static struct qcom_icc_node mas_qnm_mnoc_hf;
  56static struct qcom_icc_node mas_qnm_mnoc_sf;
  57static struct qcom_icc_node mas_qnm_pcie;
  58static struct qcom_icc_node mas_qnm_snoc_gc;
  59static struct qcom_icc_node mas_qnm_snoc_sf;
  60static struct qcom_icc_node mas_qxm_ecc;
  61static struct qcom_icc_node mas_llcc_mc;
  62static struct qcom_icc_node mas_qhm_mnoc_cfg;
  63static struct qcom_icc_node mas_qxm_camnoc_hf0;
  64static struct qcom_icc_node mas_qxm_camnoc_hf1;
  65static struct qcom_icc_node mas_qxm_camnoc_sf;
  66static struct qcom_icc_node mas_qxm_mdp0;
  67static struct qcom_icc_node mas_qxm_mdp1;
  68static struct qcom_icc_node mas_qxm_rot;
  69static struct qcom_icc_node mas_qxm_venus0;
  70static struct qcom_icc_node mas_qxm_venus1;
  71static struct qcom_icc_node mas_qxm_venus_arm9;
  72static struct qcom_icc_node mas_qhm_snoc_cfg;
  73static struct qcom_icc_node mas_qnm_aggre1_noc;
  74static struct qcom_icc_node mas_qnm_aggre2_noc;
  75static struct qcom_icc_node mas_qnm_gemnoc;
  76static struct qcom_icc_node mas_qxm_pimem;
  77static struct qcom_icc_node mas_xm_gic;
  78static struct qcom_icc_node mas_qup_core_0;
  79static struct qcom_icc_node mas_qup_core_1;
  80static struct qcom_icc_node mas_qup_core_2;
  81static struct qcom_icc_node slv_qns_a1noc_snoc;
  82static struct qcom_icc_node slv_srvc_aggre1_noc;
  83static struct qcom_icc_node slv_qns_a2noc_snoc;
  84static struct qcom_icc_node slv_qns_pcie_mem_noc;
  85static struct qcom_icc_node slv_srvc_aggre2_noc;
  86static struct qcom_icc_node slv_qns_camnoc_uncomp;
  87static struct qcom_icc_node slv_qns_cdsp_mem_noc;
  88static struct qcom_icc_node slv_qhs_a1_noc_cfg;
  89static struct qcom_icc_node slv_qhs_a2_noc_cfg;
  90static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center;
  91static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east;
  92static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west;
  93static struct qcom_icc_node slv_qhs_ahb2phy_south;
  94static struct qcom_icc_node slv_qhs_aop;
  95static struct qcom_icc_node slv_qhs_aoss;
  96static struct qcom_icc_node slv_qhs_camera_cfg;
  97static struct qcom_icc_node slv_qhs_clk_ctl;
  98static struct qcom_icc_node slv_qhs_compute_dsp;
  99static struct qcom_icc_node slv_qhs_cpr_cx;
 100static struct qcom_icc_node slv_qhs_cpr_mmcx;
 101static struct qcom_icc_node slv_qhs_cpr_mx;
 102static struct qcom_icc_node slv_qhs_crypto0_cfg;
 103static struct qcom_icc_node slv_qhs_ddrss_cfg;
 104static struct qcom_icc_node slv_qhs_display_cfg;
 105static struct qcom_icc_node slv_qhs_emac_cfg;
 106static struct qcom_icc_node slv_qhs_glm;
 107static struct qcom_icc_node slv_qhs_gpuss_cfg;
 108static struct qcom_icc_node slv_qhs_imem_cfg;
 109static struct qcom_icc_node slv_qhs_ipa;
 110static struct qcom_icc_node slv_qhs_mnoc_cfg;
 111static struct qcom_icc_node slv_qhs_npu_cfg;
 112static struct qcom_icc_node slv_qhs_pcie0_cfg;
 113static struct qcom_icc_node slv_qhs_pcie1_cfg;
 114static struct qcom_icc_node slv_qhs_pcie2_cfg;
 115static struct qcom_icc_node slv_qhs_pcie3_cfg;
 116static struct qcom_icc_node slv_qhs_pdm;
 117static struct qcom_icc_node slv_qhs_pimem_cfg;
 118static struct qcom_icc_node slv_qhs_prng;
 119static struct qcom_icc_node slv_qhs_qdss_cfg;
 120static struct qcom_icc_node slv_qhs_qspi_0;
 121static struct qcom_icc_node slv_qhs_qspi_1;
 122static struct qcom_icc_node slv_qhs_qupv3_east0;
 123static struct qcom_icc_node slv_qhs_qupv3_east1;
 124static struct qcom_icc_node slv_qhs_qupv3_west;
 125static struct qcom_icc_node slv_qhs_sdc2;
 126static struct qcom_icc_node slv_qhs_sdc4;
 127static struct qcom_icc_node slv_qhs_security;
 128static struct qcom_icc_node slv_qhs_snoc_cfg;
 129static struct qcom_icc_node slv_qhs_spss_cfg;
 130static struct qcom_icc_node slv_qhs_tcsr;
 131static struct qcom_icc_node slv_qhs_tlmm_east;
 132static struct qcom_icc_node slv_qhs_tlmm_south;
 133static struct qcom_icc_node slv_qhs_tlmm_west;
 134static struct qcom_icc_node slv_qhs_tsif;
 135static struct qcom_icc_node slv_qhs_ufs_card_cfg;
 136static struct qcom_icc_node slv_qhs_ufs_mem0_cfg;
 137static struct qcom_icc_node slv_qhs_ufs_mem1_cfg;
 138static struct qcom_icc_node slv_qhs_usb3_0;
 139static struct qcom_icc_node slv_qhs_usb3_1;
 140static struct qcom_icc_node slv_qhs_usb3_2;
 141static struct qcom_icc_node slv_qhs_venus_cfg;
 142static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg;
 143static struct qcom_icc_node slv_srvc_cnoc;
 144static struct qcom_icc_node slv_qhs_gemnoc;
 145static struct qcom_icc_node slv_qhs_llcc;
 146static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg;
 147static struct qcom_icc_node slv_qns_ecc;
 148static struct qcom_icc_node slv_qns_gem_noc_snoc;
 149static struct qcom_icc_node slv_qns_llcc;
 150static struct qcom_icc_node slv_srvc_gemnoc;
 151static struct qcom_icc_node slv_srvc_gemnoc1;
 152static struct qcom_icc_node slv_ebi;
 153static struct qcom_icc_node slv_qns2_mem_noc;
 154static struct qcom_icc_node slv_qns_mem_noc_hf;
 155static struct qcom_icc_node slv_srvc_mnoc;
 156static struct qcom_icc_node slv_qhs_apss;
 157static struct qcom_icc_node slv_qns_cnoc;
 158static struct qcom_icc_node slv_qns_gemnoc_gc;
 159static struct qcom_icc_node slv_qns_gemnoc_sf;
 160static struct qcom_icc_node slv_qxs_imem;
 161static struct qcom_icc_node slv_qxs_pimem;
 162static struct qcom_icc_node slv_srvc_snoc;
 163static struct qcom_icc_node slv_xs_pcie_0;
 164static struct qcom_icc_node slv_xs_pcie_1;
 165static struct qcom_icc_node slv_xs_pcie_2;
 166static struct qcom_icc_node slv_xs_pcie_3;
 167static struct qcom_icc_node slv_xs_qdss_stm;
 168static struct qcom_icc_node slv_xs_sys_tcu_cfg;
 169static struct qcom_icc_node slv_qup_core_0;
 170static struct qcom_icc_node slv_qup_core_1;
 171static struct qcom_icc_node slv_qup_core_2;
 172
 173static struct qcom_icc_node mas_qhm_a1noc_cfg = {
 174	.name = "mas_qhm_a1noc_cfg",
 175	.channels = 1,
 176	.buswidth = 4,
 177	.num_links = 1,
 178	.link_nodes = { &slv_srvc_aggre1_noc },
 179};
 180
 181static struct qcom_icc_node mas_xm_ufs_card = {
 182	.name = "mas_xm_ufs_card",
 183	.channels = 1,
 184	.buswidth = 8,
 185	.num_links = 1,
 186	.link_nodes = { &slv_qns_a1noc_snoc },
 187};
 188
 189static struct qcom_icc_node mas_xm_ufs_g4 = {
 190	.name = "mas_xm_ufs_g4",
 191	.channels = 1,
 192	.buswidth = 8,
 193	.num_links = 1,
 194	.link_nodes = { &slv_qns_a1noc_snoc },
 195};
 196
 197static struct qcom_icc_node mas_xm_ufs_mem = {
 198	.name = "mas_xm_ufs_mem",
 199	.channels = 1,
 200	.buswidth = 8,
 201	.num_links = 1,
 202	.link_nodes = { &slv_qns_a1noc_snoc },
 203};
 204
 205static struct qcom_icc_node mas_xm_usb3_0 = {
 206	.name = "mas_xm_usb3_0",
 207	.channels = 1,
 208	.buswidth = 8,
 209	.num_links = 1,
 210	.link_nodes = { &slv_qns_a1noc_snoc },
 211};
 212
 213static struct qcom_icc_node mas_xm_usb3_1 = {
 214	.name = "mas_xm_usb3_1",
 215	.channels = 1,
 216	.buswidth = 8,
 217	.num_links = 1,
 218	.link_nodes = { &slv_qns_a1noc_snoc },
 219};
 220
 221static struct qcom_icc_node mas_xm_usb3_2 = {
 222	.name = "mas_xm_usb3_2",
 223	.channels = 1,
 224	.buswidth = 16,
 225	.num_links = 1,
 226	.link_nodes = { &slv_qns_a1noc_snoc },
 227};
 228
 229static struct qcom_icc_node mas_qhm_a2noc_cfg = {
 230	.name = "mas_qhm_a2noc_cfg",
 231	.channels = 1,
 232	.buswidth = 4,
 233	.num_links = 1,
 234	.link_nodes = { &slv_srvc_aggre2_noc },
 235};
 236
 237static struct qcom_icc_node mas_qhm_qdss_bam = {
 238	.name = "mas_qhm_qdss_bam",
 239	.channels = 1,
 240	.buswidth = 4,
 241	.num_links = 1,
 242	.link_nodes = { &slv_qns_a2noc_snoc },
 243};
 244
 245static struct qcom_icc_node mas_qhm_qspi = {
 246	.name = "mas_qhm_qspi",
 247	.channels = 1,
 248	.buswidth = 4,
 249	.num_links = 1,
 250	.link_nodes = { &slv_qns_a2noc_snoc },
 251};
 252
 253static struct qcom_icc_node mas_qhm_qspi1 = {
 254	.name = "mas_qhm_qspi1",
 255	.channels = 1,
 256	.buswidth = 4,
 257	.num_links = 1,
 258	.link_nodes = { &slv_qns_a2noc_snoc },
 259};
 260
 261static struct qcom_icc_node mas_qhm_qup0 = {
 262	.name = "mas_qhm_qup0",
 263	.channels = 1,
 264	.buswidth = 4,
 265	.num_links = 1,
 266	.link_nodes = { &slv_qns_a2noc_snoc },
 267};
 268
 269static struct qcom_icc_node mas_qhm_qup1 = {
 270	.name = "mas_qhm_qup1",
 271	.channels = 1,
 272	.buswidth = 4,
 273	.num_links = 1,
 274	.link_nodes = { &slv_qns_a2noc_snoc },
 275};
 276
 277static struct qcom_icc_node mas_qhm_qup2 = {
 278	.name = "mas_qhm_qup2",
 279	.channels = 1,
 280	.buswidth = 4,
 281	.num_links = 1,
 282	.link_nodes = { &slv_qns_a2noc_snoc },
 283};
 284
 285static struct qcom_icc_node mas_qhm_sensorss_ahb = {
 286	.name = "mas_qhm_sensorss_ahb",
 287	.channels = 1,
 288	.buswidth = 4,
 289	.num_links = 1,
 290	.link_nodes = { &slv_qns_a2noc_snoc },
 291};
 292
 293static struct qcom_icc_node mas_qxm_crypto = {
 294	.name = "mas_qxm_crypto",
 295	.channels = 1,
 296	.buswidth = 8,
 297	.num_links = 1,
 298	.link_nodes = { &slv_qns_a2noc_snoc },
 299};
 300
 301static struct qcom_icc_node mas_qxm_ipa = {
 302	.name = "mas_qxm_ipa",
 303	.channels = 1,
 304	.buswidth = 8,
 305	.num_links = 1,
 306	.link_nodes = { &slv_qns_a2noc_snoc },
 307};
 308
 309static struct qcom_icc_node mas_xm_emac = {
 310	.name = "mas_xm_emac",
 311	.channels = 1,
 312	.buswidth = 8,
 313	.num_links = 1,
 314	.link_nodes = { &slv_qns_a2noc_snoc },
 315};
 316
 317static struct qcom_icc_node mas_xm_pcie3_0 = {
 318	.name = "mas_xm_pcie3_0",
 319	.channels = 1,
 320	.buswidth = 8,
 321	.num_links = 1,
 322	.link_nodes = { &slv_qns_pcie_mem_noc },
 323};
 324
 325static struct qcom_icc_node mas_xm_pcie3_1 = {
 326	.name = "mas_xm_pcie3_1",
 327	.channels = 1,
 328	.buswidth = 16,
 329	.num_links = 1,
 330	.link_nodes = { &slv_qns_pcie_mem_noc },
 331};
 332
 333static struct qcom_icc_node mas_xm_pcie3_2 = {
 334	.name = "mas_xm_pcie3_2",
 335	.channels = 1,
 336	.buswidth = 8,
 337	.num_links = 1,
 338	.link_nodes = { &slv_qns_pcie_mem_noc },
 339};
 340
 341static struct qcom_icc_node mas_xm_pcie3_3 = {
 342	.name = "mas_xm_pcie3_3",
 343	.channels = 1,
 344	.buswidth = 16,
 345	.num_links = 1,
 346	.link_nodes = { &slv_qns_pcie_mem_noc },
 347};
 348
 349static struct qcom_icc_node mas_xm_qdss_etr = {
 350	.name = "mas_xm_qdss_etr",
 351	.channels = 1,
 352	.buswidth = 8,
 353	.num_links = 1,
 354	.link_nodes = { &slv_qns_a2noc_snoc },
 355};
 356
 357static struct qcom_icc_node mas_xm_sdc2 = {
 358	.name = "mas_xm_sdc2",
 359	.channels = 1,
 360	.buswidth = 8,
 361	.num_links = 1,
 362	.link_nodes = { &slv_qns_a2noc_snoc },
 363};
 364
 365static struct qcom_icc_node mas_xm_sdc4 = {
 366	.name = "mas_xm_sdc4",
 367	.channels = 1,
 368	.buswidth = 8,
 369	.num_links = 1,
 370	.link_nodes = { &slv_qns_a2noc_snoc },
 371};
 372
 373static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = {
 374	.name = "mas_qxm_camnoc_hf0_uncomp",
 375	.channels = 1,
 376	.buswidth = 32,
 377	.num_links = 1,
 378	.link_nodes = { &slv_qns_camnoc_uncomp },
 379};
 380
 381static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = {
 382	.name = "mas_qxm_camnoc_hf1_uncomp",
 383	.channels = 1,
 384	.buswidth = 32,
 385	.num_links = 1,
 386	.link_nodes = { &slv_qns_camnoc_uncomp },
 387};
 388
 389static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = {
 390	.name = "mas_qxm_camnoc_sf_uncomp",
 391	.channels = 1,
 392	.buswidth = 32,
 393	.num_links = 1,
 394	.link_nodes = { &slv_qns_camnoc_uncomp },
 395};
 396
 397static struct qcom_icc_node mas_qnm_npu = {
 398	.name = "mas_qnm_npu",
 399	.channels = 1,
 400	.buswidth = 32,
 401	.num_links = 1,
 402	.link_nodes = { &slv_qns_cdsp_mem_noc },
 403};
 404
 405static struct qcom_icc_node mas_qnm_snoc = {
 406	.name = "mas_qnm_snoc",
 407	.channels = 1,
 408	.buswidth = 8,
 409	.num_links = 56,
 410	.link_nodes = { &slv_qhs_tlmm_south,
 411			&slv_qhs_compute_dsp,
 412			&slv_qhs_spss_cfg,
 413			&slv_qhs_camera_cfg,
 414			&slv_qhs_sdc4,
 415			&slv_qhs_ahb2phy_refgen_center,
 416			&slv_qhs_sdc2,
 417			&slv_qhs_pcie2_cfg,
 418			&slv_qhs_mnoc_cfg,
 419			&slv_qhs_emac_cfg,
 420			&slv_qhs_qspi_0,
 421			&slv_qhs_qspi_1,
 422			&slv_qhs_tlmm_east,
 423			&slv_qhs_snoc_cfg,
 424			&slv_qhs_ahb2phy_refgen_east,
 425			&slv_qhs_glm,
 426			&slv_qhs_pdm,
 427			&slv_qhs_pcie1_cfg,
 428			&slv_qhs_a2_noc_cfg,
 429			&slv_qhs_qdss_cfg,
 430			&slv_qhs_display_cfg,
 431			&slv_qhs_tcsr,
 432			&slv_qhs_ufs_mem0_cfg,
 433			&slv_qhs_ddrss_cfg,
 434			&slv_qhs_pcie0_cfg,
 435			&slv_qhs_qupv3_east0,
 436			&slv_qhs_qupv3_east1,
 437			&slv_qhs_npu_cfg,
 438			&slv_qhs_crypto0_cfg,
 439			&slv_qhs_gpuss_cfg,
 440			&slv_qhs_venus_cfg,
 441			&slv_qhs_tsif,
 442			&slv_qhs_ipa,
 443			&slv_qhs_clk_ctl,
 444			&slv_qhs_security,
 445			&slv_qhs_aop,
 446			&slv_qhs_ahb2phy_refgen_west,
 447			&slv_qhs_ahb2phy_south,
 448			&slv_srvc_cnoc,
 449			&slv_qhs_ufs_card_cfg,
 450			&slv_qhs_usb3_1,
 451			&slv_qhs_usb3_2,
 452			&slv_qhs_pcie3_cfg,
 453			&slv_qhs_cpr_cx,
 454			&slv_qhs_tlmm_west,
 455			&slv_qhs_a1_noc_cfg,
 456			&slv_qhs_aoss,
 457			&slv_qhs_prng,
 458			&slv_qhs_vsense_ctrl_cfg,
 459			&slv_qhs_qupv3_west,
 460			&slv_qhs_usb3_0,
 461			&slv_qhs_cpr_mmcx,
 462			&slv_qhs_pimem_cfg,
 463			&slv_qhs_ufs_mem1_cfg,
 464			&slv_qhs_cpr_mx,
 465			&slv_qhs_imem_cfg },
 466};
 467
 468static struct qcom_icc_node mas_qhm_cnoc_dc_noc = {
 469	.name = "mas_qhm_cnoc_dc_noc",
 470	.channels = 1,
 471	.buswidth = 4,
 472	.num_links = 2,
 473	.link_nodes = { &slv_qhs_llcc,
 474			&slv_qhs_gemnoc },
 475};
 476
 477static struct qcom_icc_node mas_acm_apps = {
 478	.name = "mas_acm_apps",
 479	.channels = 4,
 480	.buswidth = 64,
 481	.num_links = 3,
 482	.link_nodes = { &slv_qns_ecc,
 483			&slv_qns_llcc,
 484			&slv_qns_gem_noc_snoc },
 485};
 486
 487static struct qcom_icc_node mas_acm_gpu_tcu = {
 488	.name = "mas_acm_gpu_tcu",
 489	.channels = 1,
 490	.buswidth = 8,
 491	.num_links = 2,
 492	.link_nodes = { &slv_qns_llcc,
 493			&slv_qns_gem_noc_snoc },
 494};
 495
 496static struct qcom_icc_node mas_acm_sys_tcu = {
 497	.name = "mas_acm_sys_tcu",
 498	.channels = 1,
 499	.buswidth = 8,
 500	.num_links = 2,
 501	.link_nodes = { &slv_qns_llcc,
 502			&slv_qns_gem_noc_snoc },
 503};
 504
 505static struct qcom_icc_node mas_qhm_gemnoc_cfg = {
 506	.name = "mas_qhm_gemnoc_cfg",
 507	.channels = 1,
 508	.buswidth = 4,
 509	.num_links = 3,
 510	.link_nodes = { &slv_srvc_gemnoc1,
 511			&slv_srvc_gemnoc,
 512			&slv_qhs_mdsp_ms_mpu_cfg },
 513};
 514
 515static struct qcom_icc_node mas_qnm_cmpnoc = {
 516	.name = "mas_qnm_cmpnoc",
 517	.channels = 2,
 518	.buswidth = 32,
 519	.num_links = 3,
 520	.link_nodes = { &slv_qns_ecc,
 521			&slv_qns_llcc,
 522			&slv_qns_gem_noc_snoc },
 523};
 524
 525static struct qcom_icc_node mas_qnm_gpu = {
 526	.name = "mas_qnm_gpu",
 527	.channels = 4,
 528	.buswidth = 32,
 529	.num_links = 2,
 530	.link_nodes = { &slv_qns_llcc,
 531			&slv_qns_gem_noc_snoc },
 532};
 533
 534static struct qcom_icc_node mas_qnm_mnoc_hf = {
 535	.name = "mas_qnm_mnoc_hf",
 536	.channels = 2,
 537	.buswidth = 32,
 538	.num_links = 1,
 539	.link_nodes = { &slv_qns_llcc },
 540};
 541
 542static struct qcom_icc_node mas_qnm_mnoc_sf = {
 543	.name = "mas_qnm_mnoc_sf",
 544	.channels = 1,
 545	.buswidth = 32,
 546	.num_links = 2,
 547	.link_nodes = { &slv_qns_llcc,
 548			&slv_qns_gem_noc_snoc },
 549};
 550
 551static struct qcom_icc_node mas_qnm_pcie = {
 552	.name = "mas_qnm_pcie",
 553	.channels = 1,
 554	.buswidth = 32,
 555	.num_links = 2,
 556	.link_nodes = { &slv_qns_llcc,
 557			&slv_qns_gem_noc_snoc },
 558};
 559
 560static struct qcom_icc_node mas_qnm_snoc_gc = {
 561	.name = "mas_qnm_snoc_gc",
 562	.channels = 1,
 563	.buswidth = 8,
 564	.num_links = 1,
 565	.link_nodes = { &slv_qns_llcc },
 566};
 567
 568static struct qcom_icc_node mas_qnm_snoc_sf = {
 569	.name = "mas_qnm_snoc_sf",
 570	.channels = 1,
 571	.buswidth = 32,
 572	.num_links = 1,
 573	.link_nodes = { &slv_qns_llcc },
 574};
 575
 576static struct qcom_icc_node mas_qxm_ecc = {
 577	.name = "mas_qxm_ecc",
 578	.channels = 2,
 579	.buswidth = 32,
 580	.num_links = 1,
 581	.link_nodes = { &slv_qns_llcc },
 582};
 583
 584static struct qcom_icc_node mas_llcc_mc = {
 585	.name = "mas_llcc_mc",
 586	.channels = 8,
 587	.buswidth = 4,
 588	.num_links = 1,
 589	.link_nodes = { &slv_ebi },
 590};
 591
 592static struct qcom_icc_node mas_qhm_mnoc_cfg = {
 593	.name = "mas_qhm_mnoc_cfg",
 594	.channels = 1,
 595	.buswidth = 4,
 596	.num_links = 1,
 597	.link_nodes = { &slv_srvc_mnoc },
 598};
 599
 600static struct qcom_icc_node mas_qxm_camnoc_hf0 = {
 601	.name = "mas_qxm_camnoc_hf0",
 602	.channels = 1,
 603	.buswidth = 32,
 604	.num_links = 1,
 605	.link_nodes = { &slv_qns_mem_noc_hf },
 606};
 607
 608static struct qcom_icc_node mas_qxm_camnoc_hf1 = {
 609	.name = "mas_qxm_camnoc_hf1",
 610	.channels = 1,
 611	.buswidth = 32,
 612	.num_links = 1,
 613	.link_nodes = { &slv_qns_mem_noc_hf },
 614};
 615
 616static struct qcom_icc_node mas_qxm_camnoc_sf = {
 617	.name = "mas_qxm_camnoc_sf",
 618	.channels = 1,
 619	.buswidth = 32,
 620	.num_links = 1,
 621	.link_nodes = { &slv_qns2_mem_noc },
 622};
 623
 624static struct qcom_icc_node mas_qxm_mdp0 = {
 625	.name = "mas_qxm_mdp0",
 626	.channels = 1,
 627	.buswidth = 32,
 628	.num_links = 1,
 629	.link_nodes = { &slv_qns_mem_noc_hf },
 630};
 631
 632static struct qcom_icc_node mas_qxm_mdp1 = {
 633	.name = "mas_qxm_mdp1",
 634	.channels = 1,
 635	.buswidth = 32,
 636	.num_links = 1,
 637	.link_nodes = { &slv_qns_mem_noc_hf },
 638};
 639
 640static struct qcom_icc_node mas_qxm_rot = {
 641	.name = "mas_qxm_rot",
 642	.channels = 1,
 643	.buswidth = 32,
 644	.num_links = 1,
 645	.link_nodes = { &slv_qns2_mem_noc },
 646};
 647
 648static struct qcom_icc_node mas_qxm_venus0 = {
 649	.name = "mas_qxm_venus0",
 650	.channels = 1,
 651	.buswidth = 32,
 652	.num_links = 1,
 653	.link_nodes = { &slv_qns2_mem_noc },
 654};
 655
 656static struct qcom_icc_node mas_qxm_venus1 = {
 657	.name = "mas_qxm_venus1",
 658	.channels = 1,
 659	.buswidth = 32,
 660	.num_links = 1,
 661	.link_nodes = { &slv_qns2_mem_noc },
 662};
 663
 664static struct qcom_icc_node mas_qxm_venus_arm9 = {
 665	.name = "mas_qxm_venus_arm9",
 666	.channels = 1,
 667	.buswidth = 8,
 668	.num_links = 1,
 669	.link_nodes = { &slv_qns2_mem_noc },
 670};
 671
 672static struct qcom_icc_node mas_qhm_snoc_cfg = {
 673	.name = "mas_qhm_snoc_cfg",
 674	.channels = 1,
 675	.buswidth = 4,
 676	.num_links = 1,
 677	.link_nodes = { &slv_srvc_snoc },
 678};
 679
 680static struct qcom_icc_node mas_qnm_aggre1_noc = {
 681	.name = "mas_qnm_aggre1_noc",
 682	.channels = 1,
 683	.buswidth = 32,
 684	.num_links = 6,
 685	.link_nodes = { &slv_qns_gemnoc_sf,
 686			&slv_qxs_pimem,
 687			&slv_qxs_imem,
 688			&slv_qhs_apss,
 689			&slv_qns_cnoc,
 690			&slv_xs_qdss_stm },
 691};
 692
 693static struct qcom_icc_node mas_qnm_aggre2_noc = {
 694	.name = "mas_qnm_aggre2_noc",
 695	.channels = 1,
 696	.buswidth = 16,
 697	.num_links = 11,
 698	.link_nodes = { &slv_qns_gemnoc_sf,
 699			&slv_qxs_pimem,
 700			&slv_xs_pcie_3,
 701			&slv_qxs_imem,
 702			&slv_qhs_apss,
 703			&slv_xs_pcie_2,
 704			&slv_qns_cnoc,
 705			&slv_xs_pcie_0,
 706			&slv_xs_pcie_1,
 707			&slv_xs_sys_tcu_cfg,
 708			&slv_xs_qdss_stm },
 709};
 710
 711static struct qcom_icc_node mas_qnm_gemnoc = {
 712	.name = "mas_qnm_gemnoc",
 713	.channels = 1,
 714	.buswidth = 8,
 715	.num_links = 6,
 716	.link_nodes = { &slv_qxs_pimem,
 717			&slv_qxs_imem,
 718			&slv_qhs_apss,
 719			&slv_qns_cnoc,
 720			&slv_xs_sys_tcu_cfg,
 721			&slv_xs_qdss_stm },
 722};
 723
 724static struct qcom_icc_node mas_qxm_pimem = {
 725	.name = "mas_qxm_pimem",
 726	.channels = 1,
 727	.buswidth = 8,
 728	.num_links = 2,
 729	.link_nodes = { &slv_qns_gemnoc_gc,
 730			&slv_qxs_imem },
 731};
 732
 733static struct qcom_icc_node mas_xm_gic = {
 734	.name = "mas_xm_gic",
 735	.channels = 1,
 736	.buswidth = 8,
 737	.num_links = 2,
 738	.link_nodes = { &slv_qns_gemnoc_gc,
 739			&slv_qxs_imem },
 740};
 741
 742static struct qcom_icc_node mas_qup_core_0 = {
 743	.name = "mas_qup_core_0",
 744	.channels = 1,
 745	.buswidth = 4,
 746	.num_links = 1,
 747	.link_nodes = { &slv_qup_core_0 },
 748};
 749
 750static struct qcom_icc_node mas_qup_core_1 = {
 751	.name = "mas_qup_core_1",
 752	.channels = 1,
 753	.buswidth = 4,
 754	.num_links = 1,
 755	.link_nodes = { &slv_qup_core_1 },
 756};
 757
 758static struct qcom_icc_node mas_qup_core_2 = {
 759	.name = "mas_qup_core_2",
 760	.channels = 1,
 761	.buswidth = 4,
 762	.num_links = 1,
 763	.link_nodes = { &slv_qup_core_2 },
 764};
 765
 766static struct qcom_icc_node slv_qns_a1noc_snoc = {
 767	.name = "slv_qns_a1noc_snoc",
 768	.channels = 1,
 769	.buswidth = 32,
 770	.num_links = 1,
 771	.link_nodes = { &mas_qnm_aggre1_noc },
 772};
 773
 774static struct qcom_icc_node slv_srvc_aggre1_noc = {
 775	.name = "slv_srvc_aggre1_noc",
 776	.channels = 1,
 777	.buswidth = 4
 778};
 779
 780static struct qcom_icc_node slv_qns_a2noc_snoc = {
 781	.name = "slv_qns_a2noc_snoc",
 782	.channels = 1,
 783	.buswidth = 16,
 784	.num_links = 1,
 785	.link_nodes = { &mas_qnm_aggre2_noc },
 786};
 787
 788static struct qcom_icc_node slv_qns_pcie_mem_noc = {
 789	.name = "slv_qns_pcie_mem_noc",
 790	.channels = 1,
 791	.buswidth = 32,
 792	.num_links = 1,
 793	.link_nodes = { &mas_qnm_pcie },
 794};
 795
 796static struct qcom_icc_node slv_srvc_aggre2_noc = {
 797	.name = "slv_srvc_aggre2_noc",
 798	.channels = 1,
 799	.buswidth = 4
 800};
 801
 802static struct qcom_icc_node slv_qns_camnoc_uncomp = {
 803	.name = "slv_qns_camnoc_uncomp",
 804	.channels = 1,
 805	.buswidth = 32
 806};
 807
 808static struct qcom_icc_node slv_qns_cdsp_mem_noc = {
 809	.name = "slv_qns_cdsp_mem_noc",
 810	.channels = 2,
 811	.buswidth = 32,
 812	.num_links = 1,
 813	.link_nodes = { &mas_qnm_cmpnoc },
 814};
 815
 816static struct qcom_icc_node slv_qhs_a1_noc_cfg = {
 817	.name = "slv_qhs_a1_noc_cfg",
 818	.channels = 1,
 819	.buswidth = 4,
 820	.num_links = 1,
 821	.link_nodes = { &mas_qhm_a1noc_cfg },
 822};
 823
 824static struct qcom_icc_node slv_qhs_a2_noc_cfg = {
 825	.name = "slv_qhs_a2_noc_cfg",
 826	.channels = 1,
 827	.buswidth = 4,
 828	.num_links = 1,
 829	.link_nodes = { &mas_qhm_a2noc_cfg },
 830};
 831
 832static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = {
 833	.name = "slv_qhs_ahb2phy_refgen_center",
 834	.channels = 1,
 835	.buswidth = 4
 836};
 837
 838static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = {
 839	.name = "slv_qhs_ahb2phy_refgen_east",
 840	.channels = 1,
 841	.buswidth = 4
 842};
 843
 844static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = {
 845	.name = "slv_qhs_ahb2phy_refgen_west",
 846	.channels = 1,
 847	.buswidth = 4
 848};
 849
 850static struct qcom_icc_node slv_qhs_ahb2phy_south = {
 851	.name = "slv_qhs_ahb2phy_south",
 852	.channels = 1,
 853	.buswidth = 4
 854};
 855
 856static struct qcom_icc_node slv_qhs_aop = {
 857	.name = "slv_qhs_aop",
 858	.channels = 1,
 859	.buswidth = 4
 860};
 861
 862static struct qcom_icc_node slv_qhs_aoss = {
 863	.name = "slv_qhs_aoss",
 864	.channels = 1,
 865	.buswidth = 4
 866};
 867
 868static struct qcom_icc_node slv_qhs_camera_cfg = {
 869	.name = "slv_qhs_camera_cfg",
 870	.channels = 1,
 871	.buswidth = 4
 872};
 873
 874static struct qcom_icc_node slv_qhs_clk_ctl = {
 875	.name = "slv_qhs_clk_ctl",
 876	.channels = 1,
 877	.buswidth = 4
 878};
 879
 880static struct qcom_icc_node slv_qhs_compute_dsp = {
 881	.name = "slv_qhs_compute_dsp",
 882	.channels = 1,
 883	.buswidth = 4
 884};
 885
 886static struct qcom_icc_node slv_qhs_cpr_cx = {
 887	.name = "slv_qhs_cpr_cx",
 888	.channels = 1,
 889	.buswidth = 4
 890};
 891
 892static struct qcom_icc_node slv_qhs_cpr_mmcx = {
 893	.name = "slv_qhs_cpr_mmcx",
 894	.channels = 1,
 895	.buswidth = 4
 896};
 897
 898static struct qcom_icc_node slv_qhs_cpr_mx = {
 899	.name = "slv_qhs_cpr_mx",
 900	.channels = 1,
 901	.buswidth = 4
 902};
 903
 904static struct qcom_icc_node slv_qhs_crypto0_cfg = {
 905	.name = "slv_qhs_crypto0_cfg",
 906	.channels = 1,
 907	.buswidth = 4
 908};
 909
 910static struct qcom_icc_node slv_qhs_ddrss_cfg = {
 911	.name = "slv_qhs_ddrss_cfg",
 912	.channels = 1,
 913	.buswidth = 4,
 914	.num_links = 1,
 915	.link_nodes = { &mas_qhm_cnoc_dc_noc },
 916};
 917
 918static struct qcom_icc_node slv_qhs_display_cfg = {
 919	.name = "slv_qhs_display_cfg",
 920	.channels = 1,
 921	.buswidth = 4
 922};
 923
 924static struct qcom_icc_node slv_qhs_emac_cfg = {
 925	.name = "slv_qhs_emac_cfg",
 926	.channels = 1,
 927	.buswidth = 4
 928};
 929
 930static struct qcom_icc_node slv_qhs_glm = {
 931	.name = "slv_qhs_glm",
 932	.channels = 1,
 933	.buswidth = 4
 934};
 935
 936static struct qcom_icc_node slv_qhs_gpuss_cfg = {
 937	.name = "slv_qhs_gpuss_cfg",
 938	.channels = 1,
 939	.buswidth = 8
 940};
 941
 942static struct qcom_icc_node slv_qhs_imem_cfg = {
 943	.name = "slv_qhs_imem_cfg",
 944	.channels = 1,
 945	.buswidth = 4
 946};
 947
 948static struct qcom_icc_node slv_qhs_ipa = {
 949	.name = "slv_qhs_ipa",
 950	.channels = 1,
 951	.buswidth = 4
 952};
 953
 954static struct qcom_icc_node slv_qhs_mnoc_cfg = {
 955	.name = "slv_qhs_mnoc_cfg",
 956	.channels = 1,
 957	.buswidth = 4,
 958	.num_links = 1,
 959	.link_nodes = { &mas_qhm_mnoc_cfg },
 960};
 961
 962static struct qcom_icc_node slv_qhs_npu_cfg = {
 963	.name = "slv_qhs_npu_cfg",
 964	.channels = 1,
 965	.buswidth = 4
 966};
 967
 968static struct qcom_icc_node slv_qhs_pcie0_cfg = {
 969	.name = "slv_qhs_pcie0_cfg",
 970	.channels = 1,
 971	.buswidth = 4
 972};
 973
 974static struct qcom_icc_node slv_qhs_pcie1_cfg = {
 975	.name = "slv_qhs_pcie1_cfg",
 976	.channels = 1,
 977	.buswidth = 4
 978};
 979
 980static struct qcom_icc_node slv_qhs_pcie2_cfg = {
 981	.name = "slv_qhs_pcie2_cfg",
 982	.channels = 1,
 983	.buswidth = 4
 984};
 985
 986static struct qcom_icc_node slv_qhs_pcie3_cfg = {
 987	.name = "slv_qhs_pcie3_cfg",
 988	.channels = 1,
 989	.buswidth = 4
 990};
 991
 992static struct qcom_icc_node slv_qhs_pdm = {
 993	.name = "slv_qhs_pdm",
 994	.channels = 1,
 995	.buswidth = 4
 996};
 997
 998static struct qcom_icc_node slv_qhs_pimem_cfg = {
 999	.name = "slv_qhs_pimem_cfg",
1000	.channels = 1,
1001	.buswidth = 4
1002};
1003
1004static struct qcom_icc_node slv_qhs_prng = {
1005	.name = "slv_qhs_prng",
1006	.channels = 1,
1007	.buswidth = 4
1008};
1009
1010static struct qcom_icc_node slv_qhs_qdss_cfg = {
1011	.name = "slv_qhs_qdss_cfg",
1012	.channels = 1,
1013	.buswidth = 4
1014};
1015
1016static struct qcom_icc_node slv_qhs_qspi_0 = {
1017	.name = "slv_qhs_qspi_0",
1018	.channels = 1,
1019	.buswidth = 4
1020};
1021
1022static struct qcom_icc_node slv_qhs_qspi_1 = {
1023	.name = "slv_qhs_qspi_1",
1024	.channels = 1,
1025	.buswidth = 4
1026};
1027
1028static struct qcom_icc_node slv_qhs_qupv3_east0 = {
1029	.name = "slv_qhs_qupv3_east0",
1030	.channels = 1,
1031	.buswidth = 4
1032};
1033
1034static struct qcom_icc_node slv_qhs_qupv3_east1 = {
1035	.name = "slv_qhs_qupv3_east1",
1036	.channels = 1,
1037	.buswidth = 4
1038};
1039
1040static struct qcom_icc_node slv_qhs_qupv3_west = {
1041	.name = "slv_qhs_qupv3_west",
1042	.channels = 1,
1043	.buswidth = 4
1044};
1045
1046static struct qcom_icc_node slv_qhs_sdc2 = {
1047	.name = "slv_qhs_sdc2",
1048	.channels = 1,
1049	.buswidth = 4
1050};
1051
1052static struct qcom_icc_node slv_qhs_sdc4 = {
1053	.name = "slv_qhs_sdc4",
1054	.channels = 1,
1055	.buswidth = 4
1056};
1057
1058static struct qcom_icc_node slv_qhs_security = {
1059	.name = "slv_qhs_security",
1060	.channels = 1,
1061	.buswidth = 4
1062};
1063
1064static struct qcom_icc_node slv_qhs_snoc_cfg = {
1065	.name = "slv_qhs_snoc_cfg",
1066	.channels = 1,
1067	.buswidth = 4,
1068	.num_links = 1,
1069	.link_nodes = { &mas_qhm_snoc_cfg },
1070};
1071
1072static struct qcom_icc_node slv_qhs_spss_cfg = {
1073	.name = "slv_qhs_spss_cfg",
1074	.channels = 1,
1075	.buswidth = 4
1076};
1077
1078static struct qcom_icc_node slv_qhs_tcsr = {
1079	.name = "slv_qhs_tcsr",
1080	.channels = 1,
1081	.buswidth = 4
1082};
1083
1084static struct qcom_icc_node slv_qhs_tlmm_east = {
1085	.name = "slv_qhs_tlmm_east",
1086	.channels = 1,
1087	.buswidth = 4
1088};
1089
1090static struct qcom_icc_node slv_qhs_tlmm_south = {
1091	.name = "slv_qhs_tlmm_south",
1092	.channels = 1,
1093	.buswidth = 4
1094};
1095
1096static struct qcom_icc_node slv_qhs_tlmm_west = {
1097	.name = "slv_qhs_tlmm_west",
1098	.channels = 1,
1099	.buswidth = 4
1100};
1101
1102static struct qcom_icc_node slv_qhs_tsif = {
1103	.name = "slv_qhs_tsif",
1104	.channels = 1,
1105	.buswidth = 4
1106};
1107
1108static struct qcom_icc_node slv_qhs_ufs_card_cfg = {
1109	.name = "slv_qhs_ufs_card_cfg",
1110	.channels = 1,
1111	.buswidth = 4
1112};
1113
1114static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = {
1115	.name = "slv_qhs_ufs_mem0_cfg",
1116	.channels = 1,
1117	.buswidth = 4
1118};
1119
1120static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = {
1121	.name = "slv_qhs_ufs_mem1_cfg",
1122	.channels = 1,
1123	.buswidth = 4
1124};
1125
1126static struct qcom_icc_node slv_qhs_usb3_0 = {
1127	.name = "slv_qhs_usb3_0",
1128	.channels = 1,
1129	.buswidth = 4
1130};
1131
1132static struct qcom_icc_node slv_qhs_usb3_1 = {
1133	.name = "slv_qhs_usb3_1",
1134	.channels = 1,
1135	.buswidth = 4
1136};
1137
1138static struct qcom_icc_node slv_qhs_usb3_2 = {
1139	.name = "slv_qhs_usb3_2",
1140	.channels = 1,
1141	.buswidth = 4
1142};
1143
1144static struct qcom_icc_node slv_qhs_venus_cfg = {
1145	.name = "slv_qhs_venus_cfg",
1146	.channels = 1,
1147	.buswidth = 4
1148};
1149
1150static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = {
1151	.name = "slv_qhs_vsense_ctrl_cfg",
1152	.channels = 1,
1153	.buswidth = 4
1154};
1155
1156static struct qcom_icc_node slv_srvc_cnoc = {
1157	.name = "slv_srvc_cnoc",
1158	.channels = 1,
1159	.buswidth = 4
1160};
1161
1162static struct qcom_icc_node slv_qhs_gemnoc = {
1163	.name = "slv_qhs_gemnoc",
1164	.channels = 1,
1165	.buswidth = 4,
1166	.num_links = 1,
1167	.link_nodes = { &mas_qhm_gemnoc_cfg },
1168};
1169
1170static struct qcom_icc_node slv_qhs_llcc = {
1171	.name = "slv_qhs_llcc",
1172	.channels = 1,
1173	.buswidth = 4
1174};
1175
1176static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = {
1177	.name = "slv_qhs_mdsp_ms_mpu_cfg",
1178	.channels = 1,
1179	.buswidth = 4
1180};
1181
1182static struct qcom_icc_node slv_qns_ecc = {
1183	.name = "slv_qns_ecc",
1184	.channels = 1,
1185	.buswidth = 32
1186};
1187
1188static struct qcom_icc_node slv_qns_gem_noc_snoc = {
1189	.name = "slv_qns_gem_noc_snoc",
1190	.channels = 1,
1191	.buswidth = 8,
1192	.num_links = 1,
1193	.link_nodes = { &mas_qnm_gemnoc },
1194};
1195
1196static struct qcom_icc_node slv_qns_llcc = {
1197	.name = "slv_qns_llcc",
1198	.channels = 8,
1199	.buswidth = 16,
1200	.num_links = 1,
1201	.link_nodes = { &mas_llcc_mc },
1202};
1203
1204static struct qcom_icc_node slv_srvc_gemnoc = {
1205	.name = "slv_srvc_gemnoc",
1206	.channels = 1,
1207	.buswidth = 4
1208};
1209
1210static struct qcom_icc_node slv_srvc_gemnoc1 = {
1211	.name = "slv_srvc_gemnoc1",
1212	.channels = 1,
1213	.buswidth = 4
1214};
1215
1216static struct qcom_icc_node slv_ebi = {
1217	.name = "slv_ebi",
1218	.channels = 8,
1219	.buswidth = 4
1220};
1221
1222static struct qcom_icc_node slv_qns2_mem_noc = {
1223	.name = "slv_qns2_mem_noc",
1224	.channels = 1,
1225	.buswidth = 32,
1226	.num_links = 1,
1227	.link_nodes = { &mas_qnm_mnoc_sf },
1228};
1229
1230static struct qcom_icc_node slv_qns_mem_noc_hf = {
1231	.name = "slv_qns_mem_noc_hf",
1232	.channels = 2,
1233	.buswidth = 32,
1234	.num_links = 1,
1235	.link_nodes = { &mas_qnm_mnoc_hf },
1236};
1237
1238static struct qcom_icc_node slv_srvc_mnoc = {
1239	.name = "slv_srvc_mnoc",
1240	.channels = 1,
1241	.buswidth = 4
1242};
1243
1244static struct qcom_icc_node slv_qhs_apss = {
1245	.name = "slv_qhs_apss",
1246	.channels = 1,
1247	.buswidth = 8
1248};
1249
1250static struct qcom_icc_node slv_qns_cnoc = {
1251	.name = "slv_qns_cnoc",
1252	.channels = 1,
1253	.buswidth = 8,
1254	.num_links = 1,
1255	.link_nodes = { &mas_qnm_snoc },
1256};
1257
1258static struct qcom_icc_node slv_qns_gemnoc_gc = {
1259	.name = "slv_qns_gemnoc_gc",
1260	.channels = 1,
1261	.buswidth = 8,
1262	.num_links = 1,
1263	.link_nodes = { &mas_qnm_snoc_gc },
1264};
1265
1266static struct qcom_icc_node slv_qns_gemnoc_sf = {
1267	.name = "slv_qns_gemnoc_sf",
1268	.channels = 1,
1269	.buswidth = 32,
1270	.num_links = 1,
1271	.link_nodes = { &mas_qnm_snoc_sf },
1272};
1273
1274static struct qcom_icc_node slv_qxs_imem = {
1275	.name = "slv_qxs_imem",
1276	.channels = 1,
1277	.buswidth = 8
1278};
1279
1280static struct qcom_icc_node slv_qxs_pimem = {
1281	.name = "slv_qxs_pimem",
1282	.channels = 1,
1283	.buswidth = 8
1284};
1285
1286static struct qcom_icc_node slv_srvc_snoc = {
1287	.name = "slv_srvc_snoc",
1288	.channels = 1,
1289	.buswidth = 4
1290};
1291
1292static struct qcom_icc_node slv_xs_pcie_0 = {
1293	.name = "slv_xs_pcie_0",
1294	.channels = 1,
1295	.buswidth = 8
1296};
1297
1298static struct qcom_icc_node slv_xs_pcie_1 = {
1299	.name = "slv_xs_pcie_1",
1300	.channels = 1,
1301	.buswidth = 8
1302};
1303
1304static struct qcom_icc_node slv_xs_pcie_2 = {
1305	.name = "slv_xs_pcie_2",
1306	.channels = 1,
1307	.buswidth = 8
1308};
1309
1310static struct qcom_icc_node slv_xs_pcie_3 = {
1311	.name = "slv_xs_pcie_3",
1312	.channels = 1,
1313	.buswidth = 8
1314};
1315
1316static struct qcom_icc_node slv_xs_qdss_stm = {
1317	.name = "slv_xs_qdss_stm",
1318	.channels = 1,
1319	.buswidth = 4
1320};
1321
1322static struct qcom_icc_node slv_xs_sys_tcu_cfg = {
1323	.name = "slv_xs_sys_tcu_cfg",
1324	.channels = 1,
1325	.buswidth = 8
1326};
1327
1328static struct qcom_icc_node slv_qup_core_0 = {
1329	.name = "slv_qup_core_0",
1330	.channels = 1,
1331	.buswidth = 4
1332};
1333
1334static struct qcom_icc_node slv_qup_core_1 = {
1335	.name = "slv_qup_core_1",
1336	.channels = 1,
1337	.buswidth = 4
1338};
1339
1340static struct qcom_icc_node slv_qup_core_2 = {
1341	.name = "slv_qup_core_2",
1342	.channels = 1,
1343	.buswidth = 4
1344};
1345
1346static struct qcom_icc_bcm bcm_acv = {
1347	.name = "ACV",
1348	.enable_mask = BIT(3),
1349	.num_nodes = 1,
1350	.nodes = { &slv_ebi }
1351};
1352
1353static struct qcom_icc_bcm bcm_mc0 = {
1354	.name = "MC0",
1355	.keepalive = true,
1356	.num_nodes = 1,
1357	.nodes = { &slv_ebi }
1358};
1359
1360static struct qcom_icc_bcm bcm_sh0 = {
1361	.name = "SH0",
1362	.keepalive = true,
1363	.num_nodes = 1,
1364	.nodes = { &slv_qns_llcc }
1365};
1366
1367static struct qcom_icc_bcm bcm_mm0 = {
1368	.name = "MM0",
1369	.num_nodes = 1,
1370	.nodes = { &slv_qns_mem_noc_hf }
1371};
1372
1373static struct qcom_icc_bcm bcm_co0 = {
1374	.name = "CO0",
1375	.keepalive = true,
1376	.num_nodes = 1,
1377	.nodes = { &slv_qns_cdsp_mem_noc }
1378};
1379
1380static struct qcom_icc_bcm bcm_ce0 = {
1381	.name = "CE0",
1382	.num_nodes = 1,
1383	.nodes = { &mas_qxm_crypto }
1384};
1385
1386static struct qcom_icc_bcm bcm_cn0 = {
1387	.name = "CN0",
1388	.keepalive = true,
1389	.num_nodes = 57,
1390	.nodes = { &mas_qnm_snoc,
1391		   &slv_qhs_a1_noc_cfg,
1392		   &slv_qhs_a2_noc_cfg,
1393		   &slv_qhs_ahb2phy_refgen_center,
1394		   &slv_qhs_ahb2phy_refgen_east,
1395		   &slv_qhs_ahb2phy_refgen_west,
1396		   &slv_qhs_ahb2phy_south,
1397		   &slv_qhs_aop,
1398		   &slv_qhs_aoss,
1399		   &slv_qhs_camera_cfg,
1400		   &slv_qhs_clk_ctl,
1401		   &slv_qhs_compute_dsp,
1402		   &slv_qhs_cpr_cx,
1403		   &slv_qhs_cpr_mmcx,
1404		   &slv_qhs_cpr_mx,
1405		   &slv_qhs_crypto0_cfg,
1406		   &slv_qhs_ddrss_cfg,
1407		   &slv_qhs_display_cfg,
1408		   &slv_qhs_emac_cfg,
1409		   &slv_qhs_glm,
1410		   &slv_qhs_gpuss_cfg,
1411		   &slv_qhs_imem_cfg,
1412		   &slv_qhs_ipa,
1413		   &slv_qhs_mnoc_cfg,
1414		   &slv_qhs_npu_cfg,
1415		   &slv_qhs_pcie0_cfg,
1416		   &slv_qhs_pcie1_cfg,
1417		   &slv_qhs_pcie2_cfg,
1418		   &slv_qhs_pcie3_cfg,
1419		   &slv_qhs_pdm,
1420		   &slv_qhs_pimem_cfg,
1421		   &slv_qhs_prng,
1422		   &slv_qhs_qdss_cfg,
1423		   &slv_qhs_qspi_0,
1424		   &slv_qhs_qspi_1,
1425		   &slv_qhs_qupv3_east0,
1426		   &slv_qhs_qupv3_east1,
1427		   &slv_qhs_qupv3_west,
1428		   &slv_qhs_sdc2,
1429		   &slv_qhs_sdc4,
1430		   &slv_qhs_security,
1431		   &slv_qhs_snoc_cfg,
1432		   &slv_qhs_spss_cfg,
1433		   &slv_qhs_tcsr,
1434		   &slv_qhs_tlmm_east,
1435		   &slv_qhs_tlmm_south,
1436		   &slv_qhs_tlmm_west,
1437		   &slv_qhs_tsif,
1438		   &slv_qhs_ufs_card_cfg,
1439		   &slv_qhs_ufs_mem0_cfg,
1440		   &slv_qhs_ufs_mem1_cfg,
1441		   &slv_qhs_usb3_0,
1442		   &slv_qhs_usb3_1,
1443		   &slv_qhs_usb3_2,
1444		   &slv_qhs_venus_cfg,
1445		   &slv_qhs_vsense_ctrl_cfg,
1446		   &slv_srvc_cnoc }
1447};
1448
1449static struct qcom_icc_bcm bcm_mm1 = {
1450	.name = "MM1",
1451	.num_nodes = 7,
1452	.nodes = { &mas_qxm_camnoc_hf0_uncomp,
1453		   &mas_qxm_camnoc_hf1_uncomp,
1454		   &mas_qxm_camnoc_sf_uncomp,
1455		   &mas_qxm_camnoc_hf0,
1456		   &mas_qxm_camnoc_hf1,
1457		   &mas_qxm_mdp0,
1458		   &mas_qxm_mdp1 }
1459};
1460
1461static struct qcom_icc_bcm bcm_qup0 = {
1462	.name = "QUP0",
1463	.num_nodes = 3,
1464	.nodes = { &mas_qup_core_0,
1465		   &mas_qup_core_1,
1466		   &mas_qup_core_2 }
1467};
1468
1469static struct qcom_icc_bcm bcm_sh2 = {
1470	.name = "SH2",
1471	.num_nodes = 1,
1472	.nodes = { &slv_qns_gem_noc_snoc }
1473};
1474
1475static struct qcom_icc_bcm bcm_mm2 = {
1476	.name = "MM2",
1477	.num_nodes = 6,
1478	.nodes = { &mas_qxm_camnoc_sf,
1479		   &mas_qxm_rot,
1480		   &mas_qxm_venus0,
1481		   &mas_qxm_venus1,
1482		   &mas_qxm_venus_arm9,
1483		   &slv_qns2_mem_noc }
1484};
1485
1486static struct qcom_icc_bcm bcm_sh3 = {
1487	.name = "SH3",
1488	.keepalive = true,
1489	.num_nodes = 1,
1490	.nodes = { &mas_acm_apps }
1491};
1492
1493static struct qcom_icc_bcm bcm_sn0 = {
1494	.name = "SN0",
1495	.num_nodes = 1,
1496	.nodes = { &slv_qns_gemnoc_sf }
1497};
1498
1499static struct qcom_icc_bcm bcm_sn1 = {
1500	.name = "SN1",
1501	.num_nodes = 1,
1502	.nodes = { &slv_qxs_imem }
1503};
1504
1505static struct qcom_icc_bcm bcm_sn2 = {
1506	.name = "SN2",
1507	.keepalive = true,
1508	.num_nodes = 1,
1509	.nodes = { &slv_qns_gemnoc_gc }
1510};
1511
1512static struct qcom_icc_bcm bcm_co2 = {
1513	.name = "CO2",
1514	.num_nodes = 1,
1515	.nodes = { &mas_qnm_npu }
1516};
1517
1518static struct qcom_icc_bcm bcm_sn3 = {
1519	.name = "SN3",
1520	.keepalive = true,
1521	.num_nodes = 2,
1522	.nodes = { &slv_srvc_aggre1_noc,
1523		  &slv_qns_cnoc }
1524};
1525
1526static struct qcom_icc_bcm bcm_sn4 = {
1527	.name = "SN4",
1528	.num_nodes = 1,
1529	.nodes = { &slv_qxs_pimem }
1530};
1531
1532static struct qcom_icc_bcm bcm_sn8 = {
1533	.name = "SN8",
1534	.num_nodes = 4,
1535	.nodes = { &slv_xs_pcie_0,
1536		   &slv_xs_pcie_1,
1537		   &slv_xs_pcie_2,
1538		   &slv_xs_pcie_3 }
1539};
1540
1541static struct qcom_icc_bcm bcm_sn9 = {
1542	.name = "SN9",
1543	.num_nodes = 1,
1544	.nodes = { &mas_qnm_aggre1_noc }
1545};
1546
1547static struct qcom_icc_bcm bcm_sn11 = {
1548	.name = "SN11",
1549	.num_nodes = 1,
1550	.nodes = { &mas_qnm_aggre2_noc }
1551};
1552
1553static struct qcom_icc_bcm bcm_sn14 = {
1554	.name = "SN14",
1555	.num_nodes = 1,
1556	.nodes = { &slv_qns_pcie_mem_noc }
1557};
1558
1559static struct qcom_icc_bcm bcm_sn15 = {
1560	.name = "SN15",
1561	.keepalive = true,
1562	.num_nodes = 1,
1563	.nodes = { &mas_qnm_gemnoc }
1564};
1565
1566static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1567	&bcm_sn3,
1568	&bcm_ce0,
1569};
1570
1571static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1572	&bcm_sn14,
1573	&bcm_ce0,
1574};
1575
1576static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1577	&bcm_mm1,
1578};
1579
1580static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1581	&bcm_co0,
1582	&bcm_co2,
1583};
1584
1585static struct qcom_icc_bcm * const config_noc_bcms[] = {
1586	&bcm_cn0,
1587};
1588
1589static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1590	&bcm_sh0,
1591	&bcm_sh2,
1592	&bcm_sh3,
1593};
1594
1595static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1596	&bcm_mc0,
1597	&bcm_acv,
1598};
1599
1600static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1601	&bcm_mm0,
1602	&bcm_mm1,
1603	&bcm_mm2,
1604};
1605
1606static struct qcom_icc_bcm * const system_noc_bcms[] = {
1607	&bcm_sn0,
1608	&bcm_sn1,
1609	&bcm_sn2,
1610	&bcm_sn3,
1611	&bcm_sn4,
1612	&bcm_sn8,
1613	&bcm_sn9,
1614	&bcm_sn11,
1615	&bcm_sn15,
1616};
1617
1618static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1619	[MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg,
1620	[MASTER_UFS_CARD] = &mas_xm_ufs_card,
1621	[MASTER_UFS_GEN4] = &mas_xm_ufs_g4,
1622	[MASTER_UFS_MEM] = &mas_xm_ufs_mem,
1623	[MASTER_USB3] = &mas_xm_usb3_0,
1624	[MASTER_USB3_1] = &mas_xm_usb3_1,
1625	[MASTER_USB3_2] = &mas_xm_usb3_2,
1626	[A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc,
1627	[SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc,
1628};
1629
1630static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1631	[MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg,
1632	[MASTER_QDSS_BAM] = &mas_qhm_qdss_bam,
1633	[MASTER_QSPI_0] = &mas_qhm_qspi,
1634	[MASTER_QSPI_1] = &mas_qhm_qspi1,
1635	[MASTER_QUP_0] = &mas_qhm_qup0,
1636	[MASTER_QUP_1] = &mas_qhm_qup1,
1637	[MASTER_QUP_2] = &mas_qhm_qup2,
1638	[MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb,
1639	[MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto,
1640	[MASTER_IPA] = &mas_qxm_ipa,
1641	[MASTER_EMAC] = &mas_xm_emac,
1642	[MASTER_PCIE] = &mas_xm_pcie3_0,
1643	[MASTER_PCIE_1] = &mas_xm_pcie3_1,
1644	[MASTER_PCIE_2] = &mas_xm_pcie3_2,
1645	[MASTER_PCIE_3] = &mas_xm_pcie3_3,
1646	[MASTER_QDSS_ETR] = &mas_xm_qdss_etr,
1647	[MASTER_SDCC_2] = &mas_xm_sdc2,
1648	[MASTER_SDCC_4] = &mas_xm_sdc4,
1649	[A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc,
1650	[SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc,
1651	[SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc,
1652};
1653
1654static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1655	[MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp,
1656	[MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp,
1657	[MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp,
1658	[SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp,
1659};
1660
1661static struct qcom_icc_node * const compute_noc_nodes[] = {
1662	[MASTER_NPU] = &mas_qnm_npu,
1663	[SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc,
1664};
1665
1666static struct qcom_icc_node * const config_noc_nodes[] = {
1667	[SNOC_CNOC_MAS] = &mas_qnm_snoc,
1668	[SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg,
1669	[SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg,
1670	[SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center,
1671	[SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east,
1672	[SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west,
1673	[SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south,
1674	[SLAVE_AOP] = &slv_qhs_aop,
1675	[SLAVE_AOSS] = &slv_qhs_aoss,
1676	[SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg,
1677	[SLAVE_CLK_CTL] = &slv_qhs_clk_ctl,
1678	[SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp,
1679	[SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx,
1680	[SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx,
1681	[SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx,
1682	[SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg,
1683	[SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg,
1684	[SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg,
1685	[SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg,
1686	[SLAVE_GLM] = &slv_qhs_glm,
1687	[SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg,
1688	[SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg,
1689	[SLAVE_IPA_CFG] = &slv_qhs_ipa,
1690	[SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg,
1691	[SLAVE_NPU_CFG] = &slv_qhs_npu_cfg,
1692	[SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg,
1693	[SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg,
1694	[SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg,
1695	[SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg,
1696	[SLAVE_PDM] = &slv_qhs_pdm,
1697	[SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg,
1698	[SLAVE_PRNG] = &slv_qhs_prng,
1699	[SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg,
1700	[SLAVE_QSPI_0] = &slv_qhs_qspi_0,
1701	[SLAVE_QSPI_1] = &slv_qhs_qspi_1,
1702	[SLAVE_QUP_1] = &slv_qhs_qupv3_east0,
1703	[SLAVE_QUP_2] = &slv_qhs_qupv3_east1,
1704	[SLAVE_QUP_0] = &slv_qhs_qupv3_west,
1705	[SLAVE_SDCC_2] = &slv_qhs_sdc2,
1706	[SLAVE_SDCC_4] = &slv_qhs_sdc4,
1707	[SLAVE_SECURITY] = &slv_qhs_security,
1708	[SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg,
1709	[SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg,
1710	[SLAVE_TCSR] = &slv_qhs_tcsr,
1711	[SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east,
1712	[SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south,
1713	[SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west,
1714	[SLAVE_TSIF] = &slv_qhs_tsif,
1715	[SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg,
1716	[SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg,
1717	[SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg,
1718	[SLAVE_USB3] = &slv_qhs_usb3_0,
1719	[SLAVE_USB3_1] = &slv_qhs_usb3_1,
1720	[SLAVE_USB3_2] = &slv_qhs_usb3_2,
1721	[SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg,
1722	[SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg,
1723	[SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc,
1724};
1725
1726static struct qcom_icc_node * const dc_noc_nodes[] = {
1727	[MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc,
1728	[SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc,
1729	[SLAVE_LLCC_CFG] = &slv_qhs_llcc,
1730};
1731
1732static struct qcom_icc_node * const gem_noc_nodes[] = {
1733	[MASTER_AMPSS_M0] = &mas_acm_apps,
1734	[MASTER_GPU_TCU] = &mas_acm_gpu_tcu,
1735	[MASTER_SYS_TCU] = &mas_acm_sys_tcu,
1736	[MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg,
1737	[MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc,
1738	[MASTER_GRAPHICS_3D] = &mas_qnm_gpu,
1739	[MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf,
1740	[MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf,
1741	[MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie,
1742	[MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc,
1743	[MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf,
1744	[MASTER_ECC] = &mas_qxm_ecc,
1745	[SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg,
1746	[SLAVE_ECC] = &slv_qns_ecc,
1747	[SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc,
1748	[SLAVE_LLCC] = &slv_qns_llcc,
1749	[SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc,
1750	[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
1751};
1752
1753static struct qcom_icc_node * const mc_virt_nodes[] = {
1754	[MASTER_LLCC] = &mas_llcc_mc,
1755	[SLAVE_EBI_CH0] = &slv_ebi,
1756};
1757
1758static struct qcom_icc_node * const mmss_noc_nodes[] = {
1759	[MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg,
1760	[MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0,
1761	[MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1,
1762	[MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf,
1763	[MASTER_MDP_PORT0] = &mas_qxm_mdp0,
1764	[MASTER_MDP_PORT1] = &mas_qxm_mdp1,
1765	[MASTER_ROTATOR] = &mas_qxm_rot,
1766	[MASTER_VIDEO_P0] = &mas_qxm_venus0,
1767	[MASTER_VIDEO_P1] = &mas_qxm_venus1,
1768	[MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9,
1769	[SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc,
1770	[SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf,
1771	[SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1772};
1773
1774static struct qcom_icc_node * const system_noc_nodes[] = {
1775	[MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg,
1776	[A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc,
1777	[A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc,
1778	[MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc,
1779	[MASTER_PIMEM] = &mas_qxm_pimem,
1780	[MASTER_GIC] = &mas_xm_gic,
1781	[SLAVE_APPSS] = &slv_qhs_apss,
1782	[SNOC_CNOC_SLV] = &slv_qns_cnoc,
1783	[SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc,
1784	[SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf,
1785	[SLAVE_OCIMEM] = &slv_qxs_imem,
1786	[SLAVE_PIMEM] = &slv_qxs_pimem,
1787	[SLAVE_SERVICE_SNOC] = &slv_srvc_snoc,
1788	[SLAVE_QDSS_STM] = &slv_xs_qdss_stm,
1789	[SLAVE_TCU] = &slv_xs_sys_tcu_cfg,
1790};
1791
1792static const struct qcom_icc_desc sc8180x_aggre1_noc = {
1793	.nodes = aggre1_noc_nodes,
1794	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1795	.bcms = aggre1_noc_bcms,
1796	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1797};
1798
1799static const struct qcom_icc_desc sc8180x_aggre2_noc = {
1800	.nodes = aggre2_noc_nodes,
1801	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1802	.bcms = aggre2_noc_bcms,
1803	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1804};
1805
1806static const struct qcom_icc_desc sc8180x_camnoc_virt = {
1807	.nodes = camnoc_virt_nodes,
1808	.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1809	.bcms = camnoc_virt_bcms,
1810	.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1811};
1812
1813static const struct qcom_icc_desc sc8180x_compute_noc = {
1814	.nodes = compute_noc_nodes,
1815	.num_nodes = ARRAY_SIZE(compute_noc_nodes),
1816	.bcms = compute_noc_bcms,
1817	.num_bcms = ARRAY_SIZE(compute_noc_bcms),
1818};
1819
1820static const struct qcom_icc_desc sc8180x_config_noc = {
1821	.nodes = config_noc_nodes,
1822	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1823	.bcms = config_noc_bcms,
1824	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1825};
1826
1827static const struct qcom_icc_desc sc8180x_dc_noc = {
1828	.nodes = dc_noc_nodes,
1829	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1830};
1831
1832static const struct qcom_icc_desc sc8180x_gem_noc  = {
1833	.nodes = gem_noc_nodes,
1834	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1835	.bcms = gem_noc_bcms,
1836	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1837};
1838
1839static const struct qcom_icc_desc sc8180x_mc_virt  = {
1840	.nodes = mc_virt_nodes,
1841	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1842	.bcms = mc_virt_bcms,
1843	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1844};
1845
1846static const struct qcom_icc_desc sc8180x_mmss_noc  = {
1847	.nodes = mmss_noc_nodes,
1848	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1849	.bcms = mmss_noc_bcms,
1850	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1851};
1852
1853static const struct qcom_icc_desc sc8180x_system_noc  = {
1854	.nodes = system_noc_nodes,
1855	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1856	.bcms = system_noc_bcms,
1857	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1858};
1859
1860static struct qcom_icc_bcm * const qup_virt_bcms[] = {
1861	&bcm_qup0,
1862};
1863
1864static struct qcom_icc_node * const qup_virt_nodes[] = {
1865	[MASTER_QUP_CORE_0] = &mas_qup_core_0,
1866	[MASTER_QUP_CORE_1] = &mas_qup_core_1,
1867	[MASTER_QUP_CORE_2] = &mas_qup_core_2,
1868	[SLAVE_QUP_CORE_0] = &slv_qup_core_0,
1869	[SLAVE_QUP_CORE_1] = &slv_qup_core_1,
1870	[SLAVE_QUP_CORE_2] = &slv_qup_core_2,
1871};
1872
1873static const struct qcom_icc_desc sc8180x_qup_virt = {
1874	.nodes = qup_virt_nodes,
1875	.num_nodes = ARRAY_SIZE(qup_virt_nodes),
1876	.bcms = qup_virt_bcms,
1877	.num_bcms = ARRAY_SIZE(qup_virt_bcms),
1878};
1879
1880static const struct of_device_id qnoc_of_match[] = {
1881	{ .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc },
1882	{ .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc },
1883	{ .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt },
1884	{ .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, },
1885	{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
1886	{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
1887	{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
1888	{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
1889	{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
1890	{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
1891	{ .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc },
1892	{ }
1893};
1894MODULE_DEVICE_TABLE(of, qnoc_of_match);
1895
1896static struct platform_driver qnoc_driver = {
1897	.probe = qcom_icc_rpmh_probe,
1898	.remove = qcom_icc_rpmh_remove,
1899	.driver = {
1900		.name = "qnoc-sc8180x",
1901		.of_match_table = qnoc_of_match,
1902		.sync_state = icc_sync_state,
1903	},
1904};
1905module_platform_driver(qnoc_driver);
1906
1907MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver");
1908MODULE_LICENSE("GPL v2");