sa8775p.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
   4 * Copyright (c) 2023, Linaro Limited
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
  14
  15#include "bcm-voter.h"
  16#include "icc-rpmh.h"
  17
  18static struct qcom_icc_node qxm_qup3;
  19static struct qcom_icc_node xm_emac_0;
  20static struct qcom_icc_node xm_emac_1;
  21static struct qcom_icc_node xm_sdc1;
  22static struct qcom_icc_node xm_ufs_mem;
  23static struct qcom_icc_node xm_usb2_2;
  24static struct qcom_icc_node xm_usb3_0;
  25static struct qcom_icc_node xm_usb3_1;
  26static struct qcom_icc_node qns_a1noc_snoc;
  27static struct qcom_icc_node qhm_qdss_bam;
  28static struct qcom_icc_node qhm_qup0;
  29static struct qcom_icc_node qhm_qup1;
  30static struct qcom_icc_node qhm_qup2;
  31static struct qcom_icc_node qnm_cnoc_datapath;
  32static struct qcom_icc_node qxm_crypto_0;
  33static struct qcom_icc_node qxm_crypto_1;
  34static struct qcom_icc_node qxm_ipa;
  35static struct qcom_icc_node xm_qdss_etr_0;
  36static struct qcom_icc_node xm_qdss_etr_1;
  37static struct qcom_icc_node xm_ufs_card;
  38static struct qcom_icc_node qns_a2noc_snoc;
  39static struct qcom_icc_node qup0_core_master;
  40static struct qcom_icc_node qup1_core_master;
  41static struct qcom_icc_node qup2_core_master;
  42static struct qcom_icc_node qup3_core_master;
  43static struct qcom_icc_node qup0_core_slave;
  44static struct qcom_icc_node qup1_core_slave;
  45static struct qcom_icc_node qup2_core_slave;
  46static struct qcom_icc_node qup3_core_slave;
  47static struct qcom_icc_node qnm_gemnoc_cnoc;
  48static struct qcom_icc_node qnm_gemnoc_pcie;
  49static struct qcom_icc_node qhs_ahb2phy0;
  50static struct qcom_icc_node qhs_ahb2phy1;
  51static struct qcom_icc_node qhs_ahb2phy2;
  52static struct qcom_icc_node qhs_ahb2phy3;
  53static struct qcom_icc_node qhs_anoc_throttle_cfg;
  54static struct qcom_icc_node qhs_aoss;
  55static struct qcom_icc_node qhs_apss;
  56static struct qcom_icc_node qhs_boot_rom;
  57static struct qcom_icc_node qhs_camera_cfg;
  58static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
  59static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
  60static struct qcom_icc_node qhs_clk_ctl;
  61static struct qcom_icc_node qhs_compute0_cfg;
  62static struct qcom_icc_node qhs_compute1_cfg;
  63static struct qcom_icc_node qhs_cpr_cx;
  64static struct qcom_icc_node qhs_cpr_mmcx;
  65static struct qcom_icc_node qhs_cpr_mx;
  66static struct qcom_icc_node qhs_cpr_nspcx;
  67static struct qcom_icc_node qhs_crypto0_cfg;
  68static struct qcom_icc_node qhs_cx_rdpm;
  69static struct qcom_icc_node qhs_display0_cfg;
  70static struct qcom_icc_node qhs_display0_rt_throttle_cfg;
  71static struct qcom_icc_node qhs_display1_cfg;
  72static struct qcom_icc_node qhs_display1_rt_throttle_cfg;
  73static struct qcom_icc_node qhs_emac0_cfg;
  74static struct qcom_icc_node qhs_emac1_cfg;
  75static struct qcom_icc_node qhs_gp_dsp0_cfg;
  76static struct qcom_icc_node qhs_gp_dsp1_cfg;
  77static struct qcom_icc_node qhs_gpdsp0_throttle_cfg;
  78static struct qcom_icc_node qhs_gpdsp1_throttle_cfg;
  79static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg;
  80static struct qcom_icc_node qhs_gpuss_cfg;
  81static struct qcom_icc_node qhs_hwkm;
  82static struct qcom_icc_node qhs_imem_cfg;
  83static struct qcom_icc_node qhs_ipa;
  84static struct qcom_icc_node qhs_ipc_router;
  85static struct qcom_icc_node qhs_lpass_cfg;
  86static struct qcom_icc_node qhs_lpass_throttle_cfg;
  87static struct qcom_icc_node qhs_mx_rdpm;
  88static struct qcom_icc_node qhs_mxc_rdpm;
  89static struct qcom_icc_node qhs_pcie0_cfg;
  90static struct qcom_icc_node qhs_pcie1_cfg;
  91static struct qcom_icc_node qhs_pcie_rsc_cfg;
  92static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg;
  93static struct qcom_icc_node qhs_pcie_throttle_cfg;
  94static struct qcom_icc_node qhs_pdm;
  95static struct qcom_icc_node qhs_pimem_cfg;
  96static struct qcom_icc_node qhs_pke_wrapper_cfg;
  97static struct qcom_icc_node qhs_qdss_cfg;
  98static struct qcom_icc_node qhs_qm_cfg;
  99static struct qcom_icc_node qhs_qm_mpu_cfg;
 100static struct qcom_icc_node qhs_qup0;
 101static struct qcom_icc_node qhs_qup1;
 102static struct qcom_icc_node qhs_qup2;
 103static struct qcom_icc_node qhs_qup3;
 104static struct qcom_icc_node qhs_sail_throttle_cfg;
 105static struct qcom_icc_node qhs_sdc1;
 106static struct qcom_icc_node qhs_security;
 107static struct qcom_icc_node qhs_snoc_throttle_cfg;
 108static struct qcom_icc_node qhs_tcsr;
 109static struct qcom_icc_node qhs_tlmm;
 110static struct qcom_icc_node qhs_tsc_cfg;
 111static struct qcom_icc_node qhs_ufs_card_cfg;
 112static struct qcom_icc_node qhs_ufs_mem_cfg;
 113static struct qcom_icc_node qhs_usb2_0;
 114static struct qcom_icc_node qhs_usb3_0;
 115static struct qcom_icc_node qhs_usb3_1;
 116static struct qcom_icc_node qhs_venus_cfg;
 117static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
 118static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg;
 119static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg;
 120static struct qcom_icc_node qns_ddrss_cfg;
 121static struct qcom_icc_node qns_gpdsp_noc_cfg;
 122static struct qcom_icc_node qns_mnoc_hf_cfg;
 123static struct qcom_icc_node qns_mnoc_sf_cfg;
 124static struct qcom_icc_node qns_pcie_anoc_cfg;
 125static struct qcom_icc_node qns_snoc_cfg;
 126static struct qcom_icc_node qxs_boot_imem;
 127static struct qcom_icc_node qxs_imem;
 128static struct qcom_icc_node qxs_pimem;
 129static struct qcom_icc_node xs_pcie_0;
 130static struct qcom_icc_node xs_pcie_1;
 131static struct qcom_icc_node xs_qdss_stm;
 132static struct qcom_icc_node xs_sys_tcu_cfg;
 133static struct qcom_icc_node qnm_cnoc_dc_noc;
 134static struct qcom_icc_node qhs_llcc;
 135static struct qcom_icc_node qns_gemnoc;
 136static struct qcom_icc_node alm_gpu_tcu;
 137static struct qcom_icc_node alm_pcie_tcu;
 138static struct qcom_icc_node alm_sys_tcu;
 139static struct qcom_icc_node chm_apps;
 140static struct qcom_icc_node qnm_cmpnoc0;
 141static struct qcom_icc_node qnm_cmpnoc1;
 142static struct qcom_icc_node qnm_gemnoc_cfg;
 143static struct qcom_icc_node qnm_gpdsp_sail;
 144static struct qcom_icc_node qnm_gpu;
 145static struct qcom_icc_node qnm_mnoc_hf;
 146static struct qcom_icc_node qnm_mnoc_sf;
 147static struct qcom_icc_node qnm_pcie;
 148static struct qcom_icc_node qnm_snoc_gc;
 149static struct qcom_icc_node qnm_snoc_sf;
 150static struct qcom_icc_node qns_gem_noc_cnoc;
 151static struct qcom_icc_node qns_llcc;
 152static struct qcom_icc_node qns_pcie;
 153static struct qcom_icc_node srvc_even_gemnoc;
 154static struct qcom_icc_node srvc_odd_gemnoc;
 155static struct qcom_icc_node srvc_sys_gemnoc;
 156static struct qcom_icc_node srvc_sys_gemnoc_2;
 157static struct qcom_icc_node qxm_dsp0;
 158static struct qcom_icc_node qxm_dsp1;
 159static struct qcom_icc_node qns_gp_dsp_sail_noc;
 160static struct qcom_icc_node qhm_config_noc;
 161static struct qcom_icc_node qxm_lpass_dsp;
 162static struct qcom_icc_node qhs_lpass_core;
 163static struct qcom_icc_node qhs_lpass_lpi;
 164static struct qcom_icc_node qhs_lpass_mpu;
 165static struct qcom_icc_node qhs_lpass_top;
 166static struct qcom_icc_node qns_sysnoc;
 167static struct qcom_icc_node srvc_niu_aml_noc;
 168static struct qcom_icc_node srvc_niu_lpass_agnoc;
 169static struct qcom_icc_node llcc_mc;
 170static struct qcom_icc_node ebi;
 171static struct qcom_icc_node qnm_camnoc_hf;
 172static struct qcom_icc_node qnm_camnoc_icp;
 173static struct qcom_icc_node qnm_camnoc_sf;
 174static struct qcom_icc_node qnm_mdp0_0;
 175static struct qcom_icc_node qnm_mdp0_1;
 176static struct qcom_icc_node qnm_mdp1_0;
 177static struct qcom_icc_node qnm_mdp1_1;
 178static struct qcom_icc_node qnm_mnoc_hf_cfg;
 179static struct qcom_icc_node qnm_mnoc_sf_cfg;
 180static struct qcom_icc_node qnm_video0;
 181static struct qcom_icc_node qnm_video1;
 182static struct qcom_icc_node qnm_video_cvp;
 183static struct qcom_icc_node qnm_video_v_cpu;
 184static struct qcom_icc_node qns_mem_noc_hf;
 185static struct qcom_icc_node qns_mem_noc_sf;
 186static struct qcom_icc_node srvc_mnoc_hf;
 187static struct qcom_icc_node srvc_mnoc_sf;
 188static struct qcom_icc_node qhm_nsp_noc_config;
 189static struct qcom_icc_node qxm_nsp;
 190static struct qcom_icc_node qns_hcp;
 191static struct qcom_icc_node qns_nsp_gemnoc;
 192static struct qcom_icc_node service_nsp_noc;
 193static struct qcom_icc_node qhm_nspb_noc_config;
 194static struct qcom_icc_node qxm_nspb;
 195static struct qcom_icc_node qns_nspb_gemnoc;
 196static struct qcom_icc_node qns_nspb_hcp;
 197static struct qcom_icc_node service_nspb_noc;
 198static struct qcom_icc_node xm_pcie3_0;
 199static struct qcom_icc_node xm_pcie3_1;
 200static struct qcom_icc_node qns_pcie_mem_noc;
 201static struct qcom_icc_node qhm_gic;
 202static struct qcom_icc_node qnm_aggre1_noc;
 203static struct qcom_icc_node qnm_aggre2_noc;
 204static struct qcom_icc_node qnm_lpass_noc;
 205static struct qcom_icc_node qnm_snoc_cfg;
 206static struct qcom_icc_node qxm_pimem;
 207static struct qcom_icc_node xm_gic;
 208static struct qcom_icc_node qns_gemnoc_gc;
 209static struct qcom_icc_node qns_gemnoc_sf;
 210static struct qcom_icc_node srvc_snoc;
 211
 212static struct qcom_icc_node qxm_qup3 = {
 213	.name = "qxm_qup3",
 214	.channels = 1,
 215	.buswidth = 8,
 216	.qosbox = &(const struct qcom_icc_qosbox) {
 217		.num_ports = 1,
 218		.port_offsets = { 0x11000 },
 219		.prio_fwd_disable = 1,
 220		.prio = 2,
 221		.urg_fwd = 0,
 222	},
 223	.num_links = 1,
 224	.link_nodes = { &qns_a1noc_snoc },
 225};
 226
 227static struct qcom_icc_node xm_emac_0 = {
 228	.name = "xm_emac_0",
 229	.channels = 1,
 230	.buswidth = 8,
 231	.qosbox = &(const struct qcom_icc_qosbox) {
 232		.num_ports = 1,
 233		.port_offsets = { 0x12000 },
 234		.prio_fwd_disable = 1,
 235		.prio = 2,
 236		.urg_fwd = 0,
 237	},
 238	.num_links = 1,
 239	.link_nodes = { &qns_a1noc_snoc },
 240};
 241
 242static struct qcom_icc_node xm_emac_1 = {
 243	.name = "xm_emac_1",
 244	.channels = 1,
 245	.buswidth = 8,
 246	.qosbox = &(const struct qcom_icc_qosbox) {
 247		.num_ports = 1,
 248		.port_offsets = { 0x13000 },
 249		.prio_fwd_disable = 1,
 250		.prio = 2,
 251		.urg_fwd = 0,
 252	},
 253	.num_links = 1,
 254	.link_nodes = { &qns_a1noc_snoc },
 255};
 256
 257static struct qcom_icc_node xm_sdc1 = {
 258	.name = "xm_sdc1",
 259	.channels = 1,
 260	.buswidth = 8,
 261	.qosbox = &(const struct qcom_icc_qosbox) {
 262		.num_ports = 1,
 263		.port_offsets = { 0x14000 },
 264		.prio_fwd_disable = 1,
 265		.prio = 2,
 266		.urg_fwd = 0,
 267	},
 268	.num_links = 1,
 269	.link_nodes = { &qns_a1noc_snoc },
 270};
 271
 272static struct qcom_icc_node xm_ufs_mem = {
 273	.name = "xm_ufs_mem",
 274	.channels = 1,
 275	.buswidth = 8,
 276	.qosbox = &(const struct qcom_icc_qosbox) {
 277		.num_ports = 1,
 278		.port_offsets = { 0x15000 },
 279		.prio_fwd_disable = 1,
 280		.prio = 2,
 281		.urg_fwd = 0,
 282	},
 283	.num_links = 1,
 284	.link_nodes = { &qns_a1noc_snoc },
 285};
 286
 287static struct qcom_icc_node xm_usb2_2 = {
 288	.name = "xm_usb2_2",
 289	.channels = 1,
 290	.buswidth = 8,
 291	.qosbox = &(const struct qcom_icc_qosbox) {
 292		.num_ports = 1,
 293		.port_offsets = { 0x16000 },
 294		.prio_fwd_disable = 1,
 295		.prio = 2,
 296		.urg_fwd = 0,
 297	},
 298	.num_links = 1,
 299	.link_nodes = { &qns_a1noc_snoc },
 300};
 301
 302static struct qcom_icc_node xm_usb3_0 = {
 303	.name = "xm_usb3_0",
 304	.channels = 1,
 305	.buswidth = 8,
 306	.qosbox = &(const struct qcom_icc_qosbox) {
 307		.num_ports = 1,
 308		.port_offsets = { 0x17000 },
 309		.prio_fwd_disable = 1,
 310		.prio = 2,
 311		.urg_fwd = 0,
 312	},
 313	.num_links = 1,
 314	.link_nodes = { &qns_a1noc_snoc },
 315};
 316
 317static struct qcom_icc_node xm_usb3_1 = {
 318	.name = "xm_usb3_1",
 319	.channels = 1,
 320	.buswidth = 8,
 321	.qosbox = &(const struct qcom_icc_qosbox) {
 322		.num_ports = 1,
 323		.port_offsets = { 0x18000 },
 324		.prio_fwd_disable = 1,
 325		.prio = 2,
 326		.urg_fwd = 0,
 327	},
 328	.num_links = 1,
 329	.link_nodes = { &qns_a1noc_snoc },
 330};
 331
 332static struct qcom_icc_node qhm_qdss_bam = {
 333	.name = "qhm_qdss_bam",
 334	.channels = 1,
 335	.buswidth = 4,
 336	.qosbox = &(const struct qcom_icc_qosbox) {
 337		.num_ports = 1,
 338		.port_offsets = { 0x14000 },
 339		.prio_fwd_disable = 1,
 340		.prio = 2,
 341		.urg_fwd = 0,
 342	},
 343	.num_links = 1,
 344	.link_nodes = { &qns_a2noc_snoc },
 345};
 346
 347static struct qcom_icc_node qhm_qup0 = {
 348	.name = "qhm_qup0",
 349	.channels = 1,
 350	.buswidth = 4,
 351	.qosbox = &(const struct qcom_icc_qosbox) {
 352		.num_ports = 1,
 353		.port_offsets = { 0x17000 },
 354		.prio_fwd_disable = 1,
 355		.prio = 2,
 356		.urg_fwd = 0,
 357	},
 358	.num_links = 1,
 359	.link_nodes = { &qns_a2noc_snoc },
 360};
 361
 362static struct qcom_icc_node qhm_qup1 = {
 363	.name = "qhm_qup1",
 364	.channels = 1,
 365	.buswidth = 4,
 366	.qosbox = &(const struct qcom_icc_qosbox) {
 367		.num_ports = 1,
 368		.port_offsets = { 0x12000 },
 369		.prio_fwd_disable = 1,
 370		.prio = 2,
 371		.urg_fwd = 0,
 372	},
 373	.num_links = 1,
 374	.link_nodes = { &qns_a2noc_snoc },
 375};
 376
 377static struct qcom_icc_node qhm_qup2 = {
 378	.name = "qhm_qup2",
 379	.channels = 1,
 380	.buswidth = 4,
 381	.qosbox = &(const struct qcom_icc_qosbox) {
 382		.num_ports = 1,
 383		.port_offsets = { 0x15000 },
 384		.prio_fwd_disable = 1,
 385		.prio = 2,
 386		.urg_fwd = 0,
 387	},
 388	.num_links = 1,
 389	.link_nodes = { &qns_a2noc_snoc },
 390};
 391
 392static struct qcom_icc_node qnm_cnoc_datapath = {
 393	.name = "qnm_cnoc_datapath",
 394	.channels = 1,
 395	.buswidth = 8,
 396	.qosbox = &(const struct qcom_icc_qosbox) {
 397		.num_ports = 1,
 398		.port_offsets = { 0x16000 },
 399		.prio_fwd_disable = 1,
 400		.prio = 2,
 401		.urg_fwd = 0,
 402	},
 403	.num_links = 1,
 404	.link_nodes = { &qns_a2noc_snoc },
 405};
 406
 407static struct qcom_icc_node qxm_crypto_0 = {
 408	.name = "qxm_crypto_0",
 409	.channels = 1,
 410	.buswidth = 8,
 411	.qosbox = &(const struct qcom_icc_qosbox) {
 412		.num_ports = 1,
 413		.port_offsets = { 0x18000 },
 414		.prio_fwd_disable = 1,
 415		.prio = 2,
 416		.urg_fwd = 0,
 417	},
 418	.num_links = 1,
 419	.link_nodes = { &qns_a2noc_snoc },
 420};
 421
 422static struct qcom_icc_node qxm_crypto_1 = {
 423	.name = "qxm_crypto_1",
 424	.channels = 1,
 425	.buswidth = 8,
 426	.qosbox = &(const struct qcom_icc_qosbox) {
 427		.num_ports = 1,
 428		.port_offsets = { 0x1a000 },
 429		.prio_fwd_disable = 1,
 430		.prio = 2,
 431		.urg_fwd = 0,
 432	},
 433	.num_links = 1,
 434	.link_nodes = { &qns_a2noc_snoc },
 435};
 436
 437static struct qcom_icc_node qxm_ipa = {
 438	.name = "qxm_ipa",
 439	.channels = 1,
 440	.buswidth = 8,
 441	.qosbox = &(const struct qcom_icc_qosbox) {
 442		.num_ports = 1,
 443		.port_offsets = { 0x11000 },
 444		.prio_fwd_disable = 1,
 445		.prio = 2,
 446		.urg_fwd = 0,
 447	},
 448	.num_links = 1,
 449	.link_nodes = { &qns_a2noc_snoc },
 450};
 451
 452static struct qcom_icc_node xm_qdss_etr_0 = {
 453	.name = "xm_qdss_etr_0",
 454	.channels = 1,
 455	.buswidth = 8,
 456	.qosbox = &(const struct qcom_icc_qosbox) {
 457		.num_ports = 1,
 458		.port_offsets = { 0x13000 },
 459		.prio_fwd_disable = 1,
 460		.prio = 2,
 461		.urg_fwd = 0,
 462	},
 463	.num_links = 1,
 464	.link_nodes = { &qns_a2noc_snoc },
 465};
 466
 467static struct qcom_icc_node xm_qdss_etr_1 = {
 468	.name = "xm_qdss_etr_1",
 469	.channels = 1,
 470	.buswidth = 8,
 471	.qosbox = &(const struct qcom_icc_qosbox) {
 472		.num_ports = 1,
 473		.port_offsets = { 0x19000 },
 474		.prio_fwd_disable = 1,
 475		.prio = 2,
 476		.urg_fwd = 0,
 477	},
 478	.num_links = 1,
 479	.link_nodes = { &qns_a2noc_snoc },
 480};
 481
 482static struct qcom_icc_node xm_ufs_card = {
 483	.name = "xm_ufs_card",
 484	.channels = 1,
 485	.buswidth = 8,
 486	.qosbox = &(const struct qcom_icc_qosbox) {
 487		.num_ports = 1,
 488		.port_offsets = { 0x1b000 },
 489		.prio_fwd_disable = 1,
 490		.prio = 2,
 491		.urg_fwd = 0,
 492	},
 493	.num_links = 1,
 494	.link_nodes = { &qns_a2noc_snoc },
 495};
 496
 497static struct qcom_icc_node qup0_core_master = {
 498	.name = "qup0_core_master",
 499	.channels = 1,
 500	.buswidth = 4,
 501	.num_links = 1,
 502	.link_nodes = { &qup0_core_slave },
 503};
 504
 505static struct qcom_icc_node qup1_core_master = {
 506	.name = "qup1_core_master",
 507	.channels = 1,
 508	.buswidth = 4,
 509	.num_links = 1,
 510	.link_nodes = { &qup1_core_slave },
 511};
 512
 513static struct qcom_icc_node qup2_core_master = {
 514	.name = "qup2_core_master",
 515	.channels = 1,
 516	.buswidth = 4,
 517	.num_links = 1,
 518	.link_nodes = { &qup2_core_slave },
 519};
 520
 521static struct qcom_icc_node qup3_core_master = {
 522	.name = "qup3_core_master",
 523	.channels = 1,
 524	.buswidth = 4,
 525	.num_links = 1,
 526	.link_nodes = { &qup3_core_slave },
 527};
 528
 529static struct qcom_icc_node qnm_gemnoc_cnoc = {
 530	.name = "qnm_gemnoc_cnoc",
 531	.channels = 1,
 532	.buswidth = 16,
 533	.num_links = 82,
 534	.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
 535		      &qhs_ahb2phy2, &qhs_ahb2phy3,
 536		      &qhs_anoc_throttle_cfg, &qhs_aoss,
 537		      &qhs_apss, &qhs_boot_rom,
 538		      &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
 539		      &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
 540		      &qhs_compute0_cfg, &qhs_compute1_cfg,
 541		      &qhs_cpr_cx, &qhs_cpr_mmcx,
 542		      &qhs_cpr_mx, &qhs_cpr_nspcx,
 543		      &qhs_crypto0_cfg, &qhs_cx_rdpm,
 544		      &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
 545		      &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
 546		      &qhs_emac0_cfg, &qhs_emac1_cfg,
 547		      &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
 548		      &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
 549		      &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
 550		      &qhs_hwkm, &qhs_imem_cfg,
 551		      &qhs_ipa, &qhs_ipc_router,
 552		      &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
 553		      &qhs_mx_rdpm, &qhs_mxc_rdpm,
 554		      &qhs_pcie0_cfg, &qhs_pcie1_cfg,
 555		      &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
 556		      &qhs_pcie_throttle_cfg, &qhs_pdm,
 557		      &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
 558		      &qhs_qdss_cfg, &qhs_qm_cfg,
 559		      &qhs_qm_mpu_cfg, &qhs_qup0,
 560		      &qhs_qup1, &qhs_qup2,
 561		      &qhs_qup3, &qhs_sail_throttle_cfg,
 562		      &qhs_sdc1, &qhs_security,
 563		      &qhs_snoc_throttle_cfg, &qhs_tcsr,
 564		      &qhs_tlmm, &qhs_tsc_cfg,
 565		      &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
 566		      &qhs_usb2_0, &qhs_usb3_0,
 567		      &qhs_usb3_1, &qhs_venus_cfg,
 568		      &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
 569		      &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
 570		      &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
 571		      &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
 572		      &qns_snoc_cfg, &qxs_boot_imem,
 573		      &qxs_imem, &qxs_pimem,
 574		      &xs_qdss_stm, &xs_sys_tcu_cfg },
 575};
 576
 577static struct qcom_icc_node qnm_gemnoc_pcie = {
 578	.name = "qnm_gemnoc_pcie",
 579	.channels = 1,
 580	.buswidth = 16,
 581	.num_links = 2,
 582	.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
 583};
 584
 585static struct qcom_icc_node qnm_cnoc_dc_noc = {
 586	.name = "qnm_cnoc_dc_noc",
 587	.channels = 1,
 588	.buswidth = 4,
 589	.num_links = 2,
 590	.link_nodes = { &qhs_llcc, &qns_gemnoc },
 591};
 592
 593static struct qcom_icc_node alm_gpu_tcu = {
 594	.name = "alm_gpu_tcu",
 595	.channels = 1,
 596	.buswidth = 8,
 597	.qosbox = &(const struct qcom_icc_qosbox) {
 598		.num_ports = 1,
 599		.port_offsets = { 0xb4000 },
 600		.prio_fwd_disable = 1,
 601		.prio = 1,
 602		.urg_fwd = 0,
 603	},
 604	.num_links = 2,
 605	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 606};
 607
 608static struct qcom_icc_node alm_pcie_tcu = {
 609	.name = "alm_pcie_tcu",
 610	.channels = 1,
 611	.buswidth = 8,
 612	.qosbox = &(const struct qcom_icc_qosbox) {
 613		.num_ports = 1,
 614		.port_offsets = { 0xb5000 },
 615		.prio_fwd_disable = 1,
 616		.prio = 3,
 617		.urg_fwd = 0,
 618	},
 619	.num_links = 2,
 620	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 621};
 622
 623static struct qcom_icc_node alm_sys_tcu = {
 624	.name = "alm_sys_tcu",
 625	.channels = 1,
 626	.buswidth = 8,
 627	.qosbox = &(const struct qcom_icc_qosbox) {
 628		.num_ports = 1,
 629		.port_offsets = { 0xb6000 },
 630		.prio_fwd_disable = 1,
 631		.prio = 6,
 632		.urg_fwd = 0,
 633	},
 634	.num_links = 2,
 635	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 636};
 637
 638static struct qcom_icc_node chm_apps = {
 639	.name = "chm_apps",
 640	.channels = 4,
 641	.buswidth = 32,
 642	.num_links = 3,
 643	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 644		      &qns_pcie },
 645};
 646
 647static struct qcom_icc_node qnm_cmpnoc0 = {
 648	.name = "qnm_cmpnoc0",
 649	.channels = 2,
 650	.buswidth = 32,
 651	.qosbox = &(const struct qcom_icc_qosbox) {
 652		.num_ports = 2,
 653		.port_offsets = { 0xf3000, 0xf4000 },
 654		.prio_fwd_disable = 1,
 655		.prio = 0,
 656		.urg_fwd = 0,
 657	},
 658	.num_links = 2,
 659	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 660};
 661
 662static struct qcom_icc_node qnm_cmpnoc1 = {
 663	.name = "qnm_cmpnoc1",
 664	.channels = 2,
 665	.buswidth = 32,
 666	.qosbox = &(const struct qcom_icc_qosbox) {
 667		.num_ports = 2,
 668		.port_offsets = { 0xf5000, 0xf6000 },
 669		.prio_fwd_disable = 1,
 670		.prio = 0,
 671		.urg_fwd = 0,
 672	},
 673	.num_links = 2,
 674	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 675};
 676
 677static struct qcom_icc_node qnm_gemnoc_cfg = {
 678	.name = "qnm_gemnoc_cfg",
 679	.channels = 1,
 680	.buswidth = 4,
 681	.num_links = 4,
 682	.link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc,
 683		      &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 },
 684};
 685
 686static struct qcom_icc_node qnm_gpdsp_sail = {
 687	.name = "qnm_gpdsp_sail",
 688	.channels = 1,
 689	.buswidth = 16,
 690	.num_links = 2,
 691	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 692};
 693
 694static struct qcom_icc_node qnm_gpu = {
 695	.name = "qnm_gpu",
 696	.channels = 2,
 697	.buswidth = 32,
 698	.qosbox = &(const struct qcom_icc_qosbox) {
 699		.num_ports = 2,
 700		.port_offsets = { 0xed000, 0xee000 },
 701		.prio_fwd_disable = 1,
 702		.prio = 0,
 703		.urg_fwd = 0,
 704	},
 705	.num_links = 2,
 706	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 707};
 708
 709static struct qcom_icc_node qnm_mnoc_hf = {
 710	.name = "qnm_mnoc_hf",
 711	.channels = 2,
 712	.buswidth = 32,
 713	.qosbox = &(const struct qcom_icc_qosbox) {
 714		.num_ports = 2,
 715		.port_offsets = { 0xef000, 0xf0000 },
 716		.prio_fwd_disable = 0,
 717		.prio = 0,
 718		.urg_fwd = 1,
 719	},
 720	.num_links = 2,
 721	.link_nodes = { &qns_llcc, &qns_pcie },
 722};
 723
 724static struct qcom_icc_node qnm_mnoc_sf = {
 725	.name = "qnm_mnoc_sf",
 726	.channels = 2,
 727	.buswidth = 32,
 728	.qosbox = &(const struct qcom_icc_qosbox) {
 729		.num_ports = 2,
 730		.port_offsets = { 0xf1000, 0xf2000 },
 731		.prio_fwd_disable = 0,
 732		.prio = 0,
 733		.urg_fwd = 1,
 734	},
 735	.num_links = 3,
 736	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 737		      &qns_pcie },
 738};
 739
 740static struct qcom_icc_node qnm_pcie = {
 741	.name = "qnm_pcie",
 742	.channels = 1,
 743	.buswidth = 32,
 744	.qosbox = &(const struct qcom_icc_qosbox) {
 745		.num_ports = 1,
 746		.port_offsets = { 0xb8000 },
 747		.prio_fwd_disable = 1,
 748		.prio = 2,
 749		.urg_fwd = 0,
 750	},
 751	.num_links = 2,
 752	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 753};
 754
 755static struct qcom_icc_node qnm_snoc_gc = {
 756	.name = "qnm_snoc_gc",
 757	.channels = 1,
 758	.buswidth = 8,
 759	.qosbox = &(const struct qcom_icc_qosbox) {
 760		.num_ports = 1,
 761		.port_offsets = { 0xb9000 },
 762		.prio_fwd_disable = 0,
 763		.prio = 0,
 764		.urg_fwd = 1,
 765	},
 766	.num_links = 1,
 767	.link_nodes = { &qns_llcc },
 768};
 769
 770static struct qcom_icc_node qnm_snoc_sf = {
 771	.name = "qnm_snoc_sf",
 772	.channels = 1,
 773	.buswidth = 16,
 774	.qosbox = &(const struct qcom_icc_qosbox) {
 775		.num_ports = 1,
 776		.port_offsets = { 0xba000 },
 777		.prio_fwd_disable = 0,
 778		.prio = 0,
 779		.urg_fwd = 1,
 780	},
 781	.num_links = 3,
 782	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 783		      &qns_pcie },
 784};
 785
 786static struct qcom_icc_node qxm_dsp0 = {
 787	.name = "qxm_dsp0",
 788	.channels = 1,
 789	.buswidth = 16,
 790	.num_links = 1,
 791	.link_nodes = { &qns_gp_dsp_sail_noc },
 792};
 793
 794static struct qcom_icc_node qxm_dsp1 = {
 795	.name = "qxm_dsp1",
 796	.channels = 1,
 797	.buswidth = 16,
 798	.num_links = 1,
 799	.link_nodes = { &qns_gp_dsp_sail_noc },
 800};
 801
 802static struct qcom_icc_node qhm_config_noc = {
 803	.name = "qhm_config_noc",
 804	.channels = 1,
 805	.buswidth = 4,
 806	.num_links = 6,
 807	.link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
 808		      &qhs_lpass_mpu, &qhs_lpass_top,
 809		      &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
 810};
 811
 812static struct qcom_icc_node qxm_lpass_dsp = {
 813	.name = "qxm_lpass_dsp",
 814	.channels = 1,
 815	.buswidth = 8,
 816	.num_links = 4,
 817	.link_nodes = { &qhs_lpass_top, &qns_sysnoc,
 818		      &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
 819};
 820
 821static struct qcom_icc_node llcc_mc = {
 822	.name = "llcc_mc",
 823	.channels = 8,
 824	.buswidth = 4,
 825	.num_links = 1,
 826	.link_nodes = { &ebi },
 827};
 828
 829static struct qcom_icc_node qnm_camnoc_hf = {
 830	.name = "qnm_camnoc_hf",
 831	.channels = 1,
 832	.buswidth = 32,
 833	.qosbox = &(const struct qcom_icc_qosbox) {
 834		.num_ports = 1,
 835		.port_offsets = { 0xa000 },
 836		.prio_fwd_disable = 0,
 837		.prio = 0,
 838		.urg_fwd = 1,
 839	},
 840	.num_links = 1,
 841	.link_nodes = { &qns_mem_noc_hf },
 842};
 843
 844static struct qcom_icc_node qnm_camnoc_icp = {
 845	.name = "qnm_camnoc_icp",
 846	.channels = 1,
 847	.buswidth = 8,
 848	.qosbox = &(const struct qcom_icc_qosbox) {
 849		.num_ports = 1,
 850		.port_offsets = { 0x2a000 },
 851		.prio_fwd_disable = 0,
 852		.prio = 0,
 853		.urg_fwd = 1,
 854	},
 855	.num_links = 1,
 856	.link_nodes = { &qns_mem_noc_sf },
 857};
 858
 859static struct qcom_icc_node qnm_camnoc_sf = {
 860	.name = "qnm_camnoc_sf",
 861	.channels = 1,
 862	.buswidth = 32,
 863	.qosbox = &(const struct qcom_icc_qosbox) {
 864		.num_ports = 1,
 865		.port_offsets = { 0x2a080 },
 866		.prio_fwd_disable = 0,
 867		.prio = 0,
 868		.urg_fwd = 1,
 869	},
 870	.num_links = 1,
 871	.link_nodes = { &qns_mem_noc_sf },
 872};
 873
 874static struct qcom_icc_node qnm_mdp0_0 = {
 875	.name = "qnm_mdp0_0",
 876	.channels = 1,
 877	.buswidth = 32,
 878	.qosbox = &(const struct qcom_icc_qosbox) {
 879		.num_ports = 1,
 880		.port_offsets = { 0xa080 },
 881		.prio_fwd_disable = 0,
 882		.prio = 0,
 883		.urg_fwd = 1,
 884	},
 885	.num_links = 1,
 886	.link_nodes = { &qns_mem_noc_hf },
 887};
 888
 889static struct qcom_icc_node qnm_mdp0_1 = {
 890	.name = "qnm_mdp0_1",
 891	.channels = 1,
 892	.buswidth = 32,
 893	.qosbox = &(const struct qcom_icc_qosbox) {
 894		.num_ports = 1,
 895		.port_offsets = { 0xa180 },
 896		.prio_fwd_disable = 0,
 897		.prio = 0,
 898		.urg_fwd = 1,
 899	},
 900	.num_links = 1,
 901	.link_nodes = { &qns_mem_noc_hf },
 902};
 903
 904static struct qcom_icc_node qnm_mdp1_0 = {
 905	.name = "qnm_mdp1_0",
 906	.channels = 1,
 907	.buswidth = 32,
 908	.qosbox = &(const struct qcom_icc_qosbox) {
 909		.num_ports = 1,
 910		.port_offsets = { 0xa100 },
 911		.prio_fwd_disable = 0,
 912		.prio = 0,
 913		.urg_fwd = 1,
 914	},
 915	.num_links = 1,
 916	.link_nodes = { &qns_mem_noc_hf },
 917};
 918
 919static struct qcom_icc_node qnm_mdp1_1 = {
 920	.name = "qnm_mdp1_1",
 921	.channels = 1,
 922	.buswidth = 32,
 923	.qosbox = &(const struct qcom_icc_qosbox) {
 924		.num_ports = 1,
 925		.port_offsets = { 0xa200 },
 926		.prio_fwd_disable = 0,
 927		.prio = 0,
 928		.urg_fwd = 1,
 929	},
 930	.num_links = 1,
 931	.link_nodes = { &qns_mem_noc_hf },
 932};
 933
 934static struct qcom_icc_node qnm_mnoc_hf_cfg = {
 935	.name = "qnm_mnoc_hf_cfg",
 936	.channels = 1,
 937	.buswidth = 4,
 938	.num_links = 1,
 939	.link_nodes = { &srvc_mnoc_hf },
 940};
 941
 942static struct qcom_icc_node qnm_mnoc_sf_cfg = {
 943	.name = "qnm_mnoc_sf_cfg",
 944	.channels = 1,
 945	.buswidth = 4,
 946	.num_links = 1,
 947	.link_nodes = { &srvc_mnoc_sf },
 948};
 949
 950static struct qcom_icc_node qnm_video0 = {
 951	.name = "qnm_video0",
 952	.channels = 1,
 953	.buswidth = 32,
 954	.qosbox = &(const struct qcom_icc_qosbox) {
 955		.num_ports = 1,
 956		.port_offsets = { 0x2a100 },
 957		.prio_fwd_disable = 0,
 958		.prio = 0,
 959		.urg_fwd = 1,
 960	},
 961	.num_links = 1,
 962	.link_nodes = { &qns_mem_noc_sf },
 963};
 964
 965static struct qcom_icc_node qnm_video1 = {
 966	.name = "qnm_video1",
 967	.channels = 1,
 968	.buswidth = 32,
 969	.qosbox = &(const struct qcom_icc_qosbox) {
 970		.num_ports = 1,
 971		.port_offsets = { 0x2a180 },
 972		.prio_fwd_disable = 0,
 973		.prio = 0,
 974		.urg_fwd = 1,
 975	},
 976	.num_links = 1,
 977	.link_nodes = { &qns_mem_noc_sf },
 978};
 979
 980static struct qcom_icc_node qnm_video_cvp = {
 981	.name = "qnm_video_cvp",
 982	.channels = 1,
 983	.buswidth = 32,
 984	.qosbox = &(const struct qcom_icc_qosbox) {
 985		.num_ports = 1,
 986		.port_offsets = { 0x2a200 },
 987		.prio_fwd_disable = 0,
 988		.prio = 0,
 989		.urg_fwd = 1,
 990	},
 991	.num_links = 1,
 992	.link_nodes = { &qns_mem_noc_sf },
 993};
 994
 995static struct qcom_icc_node qnm_video_v_cpu = {
 996	.name = "qnm_video_v_cpu",
 997	.channels = 1,
 998	.buswidth = 8,
 999	.qosbox = &(const struct qcom_icc_qosbox) {
1000		.num_ports = 1,
1001		.port_offsets = { 0x2a280 },
1002		.prio_fwd_disable = 0,
1003		.prio = 0,
1004		.urg_fwd = 1,
1005	},
1006	.num_links = 1,
1007	.link_nodes = { &qns_mem_noc_sf },
1008};
1009
1010static struct qcom_icc_node qhm_nsp_noc_config = {
1011	.name = "qhm_nsp_noc_config",
1012	.channels = 1,
1013	.buswidth = 4,
1014	.num_links = 1,
1015	.link_nodes = { &service_nsp_noc },
1016};
1017
1018static struct qcom_icc_node qxm_nsp = {
1019	.name = "qxm_nsp",
1020	.channels = 2,
1021	.buswidth = 32,
1022	.num_links = 2,
1023	.link_nodes = { &qns_hcp, &qns_nsp_gemnoc },
1024};
1025
1026static struct qcom_icc_node qhm_nspb_noc_config = {
1027	.name = "qhm_nspb_noc_config",
1028	.channels = 1,
1029	.buswidth = 4,
1030	.num_links = 1,
1031	.link_nodes = { &service_nspb_noc },
1032};
1033
1034static struct qcom_icc_node qxm_nspb = {
1035	.name = "qxm_nspb",
1036	.channels = 2,
1037	.buswidth = 32,
1038	.num_links = 2,
1039	.link_nodes = { &qns_nspb_hcp, &qns_nspb_gemnoc },
1040};
1041
1042static struct qcom_icc_node xm_pcie3_0 = {
1043	.name = "xm_pcie3_0",
1044	.channels = 1,
1045	.buswidth = 16,
1046	.qosbox = &(const struct qcom_icc_qosbox) {
1047		.num_ports = 1,
1048		.port_offsets = { 0xb000 },
1049		.prio_fwd_disable = 1,
1050		.prio = 2,
1051		.urg_fwd = 0,
1052	},
1053	.num_links = 1,
1054	.link_nodes = { &qns_pcie_mem_noc },
1055};
1056
1057static struct qcom_icc_node xm_pcie3_1 = {
1058	.name = "xm_pcie3_1",
1059	.channels = 1,
1060	.buswidth = 32,
1061	.qosbox = &(const struct qcom_icc_qosbox) {
1062		.num_ports = 1,
1063		.port_offsets = { 0xc000 },
1064		.prio_fwd_disable = 1,
1065		.prio = 2,
1066		.urg_fwd = 0,
1067	},
1068	.num_links = 1,
1069	.link_nodes = { &qns_pcie_mem_noc },
1070};
1071
1072static struct qcom_icc_node qhm_gic = {
1073	.name = "qhm_gic",
1074	.channels = 1,
1075	.buswidth = 4,
1076	.qosbox = &(const struct qcom_icc_qosbox) {
1077		.num_ports = 1,
1078		.port_offsets = { 0x14000 },
1079		.prio_fwd_disable = 1,
1080		.prio = 2,
1081		.urg_fwd = 0,
1082	},
1083	.num_links = 1,
1084	.link_nodes = { &qns_gemnoc_sf },
1085};
1086
1087static struct qcom_icc_node qnm_aggre1_noc = {
1088	.name = "qnm_aggre1_noc",
1089	.channels = 1,
1090	.buswidth = 32,
1091	.num_links = 1,
1092	.link_nodes = { &qns_gemnoc_sf },
1093};
1094
1095static struct qcom_icc_node qnm_aggre2_noc = {
1096	.name = "qnm_aggre2_noc",
1097	.channels = 1,
1098	.buswidth = 16,
1099	.num_links = 1,
1100	.link_nodes = { &qns_gemnoc_sf },
1101};
1102
1103static struct qcom_icc_node qnm_lpass_noc = {
1104	.name = "qnm_lpass_noc",
1105	.channels = 1,
1106	.buswidth = 16,
1107	.qosbox = &(const struct qcom_icc_qosbox) {
1108		.num_ports = 1,
1109		.port_offsets = { 0x12000 },
1110		.prio_fwd_disable = 0,
1111		.prio = 0,
1112		.urg_fwd = 1,
1113	},
1114	.num_links = 1,
1115	.link_nodes = { &qns_gemnoc_sf },
1116};
1117
1118static struct qcom_icc_node qnm_snoc_cfg = {
1119	.name = "qnm_snoc_cfg",
1120	.channels = 1,
1121	.buswidth = 4,
1122	.num_links = 1,
1123	.link_nodes = { &srvc_snoc },
1124};
1125
1126static struct qcom_icc_node qxm_pimem = {
1127	.name = "qxm_pimem",
1128	.channels = 1,
1129	.buswidth = 8,
1130	.qosbox = &(const struct qcom_icc_qosbox) {
1131		.num_ports = 1,
1132		.port_offsets = { 0x13000 },
1133		.prio_fwd_disable = 1,
1134		.prio = 2,
1135		.urg_fwd = 0,
1136	},
1137	.num_links = 1,
1138	.link_nodes = { &qns_gemnoc_gc },
1139};
1140
1141static struct qcom_icc_node xm_gic = {
1142	.name = "xm_gic",
1143	.channels = 1,
1144	.buswidth = 8,
1145	.qosbox = &(const struct qcom_icc_qosbox) {
1146		.num_ports = 1,
1147		.port_offsets = { 0x15000 },
1148		.prio_fwd_disable = 1,
1149		.prio = 2,
1150		.urg_fwd = 0,
1151	},
1152	.num_links = 1,
1153	.link_nodes = { &qns_gemnoc_gc },
1154};
1155
1156static struct qcom_icc_node qns_a1noc_snoc = {
1157	.name = "qns_a1noc_snoc",
1158	.channels = 1,
1159	.buswidth = 32,
1160	.num_links = 1,
1161	.link_nodes = { &qnm_aggre1_noc },
1162};
1163
1164static struct qcom_icc_node qns_a2noc_snoc = {
1165	.name = "qns_a2noc_snoc",
1166	.channels = 1,
1167	.buswidth = 16,
1168	.num_links = 1,
1169	.link_nodes = { &qnm_aggre2_noc },
1170};
1171
1172static struct qcom_icc_node qup0_core_slave = {
1173	.name = "qup0_core_slave",
1174	.channels = 1,
1175	.buswidth = 4,
1176};
1177
1178static struct qcom_icc_node qup1_core_slave = {
1179	.name = "qup1_core_slave",
1180	.channels = 1,
1181	.buswidth = 4,
1182};
1183
1184static struct qcom_icc_node qup2_core_slave = {
1185	.name = "qup2_core_slave",
1186	.channels = 1,
1187	.buswidth = 4,
1188};
1189
1190static struct qcom_icc_node qup3_core_slave = {
1191	.name = "qup3_core_slave",
1192	.channels = 1,
1193	.buswidth = 4,
1194};
1195
1196static struct qcom_icc_node qhs_ahb2phy0 = {
1197	.name = "qhs_ahb2phy0",
1198	.channels = 1,
1199	.buswidth = 4,
1200};
1201
1202static struct qcom_icc_node qhs_ahb2phy1 = {
1203	.name = "qhs_ahb2phy1",
1204	.channels = 1,
1205	.buswidth = 4,
1206};
1207
1208static struct qcom_icc_node qhs_ahb2phy2 = {
1209	.name = "qhs_ahb2phy2",
1210	.channels = 1,
1211	.buswidth = 4,
1212};
1213
1214static struct qcom_icc_node qhs_ahb2phy3 = {
1215	.name = "qhs_ahb2phy3",
1216	.channels = 1,
1217	.buswidth = 4,
1218};
1219
1220static struct qcom_icc_node qhs_anoc_throttle_cfg = {
1221	.name = "qhs_anoc_throttle_cfg",
1222	.channels = 1,
1223	.buswidth = 4,
1224};
1225
1226static struct qcom_icc_node qhs_aoss = {
1227	.name = "qhs_aoss",
1228	.channels = 1,
1229	.buswidth = 4,
1230};
1231
1232static struct qcom_icc_node qhs_apss = {
1233	.name = "qhs_apss",
1234	.channels = 1,
1235	.buswidth = 8,
1236};
1237
1238static struct qcom_icc_node qhs_boot_rom = {
1239	.name = "qhs_boot_rom",
1240	.channels = 1,
1241	.buswidth = 4,
1242};
1243
1244static struct qcom_icc_node qhs_camera_cfg = {
1245	.name = "qhs_camera_cfg",
1246	.channels = 1,
1247	.buswidth = 4,
1248};
1249
1250static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
1251	.name = "qhs_camera_nrt_throttle_cfg",
1252	.channels = 1,
1253	.buswidth = 4,
1254};
1255
1256static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
1257	.name = "qhs_camera_rt_throttle_cfg",
1258	.channels = 1,
1259	.buswidth = 4,
1260};
1261
1262static struct qcom_icc_node qhs_clk_ctl = {
1263	.name = "qhs_clk_ctl",
1264	.channels = 1,
1265	.buswidth = 4,
1266};
1267
1268static struct qcom_icc_node qhs_compute0_cfg = {
1269	.name = "qhs_compute0_cfg",
1270	.channels = 1,
1271	.buswidth = 4,
1272	.num_links = 1,
1273	.link_nodes = { &qhm_nsp_noc_config },
1274};
1275
1276static struct qcom_icc_node qhs_compute1_cfg = {
1277	.name = "qhs_compute1_cfg",
1278	.channels = 1,
1279	.buswidth = 4,
1280	.num_links = 1,
1281	.link_nodes = { &qhm_nspb_noc_config },
1282};
1283
1284static struct qcom_icc_node qhs_cpr_cx = {
1285	.name = "qhs_cpr_cx",
1286	.channels = 1,
1287	.buswidth = 4,
1288};
1289
1290static struct qcom_icc_node qhs_cpr_mmcx = {
1291	.name = "qhs_cpr_mmcx",
1292	.channels = 1,
1293	.buswidth = 4,
1294};
1295
1296static struct qcom_icc_node qhs_cpr_mx = {
1297	.name = "qhs_cpr_mx",
1298	.channels = 1,
1299	.buswidth = 4,
1300};
1301
1302static struct qcom_icc_node qhs_cpr_nspcx = {
1303	.name = "qhs_cpr_nspcx",
1304	.channels = 1,
1305	.buswidth = 4,
1306};
1307
1308static struct qcom_icc_node qhs_crypto0_cfg = {
1309	.name = "qhs_crypto0_cfg",
1310	.channels = 1,
1311	.buswidth = 4,
1312};
1313
1314static struct qcom_icc_node qhs_cx_rdpm = {
1315	.name = "qhs_cx_rdpm",
1316	.channels = 1,
1317	.buswidth = 4,
1318};
1319
1320static struct qcom_icc_node qhs_display0_cfg = {
1321	.name = "qhs_display0_cfg",
1322	.channels = 1,
1323	.buswidth = 4,
1324};
1325
1326static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
1327	.name = "qhs_display0_rt_throttle_cfg",
1328	.channels = 1,
1329	.buswidth = 4,
1330};
1331
1332static struct qcom_icc_node qhs_display1_cfg = {
1333	.name = "qhs_display1_cfg",
1334	.channels = 1,
1335	.buswidth = 4,
1336};
1337
1338static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
1339	.name = "qhs_display1_rt_throttle_cfg",
1340	.channels = 1,
1341	.buswidth = 4,
1342};
1343
1344static struct qcom_icc_node qhs_emac0_cfg = {
1345	.name = "qhs_emac0_cfg",
1346	.channels = 1,
1347	.buswidth = 4,
1348};
1349
1350static struct qcom_icc_node qhs_emac1_cfg = {
1351	.name = "qhs_emac1_cfg",
1352	.channels = 1,
1353	.buswidth = 4,
1354};
1355
1356static struct qcom_icc_node qhs_gp_dsp0_cfg = {
1357	.name = "qhs_gp_dsp0_cfg",
1358	.channels = 1,
1359	.buswidth = 4,
1360};
1361
1362static struct qcom_icc_node qhs_gp_dsp1_cfg = {
1363	.name = "qhs_gp_dsp1_cfg",
1364	.channels = 1,
1365	.buswidth = 4,
1366};
1367
1368static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
1369	.name = "qhs_gpdsp0_throttle_cfg",
1370	.channels = 1,
1371	.buswidth = 4,
1372};
1373
1374static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
1375	.name = "qhs_gpdsp1_throttle_cfg",
1376	.channels = 1,
1377	.buswidth = 4,
1378};
1379
1380static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
1381	.name = "qhs_gpu_tcu_throttle_cfg",
1382	.channels = 1,
1383	.buswidth = 4,
1384};
1385
1386static struct qcom_icc_node qhs_gpuss_cfg = {
1387	.name = "qhs_gpuss_cfg",
1388	.channels = 1,
1389	.buswidth = 8,
1390};
1391
1392static struct qcom_icc_node qhs_hwkm = {
1393	.name = "qhs_hwkm",
1394	.channels = 1,
1395	.buswidth = 4,
1396};
1397
1398static struct qcom_icc_node qhs_imem_cfg = {
1399	.name = "qhs_imem_cfg",
1400	.channels = 1,
1401	.buswidth = 4,
1402};
1403
1404static struct qcom_icc_node qhs_ipa = {
1405	.name = "qhs_ipa",
1406	.channels = 1,
1407	.buswidth = 4,
1408};
1409
1410static struct qcom_icc_node qhs_ipc_router = {
1411	.name = "qhs_ipc_router",
1412	.channels = 1,
1413	.buswidth = 4,
1414};
1415
1416static struct qcom_icc_node qhs_lpass_cfg = {
1417	.name = "qhs_lpass_cfg",
1418	.channels = 1,
1419	.buswidth = 4,
1420	.num_links = 1,
1421	.link_nodes = { &qhm_config_noc },
1422};
1423
1424static struct qcom_icc_node qhs_lpass_throttle_cfg = {
1425	.name = "qhs_lpass_throttle_cfg",
1426	.channels = 1,
1427	.buswidth = 4,
1428};
1429
1430static struct qcom_icc_node qhs_mx_rdpm = {
1431	.name = "qhs_mx_rdpm",
1432	.channels = 1,
1433	.buswidth = 4,
1434};
1435
1436static struct qcom_icc_node qhs_mxc_rdpm = {
1437	.name = "qhs_mxc_rdpm",
1438	.channels = 1,
1439	.buswidth = 4,
1440};
1441
1442static struct qcom_icc_node qhs_pcie0_cfg = {
1443	.name = "qhs_pcie0_cfg",
1444	.channels = 1,
1445	.buswidth = 4,
1446};
1447
1448static struct qcom_icc_node qhs_pcie1_cfg = {
1449	.name = "qhs_pcie1_cfg",
1450	.channels = 1,
1451	.buswidth = 4,
1452};
1453
1454static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1455	.name = "qhs_pcie_rsc_cfg",
1456	.channels = 1,
1457	.buswidth = 4,
1458};
1459
1460static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
1461	.name = "qhs_pcie_tcu_throttle_cfg",
1462	.channels = 1,
1463	.buswidth = 4,
1464};
1465
1466static struct qcom_icc_node qhs_pcie_throttle_cfg = {
1467	.name = "qhs_pcie_throttle_cfg",
1468	.channels = 1,
1469	.buswidth = 4,
1470};
1471
1472static struct qcom_icc_node qhs_pdm = {
1473	.name = "qhs_pdm",
1474	.channels = 1,
1475	.buswidth = 4,
1476};
1477
1478static struct qcom_icc_node qhs_pimem_cfg = {
1479	.name = "qhs_pimem_cfg",
1480	.channels = 1,
1481	.buswidth = 4,
1482};
1483
1484static struct qcom_icc_node qhs_pke_wrapper_cfg = {
1485	.name = "qhs_pke_wrapper_cfg",
1486	.channels = 1,
1487	.buswidth = 4,
1488};
1489
1490static struct qcom_icc_node qhs_qdss_cfg = {
1491	.name = "qhs_qdss_cfg",
1492	.channels = 1,
1493	.buswidth = 4,
1494};
1495
1496static struct qcom_icc_node qhs_qm_cfg = {
1497	.name = "qhs_qm_cfg",
1498	.channels = 1,
1499	.buswidth = 4,
1500};
1501
1502static struct qcom_icc_node qhs_qm_mpu_cfg = {
1503	.name = "qhs_qm_mpu_cfg",
1504	.channels = 1,
1505	.buswidth = 4,
1506};
1507
1508static struct qcom_icc_node qhs_qup0 = {
1509	.name = "qhs_qup0",
1510	.channels = 1,
1511	.buswidth = 4,
1512};
1513
1514static struct qcom_icc_node qhs_qup1 = {
1515	.name = "qhs_qup1",
1516	.channels = 1,
1517	.buswidth = 4,
1518};
1519
1520static struct qcom_icc_node qhs_qup2 = {
1521	.name = "qhs_qup2",
1522	.channels = 1,
1523	.buswidth = 4,
1524};
1525
1526static struct qcom_icc_node qhs_qup3 = {
1527	.name = "qhs_qup3",
1528	.channels = 1,
1529	.buswidth = 4,
1530};
1531
1532static struct qcom_icc_node qhs_sail_throttle_cfg = {
1533	.name = "qhs_sail_throttle_cfg",
1534	.channels = 1,
1535	.buswidth = 4,
1536};
1537
1538static struct qcom_icc_node qhs_sdc1 = {
1539	.name = "qhs_sdc1",
1540	.channels = 1,
1541	.buswidth = 4,
1542};
1543
1544static struct qcom_icc_node qhs_security = {
1545	.name = "qhs_security",
1546	.channels = 1,
1547	.buswidth = 4,
1548};
1549
1550static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1551	.name = "qhs_snoc_throttle_cfg",
1552	.channels = 1,
1553	.buswidth = 4,
1554};
1555
1556static struct qcom_icc_node qhs_tcsr = {
1557	.name = "qhs_tcsr",
1558	.channels = 1,
1559	.buswidth = 4,
1560};
1561
1562static struct qcom_icc_node qhs_tlmm = {
1563	.name = "qhs_tlmm",
1564	.channels = 1,
1565	.buswidth = 4,
1566};
1567
1568static struct qcom_icc_node qhs_tsc_cfg = {
1569	.name = "qhs_tsc_cfg",
1570	.channels = 1,
1571	.buswidth = 4,
1572};
1573
1574static struct qcom_icc_node qhs_ufs_card_cfg = {
1575	.name = "qhs_ufs_card_cfg",
1576	.channels = 1,
1577	.buswidth = 4,
1578};
1579
1580static struct qcom_icc_node qhs_ufs_mem_cfg = {
1581	.name = "qhs_ufs_mem_cfg",
1582	.channels = 1,
1583	.buswidth = 4,
1584};
1585
1586static struct qcom_icc_node qhs_usb2_0 = {
1587	.name = "qhs_usb2_0",
1588	.channels = 1,
1589	.buswidth = 4,
1590};
1591
1592static struct qcom_icc_node qhs_usb3_0 = {
1593	.name = "qhs_usb3_0",
1594	.channels = 1,
1595	.buswidth = 4,
1596};
1597
1598static struct qcom_icc_node qhs_usb3_1 = {
1599	.name = "qhs_usb3_1",
1600	.channels = 1,
1601	.buswidth = 4,
1602};
1603
1604static struct qcom_icc_node qhs_venus_cfg = {
1605	.name = "qhs_venus_cfg",
1606	.channels = 1,
1607	.buswidth = 4,
1608};
1609
1610static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1611	.name = "qhs_venus_cvp_throttle_cfg",
1612	.channels = 1,
1613	.buswidth = 4,
1614};
1615
1616static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1617	.name = "qhs_venus_v_cpu_throttle_cfg",
1618	.channels = 1,
1619	.buswidth = 4,
1620};
1621
1622static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1623	.name = "qhs_venus_vcodec_throttle_cfg",
1624	.channels = 1,
1625	.buswidth = 4,
1626};
1627
1628static struct qcom_icc_node qns_ddrss_cfg = {
1629	.name = "qns_ddrss_cfg",
1630	.channels = 1,
1631	.buswidth = 4,
1632	.num_links = 1,
1633	.link_nodes = { &qnm_cnoc_dc_noc },
1634};
1635
1636static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1637	.name = "qns_gpdsp_noc_cfg",
1638	.channels = 1,
1639	.buswidth = 4,
1640};
1641
1642static struct qcom_icc_node qns_mnoc_hf_cfg = {
1643	.name = "qns_mnoc_hf_cfg",
1644	.channels = 1,
1645	.buswidth = 4,
1646	.num_links = 1,
1647	.link_nodes = { &qnm_mnoc_hf_cfg },
1648};
1649
1650static struct qcom_icc_node qns_mnoc_sf_cfg = {
1651	.name = "qns_mnoc_sf_cfg",
1652	.channels = 1,
1653	.buswidth = 4,
1654	.num_links = 1,
1655	.link_nodes = { &qnm_mnoc_sf_cfg },
1656};
1657
1658static struct qcom_icc_node qns_pcie_anoc_cfg = {
1659	.name = "qns_pcie_anoc_cfg",
1660	.channels = 1,
1661	.buswidth = 4,
1662};
1663
1664static struct qcom_icc_node qns_snoc_cfg = {
1665	.name = "qns_snoc_cfg",
1666	.channels = 1,
1667	.buswidth = 4,
1668	.num_links = 1,
1669	.link_nodes = { &qnm_snoc_cfg },
1670};
1671
1672static struct qcom_icc_node qxs_boot_imem = {
1673	.name = "qxs_boot_imem",
1674	.channels = 1,
1675	.buswidth = 16,
1676};
1677
1678static struct qcom_icc_node qxs_imem = {
1679	.name = "qxs_imem",
1680	.channels = 1,
1681	.buswidth = 8,
1682};
1683
1684static struct qcom_icc_node qxs_pimem = {
1685	.name = "qxs_pimem",
1686	.channels = 1,
1687	.buswidth = 8,
1688};
1689
1690static struct qcom_icc_node xs_pcie_0 = {
1691	.name = "xs_pcie_0",
1692	.channels = 1,
1693	.buswidth = 16,
1694};
1695
1696static struct qcom_icc_node xs_pcie_1 = {
1697	.name = "xs_pcie_1",
1698	.channels = 1,
1699	.buswidth = 32,
1700};
1701
1702static struct qcom_icc_node xs_qdss_stm = {
1703	.name = "xs_qdss_stm",
1704	.channels = 1,
1705	.buswidth = 4,
1706};
1707
1708static struct qcom_icc_node xs_sys_tcu_cfg = {
1709	.name = "xs_sys_tcu_cfg",
1710	.channels = 1,
1711	.buswidth = 8,
1712};
1713
1714static struct qcom_icc_node qhs_llcc = {
1715	.name = "qhs_llcc",
1716	.channels = 1,
1717	.buswidth = 4,
1718};
1719
1720static struct qcom_icc_node qns_gemnoc = {
1721	.name = "qns_gemnoc",
1722	.channels = 1,
1723	.buswidth = 4,
1724	.num_links = 1,
1725	.link_nodes = { &qnm_gemnoc_cfg },
1726};
1727
1728static struct qcom_icc_node qns_gem_noc_cnoc = {
1729	.name = "qns_gem_noc_cnoc",
1730	.channels = 1,
1731	.buswidth = 16,
1732	.num_links = 1,
1733	.link_nodes = { &qnm_gemnoc_cnoc },
1734};
1735
1736static struct qcom_icc_node qns_llcc = {
1737	.name = "qns_llcc",
1738	.channels = 6,
1739	.buswidth = 16,
1740	.num_links = 1,
1741	.link_nodes = { &llcc_mc },
1742};
1743
1744static struct qcom_icc_node qns_pcie = {
1745	.name = "qns_pcie",
1746	.channels = 1,
1747	.buswidth = 16,
1748	.num_links = 1,
1749	.link_nodes = { &qnm_gemnoc_pcie },
1750};
1751
1752static struct qcom_icc_node srvc_even_gemnoc = {
1753	.name = "srvc_even_gemnoc",
1754	.channels = 1,
1755	.buswidth = 4,
1756};
1757
1758static struct qcom_icc_node srvc_odd_gemnoc = {
1759	.name = "srvc_odd_gemnoc",
1760	.channels = 1,
1761	.buswidth = 4,
1762};
1763
1764static struct qcom_icc_node srvc_sys_gemnoc = {
1765	.name = "srvc_sys_gemnoc",
1766	.channels = 1,
1767	.buswidth = 4,
1768};
1769
1770static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1771	.name = "srvc_sys_gemnoc_2",
1772	.channels = 1,
1773	.buswidth = 4,
1774};
1775
1776static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1777	.name = "qns_gp_dsp_sail_noc",
1778	.channels = 1,
1779	.buswidth = 16,
1780	.num_links = 1,
1781	.link_nodes = { &qnm_gpdsp_sail },
1782};
1783
1784static struct qcom_icc_node qhs_lpass_core = {
1785	.name = "qhs_lpass_core",
1786	.channels = 1,
1787	.buswidth = 4,
1788};
1789
1790static struct qcom_icc_node qhs_lpass_lpi = {
1791	.name = "qhs_lpass_lpi",
1792	.channels = 1,
1793	.buswidth = 4,
1794};
1795
1796static struct qcom_icc_node qhs_lpass_mpu = {
1797	.name = "qhs_lpass_mpu",
1798	.channels = 1,
1799	.buswidth = 4,
1800};
1801
1802static struct qcom_icc_node qhs_lpass_top = {
1803	.name = "qhs_lpass_top",
1804	.channels = 1,
1805	.buswidth = 4,
1806};
1807
1808static struct qcom_icc_node qns_sysnoc = {
1809	.name = "qns_sysnoc",
1810	.channels = 1,
1811	.buswidth = 16,
1812	.num_links = 1,
1813	.link_nodes = { &qnm_lpass_noc },
1814};
1815
1816static struct qcom_icc_node srvc_niu_aml_noc = {
1817	.name = "srvc_niu_aml_noc",
1818	.channels = 1,
1819	.buswidth = 4,
1820};
1821
1822static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1823	.name = "srvc_niu_lpass_agnoc",
1824	.channels = 1,
1825	.buswidth = 4,
1826};
1827
1828static struct qcom_icc_node ebi = {
1829	.name = "ebi",
1830	.channels = 8,
1831	.buswidth = 4,
1832};
1833
1834static struct qcom_icc_node qns_mem_noc_hf = {
1835	.name = "qns_mem_noc_hf",
1836	.channels = 2,
1837	.buswidth = 32,
1838	.num_links = 1,
1839	.link_nodes = { &qnm_mnoc_hf },
1840};
1841
1842static struct qcom_icc_node qns_mem_noc_sf = {
1843	.name = "qns_mem_noc_sf",
1844	.channels = 2,
1845	.buswidth = 32,
1846	.num_links = 1,
1847	.link_nodes = { &qnm_mnoc_sf },
1848};
1849
1850static struct qcom_icc_node srvc_mnoc_hf = {
1851	.name = "srvc_mnoc_hf",
1852	.channels = 1,
1853	.buswidth = 4,
1854};
1855
1856static struct qcom_icc_node srvc_mnoc_sf = {
1857	.name = "srvc_mnoc_sf",
1858	.channels = 1,
1859	.buswidth = 4,
1860};
1861
1862static struct qcom_icc_node qns_hcp = {
1863	.name = "qns_hcp",
1864	.channels = 2,
1865	.buswidth = 32,
1866};
1867
1868static struct qcom_icc_node qns_nsp_gemnoc = {
1869	.name = "qns_nsp_gemnoc",
1870	.channels = 2,
1871	.buswidth = 32,
1872	.num_links = 1,
1873	.link_nodes = { &qnm_cmpnoc0 },
1874};
1875
1876static struct qcom_icc_node service_nsp_noc = {
1877	.name = "service_nsp_noc",
1878	.channels = 1,
1879	.buswidth = 4,
1880};
1881
1882static struct qcom_icc_node qns_nspb_gemnoc = {
1883	.name = "qns_nspb_gemnoc",
1884	.channels = 2,
1885	.buswidth = 32,
1886	.num_links = 1,
1887	.link_nodes = { &qnm_cmpnoc1 },
1888};
1889
1890static struct qcom_icc_node qns_nspb_hcp = {
1891	.name = "qns_nspb_hcp",
1892	.channels = 2,
1893	.buswidth = 32,
1894};
1895
1896static struct qcom_icc_node service_nspb_noc = {
1897	.name = "service_nspb_noc",
1898	.channels = 1,
1899	.buswidth = 4,
1900};
1901
1902static struct qcom_icc_node qns_pcie_mem_noc = {
1903	.name = "qns_pcie_mem_noc",
1904	.channels = 1,
1905	.buswidth = 32,
1906	.num_links = 1,
1907	.link_nodes = { &qnm_pcie },
1908};
1909
1910static struct qcom_icc_node qns_gemnoc_gc = {
1911	.name = "qns_gemnoc_gc",
1912	.channels = 1,
1913	.buswidth = 8,
1914	.num_links = 1,
1915	.link_nodes = { &qnm_snoc_gc },
1916};
1917
1918static struct qcom_icc_node qns_gemnoc_sf = {
1919	.name = "qns_gemnoc_sf",
1920	.channels = 1,
1921	.buswidth = 16,
1922	.num_links = 1,
1923	.link_nodes = { &qnm_snoc_sf },
1924};
1925
1926static struct qcom_icc_node srvc_snoc = {
1927	.name = "srvc_snoc",
1928	.channels = 1,
1929	.buswidth = 4,
1930};
1931
1932static struct qcom_icc_bcm bcm_acv = {
1933	.name = "ACV",
1934	.enable_mask = 0x8,
1935	.num_nodes = 1,
1936	.nodes = { &ebi },
1937};
1938
1939static struct qcom_icc_bcm bcm_ce0 = {
1940	.name = "CE0",
1941	.num_nodes = 2,
1942	.nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1943};
1944
1945static struct qcom_icc_bcm bcm_cn0 = {
1946	.name = "CN0",
1947	.keepalive = true,
1948	.num_nodes = 2,
1949	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1950};
1951
1952static struct qcom_icc_bcm bcm_cn1 = {
1953	.name = "CN1",
1954	.num_nodes = 76,
1955	.nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
1956		   &qhs_ahb2phy2, &qhs_ahb2phy3,
1957		   &qhs_anoc_throttle_cfg, &qhs_aoss,
1958		   &qhs_apss, &qhs_boot_rom,
1959		   &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1960		   &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1961		   &qhs_compute0_cfg, &qhs_compute1_cfg,
1962		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1963		   &qhs_cpr_mx, &qhs_cpr_nspcx,
1964		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
1965		   &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1966		   &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
1967		   &qhs_emac0_cfg, &qhs_emac1_cfg,
1968		   &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
1969		   &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
1970		   &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
1971		   &qhs_hwkm, &qhs_imem_cfg,
1972		   &qhs_ipa, &qhs_ipc_router,
1973		   &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
1974		   &qhs_mx_rdpm, &qhs_mxc_rdpm,
1975		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1976		   &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
1977		   &qhs_pcie_throttle_cfg, &qhs_pdm,
1978		   &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1979		   &qhs_qdss_cfg, &qhs_qm_cfg,
1980		   &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1981		   &qhs_sdc1, &qhs_security,
1982		   &qhs_snoc_throttle_cfg, &qhs_tcsr,
1983		   &qhs_tlmm, &qhs_tsc_cfg,
1984		   &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
1985		   &qhs_usb2_0, &qhs_usb3_0,
1986		   &qhs_usb3_1, &qhs_venus_cfg,
1987		   &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1988		   &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1989		   &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1990		   &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1991		   &qns_snoc_cfg, &qxs_boot_imem,
1992		   &qxs_imem, &xs_sys_tcu_cfg },
1993};
1994
1995static struct qcom_icc_bcm bcm_cn2 = {
1996	.name = "CN2",
1997	.num_nodes = 4,
1998	.nodes = { &qhs_qup0, &qhs_qup1,
1999		   &qhs_qup2, &qhs_qup3 },
2000};
2001
2002static struct qcom_icc_bcm bcm_cn3 = {
2003	.name = "CN3",
2004	.num_nodes = 2,
2005	.nodes = { &xs_pcie_0, &xs_pcie_1 },
2006};
2007
2008static struct qcom_icc_bcm bcm_gna0 = {
2009	.name = "GNA0",
2010	.num_nodes = 1,
2011	.nodes = { &qxm_dsp0 },
2012};
2013
2014static struct qcom_icc_bcm bcm_gnb0 = {
2015	.name = "GNB0",
2016	.num_nodes = 1,
2017	.nodes = { &qxm_dsp1 },
2018};
2019
2020static struct qcom_icc_bcm bcm_mc0 = {
2021	.name = "MC0",
2022	.keepalive = true,
2023	.num_nodes = 1,
2024	.nodes = { &ebi },
2025};
2026
2027static struct qcom_icc_bcm bcm_mm0 = {
2028	.name = "MM0",
2029	.keepalive = true,
2030	.num_nodes = 5,
2031	.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
2032		   &qnm_mdp0_1, &qnm_mdp1_0,
2033		   &qns_mem_noc_hf },
2034};
2035
2036static struct qcom_icc_bcm bcm_mm1 = {
2037	.name = "MM1",
2038	.num_nodes = 7,
2039	.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
2040		   &qnm_video0, &qnm_video1,
2041		   &qnm_video_cvp, &qnm_video_v_cpu,
2042		   &qns_mem_noc_sf },
2043};
2044
2045static struct qcom_icc_bcm bcm_nsa0 = {
2046	.name = "NSA0",
2047	.num_nodes = 2,
2048	.nodes = { &qns_hcp, &qns_nsp_gemnoc },
2049};
2050
2051static struct qcom_icc_bcm bcm_nsa1 = {
2052	.name = "NSA1",
2053	.num_nodes = 1,
2054	.nodes = { &qxm_nsp },
2055};
2056
2057static struct qcom_icc_bcm bcm_nsb0 = {
2058	.name = "NSB0",
2059	.num_nodes = 2,
2060	.nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
2061};
2062
2063static struct qcom_icc_bcm bcm_nsb1 = {
2064	.name = "NSB1",
2065	.num_nodes = 1,
2066	.nodes = { &qxm_nspb },
2067};
2068
2069static struct qcom_icc_bcm bcm_pci0 = {
2070	.name = "PCI0",
2071	.num_nodes = 1,
2072	.nodes = { &qns_pcie_mem_noc },
2073};
2074
2075static struct qcom_icc_bcm bcm_qup0 = {
2076	.name = "QUP0",
2077	.vote_scale = 1,
2078	.num_nodes = 1,
2079	.nodes = { &qup0_core_slave },
2080};
2081
2082static struct qcom_icc_bcm bcm_qup1 = {
2083	.name = "QUP1",
2084	.vote_scale = 1,
2085	.num_nodes = 1,
2086	.nodes = { &qup1_core_slave },
2087};
2088
2089static struct qcom_icc_bcm bcm_qup2 = {
2090	.name = "QUP2",
2091	.vote_scale = 1,
2092	.num_nodes = 2,
2093	.nodes = { &qup2_core_slave, &qup3_core_slave },
2094};
2095
2096static struct qcom_icc_bcm bcm_sh0 = {
2097	.name = "SH0",
2098	.keepalive = true,
2099	.num_nodes = 1,
2100	.nodes = { &qns_llcc },
2101};
2102
2103static struct qcom_icc_bcm bcm_sh2 = {
2104	.name = "SH2",
2105	.num_nodes = 1,
2106	.nodes = { &chm_apps },
2107};
2108
2109static struct qcom_icc_bcm bcm_sn0 = {
2110	.name = "SN0",
2111	.keepalive = true,
2112	.num_nodes = 1,
2113	.nodes = { &qns_gemnoc_sf },
2114};
2115
2116static struct qcom_icc_bcm bcm_sn1 = {
2117	.name = "SN1",
2118	.num_nodes = 1,
2119	.nodes = { &qns_gemnoc_gc },
2120};
2121
2122static struct qcom_icc_bcm bcm_sn2 = {
2123	.name = "SN2",
2124	.num_nodes = 1,
2125	.nodes = { &qxs_pimem },
2126};
2127
2128static struct qcom_icc_bcm bcm_sn3 = {
2129	.name = "SN3",
2130	.num_nodes = 2,
2131	.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
2132};
2133
2134static struct qcom_icc_bcm bcm_sn4 = {
2135	.name = "SN4",
2136	.num_nodes = 2,
2137	.nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
2138};
2139
2140static struct qcom_icc_bcm bcm_sn9 = {
2141	.name = "SN9",
2142	.num_nodes = 2,
2143	.nodes = { &qns_sysnoc, &qnm_lpass_noc },
2144};
2145
2146static struct qcom_icc_bcm bcm_sn10 = {
2147	.name = "SN10",
2148	.num_nodes = 1,
2149	.nodes = { &xs_qdss_stm },
2150};
2151
2152static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
2153	&bcm_sn3,
2154};
2155
2156static struct qcom_icc_node * const aggre1_noc_nodes[] = {
2157	[MASTER_QUP_3] = &qxm_qup3,
2158	[MASTER_EMAC] = &xm_emac_0,
2159	[MASTER_EMAC_1] = &xm_emac_1,
2160	[MASTER_SDC] = &xm_sdc1,
2161	[MASTER_UFS_MEM] = &xm_ufs_mem,
2162	[MASTER_USB2] = &xm_usb2_2,
2163	[MASTER_USB3_0] = &xm_usb3_0,
2164	[MASTER_USB3_1] = &xm_usb3_1,
2165	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
2166};
2167
2168static const struct regmap_config sa8775p_aggre1_noc_regmap_config = {
2169	.reg_bits = 32,
2170	.reg_stride = 4,
2171	.val_bits = 32,
2172	.max_register = 0x18080,
2173	.fast_io = true,
2174};
2175
2176static const struct qcom_icc_desc sa8775p_aggre1_noc = {
2177	.config = &sa8775p_aggre1_noc_regmap_config,
2178	.nodes = aggre1_noc_nodes,
2179	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
2180	.bcms = aggre1_noc_bcms,
2181	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2182	.qos_requires_clocks = true,
2183};
2184
2185static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
2186	&bcm_ce0,
2187	&bcm_sn4,
2188};
2189
2190static struct qcom_icc_node * const aggre2_noc_nodes[] = {
2191	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
2192	[MASTER_QUP_0] = &qhm_qup0,
2193	[MASTER_QUP_1] = &qhm_qup1,
2194	[MASTER_QUP_2] = &qhm_qup2,
2195	[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
2196	[MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
2197	[MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
2198	[MASTER_IPA] = &qxm_ipa,
2199	[MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
2200	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
2201	[MASTER_UFS_CARD] = &xm_ufs_card,
2202	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
2203};
2204
2205static const struct regmap_config sa8775p_aggre2_noc_regmap_config = {
2206	.reg_bits = 32,
2207	.reg_stride = 4,
2208	.val_bits = 32,
2209	.max_register = 0x1b080,
2210	.fast_io = true,
2211};
2212
2213static const struct qcom_icc_desc sa8775p_aggre2_noc = {
2214	.config = &sa8775p_aggre2_noc_regmap_config,
2215	.nodes = aggre2_noc_nodes,
2216	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
2217	.bcms = aggre2_noc_bcms,
2218	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2219	.qos_requires_clocks = true,
2220};
2221
2222static struct qcom_icc_bcm * const clk_virt_bcms[] = {
2223	&bcm_qup0,
2224	&bcm_qup1,
2225	&bcm_qup2,
2226};
2227
2228static struct qcom_icc_node * const clk_virt_nodes[] = {
2229	[MASTER_QUP_CORE_0] = &qup0_core_master,
2230	[MASTER_QUP_CORE_1] = &qup1_core_master,
2231	[MASTER_QUP_CORE_2] = &qup2_core_master,
2232	[MASTER_QUP_CORE_3] = &qup3_core_master,
2233	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
2234	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
2235	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
2236	[SLAVE_QUP_CORE_3] = &qup3_core_slave,
2237};
2238
2239static const struct qcom_icc_desc sa8775p_clk_virt = {
2240	.nodes = clk_virt_nodes,
2241	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
2242	.bcms = clk_virt_bcms,
2243	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
2244};
2245
2246static struct qcom_icc_bcm * const config_noc_bcms[] = {
2247	&bcm_cn0,
2248	&bcm_cn1,
2249	&bcm_cn2,
2250	&bcm_cn3,
2251	&bcm_sn2,
2252	&bcm_sn10,
2253};
2254
2255static struct qcom_icc_node * const config_noc_nodes[] = {
2256	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2257	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2258	[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
2259	[SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
2260	[SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
2261	[SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
2262	[SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
2263	[SLAVE_AOSS] = &qhs_aoss,
2264	[SLAVE_APPSS] = &qhs_apss,
2265	[SLAVE_BOOT_ROM] = &qhs_boot_rom,
2266	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
2267	[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
2268	[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
2269	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
2270	[SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
2271	[SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
2272	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
2273	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
2274	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
2275	[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
2276	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
2277	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
2278	[SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
2279	[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
2280	[SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
2281	[SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
2282	[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
2283	[SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
2284	[SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
2285	[SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
2286	[SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
2287	[SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
2288	[SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
2289	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
2290	[SLAVE_HWKM] = &qhs_hwkm,
2291	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
2292	[SLAVE_IPA_CFG] = &qhs_ipa,
2293	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
2294	[SLAVE_LPASS] = &qhs_lpass_cfg,
2295	[SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
2296	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
2297	[SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
2298	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
2299	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
2300	[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
2301	[SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
2302	[SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
2303	[SLAVE_PDM] = &qhs_pdm,
2304	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
2305	[SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
2306	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2307	[SLAVE_QM_CFG] = &qhs_qm_cfg,
2308	[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
2309	[SLAVE_QUP_0] = &qhs_qup0,
2310	[SLAVE_QUP_1] = &qhs_qup1,
2311	[SLAVE_QUP_2] = &qhs_qup2,
2312	[SLAVE_QUP_3] = &qhs_qup3,
2313	[SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
2314	[SLAVE_SDC1] = &qhs_sdc1,
2315	[SLAVE_SECURITY] = &qhs_security,
2316	[SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
2317	[SLAVE_TCSR] = &qhs_tcsr,
2318	[SLAVE_TLMM] = &qhs_tlmm,
2319	[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
2320	[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
2321	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2322	[SLAVE_USB2] = &qhs_usb2_0,
2323	[SLAVE_USB3_0] = &qhs_usb3_0,
2324	[SLAVE_USB3_1] = &qhs_usb3_1,
2325	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2326	[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
2327	[SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
2328	[SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
2329	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
2330	[SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
2331	[SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
2332	[SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
2333	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
2334	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
2335	[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
2336	[SLAVE_IMEM] = &qxs_imem,
2337	[SLAVE_PIMEM] = &qxs_pimem,
2338	[SLAVE_PCIE_0] = &xs_pcie_0,
2339	[SLAVE_PCIE_1] = &xs_pcie_1,
2340	[SLAVE_QDSS_STM] = &xs_qdss_stm,
2341	[SLAVE_TCU] = &xs_sys_tcu_cfg,
2342};
2343
2344static const struct regmap_config sa8775p_config_noc_regmap_config = {
2345	.reg_bits = 32,
2346	.reg_stride = 4,
2347	.val_bits = 32,
2348	.max_register = 0x13080,
2349	.fast_io = true,
2350};
2351
2352static const struct qcom_icc_desc sa8775p_config_noc = {
2353	.config = &sa8775p_config_noc_regmap_config,
2354	.nodes = config_noc_nodes,
2355	.num_nodes = ARRAY_SIZE(config_noc_nodes),
2356	.bcms = config_noc_bcms,
2357	.num_bcms = ARRAY_SIZE(config_noc_bcms),
2358};
2359
2360static struct qcom_icc_bcm * const dc_noc_bcms[] = {
2361};
2362
2363static struct qcom_icc_node * const dc_noc_nodes[] = {
2364	[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2365	[SLAVE_LLCC_CFG] = &qhs_llcc,
2366	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2367};
2368
2369static const struct regmap_config sa8775p_dc_noc_regmap_config = {
2370	.reg_bits = 32,
2371	.reg_stride = 4,
2372	.val_bits = 32,
2373	.max_register = 0x5080,
2374	.fast_io = true,
2375};
2376
2377static const struct qcom_icc_desc sa8775p_dc_noc = {
2378	.config = &sa8775p_dc_noc_regmap_config,
2379	.nodes = dc_noc_nodes,
2380	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
2381	.bcms = dc_noc_bcms,
2382	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
2383};
2384
2385static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2386	&bcm_sh0,
2387	&bcm_sh2,
2388};
2389
2390static struct qcom_icc_node * const gem_noc_nodes[] = {
2391	[MASTER_GPU_TCU] = &alm_gpu_tcu,
2392	[MASTER_PCIE_TCU] = &alm_pcie_tcu,
2393	[MASTER_SYS_TCU] = &alm_sys_tcu,
2394	[MASTER_APPSS_PROC] = &chm_apps,
2395	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2396	[MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
2397	[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2398	[MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
2399	[MASTER_GFX3D] = &qnm_gpu,
2400	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2401	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2402	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2403	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2404	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2405	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2406	[SLAVE_LLCC] = &qns_llcc,
2407	[SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2408	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2409	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2410	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2411	[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2412};
2413
2414static const struct regmap_config sa8775p_gem_noc_regmap_config = {
2415	.reg_bits = 32,
2416	.reg_stride = 4,
2417	.val_bits = 32,
2418	.max_register = 0xf6080,
2419	.fast_io = true,
2420};
2421
2422static const struct qcom_icc_desc sa8775p_gem_noc = {
2423	.config = &sa8775p_gem_noc_regmap_config,
2424	.nodes = gem_noc_nodes,
2425	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
2426	.bcms = gem_noc_bcms,
2427	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
2428};
2429
2430static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
2431	&bcm_gna0,
2432	&bcm_gnb0,
2433};
2434
2435static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
2436	[MASTER_DSP0] = &qxm_dsp0,
2437	[MASTER_DSP1] = &qxm_dsp1,
2438	[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2439};
2440
2441static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = {
2442	.reg_bits = 32,
2443	.reg_stride = 4,
2444	.val_bits = 32,
2445	.max_register = 0xe080,
2446	.fast_io = true,
2447};
2448
2449static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
2450	.config = &sa8775p_gpdsp_anoc_regmap_config,
2451	.nodes = gpdsp_anoc_nodes,
2452	.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2453	.bcms = gpdsp_anoc_bcms,
2454	.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2455};
2456
2457static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2458	&bcm_sn9,
2459};
2460
2461static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2462	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2463	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2464	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2465	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2466	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2467	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2468	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
2469	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2470	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2471};
2472
2473static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = {
2474	.reg_bits = 32,
2475	.reg_stride = 4,
2476	.val_bits = 32,
2477	.max_register = 0x17200,
2478	.fast_io = true,
2479};
2480
2481static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
2482	.config = &sa8775p_lpass_ag_noc_regmap_config,
2483	.nodes = lpass_ag_noc_nodes,
2484	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2485	.bcms = lpass_ag_noc_bcms,
2486	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2487};
2488
2489static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2490	&bcm_acv,
2491	&bcm_mc0,
2492};
2493
2494static struct qcom_icc_node * const mc_virt_nodes[] = {
2495	[MASTER_LLCC] = &llcc_mc,
2496	[SLAVE_EBI1] = &ebi,
2497};
2498
2499static const struct qcom_icc_desc sa8775p_mc_virt = {
2500	.nodes = mc_virt_nodes,
2501	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
2502	.bcms = mc_virt_bcms,
2503	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2504};
2505
2506static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2507	&bcm_mm0,
2508	&bcm_mm1,
2509};
2510
2511static struct qcom_icc_node * const mmss_noc_nodes[] = {
2512	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2513	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2514	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2515	[MASTER_MDP0] = &qnm_mdp0_0,
2516	[MASTER_MDP1] = &qnm_mdp0_1,
2517	[MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
2518	[MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
2519	[MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
2520	[MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
2521	[MASTER_VIDEO_P0] = &qnm_video0,
2522	[MASTER_VIDEO_P1] = &qnm_video1,
2523	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
2524	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2525	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2526	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2527	[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
2528	[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2529};
2530
2531static const struct regmap_config sa8775p_mmss_noc_regmap_config = {
2532	.reg_bits = 32,
2533	.reg_stride = 4,
2534	.val_bits = 32,
2535	.max_register = 0x40000,
2536	.fast_io = true,
2537};
2538
2539static const struct qcom_icc_desc sa8775p_mmss_noc = {
2540	.config = &sa8775p_mmss_noc_regmap_config,
2541	.nodes = mmss_noc_nodes,
2542	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2543	.bcms = mmss_noc_bcms,
2544	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2545};
2546
2547static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2548	&bcm_nsa0,
2549	&bcm_nsa1,
2550};
2551
2552static struct qcom_icc_node * const nspa_noc_nodes[] = {
2553	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2554	[MASTER_CDSP_PROC] = &qxm_nsp,
2555	[SLAVE_HCP_A] = &qns_hcp,
2556	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2557	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2558};
2559
2560static const struct regmap_config sa8775p_nspa_noc_regmap_config = {
2561	.reg_bits = 32,
2562	.reg_stride = 4,
2563	.val_bits = 32,
2564	.max_register = 0x16080,
2565	.fast_io = true,
2566};
2567
2568static const struct qcom_icc_desc sa8775p_nspa_noc = {
2569	.config = &sa8775p_nspa_noc_regmap_config,
2570	.nodes = nspa_noc_nodes,
2571	.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2572	.bcms = nspa_noc_bcms,
2573	.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2574};
2575
2576static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
2577	&bcm_nsb0,
2578	&bcm_nsb1,
2579};
2580
2581static const struct regmap_config sa8775p_nspb_noc_regmap_config = {
2582	.reg_bits = 32,
2583	.reg_stride = 4,
2584	.val_bits = 32,
2585	.max_register = 0x16080,
2586	.fast_io = true,
2587};
2588
2589static struct qcom_icc_node * const nspb_noc_nodes[] = {
2590	[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2591	[MASTER_CDSP_PROC_B] = &qxm_nspb,
2592	[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
2593	[SLAVE_HCP_B] = &qns_nspb_hcp,
2594	[SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
2595};
2596
2597static const struct qcom_icc_desc sa8775p_nspb_noc = {
2598	.config = &sa8775p_nspb_noc_regmap_config,
2599	.nodes = nspb_noc_nodes,
2600	.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2601	.bcms = nspb_noc_bcms,
2602	.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2603};
2604
2605static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2606	&bcm_pci0,
2607};
2608
2609static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2610	[MASTER_PCIE_0] = &xm_pcie3_0,
2611	[MASTER_PCIE_1] = &xm_pcie3_1,
2612	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2613};
2614
2615static const struct regmap_config sa8775p_pcie_anoc_regmap_config = {
2616	.reg_bits = 32,
2617	.reg_stride = 4,
2618	.val_bits = 32,
2619	.max_register = 0xc080,
2620	.fast_io = true,
2621};
2622
2623static const struct qcom_icc_desc sa8775p_pcie_anoc = {
2624	.config = &sa8775p_pcie_anoc_regmap_config,
2625	.nodes = pcie_anoc_nodes,
2626	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2627	.bcms = pcie_anoc_bcms,
2628	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2629};
2630
2631static struct qcom_icc_bcm * const system_noc_bcms[] = {
2632	&bcm_sn0,
2633	&bcm_sn1,
2634	&bcm_sn3,
2635	&bcm_sn4,
2636	&bcm_sn9,
2637};
2638
2639static struct qcom_icc_node * const system_noc_nodes[] = {
2640	[MASTER_GIC_AHB] = &qhm_gic,
2641	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2642	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2643	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2644	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2645	[MASTER_PIMEM] = &qxm_pimem,
2646	[MASTER_GIC] = &xm_gic,
2647	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2648	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2649	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2650};
2651
2652static const struct regmap_config sa8775p_system_noc_regmap_config = {
2653	.reg_bits = 32,
2654	.reg_stride = 4,
2655	.val_bits = 32,
2656	.max_register = 0x15080,
2657	.fast_io = true,
2658};
2659
2660static const struct qcom_icc_desc sa8775p_system_noc = {
2661	.config = &sa8775p_system_noc_regmap_config,
2662	.nodes = system_noc_nodes,
2663	.num_nodes = ARRAY_SIZE(system_noc_nodes),
2664	.bcms = system_noc_bcms,
2665	.num_bcms = ARRAY_SIZE(system_noc_bcms),
2666};
2667
2668static const struct of_device_id qnoc_of_match[] = {
2669	{ .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
2670	{ .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
2671	{ .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
2672	{ .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
2673	{ .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
2674	{ .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
2675	{ .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
2676	{ .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
2677	{ .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
2678	{ .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
2679	{ .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
2680	{ .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
2681	{ .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
2682	{ .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
2683	{ }
2684};
2685MODULE_DEVICE_TABLE(of, qnoc_of_match);
2686
2687static struct platform_driver qnoc_driver = {
2688	.probe = qcom_icc_rpmh_probe,
2689	.remove = qcom_icc_rpmh_remove,
2690	.driver = {
2691		.name = "qnoc-sa8775p",
2692		.of_match_table = qnoc_of_match,
2693		.sync_state = icc_sync_state,
2694	},
2695};
2696
2697static int __init qnoc_driver_init(void)
2698{
2699	return platform_driver_register(&qnoc_driver);
2700}
2701core_initcall(qnoc_driver_init);
2702
2703static void __exit qnoc_driver_exit(void)
2704{
2705	platform_driver_unregister(&qnoc_driver);
2706}
2707module_exit(qnoc_driver_exit);
2708
2709MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
2710MODULE_LICENSE("GPL");