qdu1000.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
   4 *
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
  14
  15#include "bcm-voter.h"
  16#include "icc-common.h"
  17#include "icc-rpmh.h"
  18
  19static struct qcom_icc_node qup0_core_master;
  20static struct qcom_icc_node qup1_core_master;
  21static struct qcom_icc_node alm_sys_tcu;
  22static struct qcom_icc_node chm_apps;
  23static struct qcom_icc_node qnm_ecpri_dma;
  24static struct qcom_icc_node qnm_fec_2_gemnoc;
  25static struct qcom_icc_node qnm_pcie;
  26static struct qcom_icc_node qnm_snoc_gc;
  27static struct qcom_icc_node qnm_snoc_sf;
  28static struct qcom_icc_node qxm_mdsp;
  29static struct qcom_icc_node llcc_mc;
  30static struct qcom_icc_node qhm_gic;
  31static struct qcom_icc_node qhm_qdss_bam;
  32static struct qcom_icc_node qhm_qpic;
  33static struct qcom_icc_node qhm_qspi;
  34static struct qcom_icc_node qhm_qup0;
  35static struct qcom_icc_node qhm_qup1;
  36static struct qcom_icc_node qhm_system_noc_cfg;
  37static struct qcom_icc_node qnm_aggre_noc;
  38static struct qcom_icc_node qnm_aggre_noc_gsi;
  39static struct qcom_icc_node qnm_gemnoc_cnoc;
  40static struct qcom_icc_node qnm_gemnoc_modem_slave;
  41static struct qcom_icc_node qnm_gemnoc_pcie;
  42static struct qcom_icc_node qxm_crypto;
  43static struct qcom_icc_node qxm_ecpri_gsi;
  44static struct qcom_icc_node qxm_pimem;
  45static struct qcom_icc_node xm_ecpri_dma;
  46static struct qcom_icc_node xm_gic;
  47static struct qcom_icc_node xm_pcie;
  48static struct qcom_icc_node xm_qdss_etr0;
  49static struct qcom_icc_node xm_qdss_etr1;
  50static struct qcom_icc_node xm_sdc;
  51static struct qcom_icc_node xm_usb3;
  52static struct qcom_icc_node qup0_core_slave;
  53static struct qcom_icc_node qup1_core_slave;
  54static struct qcom_icc_node qns_gem_noc_cnoc;
  55static struct qcom_icc_node qns_llcc;
  56static struct qcom_icc_node qns_modem_slave;
  57static struct qcom_icc_node qns_pcie;
  58static struct qcom_icc_node ebi;
  59static struct qcom_icc_node qhs_ahb2phy0_south;
  60static struct qcom_icc_node qhs_ahb2phy1_north;
  61static struct qcom_icc_node qhs_ahb2phy2_east;
  62static struct qcom_icc_node qhs_aoss;
  63static struct qcom_icc_node qhs_clk_ctl;
  64static struct qcom_icc_node qhs_cpr_cx;
  65static struct qcom_icc_node qhs_cpr_mx;
  66static struct qcom_icc_node qhs_crypto_cfg;
  67static struct qcom_icc_node qhs_ecpri_cfg;
  68static struct qcom_icc_node qhs_imem_cfg;
  69static struct qcom_icc_node qhs_ipc_router;
  70static struct qcom_icc_node qhs_mss_cfg;
  71static struct qcom_icc_node qhs_pcie_cfg;
  72static struct qcom_icc_node qhs_pdm;
  73static struct qcom_icc_node qhs_pimem_cfg;
  74static struct qcom_icc_node qhs_prng;
  75static struct qcom_icc_node qhs_qdss_cfg;
  76static struct qcom_icc_node qhs_qpic;
  77static struct qcom_icc_node qhs_qspi;
  78static struct qcom_icc_node qhs_qup0;
  79static struct qcom_icc_node qhs_qup1;
  80static struct qcom_icc_node qhs_sdc2;
  81static struct qcom_icc_node qhs_smbus_cfg;
  82static struct qcom_icc_node qhs_system_noc_cfg;
  83static struct qcom_icc_node qhs_tcsr;
  84static struct qcom_icc_node qhs_tlmm;
  85static struct qcom_icc_node qhs_tme_cfg;
  86static struct qcom_icc_node qhs_tsc_cfg;
  87static struct qcom_icc_node qhs_usb3;
  88static struct qcom_icc_node qhs_vsense_ctrl_cfg;
  89static struct qcom_icc_node qns_a1noc_snoc;
  90static struct qcom_icc_node qns_anoc_snoc_gsi;
  91static struct qcom_icc_node qns_ddrss_cfg;
  92static struct qcom_icc_node qns_ecpri_gemnoc;
  93static struct qcom_icc_node qns_gemnoc_gc;
  94static struct qcom_icc_node qns_gemnoc_sf;
  95static struct qcom_icc_node qns_modem;
  96static struct qcom_icc_node qns_pcie_gemnoc;
  97static struct qcom_icc_node qxs_imem;
  98static struct qcom_icc_node qxs_pimem;
  99static struct qcom_icc_node srvc_system_noc;
 100static struct qcom_icc_node xs_ethernet_ss;
 101static struct qcom_icc_node xs_pcie;
 102static struct qcom_icc_node xs_qdss_stm;
 103static struct qcom_icc_node xs_sys_tcu_cfg;
 104
 105static struct qcom_icc_node qup0_core_master = {
 106	.name = "qup0_core_master",
 107	.channels = 1,
 108	.buswidth = 4,
 109	.num_links = 1,
 110	.link_nodes = { &qup0_core_slave },
 111};
 112
 113static struct qcom_icc_node qup1_core_master = {
 114	.name = "qup1_core_master",
 115	.channels = 1,
 116	.buswidth = 4,
 117	.num_links = 1,
 118	.link_nodes = { &qup1_core_slave },
 119};
 120
 121static struct qcom_icc_node alm_sys_tcu = {
 122	.name = "alm_sys_tcu",
 123	.channels = 1,
 124	.buswidth = 8,
 125	.num_links = 2,
 126	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 127};
 128
 129static struct qcom_icc_node chm_apps = {
 130	.name = "chm_apps",
 131	.channels = 1,
 132	.buswidth = 16,
 133	.num_links = 4,
 134	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 135			&qns_modem_slave, &qns_pcie },
 136};
 137
 138static struct qcom_icc_node qnm_ecpri_dma = {
 139	.name = "qnm_ecpri_dma",
 140	.channels = 2,
 141	.buswidth = 32,
 142	.num_links = 2,
 143	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 144};
 145
 146static struct qcom_icc_node qnm_fec_2_gemnoc = {
 147	.name = "qnm_fec_2_gemnoc",
 148	.channels = 2,
 149	.buswidth = 32,
 150	.num_links = 2,
 151	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 152};
 153
 154static struct qcom_icc_node qnm_pcie = {
 155	.name = "qnm_pcie",
 156	.channels = 1,
 157	.buswidth = 64,
 158	.num_links = 3,
 159	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 160			&qns_modem_slave },
 161};
 162
 163static struct qcom_icc_node qnm_snoc_gc = {
 164	.name = "qnm_snoc_gc",
 165	.channels = 1,
 166	.buswidth = 8,
 167	.num_links = 1,
 168	.link_nodes = { &qns_llcc },
 169};
 170
 171static struct qcom_icc_node qnm_snoc_sf = {
 172	.name = "qnm_snoc_sf",
 173	.channels = 1,
 174	.buswidth = 16,
 175	.num_links = 4,
 176	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 177			&qns_modem_slave, &qns_pcie },
 178};
 179
 180static struct qcom_icc_node qxm_mdsp = {
 181	.name = "qxm_mdsp",
 182	.channels = 1,
 183	.buswidth = 16,
 184	.num_links = 3,
 185	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 186			&qns_pcie },
 187};
 188
 189static struct qcom_icc_node llcc_mc = {
 190	.name = "llcc_mc",
 191	.channels = 8,
 192	.buswidth = 4,
 193	.num_links = 1,
 194	.link_nodes = { &ebi },
 195};
 196
 197static struct qcom_icc_node qhm_gic = {
 198	.name = "qhm_gic",
 199	.channels = 1,
 200	.buswidth = 4,
 201	.num_links = 1,
 202	.link_nodes = { &qns_gemnoc_sf },
 203};
 204
 205static struct qcom_icc_node qhm_qdss_bam = {
 206	.name = "qhm_qdss_bam",
 207	.channels = 1,
 208	.buswidth = 4,
 209	.num_links = 1,
 210	.link_nodes = { &qns_gemnoc_sf },
 211};
 212
 213static struct qcom_icc_node qhm_qpic = {
 214	.name = "qhm_qpic",
 215	.channels = 1,
 216	.buswidth = 4,
 217	.num_links = 1,
 218	.link_nodes = { &qns_a1noc_snoc },
 219};
 220
 221static struct qcom_icc_node qhm_qspi = {
 222	.name = "qhm_qspi",
 223	.channels = 1,
 224	.buswidth = 4,
 225	.num_links = 1,
 226	.link_nodes = { &qns_a1noc_snoc },
 227};
 228
 229static struct qcom_icc_node qhm_qup0 = {
 230	.name = "qhm_qup0",
 231	.channels = 1,
 232	.buswidth = 4,
 233	.num_links = 1,
 234	.link_nodes = { &qns_a1noc_snoc },
 235};
 236
 237static struct qcom_icc_node qhm_qup1 = {
 238	.name = "qhm_qup1",
 239	.channels = 1,
 240	.buswidth = 4,
 241	.num_links = 1,
 242	.link_nodes = { &qns_a1noc_snoc },
 243};
 244
 245static struct qcom_icc_node qhm_system_noc_cfg = {
 246	.name = "qhm_system_noc_cfg",
 247	.channels = 1,
 248	.buswidth = 4,
 249	.num_links = 1,
 250	.link_nodes = { &srvc_system_noc },
 251};
 252
 253static struct qcom_icc_node qnm_aggre_noc = {
 254	.name = "qnm_aggre_noc",
 255	.channels = 1,
 256	.buswidth = 8,
 257	.num_links = 1,
 258	.link_nodes = { &qns_gemnoc_sf },
 259};
 260
 261static struct qcom_icc_node qnm_aggre_noc_gsi = {
 262	.name = "qnm_aggre_noc_gsi",
 263	.channels = 1,
 264	.buswidth = 8,
 265	.num_links = 1,
 266	.link_nodes = { &qns_gemnoc_gc },
 267};
 268
 269static struct qcom_icc_node qnm_gemnoc_cnoc = {
 270	.name = "qnm_gemnoc_cnoc",
 271	.channels = 1,
 272	.buswidth = 16,
 273	.num_links = 36,
 274	.link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north,
 275			&qhs_ahb2phy2_east, &qhs_aoss,
 276			&qhs_clk_ctl, &qhs_cpr_cx,
 277			&qhs_cpr_mx, &qhs_crypto_cfg,
 278			&qhs_ecpri_cfg, &qhs_imem_cfg,
 279			&qhs_ipc_router, &qhs_mss_cfg,
 280			&qhs_pcie_cfg, &qhs_pdm,
 281			&qhs_pimem_cfg, &qhs_prng,
 282			&qhs_qdss_cfg, &qhs_qpic,
 283			&qhs_qspi, &qhs_qup0,
 284			&qhs_qup1, &qhs_sdc2,
 285			&qhs_smbus_cfg, &qhs_system_noc_cfg,
 286			&qhs_tcsr, &qhs_tlmm,
 287			&qhs_tme_cfg, &qhs_tsc_cfg,
 288			&qhs_usb3, &qhs_vsense_ctrl_cfg,
 289			&qns_ddrss_cfg, &qxs_imem,
 290			&qxs_pimem, &xs_ethernet_ss,
 291			&xs_qdss_stm, &xs_sys_tcu_cfg },
 292};
 293
 294static struct qcom_icc_node qnm_gemnoc_modem_slave = {
 295	.name = "qnm_gemnoc_modem_slave",
 296	.channels = 1,
 297	.buswidth = 16,
 298	.num_links = 1,
 299	.link_nodes = { &qns_modem },
 300};
 301
 302static struct qcom_icc_node qnm_gemnoc_pcie = {
 303	.name = "qnm_gemnoc_pcie",
 304	.channels = 1,
 305	.buswidth = 16,
 306	.num_links = 1,
 307	.link_nodes = { &xs_pcie },
 308};
 309
 310static struct qcom_icc_node qxm_crypto = {
 311	.name = "qxm_crypto",
 312	.channels = 1,
 313	.buswidth = 8,
 314	.num_links = 1,
 315	.link_nodes = { &qns_a1noc_snoc },
 316};
 317
 318static struct qcom_icc_node qxm_ecpri_gsi = {
 319	.name = "qxm_ecpri_gsi",
 320	.channels = 1,
 321	.buswidth = 8,
 322	.num_links = 2,
 323	.link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie },
 324};
 325
 326static struct qcom_icc_node qxm_pimem = {
 327	.name = "qxm_pimem",
 328	.channels = 1,
 329	.buswidth = 8,
 330	.num_links = 1,
 331	.link_nodes = { &qns_gemnoc_gc },
 332};
 333
 334static struct qcom_icc_node xm_ecpri_dma = {
 335	.name = "xm_ecpri_dma",
 336	.channels = 2,
 337	.buswidth = 32,
 338	.num_links = 2,
 339	.link_nodes = { &qns_ecpri_gemnoc, &xs_pcie },
 340};
 341
 342static struct qcom_icc_node xm_gic = {
 343	.name = "xm_gic",
 344	.channels = 1,
 345	.buswidth = 8,
 346	.num_links = 1,
 347	.link_nodes = { &qns_gemnoc_gc },
 348};
 349
 350static struct qcom_icc_node xm_pcie = {
 351	.name = "xm_pcie",
 352	.channels = 1,
 353	.buswidth = 64,
 354	.num_links = 1,
 355	.link_nodes = { &qns_pcie_gemnoc },
 356};
 357
 358static struct qcom_icc_node xm_qdss_etr0 = {
 359	.name = "xm_qdss_etr0",
 360	.channels = 1,
 361	.buswidth = 8,
 362	.num_links = 1,
 363	.link_nodes = { &qns_gemnoc_sf },
 364};
 365
 366static struct qcom_icc_node xm_qdss_etr1 = {
 367	.name = "xm_qdss_etr1",
 368	.channels = 1,
 369	.buswidth = 8,
 370	.num_links = 1,
 371	.link_nodes = { &qns_gemnoc_sf },
 372};
 373
 374static struct qcom_icc_node xm_sdc = {
 375	.name = "xm_sdc",
 376	.channels = 1,
 377	.buswidth = 8,
 378	.num_links = 1,
 379	.link_nodes = { &qns_a1noc_snoc },
 380};
 381
 382static struct qcom_icc_node xm_usb3 = {
 383	.name = "xm_usb3",
 384	.channels = 1,
 385	.buswidth = 8,
 386	.num_links = 1,
 387	.link_nodes = { &qns_a1noc_snoc },
 388};
 389
 390static struct qcom_icc_node qup0_core_slave = {
 391	.name = "qup0_core_slave",
 392	.channels = 1,
 393	.buswidth = 4,
 394};
 395
 396static struct qcom_icc_node qup1_core_slave = {
 397	.name = "qup1_core_slave",
 398	.channels = 1,
 399	.buswidth = 4,
 400};
 401
 402static struct qcom_icc_node qns_gem_noc_cnoc = {
 403	.name = "qns_gem_noc_cnoc",
 404	.channels = 1,
 405	.buswidth = 16,
 406	.num_links = 1,
 407	.link_nodes = { &qnm_gemnoc_cnoc },
 408};
 409
 410static struct qcom_icc_node qns_llcc = {
 411	.name = "qns_llcc",
 412	.channels = 8,
 413	.buswidth = 16,
 414	.num_links = 1,
 415	.link_nodes = { &llcc_mc },
 416};
 417
 418static struct qcom_icc_node qns_modem_slave = {
 419	.name = "qns_modem_slave",
 420	.channels = 1,
 421	.buswidth = 16,
 422	.num_links = 1,
 423	.link_nodes = { &qnm_gemnoc_modem_slave },
 424};
 425
 426static struct qcom_icc_node qns_pcie = {
 427	.name = "qns_pcie",
 428	.channels = 1,
 429	.buswidth = 16,
 430	.num_links = 1,
 431	.link_nodes = { &qnm_gemnoc_pcie },
 432};
 433
 434static struct qcom_icc_node ebi = {
 435	.name = "ebi",
 436	.channels = 8,
 437	.buswidth = 4,
 438};
 439
 440static struct qcom_icc_node qhs_ahb2phy0_south = {
 441	.name = "qhs_ahb2phy0_south",
 442	.channels = 1,
 443	.buswidth = 4,
 444};
 445
 446static struct qcom_icc_node qhs_ahb2phy1_north = {
 447	.name = "qhs_ahb2phy1_north",
 448	.channels = 1,
 449	.buswidth = 4,
 450};
 451
 452static struct qcom_icc_node qhs_ahb2phy2_east = {
 453	.name = "qhs_ahb2phy2_east",
 454	.channels = 1,
 455	.buswidth = 4,
 456};
 457
 458static struct qcom_icc_node qhs_aoss = {
 459	.name = "qhs_aoss",
 460	.channels = 1,
 461	.buswidth = 4,
 462};
 463
 464static struct qcom_icc_node qhs_clk_ctl = {
 465	.name = "qhs_clk_ctl",
 466	.channels = 1,
 467	.buswidth = 4,
 468};
 469
 470static struct qcom_icc_node qhs_cpr_cx = {
 471	.name = "qhs_cpr_cx",
 472	.channels = 1,
 473	.buswidth = 4,
 474};
 475
 476static struct qcom_icc_node qhs_cpr_mx = {
 477	.name = "qhs_cpr_mx",
 478	.channels = 1,
 479	.buswidth = 4,
 480};
 481
 482static struct qcom_icc_node qhs_crypto_cfg = {
 483	.name = "qhs_crypto_cfg",
 484	.channels = 1,
 485	.buswidth = 4,
 486};
 487
 488static struct qcom_icc_node qhs_ecpri_cfg = {
 489	.name = "qhs_ecpri_cfg",
 490	.channels = 1,
 491	.buswidth = 4,
 492};
 493
 494static struct qcom_icc_node qhs_imem_cfg = {
 495	.name = "qhs_imem_cfg",
 496	.channels = 1,
 497	.buswidth = 4,
 498};
 499
 500static struct qcom_icc_node qhs_ipc_router = {
 501	.name = "qhs_ipc_router",
 502	.channels = 1,
 503	.buswidth = 4,
 504};
 505
 506static struct qcom_icc_node qhs_mss_cfg = {
 507	.name = "qhs_mss_cfg",
 508	.channels = 1,
 509	.buswidth = 4,
 510};
 511
 512static struct qcom_icc_node qhs_pcie_cfg = {
 513	.name = "qhs_pcie_cfg",
 514	.channels = 1,
 515	.buswidth = 4,
 516};
 517
 518static struct qcom_icc_node qhs_pdm = {
 519	.name = "qhs_pdm",
 520	.channels = 1,
 521	.buswidth = 4,
 522};
 523
 524static struct qcom_icc_node qhs_pimem_cfg = {
 525	.name = "qhs_pimem_cfg",
 526	.channels = 1,
 527	.buswidth = 4,
 528};
 529
 530static struct qcom_icc_node qhs_prng = {
 531	.name = "qhs_prng",
 532	.channels = 1,
 533	.buswidth = 4,
 534};
 535
 536static struct qcom_icc_node qhs_qdss_cfg = {
 537	.name = "qhs_qdss_cfg",
 538	.channels = 1,
 539	.buswidth = 4,
 540};
 541
 542static struct qcom_icc_node qhs_qpic = {
 543	.name = "qhs_qpic",
 544	.channels = 1,
 545	.buswidth = 4,
 546};
 547
 548static struct qcom_icc_node qhs_qspi = {
 549	.name = "qhs_qspi",
 550	.channels = 1,
 551	.buswidth = 4,
 552};
 553
 554static struct qcom_icc_node qhs_qup0 = {
 555	.name = "qhs_qup0",
 556	.channels = 1,
 557	.buswidth = 4,
 558};
 559
 560static struct qcom_icc_node qhs_qup1 = {
 561	.name = "qhs_qup1",
 562	.channels = 1,
 563	.buswidth = 4,
 564};
 565
 566static struct qcom_icc_node qhs_sdc2 = {
 567	.name = "qhs_sdc2",
 568	.channels = 1,
 569	.buswidth = 4,
 570};
 571
 572static struct qcom_icc_node qhs_smbus_cfg = {
 573	.name = "qhs_smbus_cfg",
 574	.channels = 1,
 575	.buswidth = 4,
 576};
 577
 578static struct qcom_icc_node qhs_system_noc_cfg = {
 579	.name = "qhs_system_noc_cfg",
 580	.channels = 1,
 581	.buswidth = 4,
 582	.num_links = 1,
 583	.link_nodes = { &qhm_system_noc_cfg },
 584};
 585
 586static struct qcom_icc_node qhs_tcsr = {
 587	.name = "qhs_tcsr",
 588	.channels = 1,
 589	.buswidth = 4,
 590};
 591
 592static struct qcom_icc_node qhs_tlmm = {
 593	.name = "qhs_tlmm",
 594	.channels = 1,
 595	.buswidth = 4,
 596};
 597
 598static struct qcom_icc_node qhs_tme_cfg = {
 599	.name = "qhs_tme_cfg",
 600	.channels = 1,
 601	.buswidth = 4,
 602};
 603
 604static struct qcom_icc_node qhs_tsc_cfg = {
 605	.name = "qhs_tsc_cfg",
 606	.channels = 1,
 607	.buswidth = 4,
 608};
 609
 610static struct qcom_icc_node qhs_usb3 = {
 611	.name = "qhs_usb3",
 612	.channels = 1,
 613	.buswidth = 4,
 614};
 615
 616static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
 617	.name = "qhs_vsense_ctrl_cfg",
 618	.channels = 1,
 619	.buswidth = 4,
 620};
 621
 622static struct qcom_icc_node qns_a1noc_snoc = {
 623	.name = "qns_a1noc_snoc",
 624	.channels = 1,
 625	.buswidth = 8,
 626	.num_links = 1,
 627	.link_nodes = { &qnm_aggre_noc },
 628};
 629
 630static struct qcom_icc_node qns_anoc_snoc_gsi = {
 631	.name = "qns_anoc_snoc_gsi",
 632	.channels = 1,
 633	.buswidth = 8,
 634	.num_links = 1,
 635	.link_nodes = { &qnm_aggre_noc_gsi },
 636};
 637
 638static struct qcom_icc_node qns_ddrss_cfg = {
 639	.name = "qns_ddrss_cfg",
 640	.channels = 1,
 641	.buswidth = 4,
 642};
 643
 644static struct qcom_icc_node qns_ecpri_gemnoc = {
 645	.name = "qns_ecpri_gemnoc",
 646	.channels = 2,
 647	.buswidth = 32,
 648	.num_links = 1,
 649	.link_nodes = { &qnm_ecpri_dma },
 650};
 651
 652static struct qcom_icc_node qns_gemnoc_gc = {
 653	.name = "qns_gemnoc_gc",
 654	.channels = 1,
 655	.buswidth = 8,
 656	.num_links = 1,
 657	.link_nodes = { &qnm_snoc_gc },
 658};
 659
 660static struct qcom_icc_node qns_gemnoc_sf = {
 661	.name = "qns_gemnoc_sf",
 662	.channels = 1,
 663	.buswidth = 16,
 664	.num_links = 1,
 665	.link_nodes = { &qnm_snoc_sf },
 666};
 667
 668static struct qcom_icc_node qns_modem = {
 669	.name = "qns_modem",
 670	.channels = 1,
 671	.buswidth = 32,
 672};
 673
 674static struct qcom_icc_node qns_pcie_gemnoc = {
 675	.name = "qns_pcie_gemnoc",
 676	.channels = 1,
 677	.buswidth = 64,
 678	.num_links = 1,
 679	.link_nodes = { &qnm_pcie },
 680};
 681
 682static struct qcom_icc_node qxs_imem = {
 683	.name = "qxs_imem",
 684	.channels = 1,
 685	.buswidth = 8,
 686};
 687
 688static struct qcom_icc_node qxs_pimem = {
 689	.name = "qxs_pimem",
 690	.channels = 1,
 691	.buswidth = 8,
 692};
 693
 694static struct qcom_icc_node srvc_system_noc = {
 695	.name = "srvc_system_noc",
 696	.channels = 1,
 697	.buswidth = 4,
 698};
 699
 700static struct qcom_icc_node xs_ethernet_ss = {
 701	.name = "xs_ethernet_ss",
 702	.channels = 1,
 703	.buswidth = 32,
 704};
 705
 706static struct qcom_icc_node xs_pcie = {
 707	.name = "xs_pcie",
 708	.channels = 1,
 709	.buswidth = 64,
 710};
 711
 712static struct qcom_icc_node xs_qdss_stm = {
 713	.name = "xs_qdss_stm",
 714	.channels = 1,
 715	.buswidth = 4,
 716};
 717
 718static struct qcom_icc_node xs_sys_tcu_cfg = {
 719	.name = "xs_sys_tcu_cfg",
 720	.channels = 1,
 721	.buswidth = 8,
 722};
 723
 724static struct qcom_icc_bcm bcm_acv = {
 725	.name = "ACV",
 726	.enable_mask = BIT(3),
 727	.num_nodes = 1,
 728	.nodes = { &ebi },
 729};
 730
 731static struct qcom_icc_bcm bcm_ce0 = {
 732	.name = "CE0",
 733	.num_nodes = 1,
 734	.nodes = { &qxm_crypto },
 735};
 736
 737static struct qcom_icc_bcm bcm_cn0 = {
 738	.name = "CN0",
 739	.num_nodes = 44,
 740	.nodes = { &qhm_qpic, &qhm_qspi,
 741		   &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
 742		   &qnm_gemnoc_pcie, &xm_sdc,
 743		   &xm_usb3, &qhs_ahb2phy0_south,
 744		   &qhs_ahb2phy1_north, &qhs_ahb2phy2_east,
 745		   &qhs_aoss, &qhs_clk_ctl,
 746		   &qhs_cpr_cx, &qhs_cpr_mx,
 747		   &qhs_crypto_cfg, &qhs_ecpri_cfg,
 748		   &qhs_imem_cfg, &qhs_ipc_router,
 749		   &qhs_mss_cfg, &qhs_pcie_cfg,
 750		   &qhs_pdm, &qhs_pimem_cfg,
 751		   &qhs_prng, &qhs_qdss_cfg,
 752		   &qhs_qpic, &qhs_qspi,
 753		   &qhs_qup0, &qhs_qup1,
 754		   &qhs_sdc2, &qhs_smbus_cfg,
 755		   &qhs_system_noc_cfg, &qhs_tcsr,
 756		   &qhs_tlmm, &qhs_tme_cfg,
 757		   &qhs_tsc_cfg, &qhs_usb3,
 758		   &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
 759		   &qns_modem, &qxs_imem,
 760		   &qxs_pimem, &xs_ethernet_ss,
 761		   &xs_qdss_stm, &xs_sys_tcu_cfg
 762	},
 763};
 764
 765static struct qcom_icc_bcm bcm_mc0 = {
 766	.name = "MC0",
 767	.num_nodes = 1,
 768	.nodes = { &ebi },
 769};
 770
 771static struct qcom_icc_bcm bcm_qup0 = {
 772	.name = "QUP0",
 773	.num_nodes = 2,
 774	.nodes = { &qup0_core_slave, &qup1_core_slave },
 775};
 776
 777static struct qcom_icc_bcm bcm_sh0 = {
 778	.name = "SH0",
 779	.num_nodes = 1,
 780	.nodes = { &qns_llcc },
 781};
 782
 783static struct qcom_icc_bcm bcm_sh1 = {
 784	.name = "SH1",
 785	.num_nodes = 11,
 786	.nodes = { &alm_sys_tcu, &chm_apps,
 787		   &qnm_ecpri_dma, &qnm_fec_2_gemnoc,
 788		   &qnm_pcie, &qnm_snoc_gc,
 789		   &qnm_snoc_sf, &qxm_mdsp,
 790		   &qns_gem_noc_cnoc, &qns_modem_slave,
 791		   &qns_pcie
 792	},
 793};
 794
 795static struct qcom_icc_bcm bcm_sn0 = {
 796	.name = "SN0",
 797	.num_nodes = 1,
 798	.nodes = { &qns_gemnoc_sf },
 799};
 800
 801static struct qcom_icc_bcm bcm_sn1 = {
 802	.name = "SN1",
 803	.num_nodes = 6,
 804	.nodes = { &qhm_gic, &qxm_pimem,
 805		   &xm_gic, &xm_qdss_etr0,
 806		   &xm_qdss_etr1, &qns_gemnoc_gc
 807	},
 808};
 809
 810static struct qcom_icc_bcm bcm_sn2 = {
 811	.name = "SN2",
 812	.num_nodes = 5,
 813	.nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
 814		   &xm_ecpri_dma, &qns_anoc_snoc_gsi,
 815		   &qns_ecpri_gemnoc
 816	},
 817};
 818
 819static struct qcom_icc_bcm bcm_sn7 = {
 820	.name = "SN7",
 821	.num_nodes = 2,
 822	.nodes = { &qns_pcie_gemnoc, &xs_pcie },
 823};
 824
 825static struct qcom_icc_bcm * const clk_virt_bcms[] = {
 826	&bcm_qup0,
 827};
 828
 829static struct qcom_icc_node * const clk_virt_nodes[] = {
 830	[MASTER_QUP_CORE_0] = &qup0_core_master,
 831	[MASTER_QUP_CORE_1] = &qup1_core_master,
 832	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
 833	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
 834};
 835
 836static const struct qcom_icc_desc qdu1000_clk_virt = {
 837	.nodes = clk_virt_nodes,
 838	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
 839	.bcms = clk_virt_bcms,
 840	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
 841};
 842
 843static struct qcom_icc_bcm * const gem_noc_bcms[] = {
 844	&bcm_sh0,
 845	&bcm_sh1,
 846};
 847
 848static struct qcom_icc_node * const gem_noc_nodes[] = {
 849	[MASTER_SYS_TCU] = &alm_sys_tcu,
 850	[MASTER_APPSS_PROC] = &chm_apps,
 851	[MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma,
 852	[MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc,
 853	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
 854	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
 855	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 856	[MASTER_MSS_PROC] = &qxm_mdsp,
 857	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
 858	[SLAVE_LLCC] = &qns_llcc,
 859	[SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave,
 860	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
 861};
 862
 863static const struct qcom_icc_desc qdu1000_gem_noc = {
 864	.nodes = gem_noc_nodes,
 865	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
 866	.bcms = gem_noc_bcms,
 867	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
 868};
 869
 870static struct qcom_icc_bcm * const mc_virt_bcms[] = {
 871	&bcm_acv,
 872	&bcm_mc0,
 873};
 874
 875static struct qcom_icc_node * const mc_virt_nodes[] = {
 876	[MASTER_LLCC] = &llcc_mc,
 877	[SLAVE_EBI1] = &ebi,
 878};
 879
 880static const struct qcom_icc_desc qdu1000_mc_virt = {
 881	.nodes = mc_virt_nodes,
 882	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
 883	.bcms = mc_virt_bcms,
 884	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
 885};
 886
 887static struct qcom_icc_bcm * const system_noc_bcms[] = {
 888	&bcm_ce0,
 889	&bcm_cn0,
 890	&bcm_sn0,
 891	&bcm_sn1,
 892	&bcm_sn2,
 893	&bcm_sn7,
 894};
 895
 896static struct qcom_icc_node * const system_noc_nodes[] = {
 897	[MASTER_GIC_AHB] = &qhm_gic,
 898	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
 899	[MASTER_QPIC] = &qhm_qpic,
 900	[MASTER_QSPI_0] = &qhm_qspi,
 901	[MASTER_QUP_0] = &qhm_qup0,
 902	[MASTER_QUP_1] = &qhm_qup1,
 903	[MASTER_SNOC_CFG] = &qhm_system_noc_cfg,
 904	[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
 905	[MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi,
 906	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
 907	[MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave,
 908	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
 909	[MASTER_CRYPTO] = &qxm_crypto,
 910	[MASTER_ECPRI_GSI] = &qxm_ecpri_gsi,
 911	[MASTER_PIMEM] = &qxm_pimem,
 912	[MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma,
 913	[MASTER_GIC] = &xm_gic,
 914	[MASTER_PCIE] = &xm_pcie,
 915	[MASTER_QDSS_ETR] = &xm_qdss_etr0,
 916	[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
 917	[MASTER_SDCC_1] = &xm_sdc,
 918	[MASTER_USB3] = &xm_usb3,
 919	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south,
 920	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north,
 921	[SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east,
 922	[SLAVE_AOSS] = &qhs_aoss,
 923	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
 924	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
 925	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
 926	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
 927	[SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg,
 928	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 929	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
 930	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
 931	[SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
 932	[SLAVE_PDM] = &qhs_pdm,
 933	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
 934	[SLAVE_PRNG] = &qhs_prng,
 935	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 936	[SLAVE_QPIC] = &qhs_qpic,
 937	[SLAVE_QSPI_0] = &qhs_qspi,
 938	[SLAVE_QUP_0] = &qhs_qup0,
 939	[SLAVE_QUP_1] = &qhs_qup1,
 940	[SLAVE_SDCC_2] = &qhs_sdc2,
 941	[SLAVE_SMBUS_CFG] = &qhs_smbus_cfg,
 942	[SLAVE_SNOC_CFG] = &qhs_system_noc_cfg,
 943	[SLAVE_TCSR] = &qhs_tcsr,
 944	[SLAVE_TLMM] = &qhs_tlmm,
 945	[SLAVE_TME_CFG] = &qhs_tme_cfg,
 946	[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
 947	[SLAVE_USB3_0] = &qhs_usb3,
 948	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
 949	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
 950	[SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi,
 951	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
 952	[SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc,
 953	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
 954	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 955	[SLAVE_MODEM_OFFLINE] = &qns_modem,
 956	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
 957	[SLAVE_IMEM] = &qxs_imem,
 958	[SLAVE_PIMEM] = &qxs_pimem,
 959	[SLAVE_SERVICE_SNOC] = &srvc_system_noc,
 960	[SLAVE_ETHERNET_SS] = &xs_ethernet_ss,
 961	[SLAVE_PCIE_0] = &xs_pcie,
 962	[SLAVE_QDSS_STM] = &xs_qdss_stm,
 963	[SLAVE_TCU] = &xs_sys_tcu_cfg,
 964};
 965
 966static const struct qcom_icc_desc qdu1000_system_noc = {
 967	.nodes = system_noc_nodes,
 968	.num_nodes = ARRAY_SIZE(system_noc_nodes),
 969	.bcms = system_noc_bcms,
 970	.num_bcms = ARRAY_SIZE(system_noc_bcms),
 971};
 972
 973static int qnoc_probe(struct platform_device *pdev)
 974{
 975	int ret;
 976
 977	ret = qcom_icc_rpmh_probe(pdev);
 978	if (ret)
 979		dev_err(&pdev->dev, "failed to register ICC provider\n");
 980
 981	return ret;
 982}
 983
 984static const struct of_device_id qnoc_of_match[] = {
 985	{ .compatible = "qcom,qdu1000-clk-virt",
 986	  .data = &qdu1000_clk_virt
 987	},
 988	{ .compatible = "qcom,qdu1000-gem-noc",
 989	  .data = &qdu1000_gem_noc
 990	},
 991	{ .compatible = "qcom,qdu1000-mc-virt",
 992	  .data = &qdu1000_mc_virt
 993	},
 994	{ .compatible = "qcom,qdu1000-system-noc",
 995	  .data = &qdu1000_system_noc
 996	},
 997	{ }
 998};
 999MODULE_DEVICE_TABLE(of, qnoc_of_match);
1000
1001static struct platform_driver qnoc_driver = {
1002	.probe = qnoc_probe,
1003	.remove = qcom_icc_rpmh_remove,
1004	.driver = {
1005		.name = "qnoc-qdu1000",
1006		.of_match_table = qnoc_of_match,
1007	},
1008};
1009
1010static int __init qnoc_driver_init(void)
1011{
1012	return platform_driver_register(&qnoc_driver);
1013}
1014core_initcall(qnoc_driver_init);
1015
1016static void __exit qnoc_driver_exit(void)
1017{
1018	platform_driver_unregister(&qnoc_driver);
1019}
1020module_exit(qnoc_driver_exit);
1021
1022MODULE_DESCRIPTION("QDU1000 NoC driver");
1023MODULE_LICENSE("GPL");