osm-l3.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
  5 */
  6
  7#include <linux/args.h>
  8#include <linux/bitfield.h>
  9#include <linux/clk.h>
 10#include <linux/interconnect-provider.h>
 11#include <linux/io.h>
 12#include <linux/kernel.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/platform_device.h>
 16
 17#include <dt-bindings/interconnect/qcom,osm-l3.h>
 18
 19#define LUT_MAX_ENTRIES			40U
 20#define LUT_SRC				GENMASK(31, 30)
 21#define LUT_L_VAL			GENMASK(7, 0)
 22#define CLK_HW_DIV			2
 23
 24/* OSM Register offsets */
 25#define REG_ENABLE			0x0
 26#define OSM_LUT_ROW_SIZE		32
 27#define OSM_REG_FREQ_LUT		0x110
 28#define OSM_REG_PERF_STATE		0x920
 29
 30/* EPSS Register offsets */
 31#define EPSS_LUT_ROW_SIZE		4
 32#define EPSS_REG_L3_VOTE		0x90
 33#define EPSS_REG_FREQ_LUT		0x100
 34#define EPSS_REG_PERF_STATE		0x320
 35
 36#define to_osm_l3_provider(_provider) \
 37	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
 38
 39struct qcom_osm_l3_icc_provider {
 40	void __iomem *base;
 41	unsigned int max_state;
 42	unsigned int reg_perf_state;
 43	unsigned long lut_tables[LUT_MAX_ENTRIES];
 44	struct icc_provider provider;
 45};
 46
 47/**
 48 * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
 49 * @name: the node name used in debugfs
 50 * @buswidth: width of the interconnect between a node and the bus
 51 */
 52struct qcom_osm_l3_node {
 53	const char *name;
 54	u16 buswidth;
 55};
 56
 57struct qcom_osm_l3_desc {
 58	const struct qcom_osm_l3_node * const *nodes;
 59	size_t num_nodes;
 60	unsigned int lut_row_size;
 61	unsigned int reg_freq_lut;
 62	unsigned int reg_perf_state;
 63};
 64
 65#define DEFINE_QNODE(_name, _buswidth)					\
 66	static const struct qcom_osm_l3_node _name = {			\
 67		.name = #_name,						\
 68		.buswidth = _buswidth,					\
 69	}
 70
 71DEFINE_QNODE(osm_l3_slave, 16);
 72DEFINE_QNODE(osm_l3_master, 16);
 73
 74static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
 75	[MASTER_OSM_L3_APPS] = &osm_l3_master,
 76	[SLAVE_OSM_L3] = &osm_l3_slave,
 77};
 78
 79DEFINE_QNODE(epss_l3_slave, 32);
 80DEFINE_QNODE(epss_l3_master, 32);
 81
 82static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
 83	[MASTER_EPSS_L3_APPS] = &epss_l3_master,
 84	[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
 85};
 86
 87static const struct qcom_osm_l3_desc osm_l3 = {
 88	.nodes = osm_l3_nodes,
 89	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 90	.lut_row_size = OSM_LUT_ROW_SIZE,
 91	.reg_freq_lut = OSM_REG_FREQ_LUT,
 92	.reg_perf_state = OSM_REG_PERF_STATE,
 93};
 94
 95static const struct qcom_osm_l3_desc epss_l3_perf_state = {
 96	.nodes = epss_l3_nodes,
 97	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
 98	.lut_row_size = EPSS_LUT_ROW_SIZE,
 99	.reg_freq_lut = EPSS_REG_FREQ_LUT,
100	.reg_perf_state = EPSS_REG_PERF_STATE,
101};
102
103static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
104	.nodes = epss_l3_nodes,
105	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
106	.lut_row_size = EPSS_LUT_ROW_SIZE,
107	.reg_freq_lut = EPSS_REG_FREQ_LUT,
108	.reg_perf_state = EPSS_REG_L3_VOTE,
109};
110
111static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
112{
113	struct qcom_osm_l3_icc_provider *qp;
114	struct icc_provider *provider;
115	const struct qcom_osm_l3_node *qn;
116	unsigned int index;
117	u64 rate;
118
119	qn = src->data;
120	provider = src->provider;
121	qp = to_osm_l3_provider(provider);
122
123	rate = icc_units_to_bps(dst->peak_bw);
124	do_div(rate, qn->buswidth);
125
126	for (index = 0; index < qp->max_state - 1; index++) {
127		if (qp->lut_tables[index] >= rate)
128			break;
129	}
130
131	writel_relaxed(index, qp->base + qp->reg_perf_state);
132
133	return 0;
134}
135
136static void qcom_osm_l3_remove(struct platform_device *pdev)
137{
138	struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
139
140	icc_provider_deregister(&qp->provider);
141	icc_nodes_remove(&qp->provider);
142}
143
144static int qcom_osm_l3_probe(struct platform_device *pdev)
145{
146	u32 info, src, lval, i, prev_freq = 0, freq;
147	static unsigned long hw_rate, xo_rate;
148	struct qcom_osm_l3_icc_provider *qp;
149	const struct qcom_osm_l3_desc *desc;
150	struct icc_onecell_data *data;
151	struct icc_provider *provider;
152	const struct qcom_osm_l3_node * const *qnodes;
153	struct icc_node *node;
154	size_t num_nodes;
155	struct clk *clk;
156	int ret;
157
158	clk = clk_get(&pdev->dev, "xo");
159	if (IS_ERR(clk))
160		return PTR_ERR(clk);
161
162	xo_rate = clk_get_rate(clk);
163	clk_put(clk);
164
165	clk = clk_get(&pdev->dev, "alternate");
166	if (IS_ERR(clk))
167		return PTR_ERR(clk);
168
169	hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
170	clk_put(clk);
171
172	qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
173	if (!qp)
174		return -ENOMEM;
175
176	qp->base = devm_platform_ioremap_resource(pdev, 0);
177	if (IS_ERR(qp->base))
178		return PTR_ERR(qp->base);
179
180	/* HW should be in enabled state to proceed */
181	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
182		dev_err(&pdev->dev, "error hardware not enabled\n");
183		return -ENODEV;
184	}
185
186	desc = device_get_match_data(&pdev->dev);
187	if (!desc)
188		return -EINVAL;
189
190	qp->reg_perf_state = desc->reg_perf_state;
191
192	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
193		info = readl_relaxed(qp->base + desc->reg_freq_lut +
194				     i * desc->lut_row_size);
195		src = FIELD_GET(LUT_SRC, info);
196		lval = FIELD_GET(LUT_L_VAL, info);
197		if (src)
198			freq = xo_rate * lval;
199		else
200			freq = hw_rate;
201
202		/* Two of the same frequencies signify end of table */
203		if (i > 0 && prev_freq == freq)
204			break;
205
206		dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
207
208		qp->lut_tables[i] = freq;
209		prev_freq = freq;
210	}
211	qp->max_state = i;
212
213	qnodes = desc->nodes;
214	num_nodes = desc->num_nodes;
215
216	data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes), GFP_KERNEL);
217	if (!data)
218		return -ENOMEM;
219	data->num_nodes = num_nodes;
220
221	provider = &qp->provider;
222	provider->dev = &pdev->dev;
223	provider->set = qcom_osm_l3_set;
224	provider->aggregate = icc_std_aggregate;
225	provider->xlate = of_icc_xlate_onecell;
226	provider->data = data;
227
228	icc_provider_init(provider);
229
230	/* Create nodes */
231	for (i = 0; i < num_nodes; i++) {
232		node = icc_node_create_dyn();
233
234		if (IS_ERR(node)) {
235			ret = PTR_ERR(node);
236			goto err;
237		}
238
239		ret = icc_node_set_name(node, provider, qnodes[i]->name);
240		if (ret) {
241			icc_node_destroy(node->id);
242			goto err;
243		}
244
245		/* Cast away const and add it back in qcom_osm_l3_set() */
246		node->data = (void *)qnodes[i];
247		icc_node_add(node, provider);
248
249		data->nodes[i] = node;
250	}
251
252	/* Create link */
253	icc_link_nodes(data->nodes[MASTER_OSM_L3_APPS], &data->nodes[SLAVE_OSM_L3]);
254
255	ret = icc_provider_register(provider);
256	if (ret)
257		goto err;
258
259	platform_set_drvdata(pdev, qp);
260
261	return 0;
262err:
263	icc_nodes_remove(provider);
264
265	return ret;
266}
267
268static const struct of_device_id osm_l3_of_match[] = {
269	{ .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
270	{ .compatible = "qcom,osm-l3", .data = &osm_l3 },
271	{ .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state },
272	{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
273	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
274	{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
275	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
276	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
277	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
278	{ }
279};
280MODULE_DEVICE_TABLE(of, osm_l3_of_match);
281
282static struct platform_driver osm_l3_driver = {
283	.probe = qcom_osm_l3_probe,
284	.remove = qcom_osm_l3_remove,
285	.driver = {
286		.name = "osm-l3",
287		.of_match_table = osm_l3_of_match,
288		.sync_state = icc_sync_state,
289	},
290};
291module_platform_driver(osm_l3_driver);
292
293MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
294MODULE_LICENSE("GPL v2");