msm8976.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Based on data from msm8976-bus.dtsi in Qualcomm's msm-3.10 release:
   4 *   Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/mod_devicetable.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/regmap.h>
  13
  14#include <dt-bindings/interconnect/qcom,msm8976.h>
  15
  16#include "icc-rpm.h"
  17
  18enum {
  19	QNOC_MASTER_AMPSS_M0 = 1,
  20	QNOC_MNOC_BIMC_MAS,
  21	QNOC_SNOC_BIMC_MAS,
  22	QNOC_MASTER_TCU_0,
  23	QNOC_MASTER_USB_HS2,
  24	QNOC_MASTER_BLSP_1,
  25	QNOC_MASTER_USB_HS,
  26	QNOC_MASTER_BLSP_2,
  27	QNOC_MASTER_CRYPTO_CORE0,
  28	QNOC_MASTER_SDCC_1,
  29	QNOC_MASTER_SDCC_2,
  30	QNOC_MASTER_SDCC_3,
  31	QNOC_SNOC_PNOC_MAS,
  32	QNOC_MASTER_LPASS_AHB,
  33	QNOC_MASTER_SPDM,
  34	QNOC_MASTER_DEHR,
  35	QNOC_MASTER_XM_USB_HS1,
  36	QNOC_MASTER_QDSS_BAM,
  37	QNOC_BIMC_SNOC_MAS,
  38	QNOC_MASTER_JPEG,
  39	QNOC_MASTER_GRAPHICS_3D,
  40	QNOC_MASTER_MDP_PORT0,
  41	QNOC_MASTER_MDP_PORT1,
  42	QNOC_PNOC_SNOC_MAS,
  43	QNOC_MASTER_VIDEO_P0,
  44	QNOC_MASTER_VIDEO_P1,
  45	QNOC_MASTER_VFE0,
  46	QNOC_MASTER_VFE1,
  47	QNOC_MASTER_CPP,
  48	QNOC_MASTER_QDSS_ETR,
  49	QNOC_MASTER_LPASS_PROC,
  50	QNOC_MASTER_IPA,
  51	QNOC_PNOC_M_0,
  52	QNOC_PNOC_M_1,
  53	QNOC_PNOC_INT_0,
  54	QNOC_PNOC_INT_1,
  55	QNOC_PNOC_INT_2,
  56	QNOC_PNOC_SLV_1,
  57	QNOC_PNOC_SLV_2,
  58	QNOC_PNOC_SLV_3,
  59	QNOC_PNOC_SLV_4,
  60	QNOC_PNOC_SLV_8,
  61	QNOC_PNOC_SLV_9,
  62	QNOC_SNOC_MM_INT_0,
  63	QNOC_SNOC_QDSS_INT,
  64	QNOC_SNOC_INT_0,
  65	QNOC_SNOC_INT_1,
  66	QNOC_SNOC_INT_2,
  67	QNOC_SLAVE_EBI_CH0,
  68	QNOC_BIMC_SNOC_SLV,
  69	QNOC_SLAVE_TCSR,
  70	QNOC_SLAVE_TLMM,
  71	QNOC_SLAVE_CRYPTO_0_CFG,
  72	QNOC_SLAVE_MESSAGE_RAM,
  73	QNOC_SLAVE_PDM,
  74	QNOC_SLAVE_PRNG,
  75	QNOC_SLAVE_PMIC_ARB,
  76	QNOC_SLAVE_SNOC_CFG,
  77	QNOC_SLAVE_DCC_CFG,
  78	QNOC_SLAVE_CAMERA_CFG,
  79	QNOC_SLAVE_DISPLAY_CFG,
  80	QNOC_SLAVE_VENUS_CFG,
  81	QNOC_SLAVE_SDCC_1,
  82	QNOC_SLAVE_BLSP_1,
  83	QNOC_SLAVE_USB_HS,
  84	QNOC_SLAVE_SDCC_3,
  85	QNOC_SLAVE_SDCC_2,
  86	QNOC_SLAVE_GRAPHICS_3D_CFG,
  87	QNOC_SLAVE_USB_HS2,
  88	QNOC_SLAVE_BLSP_2,
  89	QNOC_PNOC_SNOC_SLV,
  90	QNOC_SLAVE_APPSS,
  91	QNOC_MNOC_BIMC_SLV,
  92	QNOC_SNOC_BIMC_SLV,
  93	QNOC_SLAVE_SYSTEM_IMEM,
  94	QNOC_SNOC_PNOC_SLV,
  95	QNOC_SLAVE_QDSS_STM,
  96	QNOC_SLAVE_CATS_128,
  97	QNOC_SLAVE_OCMEM_64,
  98	QNOC_SLAVE_LPASS,
  99};
 100
 101static const u16 mas_apps_proc_links[] = {
 102	QNOC_SLAVE_EBI_CH0,
 103	QNOC_BIMC_SNOC_SLV
 104};
 105
 106static struct qcom_icc_node mas_apps_proc = {
 107	.name = "mas_apps_proc",
 108	.id = QNOC_MASTER_AMPSS_M0,
 109	.buswidth = 16,
 110	.mas_rpm_id = 0,
 111	.slv_rpm_id = -1,
 112	.qos.ap_owned = true,
 113	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 114	.qos.areq_prio = 0,
 115	.qos.prio_level = 0,
 116	.qos.qos_port = 0,
 117	.num_links = ARRAY_SIZE(mas_apps_proc_links),
 118	.links = mas_apps_proc_links,
 119};
 120
 121static const u16 mas_smmnoc_bimc_links[] = {
 122	QNOC_SLAVE_EBI_CH0
 123};
 124
 125static struct qcom_icc_node mas_smmnoc_bimc = {
 126	.name = "mas_smmnoc_bimc",
 127	.id = QNOC_MNOC_BIMC_MAS,
 128	.channels = 2,
 129	.buswidth = 16,
 130	.mas_rpm_id = 135,
 131	.slv_rpm_id = -1,
 132	.qos.ap_owned = true,
 133	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 134	.qos.areq_prio = 0,
 135	.qos.prio_level = 0,
 136	.qos.qos_port = 2,
 137	.num_links = ARRAY_SIZE(mas_smmnoc_bimc_links),
 138	.links = mas_smmnoc_bimc_links,
 139};
 140
 141static const u16 mas_snoc_bimc_links[] = {
 142	QNOC_SLAVE_EBI_CH0
 143};
 144
 145static struct qcom_icc_node mas_snoc_bimc = {
 146	.name = "mas_snoc_bimc",
 147	.id = QNOC_SNOC_BIMC_MAS,
 148	.channels = 2,
 149	.buswidth = 16,
 150	.mas_rpm_id = 3,
 151	.slv_rpm_id = -1,
 152	.qos.ap_owned = true,
 153	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 154	.qos.areq_prio = 0,
 155	.qos.prio_level = 0,
 156	.qos.qos_port = 3,
 157	.num_links = ARRAY_SIZE(mas_snoc_bimc_links),
 158	.links = mas_snoc_bimc_links,
 159};
 160
 161static const u16 mas_tcu_0_links[] = {
 162	QNOC_SLAVE_EBI_CH0,
 163	QNOC_BIMC_SNOC_SLV
 164};
 165
 166static struct qcom_icc_node mas_tcu_0 = {
 167	.name = "mas_tcu_0",
 168	.id = QNOC_MASTER_TCU_0,
 169	.buswidth = 16,
 170	.mas_rpm_id = 102,
 171	.slv_rpm_id = -1,
 172	.qos.ap_owned = true,
 173	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 174	.qos.areq_prio = 0,
 175	.qos.prio_level = 2,
 176	.qos.qos_port = 4,
 177	.num_links = ARRAY_SIZE(mas_tcu_0_links),
 178	.links = mas_tcu_0_links,
 179};
 180
 181static const u16 mas_usb_hs2_links[] = {
 182	QNOC_PNOC_M_0
 183};
 184
 185static struct qcom_icc_node mas_usb_hs2 = {
 186	.name = "mas_usb_hs2",
 187	.id = QNOC_MASTER_USB_HS2,
 188	.buswidth = 4,
 189	.mas_rpm_id = 57,
 190	.slv_rpm_id = -1,
 191	.num_links = ARRAY_SIZE(mas_usb_hs2_links),
 192	.links = mas_usb_hs2_links,
 193};
 194
 195static const u16 mas_blsp_1_links[] = {
 196	QNOC_PNOC_M_1
 197};
 198
 199static struct qcom_icc_node mas_blsp_1 = {
 200	.name = "mas_blsp_1",
 201	.id = QNOC_MASTER_BLSP_1,
 202	.buswidth = 4,
 203	.mas_rpm_id = 41,
 204	.slv_rpm_id = -1,
 205	.num_links = ARRAY_SIZE(mas_blsp_1_links),
 206	.links = mas_blsp_1_links,
 207};
 208
 209static const u16 mas_usb_hs1_links[] = {
 210	QNOC_PNOC_M_1
 211};
 212
 213static struct qcom_icc_node mas_usb_hs1 = {
 214	.name = "mas_usb_hs1",
 215	.id = QNOC_MASTER_USB_HS,
 216	.buswidth = 4,
 217	.mas_rpm_id = 42,
 218	.slv_rpm_id = -1,
 219	.num_links = ARRAY_SIZE(mas_usb_hs1_links),
 220	.links = mas_usb_hs1_links,
 221};
 222
 223static const u16 mas_blsp_2_links[] = {
 224	QNOC_PNOC_M_1
 225};
 226
 227static struct qcom_icc_node mas_blsp_2 = {
 228	.name = "mas_blsp_2",
 229	.id = QNOC_MASTER_BLSP_2,
 230	.buswidth = 4,
 231	.mas_rpm_id = 39,
 232	.slv_rpm_id = -1,
 233	.num_links = ARRAY_SIZE(mas_blsp_2_links),
 234	.links = mas_blsp_2_links,
 235};
 236
 237static const u16 mas_crypto_links[] = {
 238	QNOC_PNOC_INT_1
 239};
 240
 241static struct qcom_icc_node mas_crypto = {
 242	.name = "mas_crypto",
 243	.id = QNOC_MASTER_CRYPTO_CORE0,
 244	.buswidth = 8,
 245	.mas_rpm_id = 23,
 246	.slv_rpm_id = -1,
 247	.qos.ap_owned = true,
 248	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 249	.qos.areq_prio = 0,
 250	.qos.prio_level = 0,
 251	.qos.qos_port = 0,
 252	.num_links = ARRAY_SIZE(mas_crypto_links),
 253	.links = mas_crypto_links,
 254};
 255
 256static const u16 mas_sdcc_1_links[] = {
 257	QNOC_PNOC_INT_1
 258};
 259
 260static struct qcom_icc_node mas_sdcc_1 = {
 261	.name = "mas_sdcc_1",
 262	.id = QNOC_MASTER_SDCC_1,
 263	.buswidth = 8,
 264	.mas_rpm_id = 33,
 265	.slv_rpm_id = -1,
 266	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 267	.qos.areq_prio = 0,
 268	.qos.prio_level = 0,
 269	.qos.qos_port = 7,
 270	.num_links = ARRAY_SIZE(mas_sdcc_1_links),
 271	.links = mas_sdcc_1_links,
 272};
 273
 274static const u16 mas_sdcc_2_links[] = {
 275	QNOC_PNOC_INT_1
 276};
 277
 278static struct qcom_icc_node mas_sdcc_2 = {
 279	.name = "mas_sdcc_2",
 280	.id = QNOC_MASTER_SDCC_2,
 281	.buswidth = 8,
 282	.mas_rpm_id = 35,
 283	.slv_rpm_id = -1,
 284	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 285	.qos.areq_prio = 0,
 286	.qos.prio_level = 0,
 287	.qos.qos_port = 8,
 288	.num_links = ARRAY_SIZE(mas_sdcc_2_links),
 289	.links = mas_sdcc_2_links,
 290};
 291
 292static const u16 mas_sdcc_3_links[] = {
 293	QNOC_PNOC_INT_1
 294};
 295
 296static struct qcom_icc_node mas_sdcc_3 = {
 297	.name = "mas_sdcc_3",
 298	.id = QNOC_MASTER_SDCC_3,
 299	.buswidth = 8,
 300	.mas_rpm_id = 34,
 301	.slv_rpm_id = -1,
 302	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 303	.qos.areq_prio = 0,
 304	.qos.prio_level = 0,
 305	.qos.qos_port = 10,
 306	.num_links = ARRAY_SIZE(mas_sdcc_3_links),
 307	.links = mas_sdcc_3_links,
 308};
 309
 310static const u16 mas_snoc_pcnoc_links[] = {
 311	QNOC_PNOC_INT_2
 312};
 313
 314static struct qcom_icc_node mas_snoc_pcnoc = {
 315	.name = "mas_snoc_pcnoc",
 316	.id = QNOC_SNOC_PNOC_MAS,
 317	.buswidth = 8,
 318	.mas_rpm_id = 77,
 319	.slv_rpm_id = -1,
 320	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 321	.qos.areq_prio = 0,
 322	.qos.prio_level = 0,
 323	.qos.qos_port = 9,
 324	.num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
 325	.links = mas_snoc_pcnoc_links,
 326};
 327
 328static const u16 mas_lpass_ahb_links[] = {
 329	QNOC_PNOC_SNOC_SLV
 330};
 331
 332static struct qcom_icc_node mas_lpass_ahb = {
 333	.name = "mas_lpass_ahb",
 334	.id = QNOC_MASTER_LPASS_AHB,
 335	.buswidth = 8,
 336	.mas_rpm_id = 18,
 337	.slv_rpm_id = -1,
 338	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 339	.qos.areq_prio = 0,
 340	.qos.prio_level = 0,
 341	.qos.qos_port = 12,
 342	.num_links = ARRAY_SIZE(mas_lpass_ahb_links),
 343	.links = mas_lpass_ahb_links,
 344};
 345
 346static const u16 mas_spdm_links[] = {
 347	QNOC_PNOC_M_0
 348};
 349
 350static struct qcom_icc_node mas_spdm = {
 351	.name = "mas_spdm",
 352	.id = QNOC_MASTER_SPDM,
 353	.buswidth = 4,
 354	.mas_rpm_id = -1,
 355	.slv_rpm_id = -1,
 356	.num_links = ARRAY_SIZE(mas_spdm_links),
 357	.links = mas_spdm_links,
 358};
 359
 360static const u16 mas_dehr_links[] = {
 361	QNOC_PNOC_M_0
 362};
 363
 364static struct qcom_icc_node mas_dehr = {
 365	.name = "mas_dehr",
 366	.id = QNOC_MASTER_DEHR,
 367	.buswidth = 4,
 368	.mas_rpm_id = -1,
 369	.slv_rpm_id = -1,
 370	.num_links = ARRAY_SIZE(mas_dehr_links),
 371	.links = mas_dehr_links,
 372};
 373
 374static const u16 mas_xm_usb_hs1_links[] = {
 375	QNOC_PNOC_INT_0
 376};
 377
 378static struct qcom_icc_node mas_xm_usb_hs1 = {
 379	.name = "mas_xm_usb_hs1",
 380	.id = QNOC_MASTER_XM_USB_HS1,
 381	.buswidth = 8,
 382	.mas_rpm_id = -1,
 383	.slv_rpm_id = -1,
 384	.num_links = ARRAY_SIZE(mas_xm_usb_hs1_links),
 385	.links = mas_xm_usb_hs1_links,
 386};
 387
 388static const u16 mas_qdss_bam_links[] = {
 389	QNOC_SNOC_QDSS_INT
 390};
 391
 392static struct qcom_icc_node mas_qdss_bam = {
 393	.name = "mas_qdss_bam",
 394	.id = QNOC_MASTER_QDSS_BAM,
 395	.buswidth = 4,
 396	.mas_rpm_id = 19,
 397	.slv_rpm_id = -1,
 398	.qos.ap_owned = true,
 399	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 400	.qos.areq_prio = 1,
 401	.qos.prio_level = 1,
 402	.qos.qos_port = 11,
 403	.num_links = ARRAY_SIZE(mas_qdss_bam_links),
 404	.links = mas_qdss_bam_links,
 405};
 406
 407static const u16 mas_bimc_snoc_links[] = {
 408	QNOC_SNOC_INT_2
 409};
 410
 411static struct qcom_icc_node mas_bimc_snoc = {
 412	.name = "mas_bimc_snoc",
 413	.id = QNOC_BIMC_SNOC_MAS,
 414	.buswidth = 8,
 415	.mas_rpm_id = 21,
 416	.slv_rpm_id = -1,
 417	.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
 418	.links = mas_bimc_snoc_links,
 419};
 420
 421static const u16 mas_jpeg_links[] = {
 422	QNOC_SNOC_MM_INT_0,
 423	QNOC_MNOC_BIMC_SLV
 424};
 425
 426static struct qcom_icc_node mas_jpeg = {
 427	.name = "mas_jpeg",
 428	.id = QNOC_MASTER_JPEG,
 429	.buswidth = 16,
 430	.mas_rpm_id = 7,
 431	.slv_rpm_id = -1,
 432	.qos.ap_owned = true,
 433	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 434	.qos.areq_prio = 0,
 435	.qos.prio_level = 0,
 436	.qos.qos_port = 6,
 437	.num_links = ARRAY_SIZE(mas_jpeg_links),
 438	.links = mas_jpeg_links,
 439};
 440
 441static const u16 mas_oxili_links[] = {
 442	QNOC_MNOC_BIMC_SLV,
 443	QNOC_SNOC_MM_INT_0
 444};
 445
 446static struct qcom_icc_node mas_oxili = {
 447	.name = "mas_oxili",
 448	.id = QNOC_MASTER_GRAPHICS_3D,
 449	.channels = 2,
 450	.buswidth = 16,
 451	.ib_coeff = 200,
 452	.mas_rpm_id = 6,
 453	.slv_rpm_id = -1,
 454	.qos.ap_owned = true,
 455	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 456	.qos.areq_prio = 0,
 457	.qos.prio_level = 0,
 458	.qos.qos_port = 16, /* [16, 17] */
 459	.num_links = ARRAY_SIZE(mas_oxili_links),
 460	.links = mas_oxili_links,
 461};
 462
 463static const u16 mas_mdp0_links[] = {
 464	QNOC_SNOC_MM_INT_0,
 465	QNOC_MNOC_BIMC_SLV
 466};
 467
 468static struct qcom_icc_node mas_mdp0 = {
 469	.name = "mas_mdp0",
 470	.id = QNOC_MASTER_MDP_PORT0,
 471	.buswidth = 16,
 472	.ib_coeff = 50,
 473	.mas_rpm_id = 8,
 474	.slv_rpm_id = -1,
 475	.qos.ap_owned = true,
 476	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 477	.qos.areq_prio = 0,
 478	.qos.prio_level = 0,
 479	.qos.qos_port = 7,
 480	.num_links = ARRAY_SIZE(mas_mdp0_links),
 481	.links = mas_mdp0_links,
 482};
 483
 484static const u16 mas_mdp1_links[] = {
 485	QNOC_SNOC_MM_INT_0,
 486	QNOC_MNOC_BIMC_SLV
 487};
 488
 489static struct qcom_icc_node mas_mdp1 = {
 490	.name = "mas_mdp1",
 491	.id = QNOC_MASTER_MDP_PORT1,
 492	.buswidth = 16,
 493	.ib_coeff = 50,
 494	.mas_rpm_id = 61,
 495	.slv_rpm_id = -1,
 496	.qos.ap_owned = true,
 497	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 498	.qos.areq_prio = 0,
 499	.qos.prio_level = 0,
 500	.qos.qos_port = 13,
 501	.num_links = ARRAY_SIZE(mas_mdp1_links),
 502	.links = mas_mdp1_links,
 503};
 504
 505static const u16 mas_pcnoc_snoc_links[] = {
 506	QNOC_SNOC_INT_2
 507};
 508
 509static struct qcom_icc_node mas_pcnoc_snoc = {
 510	.name = "mas_pcnoc_snoc",
 511	.id = QNOC_PNOC_SNOC_MAS,
 512	.buswidth = 8,
 513	.mas_rpm_id = 29,
 514	.slv_rpm_id = -1,
 515	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 516	.qos.areq_prio = 0,
 517	.qos.prio_level = 0,
 518	.qos.qos_port = 5,
 519	.num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
 520	.links = mas_pcnoc_snoc_links,
 521};
 522
 523static const u16 mas_venus_0_links[] = {
 524	QNOC_SNOC_MM_INT_0,
 525	QNOC_MNOC_BIMC_SLV
 526};
 527
 528static struct qcom_icc_node mas_venus_0 = {
 529	.name = "mas_venus_0",
 530	.id = QNOC_MASTER_VIDEO_P0,
 531	.buswidth = 16,
 532	.mas_rpm_id = 9,
 533	.slv_rpm_id = -1,
 534	.qos.ap_owned = true,
 535	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 536	.qos.areq_prio = 0,
 537	.qos.prio_level = 0,
 538	.qos.qos_port = 8,
 539	.num_links = ARRAY_SIZE(mas_venus_0_links),
 540	.links = mas_venus_0_links,
 541};
 542
 543static const u16 mas_venus_1_links[] = {
 544	QNOC_SNOC_MM_INT_0,
 545	QNOC_MNOC_BIMC_SLV
 546};
 547
 548static struct qcom_icc_node mas_venus_1 = {
 549	.name = "mas_venus_1",
 550	.id = QNOC_MASTER_VIDEO_P1,
 551	.buswidth = 16,
 552	.mas_rpm_id = 10,
 553	.slv_rpm_id = -1,
 554	.qos.ap_owned = true,
 555	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 556	.qos.areq_prio = 0,
 557	.qos.prio_level = 0,
 558	.qos.qos_port = 14,
 559	.num_links = ARRAY_SIZE(mas_venus_1_links),
 560	.links = mas_venus_1_links,
 561};
 562
 563static const u16 mas_vfe_0_links[] = {
 564	QNOC_SNOC_MM_INT_0,
 565	QNOC_MNOC_BIMC_SLV
 566};
 567
 568static struct qcom_icc_node mas_vfe_0 = {
 569	.name = "mas_vfe_0",
 570	.id = QNOC_MASTER_VFE0,
 571	.buswidth = 16,
 572	.mas_rpm_id = 11,
 573	.slv_rpm_id = -1,
 574	.qos.ap_owned = true,
 575	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 576	.qos.areq_prio = 0,
 577	.qos.prio_level = 0,
 578	.qos.qos_port = 9,
 579	.num_links = ARRAY_SIZE(mas_vfe_0_links),
 580	.links = mas_vfe_0_links,
 581};
 582
 583static const u16 mas_vfe_1_links[] = {
 584	QNOC_SNOC_MM_INT_0,
 585	QNOC_MNOC_BIMC_SLV
 586};
 587
 588static struct qcom_icc_node mas_vfe_1 = {
 589	.name = "mas_vfe_1",
 590	.id = QNOC_MASTER_VFE1,
 591	.buswidth = 16,
 592	.mas_rpm_id = 133,
 593	.slv_rpm_id = -1,
 594	.qos.ap_owned = true,
 595	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 596	.qos.areq_prio = 0,
 597	.qos.prio_level = 0,
 598	.qos.qos_port = 15,
 599	.num_links = ARRAY_SIZE(mas_vfe_1_links),
 600	.links = mas_vfe_1_links,
 601};
 602
 603static const u16 mas_cpp_links[] = {
 604	QNOC_SNOC_MM_INT_0,
 605	QNOC_MNOC_BIMC_SLV
 606};
 607
 608static struct qcom_icc_node mas_cpp = {
 609	.name = "mas_cpp",
 610	.id = QNOC_MASTER_CPP,
 611	.buswidth = 16,
 612	.mas_rpm_id = 115,
 613	.slv_rpm_id = -1,
 614	.qos.ap_owned = true,
 615	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 616	.qos.areq_prio = 0,
 617	.qos.prio_level = 0,
 618	.qos.qos_port = 12,
 619	.num_links = ARRAY_SIZE(mas_cpp_links),
 620	.links = mas_cpp_links,
 621};
 622
 623static const u16 mas_qdss_etr_links[] = {
 624	QNOC_SNOC_QDSS_INT
 625};
 626
 627static struct qcom_icc_node mas_qdss_etr = {
 628	.name = "mas_qdss_etr",
 629	.id = QNOC_MASTER_QDSS_ETR,
 630	.buswidth = 8,
 631	.mas_rpm_id = 31,
 632	.slv_rpm_id = -1,
 633	.qos.ap_owned = true,
 634	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 635	.qos.areq_prio = 1,
 636	.qos.prio_level = 1,
 637	.qos.qos_port = 10,
 638	.num_links = ARRAY_SIZE(mas_qdss_etr_links),
 639	.links = mas_qdss_etr_links,
 640};
 641
 642static const u16 mas_lpass_proc_links[] = {
 643	QNOC_SNOC_INT_0,
 644	QNOC_SNOC_INT_1,
 645	QNOC_SNOC_BIMC_SLV
 646};
 647
 648static struct qcom_icc_node mas_lpass_proc = {
 649	.name = "mas_lpass_proc",
 650	.id = QNOC_MASTER_LPASS_PROC,
 651	.buswidth = 8,
 652	.mas_rpm_id = -1,
 653	.slv_rpm_id = -1,
 654	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 655	.qos.areq_prio = 0,
 656	.qos.prio_level = 0,
 657	.qos.qos_port = 19,
 658	.num_links = ARRAY_SIZE(mas_lpass_proc_links),
 659	.links = mas_lpass_proc_links,
 660};
 661
 662static const u16 mas_ipa_links[] = {
 663	QNOC_SNOC_INT_2
 664};
 665
 666static struct qcom_icc_node mas_ipa = {
 667	.name = "mas_ipa",
 668	.id = QNOC_MASTER_IPA,
 669	.buswidth = 8,
 670	.mas_rpm_id = 59,
 671	.slv_rpm_id = -1,
 672	.qos.ap_owned = true,
 673	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 674	.qos.areq_prio = 1,
 675	.qos.prio_level = 1,
 676	.qos.qos_port = 18,
 677	.num_links = ARRAY_SIZE(mas_ipa_links),
 678	.links = mas_ipa_links,
 679};
 680
 681static const u16 pcnoc_m_0_links[] = {
 682	QNOC_PNOC_SNOC_SLV
 683};
 684
 685static struct qcom_icc_node pcnoc_m_0 = {
 686	.name = "pcnoc_m_0",
 687	.id = QNOC_PNOC_M_0,
 688	.buswidth = 4,
 689	.mas_rpm_id = 87,
 690	.slv_rpm_id = 116,
 691	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 692	.qos.areq_prio = 0,
 693	.qos.prio_level = 0,
 694	.qos.qos_port = 5,
 695	.num_links = ARRAY_SIZE(pcnoc_m_0_links),
 696	.links = pcnoc_m_0_links,
 697};
 698
 699static const u16 pcnoc_m_1_links[] = {
 700	QNOC_PNOC_SNOC_SLV
 701};
 702
 703static struct qcom_icc_node pcnoc_m_1 = {
 704	.name = "pcnoc_m_1",
 705	.id = QNOC_PNOC_M_1,
 706	.buswidth = 4,
 707	.mas_rpm_id = 88,
 708	.slv_rpm_id = 117,
 709	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 710	.qos.areq_prio = 0,
 711	.qos.prio_level = 0,
 712	.qos.qos_port = 6,
 713	.num_links = ARRAY_SIZE(pcnoc_m_1_links),
 714	.links = pcnoc_m_1_links,
 715};
 716
 717static const u16 pcnoc_int_0_links[] = {
 718	QNOC_PNOC_SNOC_SLV,
 719	QNOC_PNOC_INT_2
 720};
 721
 722static struct qcom_icc_node pcnoc_int_0 = {
 723	.name = "pcnoc_int_0",
 724	.id = QNOC_PNOC_INT_0,
 725	.buswidth = 4,
 726	.mas_rpm_id = -1,
 727	.slv_rpm_id = -1,
 728	.num_links = ARRAY_SIZE(pcnoc_int_0_links),
 729	.links = pcnoc_int_0_links,
 730};
 731
 732static const u16 pcnoc_int_1_links[] = {
 733	QNOC_PNOC_SNOC_SLV,
 734	QNOC_PNOC_INT_2
 735};
 736
 737static struct qcom_icc_node pcnoc_int_1 = {
 738	.name = "pcnoc_int_1",
 739	.id = QNOC_PNOC_INT_1,
 740	.buswidth = 8,
 741	.mas_rpm_id = 86,
 742	.slv_rpm_id = 115,
 743	.num_links = ARRAY_SIZE(pcnoc_int_1_links),
 744	.links = pcnoc_int_1_links,
 745};
 746
 747static const u16 pcnoc_int_2_links[] = {
 748	QNOC_PNOC_SLV_1,
 749	QNOC_PNOC_SLV_2,
 750	QNOC_PNOC_SLV_4,
 751	QNOC_PNOC_SLV_8,
 752	QNOC_PNOC_SLV_9,
 753	QNOC_PNOC_SLV_3
 754};
 755
 756static struct qcom_icc_node pcnoc_int_2 = {
 757	.name = "pcnoc_int_2",
 758	.id = QNOC_PNOC_INT_2,
 759	.buswidth = 8,
 760	.mas_rpm_id = 124,
 761	.slv_rpm_id = 184,
 762	.num_links = ARRAY_SIZE(pcnoc_int_2_links),
 763	.links = pcnoc_int_2_links,
 764};
 765
 766static const u16 pcnoc_s_1_links[] = {
 767	QNOC_SLAVE_CRYPTO_0_CFG,
 768	QNOC_SLAVE_PRNG,
 769	QNOC_SLAVE_PDM,
 770	QNOC_SLAVE_MESSAGE_RAM
 771};
 772
 773static struct qcom_icc_node pcnoc_s_1 = {
 774	.name = "pcnoc_s_1",
 775	.id = QNOC_PNOC_SLV_1,
 776	.buswidth = 4,
 777	.mas_rpm_id = 90,
 778	.slv_rpm_id = 119,
 779	.num_links = ARRAY_SIZE(pcnoc_s_1_links),
 780	.links = pcnoc_s_1_links,
 781};
 782
 783static const u16 pcnoc_s_2_links[] = {
 784	QNOC_SLAVE_PMIC_ARB
 785};
 786
 787static struct qcom_icc_node pcnoc_s_2 = {
 788	.name = "pcnoc_s_2",
 789	.id = QNOC_PNOC_SLV_2,
 790	.buswidth = 4,
 791	.mas_rpm_id = 91,
 792	.slv_rpm_id = 120,
 793	.num_links = ARRAY_SIZE(pcnoc_s_2_links),
 794	.links = pcnoc_s_2_links,
 795};
 796
 797static const u16 pcnoc_s_3_links[] = {
 798	QNOC_SLAVE_SNOC_CFG,
 799	QNOC_SLAVE_DCC_CFG
 800};
 801
 802static struct qcom_icc_node pcnoc_s_3 = {
 803	.name = "pcnoc_s_3",
 804	.id = QNOC_PNOC_SLV_3,
 805	.buswidth = 4,
 806	.mas_rpm_id = 92,
 807	.slv_rpm_id = 121,
 808	.num_links = ARRAY_SIZE(pcnoc_s_3_links),
 809	.links = pcnoc_s_3_links,
 810};
 811
 812static const u16 pcnoc_s_4_links[] = {
 813	QNOC_SLAVE_CAMERA_CFG,
 814	QNOC_SLAVE_DISPLAY_CFG,
 815	QNOC_SLAVE_VENUS_CFG
 816};
 817
 818static struct qcom_icc_node pcnoc_s_4 = {
 819	.name = "pcnoc_s_4",
 820	.id = QNOC_PNOC_SLV_4,
 821	.buswidth = 4,
 822	.mas_rpm_id = 93,
 823	.slv_rpm_id = 122,
 824	.qos.ap_owned = true,
 825	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 826	.num_links = ARRAY_SIZE(pcnoc_s_4_links),
 827	.links = pcnoc_s_4_links,
 828};
 829
 830static const u16 pcnoc_s_8_links[] = {
 831	QNOC_SLAVE_USB_HS,
 832	QNOC_SLAVE_SDCC_3,
 833	QNOC_SLAVE_BLSP_1,
 834	QNOC_SLAVE_SDCC_1
 835};
 836
 837static struct qcom_icc_node pcnoc_s_8 = {
 838	.name = "pcnoc_s_8",
 839	.id = QNOC_PNOC_SLV_8,
 840	.buswidth = 4,
 841	.mas_rpm_id = 96,
 842	.slv_rpm_id = 125,
 843	.num_links = ARRAY_SIZE(pcnoc_s_8_links),
 844	.links = pcnoc_s_8_links,
 845};
 846
 847static const u16 pcnoc_s_9_links[] = {
 848	QNOC_SLAVE_GRAPHICS_3D_CFG,
 849	QNOC_SLAVE_USB_HS2,
 850	QNOC_SLAVE_SDCC_2,
 851	QNOC_SLAVE_BLSP_2
 852};
 853
 854static struct qcom_icc_node pcnoc_s_9 = {
 855	.name = "pcnoc_s_9",
 856	.id = QNOC_PNOC_SLV_9,
 857	.buswidth = 4,
 858	.mas_rpm_id = 97,
 859	.slv_rpm_id = 126,
 860	.num_links = ARRAY_SIZE(pcnoc_s_9_links),
 861	.links = pcnoc_s_9_links,
 862};
 863
 864static const u16 mm_int_0_links[] = {
 865	QNOC_SNOC_INT_0
 866};
 867
 868static struct qcom_icc_node mm_int_0 = {
 869	.name = "mm_int_0",
 870	.id = QNOC_SNOC_MM_INT_0,
 871	.buswidth = 16,
 872	.ib_coeff = 200,
 873	.mas_rpm_id = 79,
 874	.slv_rpm_id = 108,
 875	.qos.ap_owned = true,
 876	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 877	.num_links = ARRAY_SIZE(mm_int_0_links),
 878	.links = mm_int_0_links,
 879};
 880
 881static const u16 qdss_int_links[] = {
 882	QNOC_SNOC_INT_2
 883};
 884
 885static struct qcom_icc_node qdss_int = {
 886	.name = "qdss_int",
 887	.id = QNOC_SNOC_QDSS_INT,
 888	.buswidth = 8,
 889	.mas_rpm_id = 98,
 890	.slv_rpm_id = 128,
 891	.qos.ap_owned = true,
 892	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 893	.num_links = ARRAY_SIZE(qdss_int_links),
 894	.links = qdss_int_links,
 895};
 896
 897static const u16 snoc_int_0_links[] = {
 898	QNOC_SLAVE_QDSS_STM,
 899	QNOC_SLAVE_SYSTEM_IMEM,
 900	QNOC_SNOC_PNOC_SLV
 901};
 902
 903static struct qcom_icc_node snoc_int_0 = {
 904	.name = "snoc_int_0",
 905	.id = QNOC_SNOC_INT_0,
 906	.buswidth = 8,
 907	.mas_rpm_id = 99,
 908	.slv_rpm_id = 130,
 909	.num_links = ARRAY_SIZE(snoc_int_0_links),
 910	.links = snoc_int_0_links,
 911};
 912
 913static const u16 snoc_int_1_links[] = {
 914	QNOC_SLAVE_LPASS,
 915	QNOC_SLAVE_CATS_128,
 916	QNOC_SLAVE_OCMEM_64,
 917	QNOC_SLAVE_APPSS
 918};
 919
 920static struct qcom_icc_node snoc_int_1 = {
 921	.name = "snoc_int_1",
 922	.id = QNOC_SNOC_INT_1,
 923	.buswidth = 8,
 924	.mas_rpm_id = 100,
 925	.slv_rpm_id = 131,
 926	.qos.ap_owned = true,
 927	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 928	.num_links = ARRAY_SIZE(snoc_int_1_links),
 929	.links = snoc_int_1_links,
 930};
 931
 932static const u16 snoc_int_2_links[] = {
 933	QNOC_SNOC_INT_0,
 934	QNOC_SNOC_INT_1,
 935	QNOC_SNOC_BIMC_SLV
 936};
 937
 938static struct qcom_icc_node snoc_int_2 = {
 939	.name = "snoc_int_2",
 940	.id = QNOC_SNOC_INT_2,
 941	.buswidth = 8,
 942	.mas_rpm_id = 134,
 943	.slv_rpm_id = 197,
 944	.num_links = ARRAY_SIZE(snoc_int_2_links),
 945	.links = snoc_int_2_links,
 946};
 947
 948static struct qcom_icc_node slv_ebi = {
 949	.name = "slv_ebi",
 950	.id = QNOC_SLAVE_EBI_CH0,
 951	.channels = 2,
 952	.buswidth = 16,
 953	.mas_rpm_id = -1,
 954	.slv_rpm_id = 0,
 955};
 956
 957static const u16 slv_bimc_snoc_links[] = {
 958	QNOC_BIMC_SNOC_MAS
 959};
 960
 961static struct qcom_icc_node slv_bimc_snoc = {
 962	.name = "slv_bimc_snoc",
 963	.id = QNOC_BIMC_SNOC_SLV,
 964	.buswidth = 16,
 965	.mas_rpm_id = -1,
 966	.slv_rpm_id = 2,
 967	.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
 968	.links = slv_bimc_snoc_links,
 969};
 970
 971static struct qcom_icc_node slv_tcsr = {
 972	.name = "slv_tcsr",
 973	.id = QNOC_SLAVE_TCSR,
 974	.buswidth = 4,
 975	.mas_rpm_id = -1,
 976	.slv_rpm_id = 50,
 977};
 978
 979static struct qcom_icc_node slv_tlmm = {
 980	.name = "slv_tlmm",
 981	.id = QNOC_SLAVE_TLMM,
 982	.buswidth = 4,
 983	.mas_rpm_id = -1,
 984	.slv_rpm_id = 51,
 985};
 986
 987static struct qcom_icc_node slv_crypto_0_cfg = {
 988	.name = "slv_crypto_0_cfg",
 989	.id = QNOC_SLAVE_CRYPTO_0_CFG,
 990	.buswidth = 4,
 991	.mas_rpm_id = -1,
 992	.slv_rpm_id = 52,
 993	.qos.ap_owned = true,
 994	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 995};
 996
 997static struct qcom_icc_node slv_message_ram = {
 998	.name = "slv_message_ram",
 999	.id = QNOC_SLAVE_MESSAGE_RAM,
1000	.buswidth = 4,
1001	.mas_rpm_id = -1,
1002	.slv_rpm_id = 55,
1003};
1004
1005static struct qcom_icc_node slv_pdm = {
1006	.name = "slv_pdm",
1007	.id = QNOC_SLAVE_PDM,
1008	.buswidth = 4,
1009	.mas_rpm_id = -1,
1010	.slv_rpm_id = 41,
1011};
1012
1013static struct qcom_icc_node slv_prng = {
1014	.name = "slv_prng",
1015	.id = QNOC_SLAVE_PRNG,
1016	.buswidth = 4,
1017	.mas_rpm_id = -1,
1018	.slv_rpm_id = 44,
1019	.qos.ap_owned = true,
1020	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1021};
1022
1023static struct qcom_icc_node slv_pmic_arb = {
1024	.name = "slv_pmic_arb",
1025	.id = QNOC_SLAVE_PMIC_ARB,
1026	.buswidth = 4,
1027	.mas_rpm_id = -1,
1028	.slv_rpm_id = 59,
1029};
1030
1031static struct qcom_icc_node slv_snoc_cfg = {
1032	.name = "slv_snoc_cfg",
1033	.id = QNOC_SLAVE_SNOC_CFG,
1034	.buswidth = 4,
1035	.mas_rpm_id = -1,
1036	.slv_rpm_id = 70,
1037};
1038
1039static struct qcom_icc_node slv_dcc_cfg = {
1040	.name = "slv_dcc_cfg",
1041	.id = QNOC_SLAVE_DCC_CFG,
1042	.buswidth = 4,
1043	.mas_rpm_id = -1,
1044	.slv_rpm_id = 155,
1045	.qos.ap_owned = true,
1046	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1047};
1048
1049static struct qcom_icc_node slv_camera_ss_cfg = {
1050	.name = "slv_camera_ss_cfg",
1051	.id = QNOC_SLAVE_CAMERA_CFG,
1052	.buswidth = 4,
1053	.mas_rpm_id = -1,
1054	.slv_rpm_id = 3,
1055	.qos.ap_owned = true,
1056	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1057};
1058
1059static struct qcom_icc_node slv_disp_ss_cfg = {
1060	.name = "slv_disp_ss_cfg",
1061	.id = QNOC_SLAVE_DISPLAY_CFG,
1062	.buswidth = 4,
1063	.mas_rpm_id = -1,
1064	.slv_rpm_id = 4,
1065	.qos.ap_owned = true,
1066	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1067};
1068
1069static struct qcom_icc_node slv_venus_cfg = {
1070	.name = "slv_venus_cfg",
1071	.id = QNOC_SLAVE_VENUS_CFG,
1072	.buswidth = 4,
1073	.mas_rpm_id = -1,
1074	.slv_rpm_id = 10,
1075	.qos.ap_owned = true,
1076	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1077};
1078
1079static struct qcom_icc_node slv_sdcc_1 = {
1080	.name = "slv_sdcc_1",
1081	.id = QNOC_SLAVE_SDCC_1,
1082	.buswidth = 4,
1083	.mas_rpm_id = -1,
1084	.slv_rpm_id = 31,
1085};
1086
1087static struct qcom_icc_node slv_blsp_1 = {
1088	.name = "slv_blsp_1",
1089	.id = QNOC_SLAVE_BLSP_1,
1090	.buswidth = 4,
1091	.mas_rpm_id = -1,
1092	.slv_rpm_id = 39,
1093};
1094
1095static struct qcom_icc_node slv_usb_hs = {
1096	.name = "slv_usb_hs",
1097	.id = QNOC_SLAVE_USB_HS,
1098	.buswidth = 4,
1099	.mas_rpm_id = -1,
1100	.slv_rpm_id = 40,
1101};
1102
1103static struct qcom_icc_node slv_sdcc_3 = {
1104	.name = "slv_sdcc_3",
1105	.id = QNOC_SLAVE_SDCC_3,
1106	.buswidth = 4,
1107	.mas_rpm_id = -1,
1108	.slv_rpm_id = 32,
1109};
1110
1111static struct qcom_icc_node slv_sdcc_2 = {
1112	.name = "slv_sdcc_2",
1113	.id = QNOC_SLAVE_SDCC_2,
1114	.buswidth = 4,
1115	.mas_rpm_id = -1,
1116	.slv_rpm_id = 33,
1117};
1118
1119static struct qcom_icc_node slv_gpu_cfg = {
1120	.name = "slv_gpu_cfg",
1121	.id = QNOC_SLAVE_GRAPHICS_3D_CFG,
1122	.buswidth = 4,
1123	.mas_rpm_id = -1,
1124	.slv_rpm_id = 11,
1125	.qos.ap_owned = true,
1126	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1127};
1128
1129static struct qcom_icc_node slv_usb_hs2 = {
1130	.name = "slv_usb_hs2",
1131	.id = QNOC_SLAVE_USB_HS2,
1132	.buswidth = 4,
1133	.mas_rpm_id = -1,
1134	.slv_rpm_id = 79,
1135};
1136
1137static struct qcom_icc_node slv_blsp_2 = {
1138	.name = "slv_blsp_2",
1139	.id = QNOC_SLAVE_BLSP_2,
1140	.buswidth = 4,
1141	.mas_rpm_id = -1,
1142	.slv_rpm_id = 37,
1143};
1144
1145static const u16 slv_pcnoc_snoc_links[] = {
1146	QNOC_PNOC_SNOC_MAS
1147};
1148
1149static struct qcom_icc_node slv_pcnoc_snoc = {
1150	.name = "slv_pcnoc_snoc",
1151	.id = QNOC_PNOC_SNOC_SLV,
1152	.buswidth = 8,
1153	.mas_rpm_id = -1,
1154	.slv_rpm_id = 45,
1155	.num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
1156	.links = slv_pcnoc_snoc_links,
1157};
1158
1159static struct qcom_icc_node slv_kpss_ahb = {
1160	.name = "slv_kpss_ahb",
1161	.id = QNOC_SLAVE_APPSS,
1162	.buswidth = 4,
1163	.mas_rpm_id = -1,
1164	.slv_rpm_id = 20,
1165	.qos.ap_owned = true,
1166	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1167};
1168
1169static const u16 slv_smmnoc_bimc_links[] = {
1170	QNOC_MNOC_BIMC_MAS
1171};
1172
1173static struct qcom_icc_node slv_smmnoc_bimc = {
1174	.name = "slv_smmnoc_bimc",
1175	.id = QNOC_MNOC_BIMC_SLV,
1176	.channels = 2,
1177	.buswidth = 16,
1178	.ib_coeff = 200,
1179	.mas_rpm_id = -1,
1180	.slv_rpm_id = 198,
1181	.qos.ap_owned = true,
1182	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1183	.num_links = ARRAY_SIZE(slv_smmnoc_bimc_links),
1184	.links = slv_smmnoc_bimc_links,
1185};
1186
1187static const u16 slv_snoc_bimc_links[] = {
1188	QNOC_SNOC_BIMC_MAS
1189};
1190
1191static struct qcom_icc_node slv_snoc_bimc = {
1192	.name = "slv_snoc_bimc",
1193	.id = QNOC_SNOC_BIMC_SLV,
1194	.channels = 2,
1195	.buswidth = 8,
1196	.mas_rpm_id = -1,
1197	.slv_rpm_id = 24,
1198	.qos.ap_owned = true,
1199	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1200	.num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1201	.links = slv_snoc_bimc_links,
1202};
1203
1204static struct qcom_icc_node slv_imem = {
1205	.name = "slv_imem",
1206	.id = QNOC_SLAVE_SYSTEM_IMEM,
1207	.buswidth = 8,
1208	.mas_rpm_id = -1,
1209	.slv_rpm_id = 26,
1210};
1211
1212static const u16 slv_snoc_pcnoc_links[] = {
1213	QNOC_SNOC_PNOC_MAS
1214};
1215
1216static struct qcom_icc_node slv_snoc_pcnoc = {
1217	.name = "slv_snoc_pcnoc",
1218	.id = QNOC_SNOC_PNOC_SLV,
1219	.buswidth = 8,
1220	.mas_rpm_id = -1,
1221	.slv_rpm_id = 28,
1222	.num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
1223	.links = slv_snoc_pcnoc_links,
1224};
1225
1226static struct qcom_icc_node slv_qdss_stm = {
1227	.name = "slv_qdss_stm",
1228	.id = QNOC_SLAVE_QDSS_STM,
1229	.buswidth = 4,
1230	.mas_rpm_id = -1,
1231	.slv_rpm_id = 30,
1232};
1233
1234static struct qcom_icc_node slv_cats_0 = {
1235	.name = "slv_cats_0",
1236	.id = QNOC_SLAVE_CATS_128,
1237	.buswidth = 16,
1238	.mas_rpm_id = -1,
1239	.slv_rpm_id = 106,
1240	.qos.ap_owned = true,
1241	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1242};
1243
1244static struct qcom_icc_node slv_cats_1 = {
1245	.name = "slv_cats_1",
1246	.id = QNOC_SLAVE_OCMEM_64,
1247	.buswidth = 8,
1248	.mas_rpm_id = -1,
1249	.slv_rpm_id = 107,
1250	.qos.ap_owned = true,
1251	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1252};
1253
1254static struct qcom_icc_node slv_lpass = {
1255	.name = "slv_lpass",
1256	.id = QNOC_SLAVE_LPASS,
1257	.buswidth = 8,
1258	.mas_rpm_id = -1,
1259	.slv_rpm_id = 21,
1260	.qos.ap_owned = true,
1261	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1262};
1263
1264static struct qcom_icc_node * const msm8976_bimc_nodes[] = {
1265	[MAS_APPS_PROC] = &mas_apps_proc,
1266	[MAS_SMMNOC_BIMC] = &mas_smmnoc_bimc,
1267	[MAS_SNOC_BIMC] = &mas_snoc_bimc,
1268	[MAS_TCU_0] = &mas_tcu_0,
1269	[SLV_EBI] = &slv_ebi,
1270	[SLV_BIMC_SNOC] = &slv_bimc_snoc,
1271};
1272
1273static const struct regmap_config msm8976_bimc_regmap_config = {
1274	.reg_bits = 32,
1275	.reg_stride = 4,
1276	.val_bits = 32,
1277	.max_register = 0x62000,
1278	.fast_io = true,
1279};
1280
1281static const struct qcom_icc_desc msm8976_bimc = {
1282	.type = QCOM_ICC_BIMC,
1283	.nodes = msm8976_bimc_nodes,
1284	.num_nodes = ARRAY_SIZE(msm8976_bimc_nodes),
1285	.bus_clk_desc = &bimc_clk,
1286	.regmap_cfg = &msm8976_bimc_regmap_config,
1287	.qos_offset = 0x8000,
1288	.ab_coeff = 154,
1289};
1290
1291static struct qcom_icc_node * const msm8976_pcnoc_nodes[] = {
1292	[MAS_USB_HS2] = &mas_usb_hs2,
1293	[MAS_BLSP_1] = &mas_blsp_1,
1294	[MAS_USB_HS1] = &mas_usb_hs1,
1295	[MAS_BLSP_2] = &mas_blsp_2,
1296	[MAS_CRYPTO] = &mas_crypto,
1297	[MAS_SDCC_1] = &mas_sdcc_1,
1298	[MAS_SDCC_2] = &mas_sdcc_2,
1299	[MAS_SDCC_3] = &mas_sdcc_3,
1300	[MAS_SNOC_PCNOC] = &mas_snoc_pcnoc,
1301	[MAS_LPASS_AHB] = &mas_lpass_ahb,
1302	[MAS_SPDM] = &mas_spdm,
1303	[MAS_DEHR] = &mas_dehr,
1304	[MAS_XM_USB_HS1] = &mas_xm_usb_hs1,
1305	[PCNOC_M_0] = &pcnoc_m_0,
1306	[PCNOC_M_1] = &pcnoc_m_1,
1307	[PCNOC_INT_0] = &pcnoc_int_0,
1308	[PCNOC_INT_1] = &pcnoc_int_1,
1309	[PCNOC_INT_2] = &pcnoc_int_2,
1310	[PCNOC_S_1] = &pcnoc_s_1,
1311	[PCNOC_S_2] = &pcnoc_s_2,
1312	[PCNOC_S_3] = &pcnoc_s_3,
1313	[PCNOC_S_4] = &pcnoc_s_4,
1314	[PCNOC_S_8] = &pcnoc_s_8,
1315	[PCNOC_S_9] = &pcnoc_s_9,
1316	[SLV_TCSR] = &slv_tcsr,
1317	[SLV_TLMM] = &slv_tlmm,
1318	[SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1319	[SLV_MESSAGE_RAM] = &slv_message_ram,
1320	[SLV_PDM] = &slv_pdm,
1321	[SLV_PRNG] = &slv_prng,
1322	[SLV_PMIC_ARB] = &slv_pmic_arb,
1323	[SLV_SNOC_CFG] = &slv_snoc_cfg,
1324	[SLV_DCC_CFG] = &slv_dcc_cfg,
1325	[SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg,
1326	[SLV_DISP_SS_CFG] = &slv_disp_ss_cfg,
1327	[SLV_VENUS_CFG] = &slv_venus_cfg,
1328	[SLV_SDCC_1] = &slv_sdcc_1,
1329	[SLV_BLSP_1] = &slv_blsp_1,
1330	[SLV_USB_HS] = &slv_usb_hs,
1331	[SLV_SDCC_3] = &slv_sdcc_3,
1332	[SLV_SDCC_2] = &slv_sdcc_2,
1333	[SLV_GPU_CFG] = &slv_gpu_cfg,
1334	[SLV_USB_HS2] = &slv_usb_hs2,
1335	[SLV_BLSP_2] = &slv_blsp_2,
1336	[SLV_PCNOC_SNOC] = &slv_pcnoc_snoc,
1337};
1338
1339static const struct regmap_config msm8976_pcnoc_regmap_config = {
1340	.reg_bits = 32,
1341	.reg_stride = 4,
1342	.val_bits = 32,
1343	.max_register = 0x14000,
1344	.fast_io = true,
1345};
1346
1347static const struct qcom_icc_desc msm8976_pcnoc = {
1348	.type = QCOM_ICC_NOC,
1349	.nodes = msm8976_pcnoc_nodes,
1350	.num_nodes = ARRAY_SIZE(msm8976_pcnoc_nodes),
1351	.bus_clk_desc = &bus_0_clk,
1352	.qos_offset = 0x7000,
1353	.keep_alive = true,
1354	.regmap_cfg = &msm8976_pcnoc_regmap_config,
1355};
1356
1357static struct qcom_icc_node * const msm8976_snoc_nodes[] = {
1358	[MAS_QDSS_BAM] = &mas_qdss_bam,
1359	[MAS_BIMC_SNOC] = &mas_bimc_snoc,
1360	[MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
1361	[MAS_QDSS_ETR] = &mas_qdss_etr,
1362	[MAS_LPASS_PROC] = &mas_lpass_proc,
1363	[MAS_IPA] = &mas_ipa,
1364	[QDSS_INT] = &qdss_int,
1365	[SNOC_INT_0] = &snoc_int_0,
1366	[SNOC_INT_1] = &snoc_int_1,
1367	[SNOC_INT_2] = &snoc_int_2,
1368	[SLV_KPSS_AHB] = &slv_kpss_ahb,
1369	[SLV_SNOC_BIMC] = &slv_snoc_bimc,
1370	[SLV_IMEM] = &slv_imem,
1371	[SLV_SNOC_PCNOC] = &slv_snoc_pcnoc,
1372	[SLV_QDSS_STM] = &slv_qdss_stm,
1373	[SLV_CATS_0] = &slv_cats_0,
1374	[SLV_CATS_1] = &slv_cats_1,
1375	[SLV_LPASS] = &slv_lpass,
1376};
1377
1378static const struct regmap_config msm8976_snoc_regmap_config = {
1379	.reg_bits = 32,
1380	.reg_stride = 4,
1381	.val_bits = 32,
1382	.max_register = 0x1A000,
1383	.fast_io = true,
1384};
1385
1386static const struct qcom_icc_desc msm8976_snoc = {
1387	.type = QCOM_ICC_NOC,
1388	.nodes = msm8976_snoc_nodes,
1389	.num_nodes = ARRAY_SIZE(msm8976_snoc_nodes),
1390	.bus_clk_desc = &bus_1_clk,
1391	.regmap_cfg = &msm8976_snoc_regmap_config,
1392	.qos_offset = 0x7000,
1393};
1394
1395static struct qcom_icc_node * const msm8976_snoc_mm_nodes[] = {
1396	[MAS_JPEG] = &mas_jpeg,
1397	[MAS_OXILI] = &mas_oxili,
1398	[MAS_MDP0] = &mas_mdp0,
1399	[MAS_MDP1] = &mas_mdp1,
1400	[MAS_VENUS_0] = &mas_venus_0,
1401	[MAS_VENUS_1] = &mas_venus_1,
1402	[MAS_VFE_0] = &mas_vfe_0,
1403	[MAS_VFE_1] = &mas_vfe_1,
1404	[MAS_CPP] = &mas_cpp,
1405	[MM_INT_0] = &mm_int_0,
1406	[SLV_SMMNOC_BIMC] = &slv_smmnoc_bimc,
1407};
1408
1409static const struct qcom_icc_desc msm8976_snoc_mm = {
1410	.type = QCOM_ICC_NOC,
1411	.nodes = msm8976_snoc_mm_nodes,
1412	.num_nodes = ARRAY_SIZE(msm8976_snoc_mm_nodes),
1413	.bus_clk_desc = &bus_2_clk,
1414	.regmap_cfg = &msm8976_snoc_regmap_config,
1415	.qos_offset = 0x7000,
1416	.ab_coeff = 154,
1417};
1418
1419static const struct of_device_id msm8976_noc_of_match[] = {
1420	{ .compatible = "qcom,msm8976-bimc", .data = &msm8976_bimc },
1421	{ .compatible = "qcom,msm8976-pcnoc", .data = &msm8976_pcnoc },
1422	{ .compatible = "qcom,msm8976-snoc", .data = &msm8976_snoc },
1423	{ .compatible = "qcom,msm8976-snoc-mm", .data = &msm8976_snoc_mm },
1424	{ }
1425};
1426MODULE_DEVICE_TABLE(of, msm8976_noc_of_match);
1427
1428static struct platform_driver msm8976_noc_driver = {
1429	.probe = qnoc_probe,
1430	.remove = qnoc_remove,
1431	.driver = {
1432		.name = "qnoc-msm8976",
1433		.of_match_table = msm8976_noc_of_match,
1434		.sync_state = icc_sync_state,
1435	},
1436};
1437module_platform_driver(msm8976_noc_driver);
1438
1439MODULE_DESCRIPTION("Qualcomm MSM8976 NoC driver");
1440MODULE_LICENSE("GPL");