msm8939.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2020 Linaro Ltd
   4 * Author: Jun Nie <jun.nie@linaro.org>
   5 * With reference of msm8916 interconnect driver of Georgi Djakov.
   6 */
   7
   8#include <linux/device.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/mod_devicetable.h>
  13#include <linux/platform_device.h>
  14#include <linux/regmap.h>
  15
  16#include <dt-bindings/interconnect/qcom,msm8939.h>
  17
  18#include "icc-rpm.h"
  19
  20enum {
  21	MSM8939_BIMC_SNOC_MAS = 1,
  22	MSM8939_BIMC_SNOC_SLV,
  23	MSM8939_MASTER_AMPSS_M0,
  24	MSM8939_MASTER_LPASS,
  25	MSM8939_MASTER_BLSP_1,
  26	MSM8939_MASTER_DEHR,
  27	MSM8939_MASTER_GRAPHICS_3D,
  28	MSM8939_MASTER_JPEG,
  29	MSM8939_MASTER_MDP_PORT0,
  30	MSM8939_MASTER_MDP_PORT1,
  31	MSM8939_MASTER_CPP,
  32	MSM8939_MASTER_CRYPTO_CORE0,
  33	MSM8939_MASTER_SDCC_1,
  34	MSM8939_MASTER_SDCC_2,
  35	MSM8939_MASTER_QDSS_BAM,
  36	MSM8939_MASTER_QDSS_ETR,
  37	MSM8939_MASTER_SNOC_CFG,
  38	MSM8939_MASTER_SPDM,
  39	MSM8939_MASTER_TCU0,
  40	MSM8939_MASTER_USB_HS1,
  41	MSM8939_MASTER_USB_HS2,
  42	MSM8939_MASTER_VFE,
  43	MSM8939_MASTER_VIDEO_P0,
  44	MSM8939_SNOC_MM_INT_0,
  45	MSM8939_SNOC_MM_INT_1,
  46	MSM8939_SNOC_MM_INT_2,
  47	MSM8939_PNOC_INT_0,
  48	MSM8939_PNOC_INT_1,
  49	MSM8939_PNOC_MAS_0,
  50	MSM8939_PNOC_MAS_1,
  51	MSM8939_PNOC_SLV_0,
  52	MSM8939_PNOC_SLV_1,
  53	MSM8939_PNOC_SLV_2,
  54	MSM8939_PNOC_SLV_3,
  55	MSM8939_PNOC_SLV_4,
  56	MSM8939_PNOC_SLV_8,
  57	MSM8939_PNOC_SLV_9,
  58	MSM8939_PNOC_SNOC_MAS,
  59	MSM8939_PNOC_SNOC_SLV,
  60	MSM8939_SNOC_QDSS_INT,
  61	MSM8939_SLAVE_AMPSS_L2,
  62	MSM8939_SLAVE_APSS,
  63	MSM8939_SLAVE_LPASS,
  64	MSM8939_SLAVE_BIMC_CFG,
  65	MSM8939_SLAVE_BLSP_1,
  66	MSM8939_SLAVE_BOOT_ROM,
  67	MSM8939_SLAVE_CAMERA_CFG,
  68	MSM8939_SLAVE_CATS_128,
  69	MSM8939_SLAVE_OCMEM_64,
  70	MSM8939_SLAVE_CLK_CTL,
  71	MSM8939_SLAVE_CRYPTO_0_CFG,
  72	MSM8939_SLAVE_DEHR_CFG,
  73	MSM8939_SLAVE_DISPLAY_CFG,
  74	MSM8939_SLAVE_EBI_CH0,
  75	MSM8939_SLAVE_GRAPHICS_3D_CFG,
  76	MSM8939_SLAVE_IMEM_CFG,
  77	MSM8939_SLAVE_IMEM,
  78	MSM8939_SLAVE_MPM,
  79	MSM8939_SLAVE_MSG_RAM,
  80	MSM8939_SLAVE_MSS,
  81	MSM8939_SLAVE_PDM,
  82	MSM8939_SLAVE_PMIC_ARB,
  83	MSM8939_SLAVE_PNOC_CFG,
  84	MSM8939_SLAVE_PRNG,
  85	MSM8939_SLAVE_QDSS_CFG,
  86	MSM8939_SLAVE_QDSS_STM,
  87	MSM8939_SLAVE_RBCPR_CFG,
  88	MSM8939_SLAVE_SDCC_1,
  89	MSM8939_SLAVE_SDCC_2,
  90	MSM8939_SLAVE_SECURITY,
  91	MSM8939_SLAVE_SNOC_CFG,
  92	MSM8939_SLAVE_SPDM,
  93	MSM8939_SLAVE_SRVC_SNOC,
  94	MSM8939_SLAVE_TCSR,
  95	MSM8939_SLAVE_TLMM,
  96	MSM8939_SLAVE_USB_HS1,
  97	MSM8939_SLAVE_USB_HS2,
  98	MSM8939_SLAVE_VENUS_CFG,
  99	MSM8939_SNOC_BIMC_0_MAS,
 100	MSM8939_SNOC_BIMC_0_SLV,
 101	MSM8939_SNOC_BIMC_1_MAS,
 102	MSM8939_SNOC_BIMC_1_SLV,
 103	MSM8939_SNOC_BIMC_2_MAS,
 104	MSM8939_SNOC_BIMC_2_SLV,
 105	MSM8939_SNOC_INT_0,
 106	MSM8939_SNOC_INT_1,
 107	MSM8939_SNOC_INT_BIMC,
 108	MSM8939_SNOC_PNOC_MAS,
 109	MSM8939_SNOC_PNOC_SLV,
 110};
 111
 112static const u16 bimc_snoc_mas_links[] = {
 113	MSM8939_BIMC_SNOC_SLV
 114};
 115
 116static struct qcom_icc_node bimc_snoc_mas = {
 117	.name = "bimc_snoc_mas",
 118	.id = MSM8939_BIMC_SNOC_MAS,
 119	.buswidth = 8,
 120	.mas_rpm_id = -1,
 121	.slv_rpm_id = -1,
 122	.qos.ap_owned = true,
 123	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 124	.num_links = ARRAY_SIZE(bimc_snoc_mas_links),
 125	.links = bimc_snoc_mas_links,
 126};
 127
 128static const u16 bimc_snoc_slv_links[] = {
 129	MSM8939_SNOC_INT_0,
 130	MSM8939_SNOC_INT_1
 131};
 132
 133static struct qcom_icc_node bimc_snoc_slv = {
 134	.name = "bimc_snoc_slv",
 135	.id = MSM8939_BIMC_SNOC_SLV,
 136	.buswidth = 16,
 137	.mas_rpm_id = -1,
 138	.slv_rpm_id = 2,
 139	.num_links = ARRAY_SIZE(bimc_snoc_slv_links),
 140	.links = bimc_snoc_slv_links,
 141};
 142
 143static const u16 mas_apss_links[] = {
 144	MSM8939_SLAVE_EBI_CH0,
 145	MSM8939_BIMC_SNOC_MAS,
 146	MSM8939_SLAVE_AMPSS_L2
 147};
 148
 149static struct qcom_icc_node mas_apss = {
 150	.name = "mas_apss",
 151	.id = MSM8939_MASTER_AMPSS_M0,
 152	.buswidth = 16,
 153	.mas_rpm_id = -1,
 154	.slv_rpm_id = -1,
 155	.qos.ap_owned = true,
 156	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 157	.qos.areq_prio = 0,
 158	.qos.prio_level = 0,
 159	.qos.qos_port = 0,
 160	.num_links = ARRAY_SIZE(mas_apss_links),
 161	.links = mas_apss_links,
 162};
 163
 164static const u16 mas_audio_links[] = {
 165	MSM8939_PNOC_MAS_0
 166};
 167
 168static struct qcom_icc_node mas_audio = {
 169	.name = "mas_audio",
 170	.id = MSM8939_MASTER_LPASS,
 171	.buswidth = 4,
 172	.mas_rpm_id = -1,
 173	.slv_rpm_id = -1,
 174	.num_links = ARRAY_SIZE(mas_audio_links),
 175	.links = mas_audio_links,
 176};
 177
 178static const u16 mas_blsp_1_links[] = {
 179	MSM8939_PNOC_MAS_1
 180};
 181
 182static struct qcom_icc_node mas_blsp_1 = {
 183	.name = "mas_blsp_1",
 184	.id = MSM8939_MASTER_BLSP_1,
 185	.buswidth = 4,
 186	.mas_rpm_id = -1,
 187	.slv_rpm_id = -1,
 188	.num_links = ARRAY_SIZE(mas_blsp_1_links),
 189	.links = mas_blsp_1_links,
 190};
 191
 192static const u16 mas_dehr_links[] = {
 193	MSM8939_PNOC_MAS_0
 194};
 195
 196static struct qcom_icc_node mas_dehr = {
 197	.name = "mas_dehr",
 198	.id = MSM8939_MASTER_DEHR,
 199	.buswidth = 4,
 200	.mas_rpm_id = -1,
 201	.slv_rpm_id = -1,
 202	.num_links = ARRAY_SIZE(mas_dehr_links),
 203	.links = mas_dehr_links,
 204};
 205
 206static const u16 mas_gfx_links[] = {
 207	MSM8939_SLAVE_EBI_CH0,
 208	MSM8939_BIMC_SNOC_MAS,
 209	MSM8939_SLAVE_AMPSS_L2
 210};
 211
 212static struct qcom_icc_node mas_gfx = {
 213	.name = "mas_gfx",
 214	.id = MSM8939_MASTER_GRAPHICS_3D,
 215	.buswidth = 16,
 216	.mas_rpm_id = -1,
 217	.slv_rpm_id = -1,
 218	.qos.ap_owned = true,
 219	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 220	.qos.areq_prio = 0,
 221	.qos.prio_level = 0,
 222	.qos.qos_port = 2,
 223	.num_links = ARRAY_SIZE(mas_gfx_links),
 224	.links = mas_gfx_links,
 225};
 226
 227static const u16 mas_jpeg_links[] = {
 228	MSM8939_SNOC_MM_INT_0,
 229	MSM8939_SNOC_MM_INT_2
 230};
 231
 232static struct qcom_icc_node mas_jpeg = {
 233	.name = "mas_jpeg",
 234	.id = MSM8939_MASTER_JPEG,
 235	.buswidth = 16,
 236	.mas_rpm_id = -1,
 237	.slv_rpm_id = -1,
 238	.qos.ap_owned = true,
 239	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 240	.qos.areq_prio = 0,
 241	.qos.prio_level = 0,
 242	.qos.qos_port = 6,
 243	.num_links = ARRAY_SIZE(mas_jpeg_links),
 244	.links = mas_jpeg_links,
 245};
 246
 247static const u16 mas_mdp0_links[] = {
 248	MSM8939_SNOC_MM_INT_1,
 249	MSM8939_SNOC_MM_INT_2
 250};
 251
 252static struct qcom_icc_node mas_mdp0 = {
 253	.name = "mas_mdp0",
 254	.id = MSM8939_MASTER_MDP_PORT0,
 255	.buswidth = 16,
 256	.mas_rpm_id = -1,
 257	.slv_rpm_id = -1,
 258	.qos.ap_owned = true,
 259	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 260	.qos.areq_prio = 0,
 261	.qos.prio_level = 0,
 262	.qos.qos_port = 7,
 263	.num_links = ARRAY_SIZE(mas_mdp0_links),
 264	.links = mas_mdp0_links,
 265};
 266
 267static const u16 mas_mdp1_links[] = {
 268	MSM8939_SNOC_MM_INT_0,
 269	MSM8939_SNOC_MM_INT_2
 270};
 271
 272static struct qcom_icc_node mas_mdp1 = {
 273	.name = "mas_mdp1",
 274	.id = MSM8939_MASTER_MDP_PORT1,
 275	.buswidth = 16,
 276	.mas_rpm_id = -1,
 277	.slv_rpm_id = -1,
 278	.qos.ap_owned = true,
 279	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 280	.qos.areq_prio = 0,
 281	.qos.prio_level = 0,
 282	.qos.qos_port = 13,
 283	.num_links = ARRAY_SIZE(mas_mdp1_links),
 284	.links = mas_mdp1_links,
 285};
 286
 287static const u16 mas_cpp_links[] = {
 288	MSM8939_SNOC_MM_INT_0,
 289	MSM8939_SNOC_MM_INT_2
 290};
 291
 292static struct qcom_icc_node mas_cpp = {
 293	.name = "mas_cpp",
 294	.id = MSM8939_MASTER_CPP,
 295	.buswidth = 16,
 296	.mas_rpm_id = -1,
 297	.slv_rpm_id = -1,
 298	.qos.ap_owned = true,
 299	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 300	.qos.areq_prio = 0,
 301	.qos.prio_level = 0,
 302	.qos.qos_port = 12,
 303	.num_links = ARRAY_SIZE(mas_cpp_links),
 304	.links = mas_cpp_links,
 305};
 306
 307static const u16 mas_pcnoc_crypto_0_links[] = {
 308	MSM8939_PNOC_INT_1
 309};
 310
 311static struct qcom_icc_node mas_pcnoc_crypto_0 = {
 312	.name = "mas_pcnoc_crypto_0",
 313	.id = MSM8939_MASTER_CRYPTO_CORE0,
 314	.buswidth = 8,
 315	.mas_rpm_id = -1,
 316	.slv_rpm_id = -1,
 317	.num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links),
 318	.links = mas_pcnoc_crypto_0_links,
 319};
 320
 321static const u16 mas_pcnoc_sdcc_1_links[] = {
 322	MSM8939_PNOC_INT_1
 323};
 324
 325static struct qcom_icc_node mas_pcnoc_sdcc_1 = {
 326	.name = "mas_pcnoc_sdcc_1",
 327	.id = MSM8939_MASTER_SDCC_1,
 328	.buswidth = 8,
 329	.mas_rpm_id = -1,
 330	.slv_rpm_id = -1,
 331	.num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links),
 332	.links = mas_pcnoc_sdcc_1_links,
 333};
 334
 335static const u16 mas_pcnoc_sdcc_2_links[] = {
 336	MSM8939_PNOC_INT_1
 337};
 338
 339static struct qcom_icc_node mas_pcnoc_sdcc_2 = {
 340	.name = "mas_pcnoc_sdcc_2",
 341	.id = MSM8939_MASTER_SDCC_2,
 342	.buswidth = 8,
 343	.mas_rpm_id = -1,
 344	.slv_rpm_id = -1,
 345	.num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links),
 346	.links = mas_pcnoc_sdcc_2_links,
 347};
 348
 349static const u16 mas_qdss_bam_links[] = {
 350	MSM8939_SNOC_QDSS_INT
 351};
 352
 353static struct qcom_icc_node mas_qdss_bam = {
 354	.name = "mas_qdss_bam",
 355	.id = MSM8939_MASTER_QDSS_BAM,
 356	.buswidth = 8,
 357	.mas_rpm_id = -1,
 358	.slv_rpm_id = -1,
 359	.qos.ap_owned = true,
 360	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 361	.qos.areq_prio = 1,
 362	.qos.prio_level = 1,
 363	.qos.qos_port = 11,
 364	.num_links = ARRAY_SIZE(mas_qdss_bam_links),
 365	.links = mas_qdss_bam_links,
 366};
 367
 368static const u16 mas_qdss_etr_links[] = {
 369	MSM8939_SNOC_QDSS_INT
 370};
 371
 372static struct qcom_icc_node mas_qdss_etr = {
 373	.name = "mas_qdss_etr",
 374	.id = MSM8939_MASTER_QDSS_ETR,
 375	.buswidth = 8,
 376	.mas_rpm_id = -1,
 377	.slv_rpm_id = -1,
 378	.qos.ap_owned = true,
 379	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 380	.qos.areq_prio = 1,
 381	.qos.prio_level = 1,
 382	.qos.qos_port = 10,
 383	.num_links = ARRAY_SIZE(mas_qdss_etr_links),
 384	.links = mas_qdss_etr_links,
 385};
 386
 387static const u16 mas_snoc_cfg_links[] = {
 388	MSM8939_SLAVE_SRVC_SNOC
 389};
 390
 391static struct qcom_icc_node mas_snoc_cfg = {
 392	.name = "mas_snoc_cfg",
 393	.id = MSM8939_MASTER_SNOC_CFG,
 394	.buswidth = 4,
 395	.mas_rpm_id = -1,
 396	.slv_rpm_id = -1,
 397	.num_links = ARRAY_SIZE(mas_snoc_cfg_links),
 398	.links = mas_snoc_cfg_links,
 399};
 400
 401static const u16 mas_spdm_links[] = {
 402	MSM8939_PNOC_MAS_0
 403};
 404
 405static struct qcom_icc_node mas_spdm = {
 406	.name = "mas_spdm",
 407	.id = MSM8939_MASTER_SPDM,
 408	.buswidth = 4,
 409	.mas_rpm_id = -1,
 410	.slv_rpm_id = -1,
 411	.num_links = ARRAY_SIZE(mas_spdm_links),
 412	.links = mas_spdm_links,
 413};
 414
 415static const u16 mas_tcu0_links[] = {
 416	MSM8939_SLAVE_EBI_CH0,
 417	MSM8939_BIMC_SNOC_MAS,
 418	MSM8939_SLAVE_AMPSS_L2
 419};
 420
 421static struct qcom_icc_node mas_tcu0 = {
 422	.name = "mas_tcu0",
 423	.id = MSM8939_MASTER_TCU0,
 424	.buswidth = 16,
 425	.mas_rpm_id = -1,
 426	.slv_rpm_id = -1,
 427	.qos.ap_owned = true,
 428	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 429	.qos.areq_prio = 2,
 430	.qos.prio_level = 2,
 431	.qos.qos_port = 6,
 432	.num_links = ARRAY_SIZE(mas_tcu0_links),
 433	.links = mas_tcu0_links,
 434};
 435
 436static const u16 mas_usb_hs1_links[] = {
 437	MSM8939_PNOC_MAS_1
 438};
 439
 440static struct qcom_icc_node mas_usb_hs1 = {
 441	.name = "mas_usb_hs1",
 442	.id = MSM8939_MASTER_USB_HS1,
 443	.buswidth = 4,
 444	.mas_rpm_id = -1,
 445	.slv_rpm_id = -1,
 446	.num_links = ARRAY_SIZE(mas_usb_hs1_links),
 447	.links = mas_usb_hs1_links,
 448};
 449
 450static const u16 mas_usb_hs2_links[] = {
 451	MSM8939_PNOC_MAS_1
 452};
 453
 454static struct qcom_icc_node mas_usb_hs2 = {
 455	.name = "mas_usb_hs2",
 456	.id = MSM8939_MASTER_USB_HS2,
 457	.buswidth = 4,
 458	.mas_rpm_id = -1,
 459	.slv_rpm_id = -1,
 460	.num_links = ARRAY_SIZE(mas_usb_hs2_links),
 461	.links = mas_usb_hs2_links,
 462};
 463
 464static const u16 mas_vfe_links[] = {
 465	MSM8939_SNOC_MM_INT_1,
 466	MSM8939_SNOC_MM_INT_2
 467};
 468
 469static struct qcom_icc_node mas_vfe = {
 470	.name = "mas_vfe",
 471	.id = MSM8939_MASTER_VFE,
 472	.buswidth = 16,
 473	.mas_rpm_id = -1,
 474	.slv_rpm_id = -1,
 475	.qos.ap_owned = true,
 476	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 477	.qos.areq_prio = 0,
 478	.qos.prio_level = 0,
 479	.qos.qos_port = 9,
 480	.num_links = ARRAY_SIZE(mas_vfe_links),
 481	.links = mas_vfe_links,
 482};
 483
 484static const u16 mas_video_links[] = {
 485	MSM8939_SNOC_MM_INT_0,
 486	MSM8939_SNOC_MM_INT_2
 487};
 488
 489static struct qcom_icc_node mas_video = {
 490	.name = "mas_video",
 491	.id = MSM8939_MASTER_VIDEO_P0,
 492	.buswidth = 16,
 493	.mas_rpm_id = -1,
 494	.slv_rpm_id = -1,
 495	.qos.ap_owned = true,
 496	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 497	.qos.areq_prio = 0,
 498	.qos.prio_level = 0,
 499	.qos.qos_port = 8,
 500	.num_links = ARRAY_SIZE(mas_video_links),
 501	.links = mas_video_links,
 502};
 503
 504static const u16 mm_int_0_links[] = {
 505	MSM8939_SNOC_BIMC_2_MAS
 506};
 507
 508static struct qcom_icc_node mm_int_0 = {
 509	.name = "mm_int_0",
 510	.id = MSM8939_SNOC_MM_INT_0,
 511	.buswidth = 16,
 512	.mas_rpm_id = -1,
 513	.slv_rpm_id = -1,
 514	.qos.ap_owned = true,
 515	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 516	.num_links = ARRAY_SIZE(mm_int_0_links),
 517	.links = mm_int_0_links,
 518};
 519
 520static const u16 mm_int_1_links[] = {
 521	MSM8939_SNOC_BIMC_1_MAS
 522};
 523
 524static struct qcom_icc_node mm_int_1 = {
 525	.name = "mm_int_1",
 526	.id = MSM8939_SNOC_MM_INT_1,
 527	.buswidth = 16,
 528	.mas_rpm_id = -1,
 529	.slv_rpm_id = -1,
 530	.qos.ap_owned = true,
 531	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 532	.num_links = ARRAY_SIZE(mm_int_1_links),
 533	.links = mm_int_1_links,
 534};
 535
 536static const u16 mm_int_2_links[] = {
 537	MSM8939_SNOC_INT_0
 538};
 539
 540static struct qcom_icc_node mm_int_2 = {
 541	.name = "mm_int_2",
 542	.id = MSM8939_SNOC_MM_INT_2,
 543	.buswidth = 16,
 544	.mas_rpm_id = -1,
 545	.slv_rpm_id = -1,
 546	.qos.ap_owned = true,
 547	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 548	.num_links = ARRAY_SIZE(mm_int_2_links),
 549	.links = mm_int_2_links,
 550};
 551
 552static const u16 pcnoc_int_0_links[] = {
 553	MSM8939_PNOC_SNOC_MAS,
 554	MSM8939_PNOC_SLV_0,
 555	MSM8939_PNOC_SLV_1,
 556	MSM8939_PNOC_SLV_2,
 557	MSM8939_PNOC_SLV_3,
 558	MSM8939_PNOC_SLV_4,
 559	MSM8939_PNOC_SLV_8,
 560	MSM8939_PNOC_SLV_9
 561};
 562
 563static struct qcom_icc_node pcnoc_int_0 = {
 564	.name = "pcnoc_int_0",
 565	.id = MSM8939_PNOC_INT_0,
 566	.buswidth = 8,
 567	.mas_rpm_id = -1,
 568	.slv_rpm_id = -1,
 569	.num_links = ARRAY_SIZE(pcnoc_int_0_links),
 570	.links = pcnoc_int_0_links,
 571};
 572
 573static const u16 pcnoc_int_1_links[] = {
 574	MSM8939_PNOC_SNOC_MAS
 575};
 576
 577static struct qcom_icc_node pcnoc_int_1 = {
 578	.name = "pcnoc_int_1",
 579	.id = MSM8939_PNOC_INT_1,
 580	.buswidth = 8,
 581	.mas_rpm_id = -1,
 582	.slv_rpm_id = -1,
 583	.num_links = ARRAY_SIZE(pcnoc_int_1_links),
 584	.links = pcnoc_int_1_links,
 585};
 586
 587static const u16 pcnoc_m_0_links[] = {
 588	MSM8939_PNOC_INT_0
 589};
 590
 591static struct qcom_icc_node pcnoc_m_0 = {
 592	.name = "pcnoc_m_0",
 593	.id = MSM8939_PNOC_MAS_0,
 594	.buswidth = 8,
 595	.mas_rpm_id = -1,
 596	.slv_rpm_id = -1,
 597	.num_links = ARRAY_SIZE(pcnoc_m_0_links),
 598	.links = pcnoc_m_0_links,
 599};
 600
 601static const u16 pcnoc_m_1_links[] = {
 602	MSM8939_PNOC_SNOC_MAS
 603};
 604
 605static struct qcom_icc_node pcnoc_m_1 = {
 606	.name = "pcnoc_m_1",
 607	.id = MSM8939_PNOC_MAS_1,
 608	.buswidth = 8,
 609	.mas_rpm_id = -1,
 610	.slv_rpm_id = -1,
 611	.num_links = ARRAY_SIZE(pcnoc_m_1_links),
 612	.links = pcnoc_m_1_links,
 613};
 614
 615static const u16 pcnoc_s_0_links[] = {
 616	MSM8939_SLAVE_CLK_CTL,
 617	MSM8939_SLAVE_TLMM,
 618	MSM8939_SLAVE_TCSR,
 619	MSM8939_SLAVE_SECURITY,
 620	MSM8939_SLAVE_MSS
 621};
 622
 623static struct qcom_icc_node pcnoc_s_0 = {
 624	.name = "pcnoc_s_0",
 625	.id = MSM8939_PNOC_SLV_0,
 626	.buswidth = 4,
 627	.mas_rpm_id = -1,
 628	.slv_rpm_id = -1,
 629	.num_links = ARRAY_SIZE(pcnoc_s_0_links),
 630	.links = pcnoc_s_0_links,
 631};
 632
 633static const u16 pcnoc_s_1_links[] = {
 634	MSM8939_SLAVE_IMEM_CFG,
 635	MSM8939_SLAVE_CRYPTO_0_CFG,
 636	MSM8939_SLAVE_MSG_RAM,
 637	MSM8939_SLAVE_PDM,
 638	MSM8939_SLAVE_PRNG
 639};
 640
 641static struct qcom_icc_node pcnoc_s_1 = {
 642	.name = "pcnoc_s_1",
 643	.id = MSM8939_PNOC_SLV_1,
 644	.buswidth = 4,
 645	.mas_rpm_id = -1,
 646	.slv_rpm_id = -1,
 647	.num_links = ARRAY_SIZE(pcnoc_s_1_links),
 648	.links = pcnoc_s_1_links,
 649};
 650
 651static const u16 pcnoc_s_2_links[] = {
 652	MSM8939_SLAVE_SPDM,
 653	MSM8939_SLAVE_BOOT_ROM,
 654	MSM8939_SLAVE_BIMC_CFG,
 655	MSM8939_SLAVE_PNOC_CFG,
 656	MSM8939_SLAVE_PMIC_ARB
 657};
 658
 659static struct qcom_icc_node pcnoc_s_2 = {
 660	.name = "pcnoc_s_2",
 661	.id = MSM8939_PNOC_SLV_2,
 662	.buswidth = 4,
 663	.mas_rpm_id = -1,
 664	.slv_rpm_id = -1,
 665	.num_links = ARRAY_SIZE(pcnoc_s_2_links),
 666	.links = pcnoc_s_2_links,
 667};
 668
 669static const u16 pcnoc_s_3_links[] = {
 670	MSM8939_SLAVE_MPM,
 671	MSM8939_SLAVE_SNOC_CFG,
 672	MSM8939_SLAVE_RBCPR_CFG,
 673	MSM8939_SLAVE_QDSS_CFG,
 674	MSM8939_SLAVE_DEHR_CFG
 675};
 676
 677static struct qcom_icc_node pcnoc_s_3 = {
 678	.name = "pcnoc_s_3",
 679	.id = MSM8939_PNOC_SLV_3,
 680	.buswidth = 4,
 681	.mas_rpm_id = -1,
 682	.slv_rpm_id = -1,
 683	.num_links = ARRAY_SIZE(pcnoc_s_3_links),
 684	.links = pcnoc_s_3_links,
 685};
 686
 687static const u16 pcnoc_s_4_links[] = {
 688	MSM8939_SLAVE_VENUS_CFG,
 689	MSM8939_SLAVE_CAMERA_CFG,
 690	MSM8939_SLAVE_DISPLAY_CFG
 691};
 692
 693static struct qcom_icc_node pcnoc_s_4 = {
 694	.name = "pcnoc_s_4",
 695	.id = MSM8939_PNOC_SLV_4,
 696	.buswidth = 4,
 697	.mas_rpm_id = -1,
 698	.slv_rpm_id = -1,
 699	.num_links = ARRAY_SIZE(pcnoc_s_4_links),
 700	.links = pcnoc_s_4_links,
 701};
 702
 703static const u16 pcnoc_s_8_links[] = {
 704	MSM8939_SLAVE_USB_HS1,
 705	MSM8939_SLAVE_SDCC_1,
 706	MSM8939_SLAVE_BLSP_1
 707};
 708
 709static struct qcom_icc_node pcnoc_s_8 = {
 710	.name = "pcnoc_s_8",
 711	.id = MSM8939_PNOC_SLV_8,
 712	.buswidth = 4,
 713	.mas_rpm_id = -1,
 714	.slv_rpm_id = -1,
 715	.num_links = ARRAY_SIZE(pcnoc_s_8_links),
 716	.links = pcnoc_s_8_links,
 717};
 718
 719static const u16 pcnoc_s_9_links[] = {
 720	MSM8939_SLAVE_SDCC_2,
 721	MSM8939_SLAVE_LPASS,
 722	MSM8939_SLAVE_USB_HS2
 723};
 724
 725static struct qcom_icc_node pcnoc_s_9 = {
 726	.name = "pcnoc_s_9",
 727	.id = MSM8939_PNOC_SLV_9,
 728	.buswidth = 4,
 729	.mas_rpm_id = -1,
 730	.slv_rpm_id = -1,
 731	.num_links = ARRAY_SIZE(pcnoc_s_9_links),
 732	.links = pcnoc_s_9_links,
 733};
 734
 735static const u16 pcnoc_snoc_mas_links[] = {
 736	MSM8939_PNOC_SNOC_SLV
 737};
 738
 739static struct qcom_icc_node pcnoc_snoc_mas = {
 740	.name = "pcnoc_snoc_mas",
 741	.id = MSM8939_PNOC_SNOC_MAS,
 742	.buswidth = 8,
 743	.mas_rpm_id = 29,
 744	.slv_rpm_id = -1,
 745	.num_links = ARRAY_SIZE(pcnoc_snoc_mas_links),
 746	.links = pcnoc_snoc_mas_links,
 747};
 748
 749static const u16 pcnoc_snoc_slv_links[] = {
 750	MSM8939_SNOC_INT_0,
 751	MSM8939_SNOC_INT_BIMC,
 752	MSM8939_SNOC_INT_1
 753};
 754
 755static struct qcom_icc_node pcnoc_snoc_slv = {
 756	.name = "pcnoc_snoc_slv",
 757	.id = MSM8939_PNOC_SNOC_SLV,
 758	.buswidth = 8,
 759	.mas_rpm_id = -1,
 760	.slv_rpm_id = 45,
 761	.num_links = ARRAY_SIZE(pcnoc_snoc_slv_links),
 762	.links = pcnoc_snoc_slv_links,
 763};
 764
 765static const u16 qdss_int_links[] = {
 766	MSM8939_SNOC_INT_0,
 767	MSM8939_SNOC_INT_BIMC
 768};
 769
 770static struct qcom_icc_node qdss_int = {
 771	.name = "qdss_int",
 772	.id = MSM8939_SNOC_QDSS_INT,
 773	.buswidth = 8,
 774	.mas_rpm_id = -1,
 775	.slv_rpm_id = -1,
 776	.qos.ap_owned = true,
 777	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 778	.num_links = ARRAY_SIZE(qdss_int_links),
 779	.links = qdss_int_links,
 780};
 781
 782static struct qcom_icc_node slv_apps_l2 = {
 783	.name = "slv_apps_l2",
 784	.id = MSM8939_SLAVE_AMPSS_L2,
 785	.buswidth = 16,
 786	.mas_rpm_id = -1,
 787	.slv_rpm_id = -1,
 788};
 789
 790static struct qcom_icc_node slv_apss = {
 791	.name = "slv_apss",
 792	.id = MSM8939_SLAVE_APSS,
 793	.buswidth = 4,
 794	.mas_rpm_id = -1,
 795	.slv_rpm_id = -1,
 796};
 797
 798static struct qcom_icc_node slv_audio = {
 799	.name = "slv_audio",
 800	.id = MSM8939_SLAVE_LPASS,
 801	.buswidth = 4,
 802	.mas_rpm_id = -1,
 803	.slv_rpm_id = -1,
 804};
 805
 806static struct qcom_icc_node slv_bimc_cfg = {
 807	.name = "slv_bimc_cfg",
 808	.id = MSM8939_SLAVE_BIMC_CFG,
 809	.buswidth = 4,
 810	.mas_rpm_id = -1,
 811	.slv_rpm_id = -1,
 812};
 813
 814static struct qcom_icc_node slv_blsp_1 = {
 815	.name = "slv_blsp_1",
 816	.id = MSM8939_SLAVE_BLSP_1,
 817	.buswidth = 4,
 818	.mas_rpm_id = -1,
 819	.slv_rpm_id = -1,
 820};
 821
 822static struct qcom_icc_node slv_boot_rom = {
 823	.name = "slv_boot_rom",
 824	.id = MSM8939_SLAVE_BOOT_ROM,
 825	.buswidth = 4,
 826	.mas_rpm_id = -1,
 827	.slv_rpm_id = -1,
 828};
 829
 830static struct qcom_icc_node slv_camera_cfg = {
 831	.name = "slv_camera_cfg",
 832	.id = MSM8939_SLAVE_CAMERA_CFG,
 833	.buswidth = 4,
 834	.mas_rpm_id = -1,
 835	.slv_rpm_id = -1,
 836};
 837
 838static struct qcom_icc_node slv_cats_0 = {
 839	.name = "slv_cats_0",
 840	.id = MSM8939_SLAVE_CATS_128,
 841	.buswidth = 16,
 842	.mas_rpm_id = -1,
 843	.slv_rpm_id = -1,
 844};
 845
 846static struct qcom_icc_node slv_cats_1 = {
 847	.name = "slv_cats_1",
 848	.id = MSM8939_SLAVE_OCMEM_64,
 849	.buswidth = 8,
 850	.mas_rpm_id = -1,
 851	.slv_rpm_id = -1,
 852};
 853
 854static struct qcom_icc_node slv_clk_ctl = {
 855	.name = "slv_clk_ctl",
 856	.id = MSM8939_SLAVE_CLK_CTL,
 857	.buswidth = 4,
 858	.mas_rpm_id = -1,
 859	.slv_rpm_id = -1,
 860};
 861
 862static struct qcom_icc_node slv_crypto_0_cfg = {
 863	.name = "slv_crypto_0_cfg",
 864	.id = MSM8939_SLAVE_CRYPTO_0_CFG,
 865	.buswidth = 4,
 866	.mas_rpm_id = -1,
 867	.slv_rpm_id = -1,
 868};
 869
 870static struct qcom_icc_node slv_dehr_cfg = {
 871	.name = "slv_dehr_cfg",
 872	.id = MSM8939_SLAVE_DEHR_CFG,
 873	.buswidth = 4,
 874	.mas_rpm_id = -1,
 875	.slv_rpm_id = -1,
 876};
 877
 878static struct qcom_icc_node slv_display_cfg = {
 879	.name = "slv_display_cfg",
 880	.id = MSM8939_SLAVE_DISPLAY_CFG,
 881	.buswidth = 4,
 882	.mas_rpm_id = -1,
 883	.slv_rpm_id = -1,
 884};
 885
 886static struct qcom_icc_node slv_ebi_ch0 = {
 887	.name = "slv_ebi_ch0",
 888	.id = MSM8939_SLAVE_EBI_CH0,
 889	.buswidth = 16,
 890	.mas_rpm_id = -1,
 891	.slv_rpm_id = 0,
 892};
 893
 894static struct qcom_icc_node slv_gfx_cfg = {
 895	.name = "slv_gfx_cfg",
 896	.id = MSM8939_SLAVE_GRAPHICS_3D_CFG,
 897	.buswidth = 4,
 898	.mas_rpm_id = -1,
 899	.slv_rpm_id = -1,
 900};
 901
 902static struct qcom_icc_node slv_imem_cfg = {
 903	.name = "slv_imem_cfg",
 904	.id = MSM8939_SLAVE_IMEM_CFG,
 905	.buswidth = 4,
 906	.mas_rpm_id = -1,
 907	.slv_rpm_id = -1,
 908};
 909
 910static struct qcom_icc_node slv_imem = {
 911	.name = "slv_imem",
 912	.id = MSM8939_SLAVE_IMEM,
 913	.buswidth = 8,
 914	.mas_rpm_id = -1,
 915	.slv_rpm_id = 26,
 916};
 917
 918static struct qcom_icc_node slv_mpm = {
 919	.name = "slv_mpm",
 920	.id = MSM8939_SLAVE_MPM,
 921	.buswidth = 4,
 922	.mas_rpm_id = -1,
 923	.slv_rpm_id = -1,
 924};
 925
 926static struct qcom_icc_node slv_msg_ram = {
 927	.name = "slv_msg_ram",
 928	.id = MSM8939_SLAVE_MSG_RAM,
 929	.buswidth = 4,
 930	.mas_rpm_id = -1,
 931	.slv_rpm_id = -1,
 932};
 933
 934static struct qcom_icc_node slv_mss = {
 935	.name = "slv_mss",
 936	.id = MSM8939_SLAVE_MSS,
 937	.buswidth = 4,
 938	.mas_rpm_id = -1,
 939	.slv_rpm_id = -1,
 940};
 941
 942static struct qcom_icc_node slv_pdm = {
 943	.name = "slv_pdm",
 944	.id = MSM8939_SLAVE_PDM,
 945	.buswidth = 4,
 946	.mas_rpm_id = -1,
 947	.slv_rpm_id = -1,
 948};
 949
 950static struct qcom_icc_node slv_pmic_arb = {
 951	.name = "slv_pmic_arb",
 952	.id = MSM8939_SLAVE_PMIC_ARB,
 953	.buswidth = 4,
 954	.mas_rpm_id = -1,
 955	.slv_rpm_id = -1,
 956};
 957
 958static struct qcom_icc_node slv_pcnoc_cfg = {
 959	.name = "slv_pcnoc_cfg",
 960	.id = MSM8939_SLAVE_PNOC_CFG,
 961	.buswidth = 4,
 962	.mas_rpm_id = -1,
 963	.slv_rpm_id = -1,
 964};
 965
 966static struct qcom_icc_node slv_prng = {
 967	.name = "slv_prng",
 968	.id = MSM8939_SLAVE_PRNG,
 969	.buswidth = 4,
 970	.mas_rpm_id = -1,
 971	.slv_rpm_id = -1,
 972};
 973
 974static struct qcom_icc_node slv_qdss_cfg = {
 975	.name = "slv_qdss_cfg",
 976	.id = MSM8939_SLAVE_QDSS_CFG,
 977	.buswidth = 4,
 978	.mas_rpm_id = -1,
 979	.slv_rpm_id = -1,
 980};
 981
 982static struct qcom_icc_node slv_qdss_stm = {
 983	.name = "slv_qdss_stm",
 984	.id = MSM8939_SLAVE_QDSS_STM,
 985	.buswidth = 4,
 986	.mas_rpm_id = -1,
 987	.slv_rpm_id = 30,
 988};
 989
 990static struct qcom_icc_node slv_rbcpr_cfg = {
 991	.name = "slv_rbcpr_cfg",
 992	.id = MSM8939_SLAVE_RBCPR_CFG,
 993	.buswidth = 4,
 994	.mas_rpm_id = -1,
 995	.slv_rpm_id = -1,
 996};
 997
 998static struct qcom_icc_node slv_sdcc_1 = {
 999	.name = "slv_sdcc_1",
1000	.id = MSM8939_SLAVE_SDCC_1,
1001	.buswidth = 4,
1002	.mas_rpm_id = -1,
1003	.slv_rpm_id = -1,
1004};
1005
1006static struct qcom_icc_node slv_sdcc_2 = {
1007	.name = "slv_sdcc_2",
1008	.id = MSM8939_SLAVE_SDCC_2,
1009	.buswidth = 4,
1010	.mas_rpm_id = -1,
1011	.slv_rpm_id = -1,
1012};
1013
1014static struct qcom_icc_node slv_security = {
1015	.name = "slv_security",
1016	.id = MSM8939_SLAVE_SECURITY,
1017	.buswidth = 4,
1018	.mas_rpm_id = -1,
1019	.slv_rpm_id = -1,
1020};
1021
1022static struct qcom_icc_node slv_snoc_cfg = {
1023	.name = "slv_snoc_cfg",
1024	.id = MSM8939_SLAVE_SNOC_CFG,
1025	.buswidth = 4,
1026	.mas_rpm_id = -1,
1027	.slv_rpm_id = -1,
1028};
1029
1030static struct qcom_icc_node slv_spdm = {
1031	.name = "slv_spdm",
1032	.id = MSM8939_SLAVE_SPDM,
1033	.buswidth = 4,
1034	.mas_rpm_id = -1,
1035	.slv_rpm_id = -1,
1036};
1037
1038static struct qcom_icc_node slv_srvc_snoc = {
1039	.name = "slv_srvc_snoc",
1040	.id = MSM8939_SLAVE_SRVC_SNOC,
1041	.buswidth = 8,
1042	.mas_rpm_id = -1,
1043	.slv_rpm_id = -1,
1044};
1045
1046static struct qcom_icc_node slv_tcsr = {
1047	.name = "slv_tcsr",
1048	.id = MSM8939_SLAVE_TCSR,
1049	.buswidth = 4,
1050	.mas_rpm_id = -1,
1051	.slv_rpm_id = -1,
1052};
1053
1054static struct qcom_icc_node slv_tlmm = {
1055	.name = "slv_tlmm",
1056	.id = MSM8939_SLAVE_TLMM,
1057	.buswidth = 4,
1058	.mas_rpm_id = -1,
1059	.slv_rpm_id = -1,
1060};
1061
1062static struct qcom_icc_node slv_usb_hs1 = {
1063	.name = "slv_usb_hs1",
1064	.id = MSM8939_SLAVE_USB_HS1,
1065	.buswidth = 4,
1066	.mas_rpm_id = -1,
1067	.slv_rpm_id = -1,
1068};
1069
1070static struct qcom_icc_node slv_usb_hs2 = {
1071	.name = "slv_usb_hs2",
1072	.id = MSM8939_SLAVE_USB_HS2,
1073	.buswidth = 4,
1074	.mas_rpm_id = -1,
1075	.slv_rpm_id = -1,
1076};
1077
1078static struct qcom_icc_node slv_venus_cfg = {
1079	.name = "slv_venus_cfg",
1080	.id = MSM8939_SLAVE_VENUS_CFG,
1081	.buswidth = 4,
1082	.mas_rpm_id = -1,
1083	.slv_rpm_id = -1,
1084};
1085
1086static const u16 snoc_bimc_0_mas_links[] = {
1087	MSM8939_SNOC_BIMC_0_SLV
1088};
1089
1090static struct qcom_icc_node snoc_bimc_0_mas = {
1091	.name = "snoc_bimc_0_mas",
1092	.id = MSM8939_SNOC_BIMC_0_MAS,
1093	.buswidth = 16,
1094	.mas_rpm_id = -1,
1095	.slv_rpm_id = -1,
1096	.qos.ap_owned = true,
1097	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1098	.num_links = ARRAY_SIZE(snoc_bimc_0_mas_links),
1099	.links = snoc_bimc_0_mas_links,
1100};
1101
1102static const u16 snoc_bimc_0_slv_links[] = {
1103	MSM8939_SLAVE_EBI_CH0
1104};
1105
1106static struct qcom_icc_node snoc_bimc_0_slv = {
1107	.name = "snoc_bimc_0_slv",
1108	.id = MSM8939_SNOC_BIMC_0_SLV,
1109	.buswidth = 16,
1110	.mas_rpm_id = -1,
1111	.slv_rpm_id = -1,
1112	.qos.ap_owned = true,
1113	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1114	.num_links = ARRAY_SIZE(snoc_bimc_0_slv_links),
1115	.links = snoc_bimc_0_slv_links,
1116};
1117
1118static const u16 snoc_bimc_1_mas_links[] = {
1119	MSM8939_SNOC_BIMC_1_SLV
1120};
1121
1122static struct qcom_icc_node snoc_bimc_1_mas = {
1123	.name = "snoc_bimc_1_mas",
1124	.id = MSM8939_SNOC_BIMC_1_MAS,
1125	.buswidth = 16,
1126	.mas_rpm_id = 76,
1127	.slv_rpm_id = -1,
1128	.num_links = ARRAY_SIZE(snoc_bimc_1_mas_links),
1129	.links = snoc_bimc_1_mas_links,
1130};
1131
1132static const u16 snoc_bimc_1_slv_links[] = {
1133	MSM8939_SLAVE_EBI_CH0
1134};
1135
1136static struct qcom_icc_node snoc_bimc_1_slv = {
1137	.name = "snoc_bimc_1_slv",
1138	.id = MSM8939_SNOC_BIMC_1_SLV,
1139	.buswidth = 16,
1140	.mas_rpm_id = -1,
1141	.slv_rpm_id = 104,
1142	.num_links = ARRAY_SIZE(snoc_bimc_1_slv_links),
1143	.links = snoc_bimc_1_slv_links,
1144};
1145
1146static const u16 snoc_bimc_2_mas_links[] = {
1147	MSM8939_SNOC_BIMC_2_SLV
1148};
1149
1150static struct qcom_icc_node snoc_bimc_2_mas = {
1151	.name = "snoc_bimc_2_mas",
1152	.id = MSM8939_SNOC_BIMC_2_MAS,
1153	.buswidth = 16,
1154	.mas_rpm_id = -1,
1155	.slv_rpm_id = -1,
1156	.qos.ap_owned = true,
1157	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1158	.num_links = ARRAY_SIZE(snoc_bimc_2_mas_links),
1159	.links = snoc_bimc_2_mas_links,
1160};
1161
1162static const u16 snoc_bimc_2_slv_links[] = {
1163	MSM8939_SLAVE_EBI_CH0
1164};
1165
1166static struct qcom_icc_node snoc_bimc_2_slv = {
1167	.name = "snoc_bimc_2_slv",
1168	.id = MSM8939_SNOC_BIMC_2_SLV,
1169	.buswidth = 16,
1170	.mas_rpm_id = -1,
1171	.slv_rpm_id = -1,
1172	.qos.ap_owned = true,
1173	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1174	.num_links = ARRAY_SIZE(snoc_bimc_2_slv_links),
1175	.links = snoc_bimc_2_slv_links,
1176};
1177
1178static const u16 snoc_int_0_links[] = {
1179	MSM8939_SLAVE_QDSS_STM,
1180	MSM8939_SLAVE_IMEM,
1181	MSM8939_SNOC_PNOC_MAS
1182};
1183
1184static struct qcom_icc_node snoc_int_0 = {
1185	.name = "snoc_int_0",
1186	.id = MSM8939_SNOC_INT_0,
1187	.buswidth = 8,
1188	.mas_rpm_id = 99,
1189	.slv_rpm_id = 130,
1190	.num_links = ARRAY_SIZE(snoc_int_0_links),
1191	.links = snoc_int_0_links,
1192};
1193
1194static const u16 snoc_int_1_links[] = {
1195	MSM8939_SLAVE_APSS,
1196	MSM8939_SLAVE_CATS_128,
1197	MSM8939_SLAVE_OCMEM_64
1198};
1199
1200static struct qcom_icc_node snoc_int_1 = {
1201	.name = "snoc_int_1",
1202	.id = MSM8939_SNOC_INT_1,
1203	.buswidth = 8,
1204	.mas_rpm_id = -1,
1205	.slv_rpm_id = -1,
1206	.num_links = ARRAY_SIZE(snoc_int_1_links),
1207	.links = snoc_int_1_links,
1208};
1209
1210static const u16 snoc_int_bimc_links[] = {
1211	MSM8939_SNOC_BIMC_1_MAS
1212};
1213
1214static struct qcom_icc_node snoc_int_bimc = {
1215	.name = "snoc_int_bimc",
1216	.id = MSM8939_SNOC_INT_BIMC,
1217	.buswidth = 8,
1218	.mas_rpm_id = 101,
1219	.slv_rpm_id = 132,
1220	.num_links = ARRAY_SIZE(snoc_int_bimc_links),
1221	.links = snoc_int_bimc_links,
1222};
1223
1224static const u16 snoc_pcnoc_mas_links[] = {
1225	MSM8939_SNOC_PNOC_SLV
1226};
1227
1228static struct qcom_icc_node snoc_pcnoc_mas = {
1229	.name = "snoc_pcnoc_mas",
1230	.id = MSM8939_SNOC_PNOC_MAS,
1231	.buswidth = 8,
1232	.mas_rpm_id = -1,
1233	.slv_rpm_id = -1,
1234	.num_links = ARRAY_SIZE(snoc_pcnoc_mas_links),
1235	.links = snoc_pcnoc_mas_links,
1236};
1237
1238static const u16 snoc_pcnoc_slv_links[] = {
1239	MSM8939_PNOC_INT_0
1240};
1241
1242static struct qcom_icc_node snoc_pcnoc_slv = {
1243	.name = "snoc_pcnoc_slv",
1244	.id = MSM8939_SNOC_PNOC_SLV,
1245	.buswidth = 8,
1246	.mas_rpm_id = -1,
1247	.slv_rpm_id = -1,
1248	.num_links = ARRAY_SIZE(snoc_pcnoc_slv_links),
1249	.links = snoc_pcnoc_slv_links,
1250};
1251
1252static struct qcom_icc_node * const msm8939_snoc_nodes[] = {
1253	[BIMC_SNOC_SLV] = &bimc_snoc_slv,
1254	[MASTER_QDSS_BAM] = &mas_qdss_bam,
1255	[MASTER_QDSS_ETR] = &mas_qdss_etr,
1256	[MASTER_SNOC_CFG] = &mas_snoc_cfg,
1257	[PCNOC_SNOC_SLV] = &pcnoc_snoc_slv,
1258	[SLAVE_APSS] = &slv_apss,
1259	[SLAVE_CATS_128] = &slv_cats_0,
1260	[SLAVE_OCMEM_64] = &slv_cats_1,
1261	[SLAVE_IMEM] = &slv_imem,
1262	[SLAVE_QDSS_STM] = &slv_qdss_stm,
1263	[SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1264	[SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas,
1265	[SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas,
1266	[SNOC_BIMC_2_MAS] = &snoc_bimc_2_mas,
1267	[SNOC_INT_0] = &snoc_int_0,
1268	[SNOC_INT_1] = &snoc_int_1,
1269	[SNOC_INT_BIMC] = &snoc_int_bimc,
1270	[SNOC_PCNOC_MAS] = &snoc_pcnoc_mas,
1271	[SNOC_QDSS_INT] = &qdss_int,
1272};
1273
1274static const struct regmap_config msm8939_snoc_regmap_config = {
1275	.reg_bits	= 32,
1276	.reg_stride	= 4,
1277	.val_bits	= 32,
1278	.max_register	= 0x14080,
1279	.fast_io	= true,
1280};
1281
1282static const struct qcom_icc_desc msm8939_snoc = {
1283	.type = QCOM_ICC_NOC,
1284	.nodes = msm8939_snoc_nodes,
1285	.num_nodes = ARRAY_SIZE(msm8939_snoc_nodes),
1286	.bus_clk_desc = &bus_1_clk,
1287	.regmap_cfg = &msm8939_snoc_regmap_config,
1288	.qos_offset = 0x7000,
1289};
1290
1291static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = {
1292	[MASTER_VIDEO_P0] = &mas_video,
1293	[MASTER_JPEG] = &mas_jpeg,
1294	[MASTER_VFE] = &mas_vfe,
1295	[MASTER_MDP_PORT0] = &mas_mdp0,
1296	[MASTER_MDP_PORT1] = &mas_mdp1,
1297	[MASTER_CPP] = &mas_cpp,
1298	[SNOC_MM_INT_0] = &mm_int_0,
1299	[SNOC_MM_INT_1] = &mm_int_1,
1300	[SNOC_MM_INT_2] = &mm_int_2,
1301};
1302
1303static const struct qcom_icc_desc msm8939_snoc_mm = {
1304	.type = QCOM_ICC_NOC,
1305	.nodes = msm8939_snoc_mm_nodes,
1306	.num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes),
1307	.bus_clk_desc = &bus_2_clk,
1308	.regmap_cfg = &msm8939_snoc_regmap_config,
1309	.qos_offset = 0x7000,
1310};
1311
1312static struct qcom_icc_node * const msm8939_bimc_nodes[] = {
1313	[BIMC_SNOC_MAS] = &bimc_snoc_mas,
1314	[MASTER_AMPSS_M0] = &mas_apss,
1315	[MASTER_GRAPHICS_3D] = &mas_gfx,
1316	[MASTER_TCU0] = &mas_tcu0,
1317	[SLAVE_AMPSS_L2] = &slv_apps_l2,
1318	[SLAVE_EBI_CH0] = &slv_ebi_ch0,
1319	[SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv,
1320	[SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv,
1321	[SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv,
1322};
1323
1324static const struct regmap_config msm8939_bimc_regmap_config = {
1325	.reg_bits	= 32,
1326	.reg_stride	= 4,
1327	.val_bits	= 32,
1328	.max_register	= 0x62000,
1329	.fast_io	= true,
1330};
1331
1332static const struct qcom_icc_desc msm8939_bimc = {
1333	.type = QCOM_ICC_BIMC,
1334	.nodes = msm8939_bimc_nodes,
1335	.num_nodes = ARRAY_SIZE(msm8939_bimc_nodes),
1336	.bus_clk_desc = &bimc_clk,
1337	.regmap_cfg = &msm8939_bimc_regmap_config,
1338	.qos_offset = 0x8000,
1339};
1340
1341static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = {
1342	[MASTER_BLSP_1] = &mas_blsp_1,
1343	[MASTER_DEHR] = &mas_dehr,
1344	[MASTER_LPASS] = &mas_audio,
1345	[MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0,
1346	[MASTER_SDCC_1] = &mas_pcnoc_sdcc_1,
1347	[MASTER_SDCC_2] = &mas_pcnoc_sdcc_2,
1348	[MASTER_SPDM] = &mas_spdm,
1349	[MASTER_USB_HS1] = &mas_usb_hs1,
1350	[MASTER_USB_HS2] = &mas_usb_hs2,
1351	[PCNOC_INT_0] = &pcnoc_int_0,
1352	[PCNOC_INT_1] = &pcnoc_int_1,
1353	[PCNOC_MAS_0] = &pcnoc_m_0,
1354	[PCNOC_MAS_1] = &pcnoc_m_1,
1355	[PCNOC_SLV_0] = &pcnoc_s_0,
1356	[PCNOC_SLV_1] = &pcnoc_s_1,
1357	[PCNOC_SLV_2] = &pcnoc_s_2,
1358	[PCNOC_SLV_3] = &pcnoc_s_3,
1359	[PCNOC_SLV_4] = &pcnoc_s_4,
1360	[PCNOC_SLV_8] = &pcnoc_s_8,
1361	[PCNOC_SLV_9] = &pcnoc_s_9,
1362	[PCNOC_SNOC_MAS] = &pcnoc_snoc_mas,
1363	[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1364	[SLAVE_BLSP_1] = &slv_blsp_1,
1365	[SLAVE_BOOT_ROM] = &slv_boot_rom,
1366	[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1367	[SLAVE_CLK_CTL] = &slv_clk_ctl,
1368	[SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1369	[SLAVE_DEHR_CFG] = &slv_dehr_cfg,
1370	[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1371	[SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg,
1372	[SLAVE_IMEM_CFG] = &slv_imem_cfg,
1373	[SLAVE_LPASS] = &slv_audio,
1374	[SLAVE_MPM] = &slv_mpm,
1375	[SLAVE_MSG_RAM] = &slv_msg_ram,
1376	[SLAVE_MSS] = &slv_mss,
1377	[SLAVE_PDM] = &slv_pdm,
1378	[SLAVE_PMIC_ARB] = &slv_pmic_arb,
1379	[SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg,
1380	[SLAVE_PRNG] = &slv_prng,
1381	[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1382	[SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg,
1383	[SLAVE_SDCC_1] = &slv_sdcc_1,
1384	[SLAVE_SDCC_2] = &slv_sdcc_2,
1385	[SLAVE_SECURITY] = &slv_security,
1386	[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1387	[SLAVE_SPDM] = &slv_spdm,
1388	[SLAVE_TCSR] = &slv_tcsr,
1389	[SLAVE_TLMM] = &slv_tlmm,
1390	[SLAVE_USB_HS1] = &slv_usb_hs1,
1391	[SLAVE_USB_HS2] = &slv_usb_hs2,
1392	[SLAVE_VENUS_CFG] = &slv_venus_cfg,
1393	[SNOC_PCNOC_SLV] = &snoc_pcnoc_slv,
1394};
1395
1396static const struct regmap_config msm8939_pcnoc_regmap_config = {
1397	.reg_bits	= 32,
1398	.reg_stride	= 4,
1399	.val_bits	= 32,
1400	.max_register	= 0x11000,
1401	.fast_io	= true,
1402};
1403
1404static const struct qcom_icc_desc msm8939_pcnoc = {
1405	.type = QCOM_ICC_NOC,
1406	.nodes = msm8939_pcnoc_nodes,
1407	.num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes),
1408	.bus_clk_desc = &bus_0_clk,
1409	.regmap_cfg = &msm8939_pcnoc_regmap_config,
1410	.qos_offset = 0x7000,
1411};
1412
1413static const struct of_device_id msm8939_noc_of_match[] = {
1414	{ .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc },
1415	{ .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc },
1416	{ .compatible = "qcom,msm8939-snoc", .data = &msm8939_snoc },
1417	{ .compatible = "qcom,msm8939-snoc-mm", .data = &msm8939_snoc_mm },
1418	{ }
1419};
1420MODULE_DEVICE_TABLE(of, msm8939_noc_of_match);
1421
1422static struct platform_driver msm8939_noc_driver = {
1423	.probe = qnoc_probe,
1424	.remove = qnoc_remove,
1425	.driver = {
1426		.name = "qnoc-msm8939",
1427		.of_match_table = msm8939_noc_of_match,
1428		.sync_state = icc_sync_state,
1429	},
1430};
1431module_platform_driver(msm8939_noc_driver);
1432MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
1433MODULE_DESCRIPTION("Qualcomm MSM8939 NoC driver");
1434MODULE_LICENSE("GPL v2");