msm8937.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Based on data from msm8937-bus.dtsi in Qualcomm's msm-3.18 release:
   4 *   Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/mod_devicetable.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/regmap.h>
  13
  14#include <dt-bindings/interconnect/qcom,msm8937.h>
  15
  16#include "icc-rpm.h"
  17
  18enum {
  19	QNOC_MASTER_AMPSS_M0 = 1,
  20	QNOC_MASTER_GRAPHICS_3D,
  21	QNOC_SNOC_BIMC_0_MAS,
  22	QNOC_SNOC_BIMC_2_MAS,
  23	QNOC_SNOC_BIMC_1_MAS,
  24	QNOC_MASTER_TCU_0,
  25	QNOC_MASTER_SPDM,
  26	QNOC_MASTER_BLSP_1,
  27	QNOC_MASTER_BLSP_2,
  28	QNOC_MASTER_USB_HS,
  29	QNOC_MASTER_XM_USB_HS1,
  30	QNOC_MASTER_CRYPTO_CORE0,
  31	QNOC_MASTER_SDCC_1,
  32	QNOC_MASTER_SDCC_2,
  33	QNOC_SNOC_PNOC_MAS,
  34	QNOC_MASTER_QDSS_BAM,
  35	QNOC_BIMC_SNOC_MAS,
  36	QNOC_MASTER_JPEG,
  37	QNOC_MASTER_MDP_PORT0,
  38	QNOC_PNOC_SNOC_MAS,
  39	QNOC_MASTER_VIDEO_P0,
  40	QNOC_MASTER_VFE,
  41	QNOC_MASTER_VFE1,
  42	QNOC_MASTER_CPP,
  43	QNOC_MASTER_QDSS_ETR,
  44	QNOC_PNOC_M_0,
  45	QNOC_PNOC_M_1,
  46	QNOC_PNOC_INT_0,
  47	QNOC_PNOC_INT_1,
  48	QNOC_PNOC_INT_2,
  49	QNOC_PNOC_INT_3,
  50	QNOC_PNOC_SLV_0,
  51	QNOC_PNOC_SLV_1,
  52	QNOC_PNOC_SLV_2,
  53	QNOC_PNOC_SLV_3,
  54	QNOC_PNOC_SLV_4,
  55	QNOC_PNOC_SLV_6,
  56	QNOC_PNOC_SLV_7,
  57	QNOC_PNOC_SLV_8,
  58	QNOC_SNOC_QDSS_INT,
  59	QNOC_SNOC_INT_0,
  60	QNOC_SNOC_INT_1,
  61	QNOC_SNOC_INT_2,
  62	QNOC_SLAVE_EBI_CH0,
  63	QNOC_BIMC_SNOC_SLV,
  64	QNOC_SLAVE_SDCC_2,
  65	QNOC_SLAVE_SPDM_WRAPPER,
  66	QNOC_SLAVE_PDM,
  67	QNOC_SLAVE_PRNG,
  68	QNOC_SLAVE_TCSR,
  69	QNOC_SLAVE_SNOC_CFG,
  70	QNOC_SLAVE_MESSAGE_RAM,
  71	QNOC_SLAVE_CAMERA_CFG,
  72	QNOC_SLAVE_DISPLAY_CFG,
  73	QNOC_SLAVE_VENUS_CFG,
  74	QNOC_SLAVE_GRAPHICS_3D_CFG,
  75	QNOC_SLAVE_TLMM,
  76	QNOC_SLAVE_BLSP_1,
  77	QNOC_SLAVE_BLSP_2,
  78	QNOC_SLAVE_PMIC_ARB,
  79	QNOC_SLAVE_SDCC_1,
  80	QNOC_SLAVE_CRYPTO_0_CFG,
  81	QNOC_SLAVE_USB_HS,
  82	QNOC_SLAVE_TCU,
  83	QNOC_PNOC_SNOC_SLV,
  84	QNOC_SLAVE_APPSS,
  85	QNOC_SLAVE_WCSS,
  86	QNOC_SNOC_BIMC_0_SLV,
  87	QNOC_SNOC_BIMC_1_SLV,
  88	QNOC_SNOC_BIMC_2_SLV,
  89	QNOC_SLAVE_OCIMEM,
  90	QNOC_SNOC_PNOC_SLV,
  91	QNOC_SLAVE_QDSS_STM,
  92	QNOC_SLAVE_CATS_128,
  93	QNOC_SLAVE_OCMEM_64,
  94	QNOC_SLAVE_LPASS,
  95};
  96
  97static const u16 mas_apps_proc_links[] = {
  98	QNOC_SLAVE_EBI_CH0,
  99	QNOC_BIMC_SNOC_SLV
 100};
 101
 102static struct qcom_icc_node mas_apps_proc = {
 103	.name = "mas_apps_proc",
 104	.id = QNOC_MASTER_AMPSS_M0,
 105	.buswidth = 8,
 106	.mas_rpm_id = 0,
 107	.slv_rpm_id = -1,
 108	.qos.ap_owned = true,
 109	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 110	.qos.areq_prio = 0,
 111	.qos.prio_level = 0,
 112	.qos.qos_port = 0,
 113	.num_links = ARRAY_SIZE(mas_apps_proc_links),
 114	.links = mas_apps_proc_links,
 115};
 116
 117static const u16 mas_oxili_links[] = {
 118	QNOC_SLAVE_EBI_CH0,
 119	QNOC_BIMC_SNOC_SLV
 120};
 121
 122static struct qcom_icc_node mas_oxili = {
 123	.name = "mas_oxili",
 124	.id = QNOC_MASTER_GRAPHICS_3D,
 125	.buswidth = 8,
 126	.mas_rpm_id = 6,
 127	.slv_rpm_id = -1,
 128	.qos.ap_owned = true,
 129	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 130	.qos.areq_prio = 0,
 131	.qos.prio_level = 0,
 132	.qos.qos_port = 2,
 133	.num_links = ARRAY_SIZE(mas_oxili_links),
 134	.links = mas_oxili_links,
 135};
 136
 137static const u16 mas_snoc_bimc_0_links[] = {
 138	QNOC_SLAVE_EBI_CH0,
 139	QNOC_BIMC_SNOC_SLV
 140};
 141
 142static struct qcom_icc_node mas_snoc_bimc_0 = {
 143	.name = "mas_snoc_bimc_0",
 144	.id = QNOC_SNOC_BIMC_0_MAS,
 145	.buswidth = 8,
 146	.mas_rpm_id = 3,
 147	.slv_rpm_id = -1,
 148	.qos.ap_owned = true,
 149	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 150	.qos.areq_prio = 0,
 151	.qos.prio_level = 0,
 152	.qos.qos_port = 3,
 153	.num_links = ARRAY_SIZE(mas_snoc_bimc_0_links),
 154	.links = mas_snoc_bimc_0_links,
 155};
 156
 157static const u16 mas_snoc_bimc_2_links[] = {
 158	QNOC_SLAVE_EBI_CH0,
 159	QNOC_BIMC_SNOC_SLV
 160};
 161
 162static struct qcom_icc_node mas_snoc_bimc_2 = {
 163	.name = "mas_snoc_bimc_2",
 164	.id = QNOC_SNOC_BIMC_2_MAS,
 165	.buswidth = 8,
 166	.mas_rpm_id = 108,
 167	.slv_rpm_id = -1,
 168	.qos.ap_owned = true,
 169	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 170	.qos.areq_prio = 0,
 171	.qos.prio_level = 0,
 172	.qos.qos_port = 4,
 173	.num_links = ARRAY_SIZE(mas_snoc_bimc_2_links),
 174	.links = mas_snoc_bimc_2_links,
 175};
 176
 177static const u16 mas_snoc_bimc_1_links[] = {
 178	QNOC_SLAVE_EBI_CH0
 179};
 180
 181static struct qcom_icc_node mas_snoc_bimc_1 = {
 182	.name = "mas_snoc_bimc_1",
 183	.id = QNOC_SNOC_BIMC_1_MAS,
 184	.buswidth = 8,
 185	.mas_rpm_id = 76,
 186	.slv_rpm_id = -1,
 187	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 188	.qos.areq_prio = 0,
 189	.qos.prio_level = 0,
 190	.qos.qos_port = 5,
 191	.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
 192	.links = mas_snoc_bimc_1_links,
 193};
 194
 195static const u16 mas_tcu_0_links[] = {
 196	QNOC_SLAVE_EBI_CH0,
 197	QNOC_BIMC_SNOC_SLV
 198};
 199
 200static struct qcom_icc_node mas_tcu_0 = {
 201	.name = "mas_tcu_0",
 202	.id = QNOC_MASTER_TCU_0,
 203	.buswidth = 8,
 204	.mas_rpm_id = 102,
 205	.slv_rpm_id = -1,
 206	.qos.ap_owned = true,
 207	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 208	.qos.areq_prio = 0,
 209	.qos.prio_level = 2,
 210	.qos.qos_port = 6,
 211	.num_links = ARRAY_SIZE(mas_tcu_0_links),
 212	.links = mas_tcu_0_links,
 213};
 214
 215static const u16 mas_spdm_links[] = {
 216	QNOC_PNOC_M_0
 217};
 218
 219static struct qcom_icc_node mas_spdm = {
 220	.name = "mas_spdm",
 221	.id = QNOC_MASTER_SPDM,
 222	.buswidth = 4,
 223	.mas_rpm_id = 50,
 224	.slv_rpm_id = -1,
 225	.qos.ap_owned = true,
 226	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 227	.num_links = ARRAY_SIZE(mas_spdm_links),
 228	.links = mas_spdm_links,
 229};
 230
 231static const u16 mas_blsp_1_links[] = {
 232	QNOC_PNOC_M_1
 233};
 234
 235static struct qcom_icc_node mas_blsp_1 = {
 236	.name = "mas_blsp_1",
 237	.id = QNOC_MASTER_BLSP_1,
 238	.buswidth = 4,
 239	.mas_rpm_id = 41,
 240	.slv_rpm_id = -1,
 241	.num_links = ARRAY_SIZE(mas_blsp_1_links),
 242	.links = mas_blsp_1_links,
 243};
 244
 245static const u16 mas_blsp_2_links[] = {
 246	QNOC_PNOC_M_1
 247};
 248
 249static struct qcom_icc_node mas_blsp_2 = {
 250	.name = "mas_blsp_2",
 251	.id = QNOC_MASTER_BLSP_2,
 252	.buswidth = 4,
 253	.mas_rpm_id = 39,
 254	.slv_rpm_id = -1,
 255	.num_links = ARRAY_SIZE(mas_blsp_2_links),
 256	.links = mas_blsp_2_links,
 257};
 258
 259static const u16 mas_usb_hs1_links[] = {
 260	QNOC_PNOC_INT_0
 261};
 262
 263static struct qcom_icc_node mas_usb_hs1 = {
 264	.name = "mas_usb_hs1",
 265	.id = QNOC_MASTER_USB_HS,
 266	.buswidth = 4,
 267	.mas_rpm_id = 42,
 268	.slv_rpm_id = -1,
 269	.qos.ap_owned = true,
 270	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 271	.qos.areq_prio = 1,
 272	.qos.prio_level = 1,
 273	.qos.qos_port = 12,
 274	.num_links = ARRAY_SIZE(mas_usb_hs1_links),
 275	.links = mas_usb_hs1_links,
 276};
 277
 278static const u16 mas_xi_usb_hs1_links[] = {
 279	QNOC_PNOC_INT_0
 280};
 281
 282static struct qcom_icc_node mas_xi_usb_hs1 = {
 283	.name = "mas_xi_usb_hs1",
 284	.id = QNOC_MASTER_XM_USB_HS1,
 285	.buswidth = 8,
 286	.mas_rpm_id = 138,
 287	.slv_rpm_id = -1,
 288	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 289	.qos.areq_prio = 0,
 290	.qos.prio_level = 0,
 291	.qos.qos_port = 11,
 292	.num_links = ARRAY_SIZE(mas_xi_usb_hs1_links),
 293	.links = mas_xi_usb_hs1_links,
 294};
 295
 296static const u16 mas_crypto_links[] = {
 297	QNOC_PNOC_INT_0
 298};
 299
 300static struct qcom_icc_node mas_crypto = {
 301	.name = "mas_crypto",
 302	.id = QNOC_MASTER_CRYPTO_CORE0,
 303	.buswidth = 8,
 304	.mas_rpm_id = 23,
 305	.slv_rpm_id = -1,
 306	.qos.ap_owned = true,
 307	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 308	.qos.areq_prio = 1,
 309	.qos.prio_level = 1,
 310	.qos.qos_port = 0,
 311	.num_links = ARRAY_SIZE(mas_crypto_links),
 312	.links = mas_crypto_links,
 313};
 314
 315static const u16 mas_sdcc_1_links[] = {
 316	QNOC_PNOC_INT_0
 317};
 318
 319static struct qcom_icc_node mas_sdcc_1 = {
 320	.name = "mas_sdcc_1",
 321	.id = QNOC_MASTER_SDCC_1,
 322	.buswidth = 8,
 323	.mas_rpm_id = 33,
 324	.slv_rpm_id = -1,
 325	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 326	.qos.areq_prio = 0,
 327	.qos.prio_level = 0,
 328	.qos.qos_port = 7,
 329	.num_links = ARRAY_SIZE(mas_sdcc_1_links),
 330	.links = mas_sdcc_1_links,
 331};
 332
 333static const u16 mas_sdcc_2_links[] = {
 334	QNOC_PNOC_INT_0
 335};
 336
 337static struct qcom_icc_node mas_sdcc_2 = {
 338	.name = "mas_sdcc_2",
 339	.id = QNOC_MASTER_SDCC_2,
 340	.buswidth = 8,
 341	.mas_rpm_id = 35,
 342	.slv_rpm_id = -1,
 343	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 344	.qos.areq_prio = 0,
 345	.qos.prio_level = 0,
 346	.qos.qos_port = 8,
 347	.num_links = ARRAY_SIZE(mas_sdcc_2_links),
 348	.links = mas_sdcc_2_links,
 349};
 350
 351static const u16 mas_snoc_pcnoc_links[] = {
 352	QNOC_PNOC_SLV_7,
 353	QNOC_PNOC_INT_2,
 354	QNOC_PNOC_INT_3
 355};
 356
 357static struct qcom_icc_node mas_snoc_pcnoc = {
 358	.name = "mas_snoc_pcnoc",
 359	.id = QNOC_SNOC_PNOC_MAS,
 360	.buswidth = 8,
 361	.mas_rpm_id = 77,
 362	.slv_rpm_id = -1,
 363	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 364	.qos.areq_prio = 0,
 365	.qos.prio_level = 0,
 366	.qos.qos_port = 9,
 367	.num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
 368	.links = mas_snoc_pcnoc_links,
 369};
 370
 371static const u16 mas_qdss_bam_links[] = {
 372	QNOC_SNOC_QDSS_INT
 373};
 374
 375static struct qcom_icc_node mas_qdss_bam = {
 376	.name = "mas_qdss_bam",
 377	.id = QNOC_MASTER_QDSS_BAM,
 378	.buswidth = 4,
 379	.mas_rpm_id = 19,
 380	.slv_rpm_id = -1,
 381	.qos.ap_owned = true,
 382	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 383	.qos.areq_prio = 1,
 384	.qos.prio_level = 1,
 385	.qos.qos_port = 11,
 386	.num_links = ARRAY_SIZE(mas_qdss_bam_links),
 387	.links = mas_qdss_bam_links,
 388};
 389
 390static const u16 mas_bimc_snoc_links[] = {
 391	QNOC_SNOC_INT_0,
 392	QNOC_SNOC_INT_1,
 393	QNOC_SNOC_INT_2
 394};
 395
 396static struct qcom_icc_node mas_bimc_snoc = {
 397	.name = "mas_bimc_snoc",
 398	.id = QNOC_BIMC_SNOC_MAS,
 399	.buswidth = 8,
 400	.mas_rpm_id = 21,
 401	.slv_rpm_id = -1,
 402	.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
 403	.links = mas_bimc_snoc_links,
 404};
 405
 406static const u16 mas_jpeg_links[] = {
 407	QNOC_SNOC_BIMC_2_SLV
 408};
 409
 410static struct qcom_icc_node mas_jpeg = {
 411	.name = "mas_jpeg",
 412	.id = QNOC_MASTER_JPEG,
 413	.buswidth = 16,
 414	.mas_rpm_id = 7,
 415	.slv_rpm_id = -1,
 416	.qos.ap_owned = true,
 417	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 418	.qos.areq_prio = 0,
 419	.qos.prio_level = 0,
 420	.qos.qos_port = 6,
 421	.num_links = ARRAY_SIZE(mas_jpeg_links),
 422	.links = mas_jpeg_links,
 423};
 424
 425static const u16 mas_mdp_links[] = {
 426	QNOC_SNOC_BIMC_0_SLV
 427};
 428
 429static struct qcom_icc_node mas_mdp = {
 430	.name = "mas_mdp",
 431	.id = QNOC_MASTER_MDP_PORT0,
 432	.buswidth = 16,
 433	.mas_rpm_id = 8,
 434	.slv_rpm_id = -1,
 435	.qos.ap_owned = true,
 436	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 437	.qos.areq_prio = 0,
 438	.qos.prio_level = 0,
 439	.qos.qos_port = 7,
 440	.num_links = ARRAY_SIZE(mas_mdp_links),
 441	.links = mas_mdp_links,
 442};
 443
 444static const u16 mas_pcnoc_snoc_links[] = {
 445	QNOC_SNOC_INT_0,
 446	QNOC_SNOC_INT_1,
 447	QNOC_SNOC_BIMC_1_SLV
 448};
 449
 450static struct qcom_icc_node mas_pcnoc_snoc = {
 451	.name = "mas_pcnoc_snoc",
 452	.id = QNOC_PNOC_SNOC_MAS,
 453	.buswidth = 8,
 454	.mas_rpm_id = 29,
 455	.slv_rpm_id = -1,
 456	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 457	.qos.areq_prio = 0,
 458	.qos.prio_level = 0,
 459	.qos.qos_port = 5,
 460	.num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
 461	.links = mas_pcnoc_snoc_links,
 462};
 463
 464static const u16 mas_venus_links[] = {
 465	QNOC_SNOC_BIMC_2_SLV
 466};
 467
 468static struct qcom_icc_node mas_venus = {
 469	.name = "mas_venus",
 470	.id = QNOC_MASTER_VIDEO_P0,
 471	.buswidth = 16,
 472	.mas_rpm_id = 9,
 473	.slv_rpm_id = -1,
 474	.qos.ap_owned = true,
 475	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 476	.qos.areq_prio = 0,
 477	.qos.prio_level = 0,
 478	.qos.qos_port = 8,
 479	.num_links = ARRAY_SIZE(mas_venus_links),
 480	.links = mas_venus_links,
 481};
 482
 483static const u16 mas_vfe0_links[] = {
 484	QNOC_SNOC_BIMC_0_SLV
 485};
 486
 487static struct qcom_icc_node mas_vfe0 = {
 488	.name = "mas_vfe0",
 489	.id = QNOC_MASTER_VFE,
 490	.buswidth = 16,
 491	.mas_rpm_id = 11,
 492	.slv_rpm_id = -1,
 493	.qos.ap_owned = true,
 494	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 495	.qos.areq_prio = 0,
 496	.qos.prio_level = 0,
 497	.qos.qos_port = 9,
 498	.num_links = ARRAY_SIZE(mas_vfe0_links),
 499	.links = mas_vfe0_links,
 500};
 501
 502static const u16 mas_vfe1_links[] = {
 503	QNOC_SNOC_BIMC_0_SLV
 504};
 505
 506static struct qcom_icc_node mas_vfe1 = {
 507	.name = "mas_vfe1",
 508	.id = QNOC_MASTER_VFE1,
 509	.buswidth = 16,
 510	.mas_rpm_id = 133,
 511	.slv_rpm_id = -1,
 512	.qos.ap_owned = true,
 513	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 514	.qos.areq_prio = 0,
 515	.qos.prio_level = 0,
 516	.qos.qos_port = 13,
 517	.num_links = ARRAY_SIZE(mas_vfe1_links),
 518	.links = mas_vfe1_links,
 519};
 520
 521static const u16 mas_cpp_links[] = {
 522	QNOC_SNOC_BIMC_2_SLV
 523};
 524
 525static struct qcom_icc_node mas_cpp = {
 526	.name = "mas_cpp",
 527	.id = QNOC_MASTER_CPP,
 528	.buswidth = 16,
 529	.mas_rpm_id = 115,
 530	.slv_rpm_id = -1,
 531	.qos.ap_owned = true,
 532	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
 533	.qos.areq_prio = 0,
 534	.qos.prio_level = 0,
 535	.qos.qos_port = 12,
 536	.num_links = ARRAY_SIZE(mas_cpp_links),
 537	.links = mas_cpp_links,
 538};
 539
 540static const u16 mas_qdss_etr_links[] = {
 541	QNOC_SNOC_QDSS_INT
 542};
 543
 544static struct qcom_icc_node mas_qdss_etr = {
 545	.name = "mas_qdss_etr",
 546	.id = QNOC_MASTER_QDSS_ETR,
 547	.buswidth = 8,
 548	.mas_rpm_id = 31,
 549	.slv_rpm_id = -1,
 550	.qos.ap_owned = true,
 551	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 552	.qos.areq_prio = 1,
 553	.qos.prio_level = 1,
 554	.qos.qos_port = 10,
 555	.num_links = ARRAY_SIZE(mas_qdss_etr_links),
 556	.links = mas_qdss_etr_links,
 557};
 558
 559static const u16 pcnoc_m_0_links[] = {
 560	QNOC_PNOC_INT_0
 561};
 562
 563static struct qcom_icc_node pcnoc_m_0 = {
 564	.name = "pcnoc_m_0",
 565	.id = QNOC_PNOC_M_0,
 566	.buswidth = 4,
 567	.mas_rpm_id = 87,
 568	.slv_rpm_id = 116,
 569	.qos.ap_owned = true,
 570	.qos.qos_mode = NOC_QOS_MODE_FIXED,
 571	.qos.areq_prio = 1,
 572	.qos.prio_level = 1,
 573	.qos.qos_port = 5,
 574	.num_links = ARRAY_SIZE(pcnoc_m_0_links),
 575	.links = pcnoc_m_0_links,
 576};
 577
 578static const u16 pcnoc_m_1_links[] = {
 579	QNOC_PNOC_INT_0
 580};
 581
 582static struct qcom_icc_node pcnoc_m_1 = {
 583	.name = "pcnoc_m_1",
 584	.id = QNOC_PNOC_M_1,
 585	.buswidth = 4,
 586	.mas_rpm_id = 88,
 587	.slv_rpm_id = 117,
 588	.num_links = ARRAY_SIZE(pcnoc_m_1_links),
 589	.links = pcnoc_m_1_links,
 590};
 591
 592static const u16 pcnoc_int_0_links[] = {
 593	QNOC_PNOC_SNOC_SLV,
 594	QNOC_PNOC_SLV_7,
 595	QNOC_PNOC_INT_3,
 596	QNOC_PNOC_INT_2
 597};
 598
 599static struct qcom_icc_node pcnoc_int_0 = {
 600	.name = "pcnoc_int_0",
 601	.id = QNOC_PNOC_INT_0,
 602	.buswidth = 8,
 603	.mas_rpm_id = 85,
 604	.slv_rpm_id = 114,
 605	.num_links = ARRAY_SIZE(pcnoc_int_0_links),
 606	.links = pcnoc_int_0_links,
 607};
 608
 609static const u16 pcnoc_int_1_links[] = {
 610	QNOC_PNOC_SNOC_SLV,
 611	QNOC_PNOC_SLV_7,
 612	QNOC_PNOC_INT_3,
 613	QNOC_PNOC_INT_2
 614};
 615
 616static struct qcom_icc_node pcnoc_int_1 = {
 617	.name = "pcnoc_int_1",
 618	.id = QNOC_PNOC_INT_1,
 619	.buswidth = 8,
 620	.mas_rpm_id = -1,
 621	.slv_rpm_id = -1,
 622	.num_links = ARRAY_SIZE(pcnoc_int_1_links),
 623	.links = pcnoc_int_1_links,
 624};
 625
 626static const u16 pcnoc_int_2_links[] = {
 627	QNOC_PNOC_SLV_2,
 628	QNOC_PNOC_SLV_3,
 629	QNOC_PNOC_SLV_6,
 630	QNOC_PNOC_SLV_8
 631};
 632
 633static struct qcom_icc_node pcnoc_int_2 = {
 634	.name = "pcnoc_int_2",
 635	.id = QNOC_PNOC_INT_2,
 636	.buswidth = 8,
 637	.mas_rpm_id = 124,
 638	.slv_rpm_id = 184,
 639	.num_links = ARRAY_SIZE(pcnoc_int_2_links),
 640	.links = pcnoc_int_2_links,
 641};
 642
 643static const u16 pcnoc_int_3_links[] = {
 644	QNOC_PNOC_SLV_1,
 645	QNOC_PNOC_SLV_0,
 646	QNOC_PNOC_SLV_4,
 647	QNOC_SLAVE_GRAPHICS_3D_CFG,
 648	QNOC_SLAVE_TCU
 649};
 650
 651static struct qcom_icc_node pcnoc_int_3 = {
 652	.name = "pcnoc_int_3",
 653	.id = QNOC_PNOC_INT_3,
 654	.buswidth = 8,
 655	.mas_rpm_id = 125,
 656	.slv_rpm_id = 185,
 657	.num_links = ARRAY_SIZE(pcnoc_int_3_links),
 658	.links = pcnoc_int_3_links,
 659};
 660
 661static const u16 pcnoc_s_0_links[] = {
 662	QNOC_SLAVE_SPDM_WRAPPER,
 663	QNOC_SLAVE_PDM,
 664	QNOC_SLAVE_PRNG,
 665	QNOC_SLAVE_SDCC_2
 666};
 667
 668static struct qcom_icc_node pcnoc_s_0 = {
 669	.name = "pcnoc_s_0",
 670	.id = QNOC_PNOC_SLV_0,
 671	.buswidth = 4,
 672	.mas_rpm_id = 89,
 673	.slv_rpm_id = 118,
 674	.num_links = ARRAY_SIZE(pcnoc_s_0_links),
 675	.links = pcnoc_s_0_links,
 676};
 677
 678static const u16 pcnoc_s_1_links[] = {
 679	QNOC_SLAVE_TCSR
 680};
 681
 682static struct qcom_icc_node pcnoc_s_1 = {
 683	.name = "pcnoc_s_1",
 684	.id = QNOC_PNOC_SLV_1,
 685	.buswidth = 4,
 686	.mas_rpm_id = 90,
 687	.slv_rpm_id = 119,
 688	.num_links = ARRAY_SIZE(pcnoc_s_1_links),
 689	.links = pcnoc_s_1_links,
 690};
 691
 692static const u16 pcnoc_s_2_links[] = {
 693	QNOC_SLAVE_SNOC_CFG
 694};
 695
 696static struct qcom_icc_node pcnoc_s_2 = {
 697	.name = "pcnoc_s_2",
 698	.id = QNOC_PNOC_SLV_2,
 699	.buswidth = 4,
 700	.mas_rpm_id = 91,
 701	.slv_rpm_id = 120,
 702	.num_links = ARRAY_SIZE(pcnoc_s_2_links),
 703	.links = pcnoc_s_2_links,
 704};
 705
 706static const u16 pcnoc_s_3_links[] = {
 707	QNOC_SLAVE_MESSAGE_RAM
 708};
 709
 710static struct qcom_icc_node pcnoc_s_3 = {
 711	.name = "pcnoc_s_3",
 712	.id = QNOC_PNOC_SLV_3,
 713	.buswidth = 4,
 714	.mas_rpm_id = 92,
 715	.slv_rpm_id = 121,
 716	.num_links = ARRAY_SIZE(pcnoc_s_3_links),
 717	.links = pcnoc_s_3_links,
 718};
 719
 720static const u16 pcnoc_s_4_links[] = {
 721	QNOC_SLAVE_CAMERA_CFG,
 722	QNOC_SLAVE_DISPLAY_CFG,
 723	QNOC_SLAVE_VENUS_CFG
 724};
 725
 726static struct qcom_icc_node pcnoc_s_4 = {
 727	.name = "pcnoc_s_4",
 728	.id = QNOC_PNOC_SLV_4,
 729	.buswidth = 4,
 730	.mas_rpm_id = 93,
 731	.slv_rpm_id = 122,
 732	.qos.ap_owned = true,
 733	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 734	.num_links = ARRAY_SIZE(pcnoc_s_4_links),
 735	.links = pcnoc_s_4_links,
 736};
 737
 738static const u16 pcnoc_s_6_links[] = {
 739	QNOC_SLAVE_TLMM,
 740	QNOC_SLAVE_BLSP_1,
 741	QNOC_SLAVE_BLSP_2
 742};
 743
 744static struct qcom_icc_node pcnoc_s_6 = {
 745	.name = "pcnoc_s_6",
 746	.id = QNOC_PNOC_SLV_6,
 747	.buswidth = 4,
 748	.mas_rpm_id = 94,
 749	.slv_rpm_id = 123,
 750	.num_links = ARRAY_SIZE(pcnoc_s_6_links),
 751	.links = pcnoc_s_6_links,
 752};
 753
 754static const u16 pcnoc_s_7_links[] = {
 755	QNOC_SLAVE_SDCC_1,
 756	QNOC_SLAVE_PMIC_ARB
 757};
 758
 759static struct qcom_icc_node pcnoc_s_7 = {
 760	.name = "pcnoc_s_7",
 761	.id = QNOC_PNOC_SLV_7,
 762	.buswidth = 4,
 763	.mas_rpm_id = 95,
 764	.slv_rpm_id = 124,
 765	.num_links = ARRAY_SIZE(pcnoc_s_7_links),
 766	.links = pcnoc_s_7_links,
 767};
 768
 769static const u16 pcnoc_s_8_links[] = {
 770	QNOC_SLAVE_USB_HS,
 771	QNOC_SLAVE_CRYPTO_0_CFG
 772};
 773
 774static struct qcom_icc_node pcnoc_s_8 = {
 775	.name = "pcnoc_s_8",
 776	.id = QNOC_PNOC_SLV_8,
 777	.buswidth = 4,
 778	.mas_rpm_id = 96,
 779	.slv_rpm_id = 125,
 780	.num_links = ARRAY_SIZE(pcnoc_s_8_links),
 781	.links = pcnoc_s_8_links,
 782};
 783
 784static const u16 qdss_int_links[] = {
 785	QNOC_SNOC_INT_1,
 786	QNOC_SNOC_BIMC_1_SLV
 787};
 788
 789static struct qcom_icc_node qdss_int = {
 790	.name = "qdss_int",
 791	.id = QNOC_SNOC_QDSS_INT,
 792	.buswidth = 8,
 793	.mas_rpm_id = 98,
 794	.slv_rpm_id = 128,
 795	.qos.ap_owned = true,
 796	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 797	.num_links = ARRAY_SIZE(qdss_int_links),
 798	.links = qdss_int_links,
 799};
 800
 801static const u16 snoc_int_0_links[] = {
 802	QNOC_SLAVE_LPASS,
 803	QNOC_SLAVE_WCSS,
 804	QNOC_SLAVE_APPSS
 805};
 806
 807static struct qcom_icc_node snoc_int_0 = {
 808	.name = "snoc_int_0",
 809	.id = QNOC_SNOC_INT_0,
 810	.buswidth = 8,
 811	.mas_rpm_id = 99,
 812	.slv_rpm_id = 130,
 813	.qos.ap_owned = true,
 814	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 815	.num_links = ARRAY_SIZE(snoc_int_0_links),
 816	.links = snoc_int_0_links,
 817};
 818
 819static const u16 snoc_int_1_links[] = {
 820	QNOC_SLAVE_QDSS_STM,
 821	QNOC_SLAVE_OCIMEM,
 822	QNOC_SNOC_PNOC_SLV
 823};
 824
 825static struct qcom_icc_node snoc_int_1 = {
 826	.name = "snoc_int_1",
 827	.id = QNOC_SNOC_INT_1,
 828	.buswidth = 8,
 829	.mas_rpm_id = 100,
 830	.slv_rpm_id = 131,
 831	.num_links = ARRAY_SIZE(snoc_int_1_links),
 832	.links = snoc_int_1_links,
 833};
 834
 835static const u16 snoc_int_2_links[] = {
 836	QNOC_SLAVE_CATS_128,
 837	QNOC_SLAVE_OCMEM_64
 838};
 839
 840static struct qcom_icc_node snoc_int_2 = {
 841	.name = "snoc_int_2",
 842	.id = QNOC_SNOC_INT_2,
 843	.buswidth = 8,
 844	.mas_rpm_id = 134,
 845	.slv_rpm_id = 197,
 846	.qos.ap_owned = true,
 847	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 848	.num_links = ARRAY_SIZE(snoc_int_2_links),
 849	.links = snoc_int_2_links,
 850};
 851
 852static struct qcom_icc_node slv_ebi = {
 853	.name = "slv_ebi",
 854	.id = QNOC_SLAVE_EBI_CH0,
 855	.buswidth = 8,
 856	.mas_rpm_id = -1,
 857	.slv_rpm_id = 0,
 858};
 859
 860static const u16 slv_bimc_snoc_links[] = {
 861	QNOC_BIMC_SNOC_MAS
 862};
 863
 864static struct qcom_icc_node slv_bimc_snoc = {
 865	.name = "slv_bimc_snoc",
 866	.id = QNOC_BIMC_SNOC_SLV,
 867	.buswidth = 8,
 868	.mas_rpm_id = -1,
 869	.slv_rpm_id = 2,
 870	.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
 871	.links = slv_bimc_snoc_links,
 872};
 873
 874static struct qcom_icc_node slv_sdcc_2 = {
 875	.name = "slv_sdcc_2",
 876	.id = QNOC_SLAVE_SDCC_2,
 877	.buswidth = 4,
 878	.mas_rpm_id = -1,
 879	.slv_rpm_id = 33,
 880};
 881
 882static struct qcom_icc_node slv_spdm = {
 883	.name = "slv_spdm",
 884	.id = QNOC_SLAVE_SPDM_WRAPPER,
 885	.buswidth = 4,
 886	.mas_rpm_id = -1,
 887	.slv_rpm_id = 60,
 888	.qos.ap_owned = true,
 889	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 890};
 891
 892static struct qcom_icc_node slv_pdm = {
 893	.name = "slv_pdm",
 894	.id = QNOC_SLAVE_PDM,
 895	.buswidth = 4,
 896	.mas_rpm_id = -1,
 897	.slv_rpm_id = 41,
 898};
 899
 900static struct qcom_icc_node slv_prng = {
 901	.name = "slv_prng",
 902	.id = QNOC_SLAVE_PRNG,
 903	.buswidth = 4,
 904	.mas_rpm_id = -1,
 905	.slv_rpm_id = 44,
 906};
 907
 908static struct qcom_icc_node slv_tcsr = {
 909	.name = "slv_tcsr",
 910	.id = QNOC_SLAVE_TCSR,
 911	.buswidth = 4,
 912	.mas_rpm_id = -1,
 913	.slv_rpm_id = 50,
 914};
 915
 916static struct qcom_icc_node slv_snoc_cfg = {
 917	.name = "slv_snoc_cfg",
 918	.id = QNOC_SLAVE_SNOC_CFG,
 919	.buswidth = 4,
 920	.mas_rpm_id = -1,
 921	.slv_rpm_id = 70,
 922};
 923
 924static struct qcom_icc_node slv_message_ram = {
 925	.name = "slv_message_ram",
 926	.id = QNOC_SLAVE_MESSAGE_RAM,
 927	.buswidth = 4,
 928	.mas_rpm_id = -1,
 929	.slv_rpm_id = 55,
 930};
 931
 932static struct qcom_icc_node slv_camera_ss_cfg = {
 933	.name = "slv_camera_ss_cfg",
 934	.id = QNOC_SLAVE_CAMERA_CFG,
 935	.buswidth = 4,
 936	.mas_rpm_id = -1,
 937	.slv_rpm_id = 3,
 938	.qos.ap_owned = true,
 939	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 940};
 941
 942static struct qcom_icc_node slv_disp_ss_cfg = {
 943	.name = "slv_disp_ss_cfg",
 944	.id = QNOC_SLAVE_DISPLAY_CFG,
 945	.buswidth = 4,
 946	.mas_rpm_id = -1,
 947	.slv_rpm_id = 4,
 948	.qos.ap_owned = true,
 949	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 950};
 951
 952static struct qcom_icc_node slv_venus_cfg = {
 953	.name = "slv_venus_cfg",
 954	.id = QNOC_SLAVE_VENUS_CFG,
 955	.buswidth = 4,
 956	.mas_rpm_id = -1,
 957	.slv_rpm_id = 10,
 958	.qos.ap_owned = true,
 959	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 960};
 961
 962static struct qcom_icc_node slv_gpu_cfg = {
 963	.name = "slv_gpu_cfg",
 964	.id = QNOC_SLAVE_GRAPHICS_3D_CFG,
 965	.buswidth = 8,
 966	.mas_rpm_id = -1,
 967	.slv_rpm_id = 11,
 968	.qos.ap_owned = true,
 969	.qos.qos_mode = NOC_QOS_MODE_INVALID,
 970};
 971
 972static struct qcom_icc_node slv_tlmm = {
 973	.name = "slv_tlmm",
 974	.id = QNOC_SLAVE_TLMM,
 975	.buswidth = 4,
 976	.mas_rpm_id = -1,
 977	.slv_rpm_id = 51,
 978};
 979
 980static struct qcom_icc_node slv_blsp_1 = {
 981	.name = "slv_blsp_1",
 982	.id = QNOC_SLAVE_BLSP_1,
 983	.buswidth = 4,
 984	.mas_rpm_id = -1,
 985	.slv_rpm_id = 39,
 986};
 987
 988static struct qcom_icc_node slv_blsp_2 = {
 989	.name = "slv_blsp_2",
 990	.id = QNOC_SLAVE_BLSP_2,
 991	.buswidth = 4,
 992	.mas_rpm_id = -1,
 993	.slv_rpm_id = 37,
 994};
 995
 996static struct qcom_icc_node slv_pmic_arb = {
 997	.name = "slv_pmic_arb",
 998	.id = QNOC_SLAVE_PMIC_ARB,
 999	.buswidth = 4,
1000	.mas_rpm_id = -1,
1001	.slv_rpm_id = 59,
1002};
1003
1004static struct qcom_icc_node slv_sdcc_1 = {
1005	.name = "slv_sdcc_1",
1006	.id = QNOC_SLAVE_SDCC_1,
1007	.buswidth = 4,
1008	.mas_rpm_id = -1,
1009	.slv_rpm_id = 31,
1010};
1011
1012static struct qcom_icc_node slv_crypto_0_cfg = {
1013	.name = "slv_crypto_0_cfg",
1014	.id = QNOC_SLAVE_CRYPTO_0_CFG,
1015	.buswidth = 4,
1016	.mas_rpm_id = -1,
1017	.slv_rpm_id = 52,
1018};
1019
1020static struct qcom_icc_node slv_usb_hs = {
1021	.name = "slv_usb_hs",
1022	.id = QNOC_SLAVE_USB_HS,
1023	.buswidth = 4,
1024	.mas_rpm_id = -1,
1025	.slv_rpm_id = 40,
1026};
1027
1028static struct qcom_icc_node slv_tcu = {
1029	.name = "slv_tcu",
1030	.id = QNOC_SLAVE_TCU,
1031	.buswidth = 8,
1032	.mas_rpm_id = -1,
1033	.slv_rpm_id = 133,
1034	.qos.ap_owned = true,
1035	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1036};
1037
1038static const u16 slv_pcnoc_snoc_links[] = {
1039	QNOC_PNOC_SNOC_MAS
1040};
1041
1042static struct qcom_icc_node slv_pcnoc_snoc = {
1043	.name = "slv_pcnoc_snoc",
1044	.id = QNOC_PNOC_SNOC_SLV,
1045	.buswidth = 8,
1046	.mas_rpm_id = -1,
1047	.slv_rpm_id = 45,
1048	.num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
1049	.links = slv_pcnoc_snoc_links,
1050};
1051
1052static struct qcom_icc_node slv_kpss_ahb = {
1053	.name = "slv_kpss_ahb",
1054	.id = QNOC_SLAVE_APPSS,
1055	.buswidth = 4,
1056	.mas_rpm_id = -1,
1057	.slv_rpm_id = 20,
1058	.qos.ap_owned = true,
1059	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1060};
1061
1062static struct qcom_icc_node slv_wcss = {
1063	.name = "slv_wcss",
1064	.id = QNOC_SLAVE_WCSS,
1065	.buswidth = 4,
1066	.mas_rpm_id = -1,
1067	.slv_rpm_id = 23,
1068	.qos.ap_owned = true,
1069	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1070};
1071
1072static const u16 slv_snoc_bimc_0_links[] = {
1073	QNOC_SNOC_BIMC_0_MAS
1074};
1075
1076static struct qcom_icc_node slv_snoc_bimc_0 = {
1077	.name = "slv_snoc_bimc_0",
1078	.id = QNOC_SNOC_BIMC_0_SLV,
1079	.buswidth = 16,
1080	.mas_rpm_id = -1,
1081	.slv_rpm_id = 24,
1082	.qos.ap_owned = true,
1083	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1084	.num_links = ARRAY_SIZE(slv_snoc_bimc_0_links),
1085	.links = slv_snoc_bimc_0_links,
1086};
1087
1088static const u16 slv_snoc_bimc_1_links[] = {
1089	QNOC_SNOC_BIMC_1_MAS
1090};
1091
1092static struct qcom_icc_node slv_snoc_bimc_1 = {
1093	.name = "slv_snoc_bimc_1",
1094	.id = QNOC_SNOC_BIMC_1_SLV,
1095	.buswidth = 8,
1096	.mas_rpm_id = -1,
1097	.slv_rpm_id = 104,
1098	.num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
1099	.links = slv_snoc_bimc_1_links,
1100};
1101
1102static const u16 slv_snoc_bimc_2_links[] = {
1103	QNOC_SNOC_BIMC_2_MAS
1104};
1105
1106static struct qcom_icc_node slv_snoc_bimc_2 = {
1107	.name = "slv_snoc_bimc_2",
1108	.id = QNOC_SNOC_BIMC_2_SLV,
1109	.buswidth = 16,
1110	.mas_rpm_id = -1,
1111	.slv_rpm_id = 137,
1112	.qos.ap_owned = true,
1113	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1114	.num_links = ARRAY_SIZE(slv_snoc_bimc_2_links),
1115	.links = slv_snoc_bimc_2_links,
1116};
1117
1118static struct qcom_icc_node slv_imem = {
1119	.name = "slv_imem",
1120	.id = QNOC_SLAVE_OCIMEM,
1121	.buswidth = 8,
1122	.mas_rpm_id = -1,
1123	.slv_rpm_id = 26,
1124};
1125
1126static const u16 slv_snoc_pcnoc_links[] = {
1127	QNOC_SNOC_PNOC_MAS
1128};
1129
1130static struct qcom_icc_node slv_snoc_pcnoc = {
1131	.name = "slv_snoc_pcnoc",
1132	.id = QNOC_SNOC_PNOC_SLV,
1133	.buswidth = 8,
1134	.mas_rpm_id = -1,
1135	.slv_rpm_id = 28,
1136	.num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
1137	.links = slv_snoc_pcnoc_links,
1138};
1139
1140static struct qcom_icc_node slv_qdss_stm = {
1141	.name = "slv_qdss_stm",
1142	.id = QNOC_SLAVE_QDSS_STM,
1143	.buswidth = 4,
1144	.mas_rpm_id = -1,
1145	.slv_rpm_id = 30,
1146};
1147
1148static struct qcom_icc_node slv_cats_0 = {
1149	.name = "slv_cats_0",
1150	.id = QNOC_SLAVE_CATS_128,
1151	.buswidth = 16,
1152	.mas_rpm_id = -1,
1153	.slv_rpm_id = 106,
1154	.qos.ap_owned = true,
1155	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1156};
1157
1158static struct qcom_icc_node slv_cats_1 = {
1159	.name = "slv_cats_1",
1160	.id = QNOC_SLAVE_OCMEM_64,
1161	.buswidth = 8,
1162	.mas_rpm_id = -1,
1163	.slv_rpm_id = 107,
1164	.qos.ap_owned = true,
1165	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1166};
1167
1168static struct qcom_icc_node slv_lpass = {
1169	.name = "slv_lpass",
1170	.id = QNOC_SLAVE_LPASS,
1171	.buswidth = 8,
1172	.mas_rpm_id = -1,
1173	.slv_rpm_id = 21,
1174	.qos.ap_owned = true,
1175	.qos.qos_mode = NOC_QOS_MODE_INVALID,
1176};
1177
1178static struct qcom_icc_node * const msm8937_bimc_nodes[] = {
1179	[MAS_APPS_PROC] = &mas_apps_proc,
1180	[MAS_OXILI] = &mas_oxili,
1181	[MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0,
1182	[MAS_SNOC_BIMC_2] = &mas_snoc_bimc_2,
1183	[MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1,
1184	[MAS_TCU_0] = &mas_tcu_0,
1185	[SLV_EBI] = &slv_ebi,
1186	[SLV_BIMC_SNOC] = &slv_bimc_snoc,
1187};
1188
1189static const struct regmap_config msm8937_bimc_regmap_config = {
1190	.reg_bits = 32,
1191	.reg_stride = 4,
1192	.val_bits = 32,
1193	.max_register = 0x5A000,
1194	.fast_io = true,
1195};
1196
1197static const struct qcom_icc_desc msm8937_bimc = {
1198	.type = QCOM_ICC_BIMC,
1199	.nodes = msm8937_bimc_nodes,
1200	.num_nodes = ARRAY_SIZE(msm8937_bimc_nodes),
1201	.bus_clk_desc = &bimc_clk,
1202	.regmap_cfg = &msm8937_bimc_regmap_config,
1203	.qos_offset = 0x8000,
1204	.ab_coeff = 154,
1205};
1206
1207static struct qcom_icc_node * const msm8937_pcnoc_nodes[] = {
1208	[MAS_SPDM] = &mas_spdm,
1209	[MAS_BLSP_1] = &mas_blsp_1,
1210	[MAS_BLSP_2] = &mas_blsp_2,
1211	[MAS_USB_HS1] = &mas_usb_hs1,
1212	[MAS_XI_USB_HS1] = &mas_xi_usb_hs1,
1213	[MAS_CRYPTO] = &mas_crypto,
1214	[MAS_SDCC_1] = &mas_sdcc_1,
1215	[MAS_SDCC_2] = &mas_sdcc_2,
1216	[MAS_SNOC_PCNOC] = &mas_snoc_pcnoc,
1217	[PCNOC_M_0] = &pcnoc_m_0,
1218	[PCNOC_M_1] = &pcnoc_m_1,
1219	[PCNOC_INT_0] = &pcnoc_int_0,
1220	[PCNOC_INT_1] = &pcnoc_int_1,
1221	[PCNOC_INT_2] = &pcnoc_int_2,
1222	[PCNOC_INT_3] = &pcnoc_int_3,
1223	[PCNOC_S_0] = &pcnoc_s_0,
1224	[PCNOC_S_1] = &pcnoc_s_1,
1225	[PCNOC_S_2] = &pcnoc_s_2,
1226	[PCNOC_S_3] = &pcnoc_s_3,
1227	[PCNOC_S_4] = &pcnoc_s_4,
1228	[PCNOC_S_6] = &pcnoc_s_6,
1229	[PCNOC_S_7] = &pcnoc_s_7,
1230	[PCNOC_S_8] = &pcnoc_s_8,
1231	[SLV_SDCC_2] = &slv_sdcc_2,
1232	[SLV_SPDM] = &slv_spdm,
1233	[SLV_PDM] = &slv_pdm,
1234	[SLV_PRNG] = &slv_prng,
1235	[SLV_TCSR] = &slv_tcsr,
1236	[SLV_SNOC_CFG] = &slv_snoc_cfg,
1237	[SLV_MESSAGE_RAM] = &slv_message_ram,
1238	[SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg,
1239	[SLV_DISP_SS_CFG] = &slv_disp_ss_cfg,
1240	[SLV_VENUS_CFG] = &slv_venus_cfg,
1241	[SLV_GPU_CFG] = &slv_gpu_cfg,
1242	[SLV_TLMM] = &slv_tlmm,
1243	[SLV_BLSP_1] = &slv_blsp_1,
1244	[SLV_BLSP_2] = &slv_blsp_2,
1245	[SLV_PMIC_ARB] = &slv_pmic_arb,
1246	[SLV_SDCC_1] = &slv_sdcc_1,
1247	[SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1248	[SLV_USB_HS] = &slv_usb_hs,
1249	[SLV_TCU] = &slv_tcu,
1250	[SLV_PCNOC_SNOC] = &slv_pcnoc_snoc,
1251};
1252
1253static const struct regmap_config msm8937_pcnoc_regmap_config = {
1254	.reg_bits = 32,
1255	.reg_stride = 4,
1256	.val_bits = 32,
1257	.max_register = 0x13080,
1258	.fast_io = true,
1259};
1260
1261static const struct qcom_icc_desc msm8937_pcnoc = {
1262	.type = QCOM_ICC_NOC,
1263	.nodes = msm8937_pcnoc_nodes,
1264	.num_nodes = ARRAY_SIZE(msm8937_pcnoc_nodes),
1265	.bus_clk_desc = &bus_0_clk,
1266	.qos_offset = 0x7000,
1267	.keep_alive = true,
1268	.regmap_cfg = &msm8937_pcnoc_regmap_config,
1269};
1270
1271static struct qcom_icc_node * const msm8937_snoc_nodes[] = {
1272	[MAS_QDSS_BAM] = &mas_qdss_bam,
1273	[MAS_BIMC_SNOC] = &mas_bimc_snoc,
1274	[MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
1275	[MAS_QDSS_ETR] = &mas_qdss_etr,
1276	[QDSS_INT] = &qdss_int,
1277	[SNOC_INT_0] = &snoc_int_0,
1278	[SNOC_INT_1] = &snoc_int_1,
1279	[SNOC_INT_2] = &snoc_int_2,
1280	[SLV_KPSS_AHB] = &slv_kpss_ahb,
1281	[SLV_WCSS] = &slv_wcss,
1282	[SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1283	[SLV_IMEM] = &slv_imem,
1284	[SLV_SNOC_PCNOC] = &slv_snoc_pcnoc,
1285	[SLV_QDSS_STM] = &slv_qdss_stm,
1286	[SLV_CATS_1] = &slv_cats_1,
1287	[SLV_LPASS] = &slv_lpass,
1288};
1289
1290static const struct regmap_config msm8937_snoc_regmap_config = {
1291	.reg_bits = 32,
1292	.reg_stride = 4,
1293	.val_bits = 32,
1294	.max_register = 0x16080,
1295	.fast_io = true,
1296};
1297
1298static const struct qcom_icc_desc msm8937_snoc = {
1299	.type = QCOM_ICC_NOC,
1300	.nodes = msm8937_snoc_nodes,
1301	.num_nodes = ARRAY_SIZE(msm8937_snoc_nodes),
1302	.bus_clk_desc = &bus_1_clk,
1303	.regmap_cfg = &msm8937_snoc_regmap_config,
1304	.qos_offset = 0x7000,
1305};
1306
1307static struct qcom_icc_node * const msm8937_snoc_mm_nodes[] = {
1308	[MAS_JPEG] = &mas_jpeg,
1309	[MAS_MDP] = &mas_mdp,
1310	[MAS_VENUS] = &mas_venus,
1311	[MAS_VFE0] = &mas_vfe0,
1312	[MAS_VFE1] = &mas_vfe1,
1313	[MAS_CPP] = &mas_cpp,
1314	[SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0,
1315	[SLV_SNOC_BIMC_2] = &slv_snoc_bimc_2,
1316	[SLV_CATS_0] = &slv_cats_0,
1317};
1318
1319static const struct qcom_icc_desc msm8937_snoc_mm = {
1320	.type = QCOM_ICC_NOC,
1321	.nodes = msm8937_snoc_mm_nodes,
1322	.num_nodes = ARRAY_SIZE(msm8937_snoc_mm_nodes),
1323	.bus_clk_desc = &bus_2_clk,
1324	.regmap_cfg = &msm8937_snoc_regmap_config,
1325	.qos_offset = 0x7000,
1326	.ab_coeff = 154,
1327};
1328
1329static const struct of_device_id msm8937_noc_of_match[] = {
1330	{ .compatible = "qcom,msm8937-bimc", .data = &msm8937_bimc },
1331	{ .compatible = "qcom,msm8937-pcnoc", .data = &msm8937_pcnoc },
1332	{ .compatible = "qcom,msm8937-snoc", .data = &msm8937_snoc },
1333	{ .compatible = "qcom,msm8937-snoc-mm", .data = &msm8937_snoc_mm },
1334	{ }
1335};
1336MODULE_DEVICE_TABLE(of, msm8937_noc_of_match);
1337
1338static struct platform_driver msm8937_noc_driver = {
1339	.probe = qnoc_probe,
1340	.remove = qnoc_remove,
1341	.driver = {
1342		.name = "qnoc-msm8937",
1343		.of_match_table = msm8937_noc_of_match,
1344		.sync_state = icc_sync_state,
1345	},
1346};
1347module_platform_driver(msm8937_noc_driver);
1348
1349MODULE_DESCRIPTION("Qualcomm MSM8937 NoC driver");
1350MODULE_LICENSE("GPL");