milos.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
   5 */
   6
   7#include <linux/device.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/interconnect.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/of_device.h>
  13#include <linux/of_platform.h>
  14#include <linux/platform_device.h>
  15#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
  16
  17#include "bcm-voter.h"
  18#include "icc-common.h"
  19#include "icc-rpmh.h"
  20
  21static struct qcom_icc_node qhm_qup1;
  22static struct qcom_icc_node xm_ufs_mem;
  23static struct qcom_icc_node xm_usb3_0;
  24static struct qcom_icc_node qhm_qdss_bam;
  25static struct qcom_icc_node qhm_qspi;
  26static struct qcom_icc_node qhm_qup0;
  27static struct qcom_icc_node qxm_crypto;
  28static struct qcom_icc_node qxm_ipa;
  29static struct qcom_icc_node xm_qdss_etr_0;
  30static struct qcom_icc_node xm_qdss_etr_1;
  31static struct qcom_icc_node xm_sdc1;
  32static struct qcom_icc_node xm_sdc2;
  33static struct qcom_icc_node qup0_core_master;
  34static struct qcom_icc_node qup1_core_master;
  35static struct qcom_icc_node qsm_cfg;
  36static struct qcom_icc_node qnm_gemnoc_cnoc;
  37static struct qcom_icc_node qnm_gemnoc_pcie;
  38static struct qcom_icc_node alm_gpu_tcu;
  39static struct qcom_icc_node alm_sys_tcu;
  40static struct qcom_icc_node chm_apps;
  41static struct qcom_icc_node qnm_gpu;
  42static struct qcom_icc_node qnm_lpass_gemnoc;
  43static struct qcom_icc_node qnm_mdsp;
  44static struct qcom_icc_node qnm_mnoc_hf;
  45static struct qcom_icc_node qnm_mnoc_sf;
  46static struct qcom_icc_node qnm_nsp_gemnoc;
  47static struct qcom_icc_node qnm_pcie;
  48static struct qcom_icc_node qnm_snoc_gc;
  49static struct qcom_icc_node qnm_snoc_sf;
  50static struct qcom_icc_node qxm_wlan_q6;
  51static struct qcom_icc_node qxm_lpass_dsp;
  52static struct qcom_icc_node llcc_mc;
  53static struct qcom_icc_node qnm_camnoc_hf;
  54static struct qcom_icc_node qnm_camnoc_icp;
  55static struct qcom_icc_node qnm_camnoc_sf;
  56static struct qcom_icc_node qnm_mdp;
  57static struct qcom_icc_node qnm_video;
  58static struct qcom_icc_node qsm_hf_mnoc_cfg;
  59static struct qcom_icc_node qsm_sf_mnoc_cfg;
  60static struct qcom_icc_node qxm_nsp;
  61static struct qcom_icc_node qsm_pcie_anoc_cfg;
  62static struct qcom_icc_node xm_pcie3_0;
  63static struct qcom_icc_node xm_pcie3_1;
  64static struct qcom_icc_node qnm_aggre1_noc;
  65static struct qcom_icc_node qnm_aggre2_noc;
  66static struct qcom_icc_node qnm_apss_noc;
  67static struct qcom_icc_node qnm_cnoc_data;
  68static struct qcom_icc_node qxm_pimem;
  69static struct qcom_icc_node xm_gic;
  70static struct qcom_icc_node qns_a1noc_snoc;
  71static struct qcom_icc_node qns_a2noc_snoc;
  72static struct qcom_icc_node qup0_core_slave;
  73static struct qcom_icc_node qup1_core_slave;
  74static struct qcom_icc_node qhs_ahb2phy0;
  75static struct qcom_icc_node qhs_ahb2phy1;
  76static struct qcom_icc_node qhs_camera_cfg;
  77static struct qcom_icc_node qhs_clk_ctl;
  78static struct qcom_icc_node qhs_cpr_cx;
  79static struct qcom_icc_node qhs_cpr_mxa;
  80static struct qcom_icc_node qhs_crypto0_cfg;
  81static struct qcom_icc_node qhs_cx_rdpm;
  82static struct qcom_icc_node qhs_gpuss_cfg;
  83static struct qcom_icc_node qhs_imem_cfg;
  84static struct qcom_icc_node qhs_mss_cfg;
  85static struct qcom_icc_node qhs_mx_2_rdpm;
  86static struct qcom_icc_node qhs_mx_rdpm;
  87static struct qcom_icc_node qhs_pdm;
  88static struct qcom_icc_node qhs_qdss_cfg;
  89static struct qcom_icc_node qhs_qspi;
  90static struct qcom_icc_node qhs_qup0;
  91static struct qcom_icc_node qhs_qup1;
  92static struct qcom_icc_node qhs_sdc1;
  93static struct qcom_icc_node qhs_sdc2;
  94static struct qcom_icc_node qhs_tcsr;
  95static struct qcom_icc_node qhs_tlmm;
  96static struct qcom_icc_node qhs_ufs_mem_cfg;
  97static struct qcom_icc_node qhs_usb3_0;
  98static struct qcom_icc_node qhs_venus_cfg;
  99static struct qcom_icc_node qhs_vsense_ctrl_cfg;
 100static struct qcom_icc_node qhs_wlan_q6;
 101static struct qcom_icc_node qss_mnoc_hf_cfg;
 102static struct qcom_icc_node qss_mnoc_sf_cfg;
 103static struct qcom_icc_node qss_nsp_qtb_cfg;
 104static struct qcom_icc_node qss_pcie_anoc_cfg;
 105static struct qcom_icc_node qss_wlan_q6_throttle_cfg;
 106static struct qcom_icc_node srvc_cnoc_cfg;
 107static struct qcom_icc_node xs_qdss_stm;
 108static struct qcom_icc_node xs_sys_tcu_cfg;
 109static struct qcom_icc_node qhs_aoss;
 110static struct qcom_icc_node qhs_display_cfg;
 111static struct qcom_icc_node qhs_ipa;
 112static struct qcom_icc_node qhs_ipc_router;
 113static struct qcom_icc_node qhs_pcie0_cfg;
 114static struct qcom_icc_node qhs_pcie1_cfg;
 115static struct qcom_icc_node qhs_prng;
 116static struct qcom_icc_node qhs_tme_cfg;
 117static struct qcom_icc_node qss_apss;
 118static struct qcom_icc_node qss_cfg;
 119static struct qcom_icc_node qss_ddrss_cfg;
 120static struct qcom_icc_node qxs_imem;
 121static struct qcom_icc_node qxs_pimem;
 122static struct qcom_icc_node srvc_cnoc_main;
 123static struct qcom_icc_node xs_pcie_0;
 124static struct qcom_icc_node xs_pcie_1;
 125static struct qcom_icc_node qns_gem_noc_cnoc;
 126static struct qcom_icc_node qns_llcc;
 127static struct qcom_icc_node qns_pcie;
 128static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
 129static struct qcom_icc_node ebi;
 130static struct qcom_icc_node qns_mem_noc_hf;
 131static struct qcom_icc_node qns_mem_noc_sf;
 132static struct qcom_icc_node srvc_mnoc_hf;
 133static struct qcom_icc_node srvc_mnoc_sf;
 134static struct qcom_icc_node qns_nsp_gemnoc;
 135static struct qcom_icc_node qns_pcie_mem_noc;
 136static struct qcom_icc_node srvc_pcie_aggre_noc;
 137static struct qcom_icc_node qns_gemnoc_gc;
 138static struct qcom_icc_node qns_gemnoc_sf;
 139
 140static struct qcom_icc_qosbox qhm_qup1_qos = {
 141	.num_ports = 1,
 142	.port_offsets = { 0xc000 },
 143	.prio = 2,
 144	.urg_fwd = 0,
 145	.prio_fwd_disable = 1,
 146};
 147
 148static struct qcom_icc_node qhm_qup1 = {
 149	.name = "qhm_qup1",
 150	.channels = 1,
 151	.buswidth = 4,
 152	.qosbox = &qhm_qup1_qos,
 153	.num_links = 1,
 154	.link_nodes = { &qns_a1noc_snoc },
 155};
 156
 157static struct qcom_icc_qosbox xm_ufs_mem_qos = {
 158	.num_ports = 1,
 159	.port_offsets = { 0xf200 },
 160	.prio = 2,
 161	.urg_fwd = 0,
 162	.prio_fwd_disable = 1,
 163};
 164
 165static struct qcom_icc_node xm_ufs_mem = {
 166	.name = "xm_ufs_mem",
 167	.channels = 1,
 168	.buswidth = 8,
 169	.qosbox = &xm_ufs_mem_qos,
 170	.num_links = 1,
 171	.link_nodes = { &qns_a1noc_snoc },
 172};
 173
 174static struct qcom_icc_qosbox xm_usb3_0_qos = {
 175	.num_ports = 1,
 176	.port_offsets = { 0x10000 },
 177	.prio = 2,
 178	.urg_fwd = 0,
 179	.prio_fwd_disable = 1,
 180};
 181
 182static struct qcom_icc_node xm_usb3_0 = {
 183	.name = "xm_usb3_0",
 184	.channels = 1,
 185	.buswidth = 8,
 186	.qosbox = &xm_usb3_0_qos,
 187	.num_links = 1,
 188	.link_nodes = { &qns_a1noc_snoc },
 189};
 190
 191static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
 192	.num_ports = 1,
 193	.port_offsets = { 0x14000 },
 194	.prio = 2,
 195	.urg_fwd = 0,
 196	.prio_fwd_disable = 1,
 197};
 198
 199static struct qcom_icc_node qhm_qdss_bam = {
 200	.name = "qhm_qdss_bam",
 201	.channels = 1,
 202	.buswidth = 4,
 203	.qosbox = &qhm_qdss_bam_qos,
 204	.num_links = 1,
 205	.link_nodes = { &qns_a2noc_snoc },
 206};
 207
 208static struct qcom_icc_qosbox qhm_qspi_qos = {
 209	.num_ports = 1,
 210	.port_offsets = { 0x12000 },
 211	.prio = 2,
 212	.urg_fwd = 0,
 213	.prio_fwd_disable = 1,
 214};
 215
 216static struct qcom_icc_node qhm_qspi = {
 217	.name = "qhm_qspi",
 218	.channels = 1,
 219	.buswidth = 4,
 220	.qosbox = &qhm_qspi_qos,
 221	.num_links = 1,
 222	.link_nodes = { &qns_a2noc_snoc },
 223};
 224
 225static struct qcom_icc_qosbox qhm_qup0_qos = {
 226	.num_ports = 1,
 227	.port_offsets = { 0x13000 },
 228	.prio = 2,
 229	.urg_fwd = 0,
 230	.prio_fwd_disable = 1,
 231};
 232
 233static struct qcom_icc_node qhm_qup0 = {
 234	.name = "qhm_qup0",
 235	.channels = 1,
 236	.buswidth = 4,
 237	.qosbox = &qhm_qup0_qos,
 238	.num_links = 1,
 239	.link_nodes = { &qns_a2noc_snoc },
 240};
 241
 242static struct qcom_icc_qosbox qxm_crypto_qos = {
 243	.num_ports = 1,
 244	.port_offsets = { 0x15000 },
 245	.prio = 2,
 246	.urg_fwd = 0,
 247	.prio_fwd_disable = 1,
 248};
 249
 250static struct qcom_icc_node qxm_crypto = {
 251	.name = "qxm_crypto",
 252	.channels = 1,
 253	.buswidth = 8,
 254	.qosbox = &qxm_crypto_qos,
 255	.num_links = 1,
 256	.link_nodes = { &qns_a2noc_snoc },
 257};
 258
 259static struct qcom_icc_qosbox qxm_ipa_qos = {
 260	.num_ports = 1,
 261	.port_offsets = { 0x16000 },
 262	.prio = 2,
 263	.urg_fwd = 0,
 264	.prio_fwd_disable = 1,
 265};
 266
 267static struct qcom_icc_node qxm_ipa = {
 268	.name = "qxm_ipa",
 269	.channels = 1,
 270	.buswidth = 8,
 271	.qosbox = &qxm_ipa_qos,
 272	.num_links = 1,
 273	.link_nodes = { &qns_a2noc_snoc },
 274};
 275
 276static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
 277	.num_ports = 1,
 278	.port_offsets = { 0x17000 },
 279	.prio = 2,
 280	.urg_fwd = 0,
 281	.prio_fwd_disable = 1,
 282};
 283
 284static struct qcom_icc_node xm_qdss_etr_0 = {
 285	.name = "xm_qdss_etr_0",
 286	.channels = 1,
 287	.buswidth = 8,
 288	.qosbox = &xm_qdss_etr_0_qos,
 289	.num_links = 1,
 290	.link_nodes = { &qns_a2noc_snoc },
 291};
 292
 293static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
 294	.num_ports = 1,
 295	.port_offsets = { 0x18000 },
 296	.prio = 2,
 297	.urg_fwd = 0,
 298	.prio_fwd_disable = 1,
 299};
 300
 301static struct qcom_icc_node xm_qdss_etr_1 = {
 302	.name = "xm_qdss_etr_1",
 303	.channels = 1,
 304	.buswidth = 8,
 305	.qosbox = &xm_qdss_etr_1_qos,
 306	.num_links = 1,
 307	.link_nodes = { &qns_a2noc_snoc },
 308};
 309
 310static struct qcom_icc_qosbox xm_sdc1_qos = {
 311	.num_ports = 1,
 312	.port_offsets = { 0x1a000 },
 313	.prio = 2,
 314	.urg_fwd = 0,
 315	.prio_fwd_disable = 1,
 316};
 317
 318static struct qcom_icc_node xm_sdc1 = {
 319	.name = "xm_sdc1",
 320	.channels = 1,
 321	.buswidth = 8,
 322	.qosbox = &xm_sdc1_qos,
 323	.num_links = 1,
 324	.link_nodes = { &qns_a2noc_snoc },
 325};
 326
 327static struct qcom_icc_qosbox xm_sdc2_qos = {
 328	.num_ports = 1,
 329	.port_offsets = { 0x19000 },
 330	.prio = 2,
 331	.urg_fwd = 0,
 332	.prio_fwd_disable = 1,
 333};
 334
 335static struct qcom_icc_node xm_sdc2 = {
 336	.name = "xm_sdc2",
 337	.channels = 1,
 338	.buswidth = 8,
 339	.qosbox = &xm_sdc2_qos,
 340	.num_links = 1,
 341	.link_nodes = { &qns_a2noc_snoc },
 342};
 343
 344static struct qcom_icc_node qup0_core_master = {
 345	.name = "qup0_core_master",
 346	.channels = 1,
 347	.buswidth = 4,
 348	.num_links = 1,
 349	.link_nodes = { &qup0_core_slave },
 350};
 351
 352static struct qcom_icc_node qup1_core_master = {
 353	.name = "qup1_core_master",
 354	.channels = 1,
 355	.buswidth = 4,
 356	.num_links = 1,
 357	.link_nodes = { &qup1_core_slave },
 358};
 359
 360static struct qcom_icc_node qsm_cfg = {
 361	.name = "qsm_cfg",
 362	.channels = 1,
 363	.buswidth = 4,
 364	.num_links = 35,
 365	.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
 366		   &qhs_camera_cfg, &qhs_clk_ctl,
 367		   &qhs_cpr_cx, &qhs_cpr_mxa,
 368		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
 369		   &qhs_gpuss_cfg, &qhs_imem_cfg,
 370		   &qhs_mss_cfg, &qhs_mx_2_rdpm,
 371		   &qhs_mx_rdpm, &qhs_pdm,
 372		   &qhs_qdss_cfg, &qhs_qspi,
 373		   &qhs_qup0, &qhs_qup1,
 374		   &qhs_sdc1, &qhs_sdc2,
 375		   &qhs_tcsr, &qhs_tlmm,
 376		   &qhs_ufs_mem_cfg, &qhs_usb3_0,
 377		   &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
 378		   &qhs_wlan_q6, &qss_mnoc_hf_cfg,
 379		   &qss_mnoc_sf_cfg, &qss_nsp_qtb_cfg,
 380		   &qss_pcie_anoc_cfg, &qss_wlan_q6_throttle_cfg,
 381		   &srvc_cnoc_cfg, &xs_qdss_stm,
 382		   &xs_sys_tcu_cfg },
 383};
 384
 385static struct qcom_icc_node qnm_gemnoc_cnoc = {
 386	.name = "qnm_gemnoc_cnoc",
 387	.channels = 1,
 388	.buswidth = 16,
 389	.num_links = 14,
 390	.link_nodes = { &qhs_aoss, &qhs_display_cfg,
 391		   &qhs_ipa, &qhs_ipc_router,
 392		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
 393		   &qhs_prng, &qhs_tme_cfg,
 394		   &qss_apss, &qss_cfg,
 395		   &qss_ddrss_cfg, &qxs_imem,
 396		   &qxs_pimem, &srvc_cnoc_main },
 397};
 398
 399static struct qcom_icc_node qnm_gemnoc_pcie = {
 400	.name = "qnm_gemnoc_pcie",
 401	.channels = 1,
 402	.buswidth = 8,
 403	.num_links = 2,
 404	.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
 405};
 406
 407static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
 408	.num_ports = 1,
 409	.port_offsets = { 0xf1000 },
 410	.prio = 1,
 411	.urg_fwd = 0,
 412	.prio_fwd_disable = 1,
 413};
 414
 415static struct qcom_icc_node alm_gpu_tcu = {
 416	.name = "alm_gpu_tcu",
 417	.channels = 1,
 418	.buswidth = 8,
 419	.qosbox = &alm_gpu_tcu_qos,
 420	.num_links = 2,
 421	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 422};
 423
 424static struct qcom_icc_qosbox alm_sys_tcu_qos = {
 425	.num_ports = 1,
 426	.port_offsets = { 0xf3000 },
 427	.prio = 6,
 428	.urg_fwd = 0,
 429	.prio_fwd_disable = 1,
 430};
 431
 432static struct qcom_icc_node alm_sys_tcu = {
 433	.name = "alm_sys_tcu",
 434	.channels = 1,
 435	.buswidth = 8,
 436	.qosbox = &alm_sys_tcu_qos,
 437	.num_links = 2,
 438	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 439};
 440
 441static struct qcom_icc_node chm_apps = {
 442	.name = "chm_apps",
 443	.channels = 3,
 444	.buswidth = 32,
 445	.num_links = 3,
 446	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 447		   &qns_pcie },
 448};
 449
 450static struct qcom_icc_qosbox qnm_gpu_qos = {
 451	.num_ports = 2,
 452	.port_offsets = { 0x31000, 0x71000 },
 453	.prio = 0,
 454	.urg_fwd = 0,
 455	.prio_fwd_disable = 1,
 456};
 457
 458static struct qcom_icc_node qnm_gpu = {
 459	.name = "qnm_gpu",
 460	.channels = 2,
 461	.buswidth = 32,
 462	.qosbox = &qnm_gpu_qos,
 463	.num_links = 2,
 464	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 465};
 466
 467static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
 468	.num_ports = 1,
 469	.port_offsets = { 0xf5000 },
 470	.prio = 0,
 471	.urg_fwd = 1,
 472	.prio_fwd_disable = 0,
 473};
 474
 475static struct qcom_icc_node qnm_lpass_gemnoc = {
 476	.name = "qnm_lpass_gemnoc",
 477	.channels = 1,
 478	.buswidth = 16,
 479	.qosbox = &qnm_lpass_gemnoc_qos,
 480	.num_links = 3,
 481	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 482		   &qns_pcie },
 483};
 484
 485static struct qcom_icc_node qnm_mdsp = {
 486	.name = "qnm_mdsp",
 487	.channels = 1,
 488	.buswidth = 16,
 489	.num_links = 3,
 490	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 491		   &qns_pcie },
 492};
 493
 494static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
 495	.num_ports = 2,
 496	.port_offsets = { 0x33000, 0x73000 },
 497	.prio = 0,
 498	.urg_fwd = 1,
 499	.prio_fwd_disable = 0,
 500};
 501
 502static struct qcom_icc_node qnm_mnoc_hf = {
 503	.name = "qnm_mnoc_hf",
 504	.channels = 2,
 505	.buswidth = 32,
 506	.qosbox = &qnm_mnoc_hf_qos,
 507	.num_links = 2,
 508	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 509};
 510
 511static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
 512	.num_ports = 2,
 513	.port_offsets = { 0x35000, 0x75000 },
 514	.prio = 0,
 515	.urg_fwd = 1,
 516	.prio_fwd_disable = 0,
 517};
 518
 519static struct qcom_icc_node qnm_mnoc_sf = {
 520	.name = "qnm_mnoc_sf",
 521	.channels = 2,
 522	.buswidth = 32,
 523	.qosbox = &qnm_mnoc_sf_qos,
 524	.num_links = 2,
 525	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 526};
 527
 528static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
 529	.num_ports = 2,
 530	.port_offsets = { 0x37000, 0x77000 },
 531	.prio = 0,
 532	.urg_fwd = 0,
 533	.prio_fwd_disable = 1,
 534};
 535
 536static struct qcom_icc_node qnm_nsp_gemnoc = {
 537	.name = "qnm_nsp_gemnoc",
 538	.channels = 2,
 539	.buswidth = 32,
 540	.qosbox = &qnm_nsp_gemnoc_qos,
 541	.num_links = 3,
 542	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 543		   &qns_pcie },
 544};
 545
 546static struct qcom_icc_qosbox qnm_pcie_qos = {
 547	.num_ports = 1,
 548	.port_offsets = { 0xf7000 },
 549	.prio = 2,
 550	.urg_fwd = 1,
 551	.prio_fwd_disable = 0,
 552};
 553
 554static struct qcom_icc_node qnm_pcie = {
 555	.name = "qnm_pcie",
 556	.channels = 1,
 557	.buswidth = 8,
 558	.qosbox = &qnm_pcie_qos,
 559	.num_links = 2,
 560	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 561};
 562
 563static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
 564	.num_ports = 1,
 565	.port_offsets = { 0xf9000 },
 566	.prio = 0,
 567	.urg_fwd = 1,
 568	.prio_fwd_disable = 0,
 569};
 570
 571static struct qcom_icc_node qnm_snoc_gc = {
 572	.name = "qnm_snoc_gc",
 573	.channels = 1,
 574	.buswidth = 8,
 575	.qosbox = &qnm_snoc_gc_qos,
 576	.num_links = 1,
 577	.link_nodes = { &qns_llcc },
 578};
 579
 580static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
 581	.num_ports = 1,
 582	.port_offsets = { 0xfb000 },
 583	.prio = 0,
 584	.urg_fwd = 1,
 585	.prio_fwd_disable = 0,
 586};
 587
 588static struct qcom_icc_node qnm_snoc_sf = {
 589	.name = "qnm_snoc_sf",
 590	.channels = 1,
 591	.buswidth = 16,
 592	.qosbox = &qnm_snoc_sf_qos,
 593	.num_links = 3,
 594	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 595		   &qns_pcie },
 596};
 597
 598static struct qcom_icc_node qxm_wlan_q6 = {
 599	.name = "qxm_wlan_q6",
 600	.channels = 1,
 601	.buswidth = 8,
 602	.num_links = 3,
 603	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 604		   &qns_pcie },
 605};
 606
 607static struct qcom_icc_node qxm_lpass_dsp = {
 608	.name = "qxm_lpass_dsp",
 609	.channels = 1,
 610	.buswidth = 8,
 611	.num_links = 1,
 612	.link_nodes = { &qns_lpass_ag_noc_gemnoc },
 613};
 614
 615static struct qcom_icc_node llcc_mc = {
 616	.name = "llcc_mc",
 617	.channels = 2,
 618	.buswidth = 4,
 619	.num_links = 1,
 620	.link_nodes = { &ebi },
 621};
 622
 623static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
 624	.num_ports = 2,
 625	.port_offsets = { 0xa8000, 0xa9000 },
 626	.prio = 0,
 627	.urg_fwd = 1,
 628	.prio_fwd_disable = 0,
 629};
 630
 631static struct qcom_icc_node qnm_camnoc_hf = {
 632	.name = "qnm_camnoc_hf",
 633	.channels = 2,
 634	.buswidth = 32,
 635	.qosbox = &qnm_camnoc_hf_qos,
 636	.num_links = 1,
 637	.link_nodes = { &qns_mem_noc_hf },
 638};
 639
 640static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
 641	.num_ports = 1,
 642	.port_offsets = { 0x2a000 },
 643	.prio = 5,
 644	.urg_fwd = 0,
 645	.prio_fwd_disable = 1,
 646};
 647
 648static struct qcom_icc_node qnm_camnoc_icp = {
 649	.name = "qnm_camnoc_icp",
 650	.channels = 1,
 651	.buswidth = 8,
 652	.qosbox = &qnm_camnoc_icp_qos,
 653	.num_links = 1,
 654	.link_nodes = { &qns_mem_noc_sf },
 655};
 656
 657static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
 658	.num_ports = 2,
 659	.port_offsets = { 0x2b000, 0x2c000 },
 660	.prio = 0,
 661	.urg_fwd = 1,
 662	.prio_fwd_disable = 0,
 663};
 664
 665static struct qcom_icc_node qnm_camnoc_sf = {
 666	.name = "qnm_camnoc_sf",
 667	.channels = 2,
 668	.buswidth = 32,
 669	.qosbox = &qnm_camnoc_sf_qos,
 670	.num_links = 1,
 671	.link_nodes = { &qns_mem_noc_sf },
 672};
 673
 674static struct qcom_icc_qosbox qnm_mdp_qos = {
 675	.num_ports = 1,
 676	.port_offsets = { 0xad000 },
 677	.prio = 0,
 678	.urg_fwd = 1,
 679	.prio_fwd_disable = 0,
 680};
 681
 682static struct qcom_icc_node qnm_mdp = {
 683	.name = "qnm_mdp",
 684	.channels = 1,
 685	.buswidth = 32,
 686	.qosbox = &qnm_mdp_qos,
 687	.num_links = 1,
 688	.link_nodes = { &qns_mem_noc_hf },
 689};
 690
 691static struct qcom_icc_qosbox qnm_video_qos = {
 692	.num_ports = 1,
 693	.port_offsets = { 0x30000 },
 694	.prio = 0,
 695	.urg_fwd = 1,
 696	.prio_fwd_disable = 0,
 697};
 698
 699static struct qcom_icc_node qnm_video = {
 700	.name = "qnm_video",
 701	.channels = 1,
 702	.buswidth = 32,
 703	.qosbox = &qnm_video_qos,
 704	.num_links = 1,
 705	.link_nodes = { &qns_mem_noc_sf },
 706};
 707
 708static struct qcom_icc_node qsm_hf_mnoc_cfg = {
 709	.name = "qsm_hf_mnoc_cfg",
 710	.channels = 1,
 711	.buswidth = 4,
 712	.num_links = 1,
 713	.link_nodes = { &srvc_mnoc_hf },
 714};
 715
 716static struct qcom_icc_node qsm_sf_mnoc_cfg = {
 717	.name = "qsm_sf_mnoc_cfg",
 718	.channels = 1,
 719	.buswidth = 4,
 720	.num_links = 1,
 721	.link_nodes = { &srvc_mnoc_sf },
 722};
 723
 724static struct qcom_icc_node qxm_nsp = {
 725	.name = "qxm_nsp",
 726	.channels = 2,
 727	.buswidth = 32,
 728	.num_links = 1,
 729	.link_nodes = { &qns_nsp_gemnoc },
 730};
 731
 732static struct qcom_icc_node qsm_pcie_anoc_cfg = {
 733	.name = "qsm_pcie_anoc_cfg",
 734	.channels = 1,
 735	.buswidth = 4,
 736	.num_links = 1,
 737	.link_nodes = { &srvc_pcie_aggre_noc },
 738};
 739
 740static struct qcom_icc_qosbox xm_pcie3_0_qos = {
 741	.num_ports = 1,
 742	.port_offsets = { 0xb000 },
 743	.prio = 2,
 744	.urg_fwd = 0,
 745	.prio_fwd_disable = 1,
 746};
 747
 748static struct qcom_icc_node xm_pcie3_0 = {
 749	.name = "xm_pcie3_0",
 750	.channels = 1,
 751	.buswidth = 8,
 752	.qosbox = &xm_pcie3_0_qos,
 753	.num_links = 1,
 754	.link_nodes = { &qns_pcie_mem_noc },
 755};
 756
 757static struct qcom_icc_qosbox xm_pcie3_1_qos = {
 758	.num_ports = 1,
 759	.port_offsets = { 0xc000 },
 760	.prio = 2,
 761	.urg_fwd = 0,
 762	.prio_fwd_disable = 1,
 763};
 764
 765static struct qcom_icc_node xm_pcie3_1 = {
 766	.name = "xm_pcie3_1",
 767	.channels = 1,
 768	.buswidth = 8,
 769	.qosbox = &xm_pcie3_1_qos,
 770	.num_links = 1,
 771	.link_nodes = { &qns_pcie_mem_noc },
 772};
 773
 774static struct qcom_icc_node qnm_aggre1_noc = {
 775	.name = "qnm_aggre1_noc",
 776	.channels = 1,
 777	.buswidth = 16,
 778	.num_links = 1,
 779	.link_nodes = { &qns_gemnoc_sf },
 780};
 781
 782static struct qcom_icc_node qnm_aggre2_noc = {
 783	.name = "qnm_aggre2_noc",
 784	.channels = 1,
 785	.buswidth = 16,
 786	.num_links = 1,
 787	.link_nodes = { &qns_gemnoc_sf },
 788};
 789
 790static struct qcom_icc_qosbox qnm_apss_noc_qos = {
 791	.num_ports = 1,
 792	.port_offsets = { 0x1c000 },
 793	.prio = 2,
 794	.urg_fwd = 0,
 795	.prio_fwd_disable = 1,
 796};
 797
 798static struct qcom_icc_node qnm_apss_noc = {
 799	.name = "qnm_apss_noc",
 800	.channels = 1,
 801	.buswidth = 4,
 802	.qosbox = &qnm_apss_noc_qos,
 803	.num_links = 1,
 804	.link_nodes = { &qns_gemnoc_sf },
 805};
 806
 807static struct qcom_icc_qosbox qnm_cnoc_data_qos = {
 808	.num_ports = 1,
 809	.port_offsets = { 0x1d000 },
 810	.prio = 2,
 811	.urg_fwd = 0,
 812	.prio_fwd_disable = 1,
 813};
 814
 815static struct qcom_icc_node qnm_cnoc_data = {
 816	.name = "qnm_cnoc_data",
 817	.channels = 1,
 818	.buswidth = 8,
 819	.qosbox = &qnm_cnoc_data_qos,
 820	.num_links = 1,
 821	.link_nodes = { &qns_gemnoc_sf },
 822};
 823
 824static struct qcom_icc_qosbox qxm_pimem_qos = {
 825	.num_ports = 1,
 826	.port_offsets = { 0x1e000 },
 827	.prio = 2,
 828	.urg_fwd = 0,
 829	.prio_fwd_disable = 1,
 830};
 831
 832static struct qcom_icc_node qxm_pimem = {
 833	.name = "qxm_pimem",
 834	.channels = 1,
 835	.buswidth = 8,
 836	.qosbox = &qxm_pimem_qos,
 837	.num_links = 1,
 838	.link_nodes = { &qns_gemnoc_gc },
 839};
 840
 841static struct qcom_icc_qosbox xm_gic_qos = {
 842	.num_ports = 1,
 843	.port_offsets = { 0x1f000 },
 844	.prio = 2,
 845	.urg_fwd = 0,
 846	.prio_fwd_disable = 1,
 847};
 848
 849static struct qcom_icc_node xm_gic = {
 850	.name = "xm_gic",
 851	.channels = 1,
 852	.buswidth = 8,
 853	.qosbox = &xm_gic_qos,
 854	.num_links = 1,
 855	.link_nodes = { &qns_gemnoc_gc },
 856};
 857
 858static struct qcom_icc_node qns_a1noc_snoc = {
 859	.name = "qns_a1noc_snoc",
 860	.channels = 1,
 861	.buswidth = 16,
 862	.num_links = 1,
 863	.link_nodes = { &qnm_aggre1_noc },
 864};
 865
 866static struct qcom_icc_node qns_a2noc_snoc = {
 867	.name = "qns_a2noc_snoc",
 868	.channels = 1,
 869	.buswidth = 16,
 870	.num_links = 1,
 871	.link_nodes = { &qnm_aggre2_noc },
 872};
 873
 874static struct qcom_icc_node qup0_core_slave = {
 875	.name = "qup0_core_slave",
 876	.channels = 1,
 877	.buswidth = 4,
 878	.num_links = 0,
 879};
 880
 881static struct qcom_icc_node qup1_core_slave = {
 882	.name = "qup1_core_slave",
 883	.channels = 1,
 884	.buswidth = 4,
 885	.num_links = 0,
 886};
 887
 888static struct qcom_icc_node qhs_ahb2phy0 = {
 889	.name = "qhs_ahb2phy0",
 890	.channels = 1,
 891	.buswidth = 4,
 892	.num_links = 0,
 893};
 894
 895static struct qcom_icc_node qhs_ahb2phy1 = {
 896	.name = "qhs_ahb2phy1",
 897	.channels = 1,
 898	.buswidth = 4,
 899	.num_links = 0,
 900};
 901
 902static struct qcom_icc_node qhs_camera_cfg = {
 903	.name = "qhs_camera_cfg",
 904	.channels = 1,
 905	.buswidth = 4,
 906	.num_links = 0,
 907};
 908
 909static struct qcom_icc_node qhs_clk_ctl = {
 910	.name = "qhs_clk_ctl",
 911	.channels = 1,
 912	.buswidth = 4,
 913	.num_links = 0,
 914};
 915
 916static struct qcom_icc_node qhs_cpr_cx = {
 917	.name = "qhs_cpr_cx",
 918	.channels = 1,
 919	.buswidth = 4,
 920	.num_links = 0,
 921};
 922
 923static struct qcom_icc_node qhs_cpr_mxa = {
 924	.name = "qhs_cpr_mxa",
 925	.channels = 1,
 926	.buswidth = 4,
 927	.num_links = 0,
 928};
 929
 930static struct qcom_icc_node qhs_crypto0_cfg = {
 931	.name = "qhs_crypto0_cfg",
 932	.channels = 1,
 933	.buswidth = 4,
 934	.num_links = 0,
 935};
 936
 937static struct qcom_icc_node qhs_cx_rdpm = {
 938	.name = "qhs_cx_rdpm",
 939	.channels = 1,
 940	.buswidth = 4,
 941	.num_links = 0,
 942};
 943
 944static struct qcom_icc_node qhs_gpuss_cfg = {
 945	.name = "qhs_gpuss_cfg",
 946	.channels = 1,
 947	.buswidth = 8,
 948	.num_links = 0,
 949};
 950
 951static struct qcom_icc_node qhs_imem_cfg = {
 952	.name = "qhs_imem_cfg",
 953	.channels = 1,
 954	.buswidth = 4,
 955	.num_links = 0,
 956};
 957
 958static struct qcom_icc_node qhs_mss_cfg = {
 959	.name = "qhs_mss_cfg",
 960	.channels = 1,
 961	.buswidth = 4,
 962	.num_links = 0,
 963};
 964
 965static struct qcom_icc_node qhs_mx_2_rdpm = {
 966	.name = "qhs_mx_2_rdpm",
 967	.channels = 1,
 968	.buswidth = 4,
 969	.num_links = 0,
 970};
 971
 972static struct qcom_icc_node qhs_mx_rdpm = {
 973	.name = "qhs_mx_rdpm",
 974	.channels = 1,
 975	.buswidth = 4,
 976	.num_links = 0,
 977};
 978
 979static struct qcom_icc_node qhs_pdm = {
 980	.name = "qhs_pdm",
 981	.channels = 1,
 982	.buswidth = 4,
 983	.num_links = 0,
 984};
 985
 986static struct qcom_icc_node qhs_qdss_cfg = {
 987	.name = "qhs_qdss_cfg",
 988	.channels = 1,
 989	.buswidth = 4,
 990	.num_links = 0,
 991};
 992
 993static struct qcom_icc_node qhs_qspi = {
 994	.name = "qhs_qspi",
 995	.channels = 1,
 996	.buswidth = 4,
 997	.num_links = 0,
 998};
 999
1000static struct qcom_icc_node qhs_qup0 = {
1001	.name = "qhs_qup0",
1002	.channels = 1,
1003	.buswidth = 4,
1004	.num_links = 0,
1005};
1006
1007static struct qcom_icc_node qhs_qup1 = {
1008	.name = "qhs_qup1",
1009	.channels = 1,
1010	.buswidth = 4,
1011	.num_links = 0,
1012};
1013
1014static struct qcom_icc_node qhs_sdc1 = {
1015	.name = "qhs_sdc1",
1016	.channels = 1,
1017	.buswidth = 4,
1018	.num_links = 0,
1019};
1020
1021static struct qcom_icc_node qhs_sdc2 = {
1022	.name = "qhs_sdc2",
1023	.channels = 1,
1024	.buswidth = 4,
1025	.num_links = 0,
1026};
1027
1028static struct qcom_icc_node qhs_tcsr = {
1029	.name = "qhs_tcsr",
1030	.channels = 1,
1031	.buswidth = 4,
1032	.num_links = 0,
1033};
1034
1035static struct qcom_icc_node qhs_tlmm = {
1036	.name = "qhs_tlmm",
1037	.channels = 1,
1038	.buswidth = 4,
1039	.num_links = 0,
1040};
1041
1042static struct qcom_icc_node qhs_ufs_mem_cfg = {
1043	.name = "qhs_ufs_mem_cfg",
1044	.channels = 1,
1045	.buswidth = 4,
1046	.num_links = 0,
1047};
1048
1049static struct qcom_icc_node qhs_usb3_0 = {
1050	.name = "qhs_usb3_0",
1051	.channels = 1,
1052	.buswidth = 4,
1053	.num_links = 0,
1054};
1055
1056static struct qcom_icc_node qhs_venus_cfg = {
1057	.name = "qhs_venus_cfg",
1058	.channels = 1,
1059	.buswidth = 4,
1060	.num_links = 0,
1061};
1062
1063static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1064	.name = "qhs_vsense_ctrl_cfg",
1065	.channels = 1,
1066	.buswidth = 4,
1067	.num_links = 0,
1068};
1069
1070static struct qcom_icc_node qhs_wlan_q6 = {
1071	.name = "qhs_wlan_q6",
1072	.channels = 1,
1073	.buswidth = 4,
1074	.num_links = 0,
1075};
1076
1077static struct qcom_icc_node qss_mnoc_hf_cfg = {
1078	.name = "qss_mnoc_hf_cfg",
1079	.channels = 1,
1080	.buswidth = 4,
1081	.num_links = 1,
1082	.link_nodes = { &qsm_hf_mnoc_cfg },
1083};
1084
1085static struct qcom_icc_node qss_mnoc_sf_cfg = {
1086	.name = "qss_mnoc_sf_cfg",
1087	.channels = 1,
1088	.buswidth = 4,
1089	.num_links = 1,
1090	.link_nodes = { &qsm_sf_mnoc_cfg },
1091};
1092
1093static struct qcom_icc_node qss_nsp_qtb_cfg = {
1094	.name = "qss_nsp_qtb_cfg",
1095	.channels = 1,
1096	.buswidth = 4,
1097	.num_links = 0,
1098};
1099
1100static struct qcom_icc_node qss_pcie_anoc_cfg = {
1101	.name = "qss_pcie_anoc_cfg",
1102	.channels = 1,
1103	.buswidth = 4,
1104	.num_links = 1,
1105	.link_nodes = { &qsm_pcie_anoc_cfg },
1106};
1107
1108static struct qcom_icc_node qss_wlan_q6_throttle_cfg = {
1109	.name = "qss_wlan_q6_throttle_cfg",
1110	.channels = 1,
1111	.buswidth = 4,
1112	.num_links = 0,
1113};
1114
1115static struct qcom_icc_node srvc_cnoc_cfg = {
1116	.name = "srvc_cnoc_cfg",
1117	.channels = 1,
1118	.buswidth = 4,
1119	.num_links = 0,
1120};
1121
1122static struct qcom_icc_node xs_qdss_stm = {
1123	.name = "xs_qdss_stm",
1124	.channels = 1,
1125	.buswidth = 4,
1126	.num_links = 0,
1127};
1128
1129static struct qcom_icc_node xs_sys_tcu_cfg = {
1130	.name = "xs_sys_tcu_cfg",
1131	.channels = 1,
1132	.buswidth = 8,
1133	.num_links = 0,
1134};
1135
1136static struct qcom_icc_node qhs_aoss = {
1137	.name = "qhs_aoss",
1138	.channels = 1,
1139	.buswidth = 4,
1140	.num_links = 0,
1141};
1142
1143static struct qcom_icc_node qhs_display_cfg = {
1144	.name = "qhs_display_cfg",
1145	.channels = 1,
1146	.buswidth = 4,
1147	.num_links = 0,
1148};
1149
1150static struct qcom_icc_node qhs_ipa = {
1151	.name = "qhs_ipa",
1152	.channels = 1,
1153	.buswidth = 4,
1154	.num_links = 0,
1155};
1156
1157static struct qcom_icc_node qhs_ipc_router = {
1158	.name = "qhs_ipc_router",
1159	.channels = 1,
1160	.buswidth = 4,
1161	.num_links = 0,
1162};
1163
1164static struct qcom_icc_node qhs_pcie0_cfg = {
1165	.name = "qhs_pcie0_cfg",
1166	.channels = 1,
1167	.buswidth = 4,
1168	.num_links = 0,
1169};
1170
1171static struct qcom_icc_node qhs_pcie1_cfg = {
1172	.name = "qhs_pcie1_cfg",
1173	.channels = 1,
1174	.buswidth = 4,
1175	.num_links = 0,
1176};
1177
1178static struct qcom_icc_node qhs_prng = {
1179	.name = "qhs_prng",
1180	.channels = 1,
1181	.buswidth = 4,
1182	.num_links = 0,
1183};
1184
1185static struct qcom_icc_node qhs_tme_cfg = {
1186	.name = "qhs_tme_cfg",
1187	.channels = 1,
1188	.buswidth = 4,
1189	.num_links = 0,
1190};
1191
1192static struct qcom_icc_node qss_apss = {
1193	.name = "qss_apss",
1194	.channels = 1,
1195	.buswidth = 4,
1196	.num_links = 0,
1197};
1198
1199static struct qcom_icc_node qss_cfg = {
1200	.name = "qss_cfg",
1201	.channels = 1,
1202	.buswidth = 4,
1203	.num_links = 1,
1204	.link_nodes = { &qsm_cfg },
1205};
1206
1207static struct qcom_icc_node qss_ddrss_cfg = {
1208	.name = "qss_ddrss_cfg",
1209	.channels = 1,
1210	.buswidth = 4,
1211	.num_links = 0,
1212};
1213
1214static struct qcom_icc_node qxs_imem = {
1215	.name = "qxs_imem",
1216	.channels = 1,
1217	.buswidth = 8,
1218	.num_links = 0,
1219};
1220
1221static struct qcom_icc_node qxs_pimem = {
1222	.name = "qxs_pimem",
1223	.channels = 1,
1224	.buswidth = 8,
1225	.num_links = 0,
1226};
1227
1228static struct qcom_icc_node srvc_cnoc_main = {
1229	.name = "srvc_cnoc_main",
1230	.channels = 1,
1231	.buswidth = 4,
1232	.num_links = 0,
1233};
1234
1235static struct qcom_icc_node xs_pcie_0 = {
1236	.name = "xs_pcie_0",
1237	.channels = 1,
1238	.buswidth = 8,
1239	.num_links = 0,
1240};
1241
1242static struct qcom_icc_node xs_pcie_1 = {
1243	.name = "xs_pcie_1",
1244	.channels = 1,
1245	.buswidth = 8,
1246	.num_links = 0,
1247};
1248
1249static struct qcom_icc_node qns_gem_noc_cnoc = {
1250	.name = "qns_gem_noc_cnoc",
1251	.channels = 1,
1252	.buswidth = 16,
1253	.num_links = 1,
1254	.link_nodes = { &qnm_gemnoc_cnoc },
1255};
1256
1257static struct qcom_icc_node qns_llcc = {
1258	.name = "qns_llcc",
1259	.channels = 2,
1260	.buswidth = 16,
1261	.num_links = 1,
1262	.link_nodes = { &llcc_mc },
1263};
1264
1265static struct qcom_icc_node qns_pcie = {
1266	.name = "qns_pcie",
1267	.channels = 1,
1268	.buswidth = 8,
1269	.num_links = 1,
1270	.link_nodes = { &qnm_gemnoc_pcie },
1271};
1272
1273static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1274	.name = "qns_lpass_ag_noc_gemnoc",
1275	.channels = 1,
1276	.buswidth = 16,
1277	.num_links = 1,
1278	.link_nodes = { &qnm_lpass_gemnoc },
1279};
1280
1281static struct qcom_icc_node ebi = {
1282	.name = "ebi",
1283	.channels = 2,
1284	.buswidth = 4,
1285	.num_links = 0,
1286};
1287
1288static struct qcom_icc_node qns_mem_noc_hf = {
1289	.name = "qns_mem_noc_hf",
1290	.channels = 2,
1291	.buswidth = 32,
1292	.num_links = 1,
1293	.link_nodes = { &qnm_mnoc_hf },
1294};
1295
1296static struct qcom_icc_node qns_mem_noc_sf = {
1297	.name = "qns_mem_noc_sf",
1298	.channels = 2,
1299	.buswidth = 32,
1300	.num_links = 1,
1301	.link_nodes = { &qnm_mnoc_sf },
1302};
1303
1304static struct qcom_icc_node srvc_mnoc_hf = {
1305	.name = "srvc_mnoc_hf",
1306	.channels = 1,
1307	.buswidth = 4,
1308	.num_links = 0,
1309};
1310
1311static struct qcom_icc_node srvc_mnoc_sf = {
1312	.name = "srvc_mnoc_sf",
1313	.channels = 1,
1314	.buswidth = 4,
1315	.num_links = 0,
1316};
1317
1318static struct qcom_icc_node qns_nsp_gemnoc = {
1319	.name = "qns_nsp_gemnoc",
1320	.channels = 2,
1321	.buswidth = 32,
1322	.num_links = 1,
1323	.link_nodes = { &qnm_nsp_gemnoc },
1324};
1325
1326static struct qcom_icc_node qns_pcie_mem_noc = {
1327	.name = "qns_pcie_mem_noc",
1328	.channels = 1,
1329	.buswidth = 8,
1330	.num_links = 1,
1331	.link_nodes = { &qnm_pcie },
1332};
1333
1334static struct qcom_icc_node srvc_pcie_aggre_noc = {
1335	.name = "srvc_pcie_aggre_noc",
1336	.channels = 1,
1337	.buswidth = 4,
1338	.num_links = 0,
1339};
1340
1341static struct qcom_icc_node qns_gemnoc_gc = {
1342	.name = "qns_gemnoc_gc",
1343	.channels = 1,
1344	.buswidth = 8,
1345	.num_links = 1,
1346	.link_nodes = { &qnm_snoc_gc },
1347};
1348
1349static struct qcom_icc_node qns_gemnoc_sf = {
1350	.name = "qns_gemnoc_sf",
1351	.channels = 1,
1352	.buswidth = 16,
1353	.num_links = 1,
1354	.link_nodes = { &qnm_snoc_sf },
1355};
1356
1357static struct qcom_icc_bcm bcm_acv = {
1358	.name = "ACV",
1359	.enable_mask = 0x1,
1360	.num_nodes = 1,
1361	.nodes = { &ebi, },
1362};
1363
1364static struct qcom_icc_bcm bcm_ce0 = {
1365	.name = "CE0",
1366	.num_nodes = 1,
1367	.nodes = { &qxm_crypto },
1368};
1369
1370static struct qcom_icc_bcm bcm_cn0 = {
1371	.name = "CN0",
1372	.enable_mask = 0x1,
1373	.keepalive = true,
1374	.num_nodes = 51,
1375	.nodes = { &qsm_cfg, &qhs_ahb2phy0,
1376		   &qhs_ahb2phy1, &qhs_camera_cfg,
1377		   &qhs_clk_ctl, &qhs_cpr_cx,
1378		   &qhs_cpr_mxa, &qhs_crypto0_cfg,
1379		   &qhs_cx_rdpm, &qhs_gpuss_cfg,
1380		   &qhs_imem_cfg, &qhs_mss_cfg,
1381		   &qhs_mx_2_rdpm, &qhs_mx_rdpm,
1382		   &qhs_pdm, &qhs_qdss_cfg,
1383		   &qhs_qspi, &qhs_sdc1,
1384		   &qhs_sdc2, &qhs_tcsr,
1385		   &qhs_tlmm, &qhs_ufs_mem_cfg,
1386		   &qhs_usb3_0, &qhs_venus_cfg,
1387		   &qhs_vsense_ctrl_cfg, &qhs_wlan_q6,
1388		   &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg,
1389		   &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1390		   &qss_wlan_q6_throttle_cfg, &srvc_cnoc_cfg,
1391		   &xs_qdss_stm, &xs_sys_tcu_cfg,
1392		   &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1393		   &qhs_aoss, &qhs_ipa,
1394		   &qhs_ipc_router, &qhs_pcie0_cfg,
1395		   &qhs_pcie1_cfg, &qhs_prng,
1396		   &qhs_tme_cfg, &qss_apss,
1397		   &qss_cfg, &qss_ddrss_cfg,
1398		   &qxs_imem, &qxs_pimem,
1399		   &srvc_cnoc_main, &xs_pcie_0,
1400		   &xs_pcie_1 },
1401};
1402
1403static struct qcom_icc_bcm bcm_cn1 = {
1404	.name = "CN1",
1405	.num_nodes = 3,
1406	.nodes = { &qhs_qup0, &qhs_qup1,
1407		   &qhs_display_cfg },
1408};
1409
1410static struct qcom_icc_bcm bcm_co0 = {
1411	.name = "CO0",
1412	.enable_mask = 0x1,
1413	.num_nodes = 2,
1414	.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1415};
1416
1417static struct qcom_icc_bcm bcm_mc0 = {
1418	.name = "MC0",
1419	.keepalive = true,
1420	.num_nodes = 1,
1421	.nodes = { &ebi },
1422};
1423
1424static struct qcom_icc_bcm bcm_mm0 = {
1425	.name = "MM0",
1426	.num_nodes = 1,
1427	.nodes = { &qns_mem_noc_hf },
1428};
1429
1430static struct qcom_icc_bcm bcm_mm1 = {
1431	.name = "MM1",
1432	.enable_mask = 0x1,
1433	.num_nodes = 4,
1434	.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1435		   &qnm_camnoc_sf, &qns_mem_noc_sf },
1436};
1437
1438static struct qcom_icc_bcm bcm_qup0 = {
1439	.name = "QUP0",
1440	.keepalive = true,
1441	.vote_scale = 1,
1442	.num_nodes = 1,
1443	.nodes = { &qup0_core_slave },
1444};
1445
1446static struct qcom_icc_bcm bcm_qup1 = {
1447	.name = "QUP1",
1448	.keepalive = true,
1449	.vote_scale = 1,
1450	.num_nodes = 1,
1451	.nodes = { &qup1_core_slave },
1452};
1453
1454static struct qcom_icc_bcm bcm_sh0 = {
1455	.name = "SH0",
1456	.keepalive = true,
1457	.num_nodes = 1,
1458	.nodes = { &qns_llcc },
1459};
1460
1461static struct qcom_icc_bcm bcm_sh1 = {
1462	.name = "SH1",
1463	.enable_mask = 0x1,
1464	.num_nodes = 14,
1465	.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1466		   &chm_apps, &qnm_gpu,
1467		   &qnm_mdsp, &qnm_mnoc_hf,
1468		   &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1469		   &qnm_pcie, &qnm_snoc_gc,
1470		   &qnm_snoc_sf, &qxm_wlan_q6,
1471		   &qns_gem_noc_cnoc, &qns_pcie },
1472};
1473
1474static struct qcom_icc_bcm bcm_sn0 = {
1475	.name = "SN0",
1476	.keepalive = true,
1477	.num_nodes = 2,
1478	.nodes = { &qns_gemnoc_gc, &qns_gemnoc_sf },
1479};
1480
1481static struct qcom_icc_bcm bcm_sn1 = {
1482	.name = "SN1",
1483	.enable_mask = 0x1,
1484	.num_nodes = 1,
1485	.nodes = { &qxm_pimem },
1486};
1487
1488static struct qcom_icc_bcm bcm_sn2 = {
1489	.name = "SN2",
1490	.num_nodes = 1,
1491	.nodes = { &qnm_aggre1_noc },
1492};
1493
1494static struct qcom_icc_bcm bcm_sn3 = {
1495	.name = "SN3",
1496	.num_nodes = 1,
1497	.nodes = { &qnm_aggre2_noc },
1498};
1499
1500static struct qcom_icc_bcm bcm_sn4 = {
1501	.name = "SN4",
1502	.num_nodes = 1,
1503	.nodes = { &qns_pcie_mem_noc },
1504};
1505
1506static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1507	[MASTER_QUP_1] = &qhm_qup1,
1508	[MASTER_UFS_MEM] = &xm_ufs_mem,
1509	[MASTER_USB3_0] = &xm_usb3_0,
1510	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1511};
1512
1513static const struct regmap_config milos_aggre1_noc_regmap_config = {
1514	.reg_bits = 32,
1515	.reg_stride = 4,
1516	.val_bits = 32,
1517	.max_register = 0x16400,
1518	.fast_io = true,
1519};
1520
1521static const struct qcom_icc_desc milos_aggre1_noc = {
1522	.config = &milos_aggre1_noc_regmap_config,
1523	.nodes = aggre1_noc_nodes,
1524	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1525};
1526
1527static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1528	&bcm_ce0,
1529};
1530
1531static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1532	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1533	[MASTER_QSPI_0] = &qhm_qspi,
1534	[MASTER_QUP_0] = &qhm_qup0,
1535	[MASTER_CRYPTO] = &qxm_crypto,
1536	[MASTER_IPA] = &qxm_ipa,
1537	[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1538	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1539	[MASTER_SDCC_1] = &xm_sdc1,
1540	[MASTER_SDCC_2] = &xm_sdc2,
1541	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1542};
1543
1544static const struct regmap_config milos_aggre2_noc_regmap_config = {
1545	.reg_bits = 32,
1546	.reg_stride = 4,
1547	.val_bits = 32,
1548	.max_register = 0x1f400,
1549	.fast_io = true,
1550};
1551
1552static const struct qcom_icc_desc milos_aggre2_noc = {
1553	.config = &milos_aggre2_noc_regmap_config,
1554	.nodes = aggre2_noc_nodes,
1555	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1556	.bcms = aggre2_noc_bcms,
1557	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1558};
1559
1560static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1561	&bcm_qup0,
1562	&bcm_qup1,
1563};
1564
1565static struct qcom_icc_node * const clk_virt_nodes[] = {
1566	[MASTER_QUP_CORE_0] = &qup0_core_master,
1567	[MASTER_QUP_CORE_1] = &qup1_core_master,
1568	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1569	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1570};
1571
1572static const struct qcom_icc_desc milos_clk_virt = {
1573	.nodes = clk_virt_nodes,
1574	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1575	.bcms = clk_virt_bcms,
1576	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1577};
1578
1579static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
1580	&bcm_cn0,
1581	&bcm_cn1,
1582};
1583
1584static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
1585	[MASTER_CNOC_CFG] = &qsm_cfg,
1586	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1587	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1588	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1589	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1590	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1591	[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1592	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1593	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1594	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1595	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1596	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1597	[SLAVE_MX_2_RDPM] = &qhs_mx_2_rdpm,
1598	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1599	[SLAVE_PDM] = &qhs_pdm,
1600	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1601	[SLAVE_QSPI_0] = &qhs_qspi,
1602	[SLAVE_QUP_0] = &qhs_qup0,
1603	[SLAVE_QUP_1] = &qhs_qup1,
1604	[SLAVE_SDC1] = &qhs_sdc1,
1605	[SLAVE_SDCC_2] = &qhs_sdc2,
1606	[SLAVE_TCSR] = &qhs_tcsr,
1607	[SLAVE_TLMM] = &qhs_tlmm,
1608	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1609	[SLAVE_USB3_0] = &qhs_usb3_0,
1610	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1611	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1612	[SLAVE_WLAN] = &qhs_wlan_q6,
1613	[SLAVE_CNOC_MNOC_HF_CFG] = &qss_mnoc_hf_cfg,
1614	[SLAVE_CNOC_MNOC_SF_CFG] = &qss_mnoc_sf_cfg,
1615	[SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1616	[SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1617	[SLAVE_WLAN_Q6_THROTTLE_CFG] = &qss_wlan_q6_throttle_cfg,
1618	[SLAVE_SERVICE_CNOC_CFG] = &srvc_cnoc_cfg,
1619	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1620	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1621};
1622
1623static const struct regmap_config milos_cnoc_cfg_regmap_config = {
1624	.reg_bits = 32,
1625	.reg_stride = 4,
1626	.val_bits = 32,
1627	.max_register = 0x6e00,
1628	.fast_io = true,
1629};
1630
1631static const struct qcom_icc_desc milos_cnoc_cfg = {
1632	.config = &milos_cnoc_cfg_regmap_config,
1633	.nodes = cnoc_cfg_nodes,
1634	.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
1635	.bcms = cnoc_cfg_bcms,
1636	.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
1637};
1638
1639static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1640	&bcm_cn0,
1641	&bcm_cn1,
1642};
1643
1644static struct qcom_icc_node * const cnoc_main_nodes[] = {
1645	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1646	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1647	[SLAVE_AOSS] = &qhs_aoss,
1648	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1649	[SLAVE_IPA_CFG] = &qhs_ipa,
1650	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1651	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1652	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1653	[SLAVE_PRNG] = &qhs_prng,
1654	[SLAVE_TME_CFG] = &qhs_tme_cfg,
1655	[SLAVE_APPSS] = &qss_apss,
1656	[SLAVE_CNOC_CFG] = &qss_cfg,
1657	[SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1658	[SLAVE_IMEM] = &qxs_imem,
1659	[SLAVE_PIMEM] = &qxs_pimem,
1660	[SLAVE_SERVICE_CNOC] = &srvc_cnoc_main,
1661	[SLAVE_PCIE_0] = &xs_pcie_0,
1662	[SLAVE_PCIE_1] = &xs_pcie_1,
1663};
1664
1665static const struct regmap_config milos_cnoc_main_regmap_config = {
1666	.reg_bits = 32,
1667	.reg_stride = 4,
1668	.val_bits = 32,
1669	.max_register = 0x14400,
1670	.fast_io = true,
1671};
1672
1673static const struct qcom_icc_desc milos_cnoc_main = {
1674	.config = &milos_cnoc_main_regmap_config,
1675	.nodes = cnoc_main_nodes,
1676	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1677	.bcms = cnoc_main_bcms,
1678	.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1679};
1680
1681static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1682	&bcm_sh0,
1683	&bcm_sh1,
1684};
1685
1686static struct qcom_icc_node * const gem_noc_nodes[] = {
1687	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1688	[MASTER_SYS_TCU] = &alm_sys_tcu,
1689	[MASTER_APPSS_PROC] = &chm_apps,
1690	[MASTER_GFX3D] = &qnm_gpu,
1691	[MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1692	[MASTER_MSS_PROC] = &qnm_mdsp,
1693	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1694	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1695	[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1696	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1697	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1698	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1699	[MASTER_WLAN_Q6] = &qxm_wlan_q6,
1700	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1701	[SLAVE_LLCC] = &qns_llcc,
1702	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1703};
1704
1705static const struct regmap_config milos_gem_noc_regmap_config = {
1706	.reg_bits = 32,
1707	.reg_stride = 4,
1708	.val_bits = 32,
1709	.max_register = 0xff080,
1710	.fast_io = true,
1711};
1712
1713static const struct qcom_icc_desc milos_gem_noc = {
1714	.config = &milos_gem_noc_regmap_config,
1715	.nodes = gem_noc_nodes,
1716	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1717	.bcms = gem_noc_bcms,
1718	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1719};
1720
1721static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1722	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1723	[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1724};
1725
1726static const struct regmap_config milos_lpass_ag_noc_regmap_config = {
1727	.reg_bits = 32,
1728	.reg_stride = 4,
1729	.val_bits = 32,
1730	.max_register = 0x17200,
1731	.fast_io = true,
1732};
1733
1734static const struct qcom_icc_desc milos_lpass_ag_noc = {
1735	.config = &milos_lpass_ag_noc_regmap_config,
1736	.nodes = lpass_ag_noc_nodes,
1737	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1738};
1739
1740static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1741	&bcm_acv,
1742	&bcm_mc0,
1743};
1744
1745static struct qcom_icc_node * const mc_virt_nodes[] = {
1746	[MASTER_LLCC] = &llcc_mc,
1747	[SLAVE_EBI1] = &ebi,
1748};
1749
1750static const struct qcom_icc_desc milos_mc_virt = {
1751	.nodes = mc_virt_nodes,
1752	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1753	.bcms = mc_virt_bcms,
1754	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1755};
1756
1757static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1758	&bcm_mm0,
1759	&bcm_mm1,
1760};
1761
1762static struct qcom_icc_node * const mmss_noc_nodes[] = {
1763	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1764	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1765	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1766	[MASTER_MDP] = &qnm_mdp,
1767	[MASTER_VIDEO] = &qnm_video,
1768	[MASTER_CNOC_MNOC_HF_CFG] = &qsm_hf_mnoc_cfg,
1769	[MASTER_CNOC_MNOC_SF_CFG] = &qsm_sf_mnoc_cfg,
1770	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1771	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1772	[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
1773	[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
1774};
1775
1776static const struct regmap_config milos_mmss_noc_regmap_config = {
1777	.reg_bits = 32,
1778	.reg_stride = 4,
1779	.val_bits = 32,
1780	.max_register = 0xdb800,
1781	.fast_io = true,
1782};
1783
1784static const struct qcom_icc_desc milos_mmss_noc = {
1785	.config = &milos_mmss_noc_regmap_config,
1786	.nodes = mmss_noc_nodes,
1787	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1788	.bcms = mmss_noc_bcms,
1789	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1790};
1791
1792static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1793	&bcm_co0,
1794};
1795
1796static struct qcom_icc_node * const nsp_noc_nodes[] = {
1797	[MASTER_CDSP_PROC] = &qxm_nsp,
1798	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1799};
1800
1801static const struct regmap_config milos_nsp_noc_regmap_config = {
1802	.reg_bits = 32,
1803	.reg_stride = 4,
1804	.val_bits = 32,
1805	.max_register = 0xe080,
1806	.fast_io = true,
1807};
1808
1809static const struct qcom_icc_desc milos_nsp_noc = {
1810	.config = &milos_nsp_noc_regmap_config,
1811	.nodes = nsp_noc_nodes,
1812	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1813	.bcms = nsp_noc_bcms,
1814	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1815};
1816
1817static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1818	&bcm_sn4,
1819};
1820
1821static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1822	[MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1823	[MASTER_PCIE_0] = &xm_pcie3_0,
1824	[MASTER_PCIE_1] = &xm_pcie3_1,
1825	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1826	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1827};
1828
1829static const struct regmap_config milos_pcie_anoc_regmap_config = {
1830	.reg_bits = 32,
1831	.reg_stride = 4,
1832	.val_bits = 32,
1833	.max_register = 0x12400,
1834	.fast_io = true,
1835};
1836
1837static const struct qcom_icc_desc milos_pcie_anoc = {
1838	.config = &milos_pcie_anoc_regmap_config,
1839	.nodes = pcie_anoc_nodes,
1840	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1841	.bcms = pcie_anoc_bcms,
1842	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1843};
1844
1845static struct qcom_icc_bcm * const system_noc_bcms[] = {
1846	&bcm_sn0,
1847	&bcm_sn1,
1848	&bcm_sn2,
1849	&bcm_sn3,
1850};
1851
1852static struct qcom_icc_node * const system_noc_nodes[] = {
1853	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1854	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1855	[MASTER_APSS_NOC] = &qnm_apss_noc,
1856	[MASTER_CNOC_SNOC] = &qnm_cnoc_data,
1857	[MASTER_PIMEM] = &qxm_pimem,
1858	[MASTER_GIC] = &xm_gic,
1859	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1860	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1861};
1862
1863static const struct regmap_config milos_system_noc_regmap_config = {
1864	.reg_bits = 32,
1865	.reg_stride = 4,
1866	.val_bits = 32,
1867	.max_register = 0x40000,
1868	.fast_io = true,
1869};
1870
1871static const struct qcom_icc_desc milos_system_noc = {
1872	.config = &milos_system_noc_regmap_config,
1873	.nodes = system_noc_nodes,
1874	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1875	.bcms = system_noc_bcms,
1876	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1877};
1878
1879static const struct of_device_id qnoc_of_match[] = {
1880	{ .compatible = "qcom,milos-aggre1-noc", .data = &milos_aggre1_noc },
1881	{ .compatible = "qcom,milos-aggre2-noc", .data = &milos_aggre2_noc },
1882	{ .compatible = "qcom,milos-clk-virt", .data = &milos_clk_virt },
1883	{ .compatible = "qcom,milos-cnoc-cfg", .data = &milos_cnoc_cfg },
1884	{ .compatible = "qcom,milos-cnoc-main", .data = &milos_cnoc_main },
1885	{ .compatible = "qcom,milos-gem-noc", .data = &milos_gem_noc },
1886	{ .compatible = "qcom,milos-lpass-ag-noc", .data = &milos_lpass_ag_noc },
1887	{ .compatible = "qcom,milos-mc-virt", .data = &milos_mc_virt },
1888	{ .compatible = "qcom,milos-mmss-noc", .data = &milos_mmss_noc },
1889	{ .compatible = "qcom,milos-nsp-noc", .data = &milos_nsp_noc },
1890	{ .compatible = "qcom,milos-pcie-anoc", .data = &milos_pcie_anoc },
1891	{ .compatible = "qcom,milos-system-noc", .data = &milos_system_noc },
1892	{ }
1893};
1894MODULE_DEVICE_TABLE(of, qnoc_of_match);
1895
1896static struct platform_driver qnoc_driver = {
1897	.probe = qcom_icc_rpmh_probe,
1898	.remove = qcom_icc_rpmh_remove,
1899	.driver = {
1900		.name = "qnoc-milos",
1901		.of_match_table = qnoc_of_match,
1902		.sync_state = icc_sync_state,
1903	},
1904};
1905
1906static int __init qnoc_driver_init(void)
1907{
1908	return platform_driver_register(&qnoc_driver);
1909}
1910core_initcall(qnoc_driver_init);
1911
1912static void __exit qnoc_driver_exit(void)
1913{
1914	platform_driver_unregister(&qnoc_driver);
1915}
1916module_exit(qnoc_driver_exit);
1917
1918MODULE_DESCRIPTION("Milos NoC driver");
1919MODULE_LICENSE("GPL");