main.c

   1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2/*
   3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
   5 */
   6
   7#include <linux/debugfs.h>
   8#include <linux/highmem.h>
   9#include <linux/module.h>
  10#include <linux/init.h>
  11#include <linux/errno.h>
  12#include <linux/pci.h>
  13#include <linux/dma-mapping.h>
  14#include <linux/slab.h>
  15#include <linux/bitmap.h>
  16#include <linux/log2.h>
  17#include <linux/sched.h>
  18#include <linux/sched/mm.h>
  19#include <linux/sched/task.h>
  20#include <linux/delay.h>
  21#include <rdma/ib_user_verbs.h>
  22#include <rdma/ib_addr.h>
  23#include <rdma/ib_cache.h>
  24#include <linux/mlx5/port.h>
  25#include <linux/mlx5/vport.h>
  26#include <linux/mlx5/fs.h>
  27#include <linux/mlx5/eswitch.h>
  28#include <linux/mlx5/driver.h>
  29#include <linux/list.h>
  30#include <rdma/ib_smi.h>
  31#include <rdma/ib_umem_odp.h>
  32#include <rdma/lag.h>
  33#include <linux/in.h>
  34#include <linux/etherdevice.h>
  35#include "mlx5_ib.h"
  36#include "ib_rep.h"
  37#include "cmd.h"
  38#include "devx.h"
  39#include "dm.h"
  40#include "fs.h"
  41#include "srq.h"
  42#include "qp.h"
  43#include "wr.h"
  44#include "restrack.h"
  45#include "counters.h"
  46#include "umr.h"
  47#include <rdma/uverbs_std_types.h>
  48#include <rdma/uverbs_ioctl.h>
  49#include <rdma/mlx5_user_ioctl_verbs.h>
  50#include <rdma/mlx5_user_ioctl_cmds.h>
  51#include <rdma/ib_ucaps.h>
  52#include "macsec.h"
  53#include "data_direct.h"
  54#include "dmah.h"
  55
  56#define UVERBS_MODULE_NAME mlx5_ib
  57#include <rdma/uverbs_named_ioctl.h>
  58
  59MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  60MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  61MODULE_LICENSE("Dual BSD/GPL");
  62
  63struct mlx5_ib_event_work {
  64	struct work_struct	work;
  65	union {
  66		struct mlx5_ib_dev	      *dev;
  67		struct mlx5_ib_multiport_info *mpi;
  68	};
  69	bool			is_slave;
  70	unsigned int		event;
  71	void			*param;
  72};
  73
  74enum {
  75	MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  76};
  77
  78static struct workqueue_struct *mlx5_ib_event_wq;
  79static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  80static LIST_HEAD(mlx5_ib_dev_list);
  81/*
  82 * This mutex should be held when accessing either of the above lists
  83 */
  84static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  85
  86struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  87{
  88	struct mlx5_ib_dev *dev;
  89
  90	mutex_lock(&mlx5_ib_multiport_mutex);
  91	dev = mpi->ibdev;
  92	mutex_unlock(&mlx5_ib_multiport_mutex);
  93	return dev;
  94}
  95
  96static enum rdma_link_layer
  97mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  98{
  99	switch (port_type_cap) {
 100	case MLX5_CAP_PORT_TYPE_IB:
 101		return IB_LINK_LAYER_INFINIBAND;
 102	case MLX5_CAP_PORT_TYPE_ETH:
 103		return IB_LINK_LAYER_ETHERNET;
 104	default:
 105		return IB_LINK_LAYER_UNSPECIFIED;
 106	}
 107}
 108
 109static enum rdma_link_layer
 110mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
 111{
 112	struct mlx5_ib_dev *dev = to_mdev(device);
 113	int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 114
 115	return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 116}
 117
 118static int get_port_state(struct ib_device *ibdev,
 119			  u32 port_num,
 120			  enum ib_port_state *state)
 121{
 122	struct ib_port_attr attr;
 123	int ret;
 124
 125	memset(&attr, 0, sizeof(attr));
 126	ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 127	if (!ret)
 128		*state = attr.state;
 129	return ret;
 130}
 131
 132static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 133					   struct net_device *ndev,
 134					   struct net_device *upper,
 135					   u32 *port_num)
 136{
 137	struct net_device *rep_ndev;
 138	struct mlx5_ib_port *port;
 139	int i;
 140
 141	for (i = 0; i < dev->num_ports; i++) {
 142		port  = &dev->port[i];
 143		if (!port->rep)
 144			continue;
 145
 146		if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
 147			*port_num = i + 1;
 148			return &port->roce;
 149		}
 150
 151		if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
 152			continue;
 153		rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1);
 154		if (rep_ndev && rep_ndev == ndev) {
 155			dev_put(rep_ndev);
 156			*port_num = i + 1;
 157			return &port->roce;
 158		}
 159
 160		dev_put(rep_ndev);
 161	}
 162
 163	return NULL;
 164}
 165
 166static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev,
 167				   struct net_device *ndev,
 168				   struct net_device *upper,
 169				   struct net_device *ib_ndev)
 170{
 171	if (!dev->ib_active)
 172		return false;
 173
 174	/* Event is about our upper device */
 175	if (upper == ndev)
 176		return true;
 177
 178	/* RDMA device is not in lag and not in switchdev */
 179	if (!dev->is_rep && !upper && ndev == ib_ndev)
 180		return true;
 181
 182	/* RDMA devie is in switchdev */
 183	if (dev->is_rep && ndev == ib_ndev)
 184		return true;
 185
 186	return false;
 187}
 188
 189static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev)
 190{
 191	struct mlx5_ib_port *port;
 192	int i;
 193
 194	for (i = 0; i < ibdev->num_ports; i++) {
 195		port = &ibdev->port[i];
 196		if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) {
 197			return ib_device_get_netdev(&ibdev->ib_dev, i + 1);
 198		}
 199	}
 200
 201	return NULL;
 202}
 203
 204static int mlx5_netdev_event(struct notifier_block *this,
 205			     unsigned long event, void *ptr)
 206{
 207	struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 208	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 209	u32 port_num = roce->native_port_num;
 210	struct net_device *ib_ndev = NULL;
 211	struct mlx5_core_dev *mdev;
 212	struct mlx5_ib_dev *ibdev;
 213
 214	ibdev = roce->dev;
 215	mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 216	if (!mdev)
 217		return NOTIFY_DONE;
 218
 219	switch (event) {
 220	case NETDEV_REGISTER:
 221		/* Should already be registered during the load */
 222		if (ibdev->is_rep)
 223			break;
 224
 225		ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 226		/* Exit if already registered */
 227		if (ib_ndev)
 228			goto put_ndev;
 229
 230		if (ndev->dev.parent == mdev->device)
 231			ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num);
 232		break;
 233
 234	case NETDEV_UNREGISTER:
 235		/* In case of reps, ib device goes away before the netdevs */
 236		if (ibdev->is_rep)
 237			break;
 238		ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 239		if (ib_ndev == ndev)
 240			ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num);
 241		goto put_ndev;
 242
 243	case NETDEV_CHANGE:
 244	case NETDEV_UP:
 245	case NETDEV_DOWN: {
 246		struct net_device *upper = NULL;
 247
 248		if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) &&
 249		    !mlx5_core_mp_enabled(mdev))
 250			return NOTIFY_DONE;
 251
 252		if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) {
 253			struct net_device *lag_ndev;
 254
 255			if(mlx5_lag_is_roce(mdev))
 256				lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1);
 257			else /* sriov lag */
 258				lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev);
 259
 260			if (lag_ndev) {
 261				upper = netdev_master_upper_dev_get(lag_ndev);
 262				dev_put(lag_ndev);
 263			} else {
 264				goto done;
 265			}
 266		}
 267
 268		if (ibdev->is_rep)
 269			roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
 270		if (!roce)
 271			return NOTIFY_DONE;
 272
 273		ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num);
 274
 275		if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) {
 276			struct ib_event ibev = { };
 277			enum ib_port_state port_state;
 278
 279			if (get_port_state(&ibdev->ib_dev, port_num,
 280					   &port_state))
 281				goto put_ndev;
 282
 283			if (roce->last_port_state == port_state)
 284				goto put_ndev;
 285
 286			roce->last_port_state = port_state;
 287			ibev.device = &ibdev->ib_dev;
 288			if (port_state == IB_PORT_DOWN)
 289				ibev.event = IB_EVENT_PORT_ERR;
 290			else if (port_state == IB_PORT_ACTIVE)
 291				ibev.event = IB_EVENT_PORT_ACTIVE;
 292			else
 293				goto put_ndev;
 294
 295			ibev.element.port_num = port_num;
 296			ib_dispatch_event(&ibev);
 297		}
 298		break;
 299	}
 300
 301	default:
 302		break;
 303	}
 304put_ndev:
 305	dev_put(ib_ndev);
 306done:
 307	mlx5_ib_put_native_port_mdev(ibdev, port_num);
 308	return NOTIFY_DONE;
 309}
 310
 311struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 312						   u32 ib_port_num,
 313						   u32 *native_port_num)
 314{
 315	enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 316							  ib_port_num);
 317	struct mlx5_core_dev *mdev = NULL;
 318	struct mlx5_ib_multiport_info *mpi;
 319	struct mlx5_ib_port *port;
 320
 321	if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
 322		if (native_port_num)
 323			*native_port_num = smi_to_native_portnum(ibdev,
 324								 ib_port_num);
 325		return ibdev->mdev;
 326
 327	}
 328
 329	if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 330	    ll != IB_LINK_LAYER_ETHERNET) {
 331		if (native_port_num)
 332			*native_port_num = ib_port_num;
 333		return ibdev->mdev;
 334	}
 335
 336	if (native_port_num)
 337		*native_port_num = 1;
 338
 339	port = &ibdev->port[ib_port_num - 1];
 340	spin_lock(&port->mp.mpi_lock);
 341	mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 342	if (mpi && !mpi->unaffiliate) {
 343		mdev = mpi->mdev;
 344		/* If it's the master no need to refcount, it'll exist
 345		 * as long as the ib_dev exists.
 346		 */
 347		if (!mpi->is_master)
 348			mpi->mdev_refcnt++;
 349	}
 350	spin_unlock(&port->mp.mpi_lock);
 351
 352	return mdev;
 353}
 354
 355void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
 356{
 357	enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 358							  port_num);
 359	struct mlx5_ib_multiport_info *mpi;
 360	struct mlx5_ib_port *port;
 361
 362	if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 363		return;
 364
 365	port = &ibdev->port[port_num - 1];
 366
 367	spin_lock(&port->mp.mpi_lock);
 368	mpi = ibdev->port[port_num - 1].mp.mpi;
 369	if (mpi->is_master)
 370		goto out;
 371
 372	mpi->mdev_refcnt--;
 373	if (mpi->unaffiliate)
 374		complete(&mpi->unref_comp);
 375out:
 376	spin_unlock(&port->mp.mpi_lock);
 377}
 378
 379static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 380					   u16 *active_speed, u8 *active_width)
 381{
 382	switch (eth_proto_oper) {
 383	case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 384	case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 385	case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 386	case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 387		*active_width = IB_WIDTH_1X;
 388		*active_speed = IB_SPEED_SDR;
 389		break;
 390	case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 391	case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 392	case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 393	case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 394	case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 395	case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 396	case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 397		*active_width = IB_WIDTH_1X;
 398		*active_speed = IB_SPEED_QDR;
 399		break;
 400	case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 401	case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 402	case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 403		*active_width = IB_WIDTH_1X;
 404		*active_speed = IB_SPEED_EDR;
 405		break;
 406	case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 407	case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 408	case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 409	case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 410		*active_width = IB_WIDTH_4X;
 411		*active_speed = IB_SPEED_QDR;
 412		break;
 413	case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 414	case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 415	case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 416		*active_width = IB_WIDTH_1X;
 417		*active_speed = IB_SPEED_HDR;
 418		break;
 419	case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 420		*active_width = IB_WIDTH_4X;
 421		*active_speed = IB_SPEED_FDR;
 422		break;
 423	case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 424	case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 425	case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 426	case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 427		*active_width = IB_WIDTH_4X;
 428		*active_speed = IB_SPEED_EDR;
 429		break;
 430	default:
 431		return -EINVAL;
 432	}
 433
 434	return 0;
 435}
 436
 437static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 438					u8 *active_width)
 439{
 440	switch (eth_proto_oper) {
 441	case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 442	case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 443		*active_width = IB_WIDTH_1X;
 444		*active_speed = IB_SPEED_SDR;
 445		break;
 446	case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 447		*active_width = IB_WIDTH_1X;
 448		*active_speed = IB_SPEED_DDR;
 449		break;
 450	case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 451		*active_width = IB_WIDTH_1X;
 452		*active_speed = IB_SPEED_QDR;
 453		break;
 454	case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 455		*active_width = IB_WIDTH_4X;
 456		*active_speed = IB_SPEED_QDR;
 457		break;
 458	case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 459		*active_width = IB_WIDTH_1X;
 460		*active_speed = IB_SPEED_EDR;
 461		break;
 462	case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 463		*active_width = IB_WIDTH_2X;
 464		*active_speed = IB_SPEED_EDR;
 465		break;
 466	case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 467		*active_width = IB_WIDTH_1X;
 468		*active_speed = IB_SPEED_HDR;
 469		break;
 470	case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 471		*active_width = IB_WIDTH_4X;
 472		*active_speed = IB_SPEED_EDR;
 473		break;
 474	case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 475		*active_width = IB_WIDTH_2X;
 476		*active_speed = IB_SPEED_HDR;
 477		break;
 478	case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
 479		*active_width = IB_WIDTH_1X;
 480		*active_speed = IB_SPEED_NDR;
 481		break;
 482	case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 483		*active_width = IB_WIDTH_4X;
 484		*active_speed = IB_SPEED_HDR;
 485		break;
 486	case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
 487		*active_width = IB_WIDTH_2X;
 488		*active_speed = IB_SPEED_NDR;
 489		break;
 490	case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1):
 491		*active_width = IB_WIDTH_1X;
 492		*active_speed = IB_SPEED_XDR;
 493		break;
 494	case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8):
 495		*active_width = IB_WIDTH_8X;
 496		*active_speed = IB_SPEED_HDR;
 497		break;
 498	case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
 499		*active_width = IB_WIDTH_4X;
 500		*active_speed = IB_SPEED_NDR;
 501		break;
 502	case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2):
 503		*active_width = IB_WIDTH_2X;
 504		*active_speed = IB_SPEED_XDR;
 505		break;
 506	case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
 507		*active_width = IB_WIDTH_8X;
 508		*active_speed = IB_SPEED_NDR;
 509		break;
 510	case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4):
 511		*active_width = IB_WIDTH_4X;
 512		*active_speed = IB_SPEED_XDR;
 513		break;
 514	case MLX5E_PROT_MASK(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8):
 515		*active_width = IB_WIDTH_8X;
 516		*active_speed = IB_SPEED_XDR;
 517		break;
 518	default:
 519		return -EINVAL;
 520	}
 521
 522	return 0;
 523}
 524
 525static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 526				    u8 *active_width, bool ext)
 527{
 528	return ext ?
 529		translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 530					     active_width) :
 531		translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 532						active_width);
 533}
 534
 535static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
 536				struct ib_port_attr *props)
 537{
 538	struct mlx5_ib_dev *dev = to_mdev(device);
 539	u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 540	struct mlx5_core_dev *mdev;
 541	struct net_device *ndev, *upper;
 542	enum ib_mtu ndev_ib_mtu;
 543	bool put_mdev = true;
 544	u32 eth_prot_oper;
 545	u32 mdev_port_num;
 546	bool ext;
 547	int err;
 548
 549	mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 550	if (!mdev) {
 551		/* This means the port isn't affiliated yet. Get the
 552		 * info for the master port instead.
 553		 */
 554		put_mdev = false;
 555		mdev = dev->mdev;
 556		mdev_port_num = 1;
 557		port_num = 1;
 558	}
 559
 560	/* Possible bad flows are checked before filling out props so in case
 561	 * of an error it will still be zeroed out.
 562	 * Use native port in case of reps
 563	 */
 564	if (dev->is_rep) {
 565		struct mlx5_eswitch_rep *rep;
 566
 567		rep = dev->port[port_num - 1].rep;
 568		if (rep) {
 569			mdev = mlx5_eswitch_get_core_dev(rep->esw);
 570			WARN_ON(!mdev);
 571		}
 572		mdev_port_num = 1;
 573	}
 574
 575	err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 576				   mdev_port_num, 0);
 577
 578	if (err)
 579		goto out;
 580	ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 581	eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 582
 583	props->active_width     = IB_WIDTH_4X;
 584	props->active_speed     = IB_SPEED_QDR;
 585
 586	translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 587				 &props->active_width, ext);
 588
 589	if (!dev->is_rep && dev->mdev->roce.roce_en) {
 590		u16 qkey_viol_cntr;
 591
 592		props->port_cap_flags |= IB_PORT_CM_SUP;
 593		props->ip_gids = true;
 594		props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
 595						   roce_address_table_size);
 596		mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 597		props->qkey_viol_cntr = qkey_viol_cntr;
 598	}
 599	props->max_mtu          = IB_MTU_4096;
 600	props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 601	props->pkey_tbl_len     = 1;
 602	props->state            = IB_PORT_DOWN;
 603	props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 604
 605	/* If this is a stub query for an unaffiliated port stop here */
 606	if (!put_mdev)
 607		goto out;
 608
 609	ndev = ib_device_get_netdev(device, port_num);
 610	if (!ndev)
 611		goto out;
 612
 613	if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) {
 614		rcu_read_lock();
 615		upper = netdev_master_upper_dev_get_rcu(ndev);
 616		if (upper) {
 617			dev_put(ndev);
 618			ndev = upper;
 619			dev_hold(ndev);
 620		}
 621		rcu_read_unlock();
 622	}
 623
 624	if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 625		props->state      = IB_PORT_ACTIVE;
 626		props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 627	}
 628
 629	ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 630
 631	dev_put(ndev);
 632
 633	props->active_mtu	= min(props->max_mtu, ndev_ib_mtu);
 634out:
 635	if (put_mdev)
 636		mlx5_ib_put_native_port_mdev(dev, port_num);
 637	return err;
 638}
 639
 640int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
 641		  unsigned int index, const union ib_gid *gid,
 642		  const struct ib_gid_attr *attr)
 643{
 644	enum ib_gid_type gid_type;
 645	u16 vlan_id = 0xffff;
 646	u8 roce_version = 0;
 647	u8 roce_l3_type = 0;
 648	u8 mac[ETH_ALEN];
 649	int ret;
 650
 651	gid_type = attr->gid_type;
 652	if (gid) {
 653		ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 654		if (ret)
 655			return ret;
 656	}
 657
 658	switch (gid_type) {
 659	case IB_GID_TYPE_ROCE:
 660		roce_version = MLX5_ROCE_VERSION_1;
 661		break;
 662	case IB_GID_TYPE_ROCE_UDP_ENCAP:
 663		roce_version = MLX5_ROCE_VERSION_2;
 664		if (gid && ipv6_addr_v4mapped((void *)gid))
 665			roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 666		else
 667			roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 668		break;
 669
 670	default:
 671		mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 672	}
 673
 674	return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 675				      roce_l3_type, gid->raw, mac,
 676				      vlan_id < VLAN_CFI_MASK, vlan_id,
 677				      port_num);
 678}
 679
 680static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 681			   __always_unused void **context)
 682{
 683	int ret;
 684
 685	ret = mlx5r_add_gid_macsec_operations(attr);
 686	if (ret)
 687		return ret;
 688
 689	return set_roce_addr(to_mdev(attr->device), attr->port_num,
 690			     attr->index, &attr->gid, attr);
 691}
 692
 693static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 694			   __always_unused void **context)
 695{
 696	int ret;
 697
 698	ret = set_roce_addr(to_mdev(attr->device), attr->port_num,
 699			    attr->index, NULL, attr);
 700	if (ret)
 701		return ret;
 702
 703	mlx5r_del_gid_macsec_operations(attr);
 704	return 0;
 705}
 706
 707__be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 708				   const struct ib_gid_attr *attr)
 709{
 710	if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 711		return 0;
 712
 713	return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 714}
 715
 716static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 717{
 718	if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 719		return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 720	return 0;
 721}
 722
 723enum {
 724	MLX5_VPORT_ACCESS_METHOD_MAD,
 725	MLX5_VPORT_ACCESS_METHOD_HCA,
 726	MLX5_VPORT_ACCESS_METHOD_NIC,
 727};
 728
 729static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 730{
 731	if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 732		return MLX5_VPORT_ACCESS_METHOD_MAD;
 733
 734	if (mlx5_ib_port_link_layer(ibdev, 1) ==
 735	    IB_LINK_LAYER_ETHERNET)
 736		return MLX5_VPORT_ACCESS_METHOD_NIC;
 737
 738	return MLX5_VPORT_ACCESS_METHOD_HCA;
 739}
 740
 741static void get_atomic_caps(struct mlx5_ib_dev *dev,
 742			    u8 atomic_size_qp,
 743			    struct ib_device_attr *props)
 744{
 745	u8 tmp;
 746	u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 747	u8 atomic_req_8B_endianness_mode =
 748		MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 749
 750	/* Check if HW supports 8 bytes standard atomic operations and capable
 751	 * of host endianness respond
 752	 */
 753	tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 754	if (((atomic_operations & tmp) == tmp) &&
 755	    (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 756	    (atomic_req_8B_endianness_mode)) {
 757		props->atomic_cap = IB_ATOMIC_HCA;
 758	} else {
 759		props->atomic_cap = IB_ATOMIC_NONE;
 760	}
 761}
 762
 763static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 764			       struct ib_device_attr *props)
 765{
 766	u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 767
 768	get_atomic_caps(dev, atomic_size_qp, props);
 769}
 770
 771static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 772					__be64 *sys_image_guid)
 773{
 774	struct mlx5_ib_dev *dev = to_mdev(ibdev);
 775	struct mlx5_core_dev *mdev = dev->mdev;
 776	u64 tmp;
 777	int err;
 778
 779	switch (mlx5_get_vport_access_method(ibdev)) {
 780	case MLX5_VPORT_ACCESS_METHOD_MAD:
 781		return mlx5_query_mad_ifc_system_image_guid(ibdev,
 782							    sys_image_guid);
 783
 784	case MLX5_VPORT_ACCESS_METHOD_HCA:
 785		err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 786		break;
 787
 788	case MLX5_VPORT_ACCESS_METHOD_NIC:
 789		err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 790		break;
 791
 792	default:
 793		return -EINVAL;
 794	}
 795
 796	if (!err)
 797		*sys_image_guid = cpu_to_be64(tmp);
 798
 799	return err;
 800
 801}
 802
 803static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 804				u16 *max_pkeys)
 805{
 806	struct mlx5_ib_dev *dev = to_mdev(ibdev);
 807	struct mlx5_core_dev *mdev = dev->mdev;
 808
 809	switch (mlx5_get_vport_access_method(ibdev)) {
 810	case MLX5_VPORT_ACCESS_METHOD_MAD:
 811		return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 812
 813	case MLX5_VPORT_ACCESS_METHOD_HCA:
 814	case MLX5_VPORT_ACCESS_METHOD_NIC:
 815		*max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 816						pkey_table_size));
 817		return 0;
 818
 819	default:
 820		return -EINVAL;
 821	}
 822}
 823
 824static int mlx5_query_vendor_id(struct ib_device *ibdev,
 825				u32 *vendor_id)
 826{
 827	struct mlx5_ib_dev *dev = to_mdev(ibdev);
 828
 829	switch (mlx5_get_vport_access_method(ibdev)) {
 830	case MLX5_VPORT_ACCESS_METHOD_MAD:
 831		return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 832
 833	case MLX5_VPORT_ACCESS_METHOD_HCA:
 834	case MLX5_VPORT_ACCESS_METHOD_NIC:
 835		return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 836
 837	default:
 838		return -EINVAL;
 839	}
 840}
 841
 842static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 843				__be64 *node_guid)
 844{
 845	u64 tmp;
 846	int err;
 847
 848	switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 849	case MLX5_VPORT_ACCESS_METHOD_MAD:
 850		return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 851
 852	case MLX5_VPORT_ACCESS_METHOD_HCA:
 853		err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 854		break;
 855
 856	case MLX5_VPORT_ACCESS_METHOD_NIC:
 857		err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp);
 858		break;
 859
 860	default:
 861		return -EINVAL;
 862	}
 863
 864	if (!err)
 865		*node_guid = cpu_to_be64(tmp);
 866
 867	return err;
 868}
 869
 870struct mlx5_reg_node_desc {
 871	u8	desc[IB_DEVICE_NODE_DESC_MAX];
 872};
 873
 874static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 875{
 876	struct mlx5_reg_node_desc in;
 877
 878	if (mlx5_use_mad_ifc(dev))
 879		return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 880
 881	memset(&in, 0, sizeof(in));
 882
 883	return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 884				    sizeof(struct mlx5_reg_node_desc),
 885				    MLX5_REG_NODE_DESC, 0, 0);
 886}
 887
 888static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev,
 889				struct mlx5_ib_query_device_resp *resp)
 890{
 891	struct mlx5_eswitch *esw = mdev->priv.eswitch;
 892	u16 vport = mlx5_eswitch_manager_vport(mdev);
 893
 894	resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw,
 895								      vport);
 896	resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask();
 897}
 898
 899/*
 900 * Calculate maximum SQ overhead across all QP types.
 901 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT)
 902 * have smaller overhead than the types calculated below,
 903 * so they are implicitly included.
 904 */
 905static u32 mlx5_ib_calc_max_sq_overhead(void)
 906{
 907	u32 max_overhead_xrc, overhead_ud_lso, a, b;
 908
 909	/* XRC_INI */
 910	max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg);
 911	max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg);
 912	a = sizeof(struct mlx5_wqe_atomic_seg) +
 913	    sizeof(struct mlx5_wqe_raddr_seg);
 914	b = sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 915	    sizeof(struct mlx5_mkey_seg) +
 916	    MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD;
 917	max_overhead_xrc += max(a, b);
 918
 919	/* UD with LSO */
 920	overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg);
 921	overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad);
 922	overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg);
 923	overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg);
 924
 925	return max(max_overhead_xrc, overhead_ud_lso);
 926}
 927
 928static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev)
 929{
 930	struct mlx5_core_dev *mdev = dev->mdev;
 931	u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 932	u32 max_wqe_size;
 933	/* max QP overhead + 1 SGE, no inline, no special features */
 934	max_wqe_size = mlx5_ib_calc_max_sq_overhead() +
 935		       sizeof(struct mlx5_wqe_data_seg);
 936
 937	max_wqe_size = roundup_pow_of_two(max_wqe_size);
 938
 939	max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB);
 940
 941	return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size;
 942}
 943
 944static int mlx5_ib_query_device(struct ib_device *ibdev,
 945				struct ib_device_attr *props,
 946				struct ib_udata *uhw)
 947{
 948	size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 949	struct mlx5_ib_dev *dev = to_mdev(ibdev);
 950	struct mlx5_core_dev *mdev = dev->mdev;
 951	int err = -ENOMEM;
 952	int max_sq_desc;
 953	int max_rq_sg;
 954	int max_sq_sg;
 955	u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 956	bool raw_support = !mlx5_core_mp_enabled(mdev);
 957	struct mlx5_ib_query_device_resp resp = {};
 958	size_t resp_len;
 959	u64 max_tso;
 960
 961	resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 962	if (uhw_outlen && uhw_outlen < resp_len)
 963		return -EINVAL;
 964
 965	resp.response_length = resp_len;
 966
 967	if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 968		return -EINVAL;
 969
 970	memset(props, 0, sizeof(*props));
 971	err = mlx5_query_system_image_guid(ibdev,
 972					   &props->sys_image_guid);
 973	if (err)
 974		return err;
 975
 976	props->max_pkeys = dev->pkey_table_len;
 977
 978	err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 979	if (err)
 980		return err;
 981
 982	props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 983		(fw_rev_min(dev->mdev) << 16) |
 984		fw_rev_sub(dev->mdev);
 985	props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 986		IB_DEVICE_PORT_ACTIVE_EVENT		|
 987		IB_DEVICE_SYS_IMAGE_GUID		|
 988		IB_DEVICE_RC_RNR_NAK_GEN;
 989
 990	if (MLX5_CAP_GEN(mdev, pkv))
 991		props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 992	if (MLX5_CAP_GEN(mdev, qkv))
 993		props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 994	if (MLX5_CAP_GEN(mdev, apm))
 995		props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 996	if (MLX5_CAP_GEN(mdev, xrc))
 997		props->device_cap_flags |= IB_DEVICE_XRC;
 998	if (MLX5_CAP_GEN(mdev, imaicl)) {
 999		props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
1000					   IB_DEVICE_MEM_WINDOW_TYPE_2B;
1001		props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002		/* We support 'Gappy' memory registration too */
1003		props->kernel_cap_flags |= IBK_SG_GAPS_REG;
1004	}
1005	/* IB_WR_REG_MR always requires changing the entity size with UMR */
1006	if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1007		props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
1008	if (MLX5_CAP_GEN(mdev, sho)) {
1009		props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
1010		/* At this stage no support for signature handover */
1011		props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
1012				      IB_PROT_T10DIF_TYPE_2 |
1013				      IB_PROT_T10DIF_TYPE_3;
1014		props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
1015				       IB_GUARD_T10DIF_CSUM;
1016	}
1017	if (MLX5_CAP_GEN(mdev, block_lb_mc))
1018		props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
1019
1020	if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
1021		if (MLX5_CAP_ETH(mdev, csum_cap)) {
1022			/* Legacy bit to support old userspace libraries */
1023			props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
1024			props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
1025		}
1026
1027		if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
1028			props->raw_packet_caps |=
1029				IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
1030
1031		if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
1032			max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
1033			if (max_tso) {
1034				resp.tso_caps.max_tso = 1 << max_tso;
1035				resp.tso_caps.supported_qpts |=
1036					1 << IB_QPT_RAW_PACKET;
1037				resp.response_length += sizeof(resp.tso_caps);
1038			}
1039		}
1040
1041		if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
1042			resp.rss_caps.rx_hash_function =
1043						MLX5_RX_HASH_FUNC_TOEPLITZ;
1044			resp.rss_caps.rx_hash_fields_mask =
1045						MLX5_RX_HASH_SRC_IPV4 |
1046						MLX5_RX_HASH_DST_IPV4 |
1047						MLX5_RX_HASH_SRC_IPV6 |
1048						MLX5_RX_HASH_DST_IPV6 |
1049						MLX5_RX_HASH_SRC_PORT_TCP |
1050						MLX5_RX_HASH_DST_PORT_TCP |
1051						MLX5_RX_HASH_SRC_PORT_UDP |
1052						MLX5_RX_HASH_DST_PORT_UDP |
1053						MLX5_RX_HASH_INNER;
1054			resp.response_length += sizeof(resp.rss_caps);
1055		}
1056	} else {
1057		if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
1058			resp.response_length += sizeof(resp.tso_caps);
1059		if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
1060			resp.response_length += sizeof(resp.rss_caps);
1061	}
1062
1063	if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1064		props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
1065		props->kernel_cap_flags |= IBK_UD_TSO;
1066	}
1067
1068	if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
1069	    MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
1070	    raw_support)
1071		props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
1072
1073	if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
1074	    MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
1075		props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
1076
1077	if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1078	    MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
1079	    raw_support) {
1080		/* Legacy bit to support old userspace libraries */
1081		props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
1082		props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
1083	}
1084
1085	if (MLX5_CAP_DEV_MEM(mdev, memic)) {
1086		props->max_dm_size =
1087			MLX5_CAP_DEV_MEM(mdev, max_memic_size);
1088	}
1089
1090	if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
1091		props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
1092
1093	if (MLX5_CAP_GEN(mdev, end_pad))
1094		props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
1095
1096	props->vendor_part_id	   = mdev->pdev->device;
1097	props->hw_ver		   = mdev->pdev->revision;
1098
1099	props->max_mr_size	   = ~0ull;
1100	props->page_size_cap	   = ~(min_page_size - 1);
1101	props->max_qp		   = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
1102	props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev);
1103	max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
1104		     sizeof(struct mlx5_wqe_data_seg);
1105	max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
1106	max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
1107		     sizeof(struct mlx5_wqe_raddr_seg)) /
1108		sizeof(struct mlx5_wqe_data_seg);
1109	props->max_send_sge = max_sq_sg;
1110	props->max_recv_sge = max_rq_sg;
1111	props->max_sge_rd	   = MLX5_MAX_SGE_RD;
1112	props->max_cq		   = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1113	props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1114	props->max_mr		   = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1115	props->max_pd		   = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1116	props->max_qp_rd_atom	   = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1117	props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1118	props->max_srq		   = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1119	props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1120	props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1121	props->max_res_rd_atom	   = props->max_qp_rd_atom * props->max_qp;
1122	props->max_srq_sge	   = max_rq_sg - 1;
1123	props->max_fast_reg_page_list_len =
1124		1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1125	props->max_pi_fast_reg_page_list_len =
1126		props->max_fast_reg_page_list_len / 2;
1127	props->max_sgl_rd =
1128		MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
1129	get_atomic_caps_qp(dev, props);
1130	props->masked_atomic_cap   = IB_ATOMIC_NONE;
1131	props->max_mcast_grp	   = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1132	props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1133	props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1134					   props->max_mcast_grp;
1135	props->max_ah = INT_MAX;
1136	props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1137	props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1138
1139	if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1140		if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1141			props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
1142		props->odp_caps = dev->odp_caps;
1143		if (!uhw) {
1144			/* ODP for kernel QPs is not implemented for receive
1145			 * WQEs and SRQ WQEs
1146			 */
1147			props->odp_caps.per_transport_caps.rc_odp_caps &=
1148				~(IB_ODP_SUPPORT_READ |
1149				  IB_ODP_SUPPORT_SRQ_RECV);
1150			props->odp_caps.per_transport_caps.uc_odp_caps &=
1151				~(IB_ODP_SUPPORT_READ |
1152				  IB_ODP_SUPPORT_SRQ_RECV);
1153			props->odp_caps.per_transport_caps.ud_odp_caps &=
1154				~(IB_ODP_SUPPORT_READ |
1155				  IB_ODP_SUPPORT_SRQ_RECV);
1156			props->odp_caps.per_transport_caps.xrc_odp_caps &=
1157				~(IB_ODP_SUPPORT_READ |
1158				  IB_ODP_SUPPORT_SRQ_RECV);
1159		}
1160	}
1161
1162	if (mlx5_core_is_vf(mdev))
1163		props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1164
1165	if (mlx5_ib_port_link_layer(ibdev, 1) ==
1166	    IB_LINK_LAYER_ETHERNET && raw_support) {
1167		props->rss_caps.max_rwq_indirection_tables =
1168			1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1169		props->rss_caps.max_rwq_indirection_table_size =
1170			1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1171		props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1172		props->max_wq_type_rq =
1173			1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1174	}
1175
1176	if (MLX5_CAP_GEN(mdev, tag_matching)) {
1177		props->tm_caps.max_num_tags =
1178			(1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1179		props->tm_caps.max_ops =
1180			1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1181		props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1182	}
1183
1184	if (MLX5_CAP_GEN(mdev, tag_matching) &&
1185	    MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1186		props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1187		props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1188	}
1189
1190	if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1191		props->cq_caps.max_cq_moderation_count =
1192						MLX5_MAX_CQ_COUNT;
1193		props->cq_caps.max_cq_moderation_period =
1194						MLX5_MAX_CQ_PERIOD;
1195	}
1196
1197	if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1198		resp.response_length += sizeof(resp.cqe_comp_caps);
1199
1200		if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1201			resp.cqe_comp_caps.max_num =
1202				MLX5_CAP_GEN(dev->mdev,
1203					     cqe_compression_max_num);
1204
1205			resp.cqe_comp_caps.supported_format =
1206				MLX5_IB_CQE_RES_FORMAT_HASH |
1207				MLX5_IB_CQE_RES_FORMAT_CSUM;
1208
1209			if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1210				resp.cqe_comp_caps.supported_format |=
1211					MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1212		}
1213	}
1214
1215	if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1216	    raw_support) {
1217		if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1218		    MLX5_CAP_GEN(mdev, qos)) {
1219			resp.packet_pacing_caps.qp_rate_limit_max =
1220				MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1221			resp.packet_pacing_caps.qp_rate_limit_min =
1222				MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1223			resp.packet_pacing_caps.supported_qpts |=
1224				1 << IB_QPT_RAW_PACKET;
1225			if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1226			    MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1227				resp.packet_pacing_caps.cap_flags |=
1228					MLX5_IB_PP_SUPPORT_BURST;
1229		}
1230		resp.response_length += sizeof(resp.packet_pacing_caps);
1231	}
1232
1233	if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1234	    uhw_outlen) {
1235		if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1236			resp.mlx5_ib_support_multi_pkt_send_wqes =
1237				MLX5_IB_ALLOW_MPW;
1238
1239		if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1240			resp.mlx5_ib_support_multi_pkt_send_wqes |=
1241				MLX5_IB_SUPPORT_EMPW;
1242
1243		resp.response_length +=
1244			sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1245	}
1246
1247	if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1248		resp.response_length += sizeof(resp.flags);
1249
1250		if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1251			resp.flags |=
1252				MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1253
1254		if (MLX5_CAP_GEN(mdev, cqe_128_always))
1255			resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1256		if (MLX5_CAP_GEN(mdev, qp_packet_based))
1257			resp.flags |=
1258				MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1259
1260		resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1261
1262		if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) &&
1263		    (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) ||
1264		    MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) ||
1265		    MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) ||
1266		    MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) ||
1267		    MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc)))
1268			resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP;
1269	}
1270
1271	if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1272		resp.response_length += sizeof(resp.sw_parsing_caps);
1273		if (MLX5_CAP_ETH(mdev, swp)) {
1274			resp.sw_parsing_caps.sw_parsing_offloads |=
1275				MLX5_IB_SW_PARSING;
1276
1277			if (MLX5_CAP_ETH(mdev, swp_csum))
1278				resp.sw_parsing_caps.sw_parsing_offloads |=
1279					MLX5_IB_SW_PARSING_CSUM;
1280
1281			if (MLX5_CAP_ETH(mdev, swp_lso))
1282				resp.sw_parsing_caps.sw_parsing_offloads |=
1283					MLX5_IB_SW_PARSING_LSO;
1284
1285			if (resp.sw_parsing_caps.sw_parsing_offloads)
1286				resp.sw_parsing_caps.supported_qpts =
1287					BIT(IB_QPT_RAW_PACKET);
1288		}
1289	}
1290
1291	if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1292	    raw_support) {
1293		resp.response_length += sizeof(resp.striding_rq_caps);
1294		if (MLX5_CAP_GEN(mdev, striding_rq)) {
1295			resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1296				MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1297			resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1298				MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1299			if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1300				resp.striding_rq_caps
1301					.min_single_wqe_log_num_of_strides =
1302					MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1303			else
1304				resp.striding_rq_caps
1305					.min_single_wqe_log_num_of_strides =
1306					MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1307			resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1308				MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1309			resp.striding_rq_caps.supported_qpts =
1310				BIT(IB_QPT_RAW_PACKET);
1311		}
1312	}
1313
1314	if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1315		resp.response_length += sizeof(resp.tunnel_offloads_caps);
1316		if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1317			resp.tunnel_offloads_caps |=
1318				MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1319		if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1320			resp.tunnel_offloads_caps |=
1321				MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1322		if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1323			resp.tunnel_offloads_caps |=
1324				MLX5_IB_TUNNELED_OFFLOADS_GRE;
1325		if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1326			resp.tunnel_offloads_caps |=
1327				MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1328		if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1329			resp.tunnel_offloads_caps |=
1330				MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1331	}
1332
1333	if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1334		resp.response_length += sizeof(resp.dci_streams_caps);
1335
1336		resp.dci_streams_caps.max_log_num_concurent =
1337			MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1338
1339		resp.dci_streams_caps.max_log_num_errored =
1340			MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1341	}
1342
1343	if (offsetofend(typeof(resp), reserved) <= uhw_outlen)
1344		resp.response_length += sizeof(resp.reserved);
1345
1346	if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) {
1347		struct mlx5_eswitch *esw = mdev->priv.eswitch;
1348
1349		resp.response_length += sizeof(resp.reg_c0);
1350
1351		if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS &&
1352		    mlx5_eswitch_vport_match_metadata_enabled(esw))
1353			fill_esw_mgr_reg_c0(mdev, &resp);
1354	}
1355
1356	if (uhw_outlen) {
1357		err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1358
1359		if (err)
1360			return err;
1361	}
1362
1363	return 0;
1364}
1365
1366static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1367				   u8 *ib_width)
1368{
1369	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1370
1371	if (active_width & MLX5_PTYS_WIDTH_1X)
1372		*ib_width = IB_WIDTH_1X;
1373	else if (active_width & MLX5_PTYS_WIDTH_2X)
1374		*ib_width = IB_WIDTH_2X;
1375	else if (active_width & MLX5_PTYS_WIDTH_4X)
1376		*ib_width = IB_WIDTH_4X;
1377	else if (active_width & MLX5_PTYS_WIDTH_8X)
1378		*ib_width = IB_WIDTH_8X;
1379	else if (active_width & MLX5_PTYS_WIDTH_12X)
1380		*ib_width = IB_WIDTH_12X;
1381	else {
1382		mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1383			    active_width);
1384		*ib_width = IB_WIDTH_4X;
1385	}
1386
1387	return;
1388}
1389
1390static int mlx5_mtu_to_ib_mtu(int mtu)
1391{
1392	switch (mtu) {
1393	case 256: return 1;
1394	case 512: return 2;
1395	case 1024: return 3;
1396	case 2048: return 4;
1397	case 4096: return 5;
1398	default:
1399		pr_warn("invalid mtu\n");
1400		return -1;
1401	}
1402}
1403
1404enum ib_max_vl_num {
1405	__IB_MAX_VL_0		= 1,
1406	__IB_MAX_VL_0_1		= 2,
1407	__IB_MAX_VL_0_3		= 3,
1408	__IB_MAX_VL_0_7		= 4,
1409	__IB_MAX_VL_0_14	= 5,
1410};
1411
1412enum mlx5_vl_hw_cap {
1413	MLX5_VL_HW_0	= 1,
1414	MLX5_VL_HW_0_1	= 2,
1415	MLX5_VL_HW_0_2	= 3,
1416	MLX5_VL_HW_0_3	= 4,
1417	MLX5_VL_HW_0_4	= 5,
1418	MLX5_VL_HW_0_5	= 6,
1419	MLX5_VL_HW_0_6	= 7,
1420	MLX5_VL_HW_0_7	= 8,
1421	MLX5_VL_HW_0_14	= 15
1422};
1423
1424static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1425				u8 *max_vl_num)
1426{
1427	switch (vl_hw_cap) {
1428	case MLX5_VL_HW_0:
1429		*max_vl_num = __IB_MAX_VL_0;
1430		break;
1431	case MLX5_VL_HW_0_1:
1432		*max_vl_num = __IB_MAX_VL_0_1;
1433		break;
1434	case MLX5_VL_HW_0_3:
1435		*max_vl_num = __IB_MAX_VL_0_3;
1436		break;
1437	case MLX5_VL_HW_0_7:
1438		*max_vl_num = __IB_MAX_VL_0_7;
1439		break;
1440	case MLX5_VL_HW_0_14:
1441		*max_vl_num = __IB_MAX_VL_0_14;
1442		break;
1443
1444	default:
1445		return -EINVAL;
1446	}
1447
1448	return 0;
1449}
1450
1451static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1452			       struct ib_port_attr *props)
1453{
1454	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455	struct mlx5_core_dev *mdev = dev->mdev;
1456	struct mlx5_hca_vport_context *rep;
1457	u8 vl_hw_cap, plane_index = 0;
1458	u16 max_mtu;
1459	u16 oper_mtu;
1460	int err;
1461	u16 ib_link_width_oper;
1462
1463	rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1464	if (!rep) {
1465		err = -ENOMEM;
1466		goto out;
1467	}
1468
1469	/* props being zeroed by the caller, avoid zeroing it here */
1470
1471	if (ibdev->type == RDMA_DEVICE_TYPE_SMI) {
1472		plane_index = port;
1473		port = smi_to_native_portnum(dev, port);
1474	}
1475
1476	err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1477	if (err)
1478		goto out;
1479
1480	props->lid		= rep->lid;
1481	props->lmc		= rep->lmc;
1482	props->sm_lid		= rep->sm_lid;
1483	props->sm_sl		= rep->sm_sl;
1484	props->state		= rep->vport_state;
1485	props->phys_state	= rep->port_physical_state;
1486
1487	props->port_cap_flags = rep->cap_mask1;
1488	if (dev->num_plane) {
1489		props->port_cap_flags |= IB_PORT_SM_DISABLED;
1490		props->port_cap_flags &= ~IB_PORT_SM;
1491	} else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
1492		props->port_cap_flags &= ~IB_PORT_CM_SUP;
1493
1494	props->gid_tbl_len	= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1495	props->max_msg_sz	= 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1496	props->pkey_tbl_len	= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1497	props->bad_pkey_cntr	= rep->pkey_violation_counter;
1498	props->qkey_viol_cntr	= rep->qkey_violation_counter;
1499	props->subnet_timeout	= rep->subnet_timeout;
1500	props->init_type_reply	= rep->init_type_reply;
1501
1502	if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1503		props->port_cap_flags2 = rep->cap_mask2;
1504
1505	err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1506				      &props->active_speed, port, plane_index);
1507	if (err)
1508		goto out;
1509
1510	translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1511
1512	mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1513
1514	props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1515
1516	mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1517
1518	props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1519
1520	err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1521	if (err)
1522		goto out;
1523
1524	err = translate_max_vl_num(ibdev, vl_hw_cap,
1525				   &props->max_vl_num);
1526out:
1527	kfree(rep);
1528	return err;
1529}
1530
1531int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1532		       struct ib_port_attr *props)
1533{
1534	unsigned int count;
1535	int ret;
1536
1537	switch (mlx5_get_vport_access_method(ibdev)) {
1538	case MLX5_VPORT_ACCESS_METHOD_MAD:
1539		ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1540		break;
1541
1542	case MLX5_VPORT_ACCESS_METHOD_HCA:
1543		ret = mlx5_query_hca_port(ibdev, port, props);
1544		break;
1545
1546	case MLX5_VPORT_ACCESS_METHOD_NIC:
1547		ret = mlx5_query_port_roce(ibdev, port, props);
1548		break;
1549
1550	default:
1551		ret = -EINVAL;
1552	}
1553
1554	if (!ret && props) {
1555		struct mlx5_ib_dev *dev = to_mdev(ibdev);
1556		struct mlx5_core_dev *mdev;
1557		bool put_mdev = true;
1558
1559		mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1560		if (!mdev) {
1561			/* If the port isn't affiliated yet query the master.
1562			 * The master and slave will have the same values.
1563			 */
1564			mdev = dev->mdev;
1565			port = 1;
1566			put_mdev = false;
1567		}
1568		count = mlx5_core_reserved_gids_count(mdev);
1569		if (put_mdev)
1570			mlx5_ib_put_native_port_mdev(dev, port);
1571		props->gid_tbl_len -= count;
1572	}
1573	return ret;
1574}
1575
1576static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1577				  struct ib_port_attr *props)
1578{
1579	return mlx5_query_port_roce(ibdev, port, props);
1580}
1581
1582static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1583				  u16 *pkey)
1584{
1585	/* Default special Pkey for representor device port as per the
1586	 * IB specification 1.3 section 10.9.1.2.
1587	 */
1588	*pkey = 0xffff;
1589	return 0;
1590}
1591
1592static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1593			     union ib_gid *gid)
1594{
1595	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1596	struct mlx5_core_dev *mdev = dev->mdev;
1597
1598	switch (mlx5_get_vport_access_method(ibdev)) {
1599	case MLX5_VPORT_ACCESS_METHOD_MAD:
1600		return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1601
1602	case MLX5_VPORT_ACCESS_METHOD_HCA:
1603		return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1604
1605	default:
1606		return -EINVAL;
1607	}
1608
1609}
1610
1611static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1612				   u16 index, u16 *pkey)
1613{
1614	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1615	struct mlx5_core_dev *mdev;
1616	bool put_mdev = true;
1617	u32 mdev_port_num;
1618	int err;
1619
1620	mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1621	if (!mdev) {
1622		/* The port isn't affiliated yet, get the PKey from the master
1623		 * port. For RoCE the PKey tables will be the same.
1624		 */
1625		put_mdev = false;
1626		mdev = dev->mdev;
1627		mdev_port_num = 1;
1628	}
1629
1630	err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1631					index, pkey);
1632	if (put_mdev)
1633		mlx5_ib_put_native_port_mdev(dev, port);
1634
1635	return err;
1636}
1637
1638static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1639			      u16 *pkey)
1640{
1641	switch (mlx5_get_vport_access_method(ibdev)) {
1642	case MLX5_VPORT_ACCESS_METHOD_MAD:
1643		return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1644
1645	case MLX5_VPORT_ACCESS_METHOD_HCA:
1646	case MLX5_VPORT_ACCESS_METHOD_NIC:
1647		return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1648	default:
1649		return -EINVAL;
1650	}
1651}
1652
1653static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1654				 struct ib_device_modify *props)
1655{
1656	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1657	struct mlx5_reg_node_desc in;
1658	struct mlx5_reg_node_desc out;
1659	int err;
1660
1661	if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1662		return -EOPNOTSUPP;
1663
1664	if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1665		return 0;
1666
1667	/*
1668	 * If possible, pass node desc to FW, so it can generate
1669	 * a 144 trap.  If cmd fails, just ignore.
1670	 */
1671	memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1672	err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1673				   sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1674	if (err)
1675		return err;
1676
1677	memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1678
1679	return err;
1680}
1681
1682static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1683				u32 value)
1684{
1685	struct mlx5_hca_vport_context ctx = {};
1686	struct mlx5_core_dev *mdev;
1687	u32 mdev_port_num;
1688	int err;
1689
1690	mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1691	if (!mdev)
1692		return -ENODEV;
1693
1694	err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1695	if (err)
1696		goto out;
1697
1698	if (~ctx.cap_mask1_perm & mask) {
1699		mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1700			     mask, ctx.cap_mask1_perm);
1701		err = -EINVAL;
1702		goto out;
1703	}
1704
1705	ctx.cap_mask1 = value;
1706	ctx.cap_mask1_perm = mask;
1707	err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1708						 0, &ctx);
1709
1710out:
1711	mlx5_ib_put_native_port_mdev(dev, port_num);
1712
1713	return err;
1714}
1715
1716static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1717			       struct ib_port_modify *props)
1718{
1719	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1720	struct ib_port_attr attr;
1721	u32 tmp;
1722	int err;
1723	u32 change_mask;
1724	u32 value;
1725	bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1726		      IB_LINK_LAYER_INFINIBAND);
1727
1728	/* CM layer calls ib_modify_port() regardless of the link layer. For
1729	 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1730	 */
1731	if (!is_ib)
1732		return 0;
1733
1734	if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1735		change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1736		value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1737		return set_port_caps_atomic(dev, port, change_mask, value);
1738	}
1739
1740	mutex_lock(&dev->cap_mask_mutex);
1741
1742	err = ib_query_port(ibdev, port, &attr);
1743	if (err)
1744		goto out;
1745
1746	tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1747		~props->clr_port_cap_mask;
1748
1749	err = mlx5_set_port_caps(dev->mdev, port, tmp);
1750
1751out:
1752	mutex_unlock(&dev->cap_mask_mutex);
1753	return err;
1754}
1755
1756static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1757{
1758	mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1759		    caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1760}
1761
1762static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1763{
1764	/* Large page with non 4k uar support might limit the dynamic size */
1765	if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1766		return MLX5_MIN_DYN_BFREGS;
1767
1768	return MLX5_MAX_DYN_BFREGS;
1769}
1770
1771static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1772			     struct mlx5_ib_alloc_ucontext_req_v2 *req,
1773			     struct mlx5_bfreg_info *bfregi)
1774{
1775	int uars_per_sys_page;
1776	int bfregs_per_sys_page;
1777	int ref_bfregs = req->total_num_bfregs;
1778
1779	if (req->total_num_bfregs == 0)
1780		return -EINVAL;
1781
1782	BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1783	BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1784
1785	if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1786		return -ENOMEM;
1787
1788	uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1789	bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1790	/* This holds the required static allocation asked by the user */
1791	req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1792	if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1793		return -EINVAL;
1794
1795	bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1796	bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1797	bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1798	bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1799
1800	mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1801		    MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1802		    lib_uar_4k ? "yes" : "no", ref_bfregs,
1803		    req->total_num_bfregs, bfregi->total_num_bfregs,
1804		    bfregi->num_sys_pages);
1805
1806	return 0;
1807}
1808
1809static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1810{
1811	struct mlx5_bfreg_info *bfregi;
1812	int err;
1813	int i;
1814
1815	bfregi = &context->bfregi;
1816	for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1817		err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1818					 context->devx_uid);
1819		if (err)
1820			goto error;
1821
1822		mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1823	}
1824
1825	for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1826		bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1827
1828	return 0;
1829
1830error:
1831	for (--i; i >= 0; i--)
1832		if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1833					 context->devx_uid))
1834			mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1835
1836	return err;
1837}
1838
1839static void deallocate_uars(struct mlx5_ib_dev *dev,
1840			    struct mlx5_ib_ucontext *context)
1841{
1842	struct mlx5_bfreg_info *bfregi;
1843	int i;
1844
1845	bfregi = &context->bfregi;
1846	for (i = 0; i < bfregi->num_sys_pages; i++)
1847		if (i < bfregi->num_static_sys_pages ||
1848		    bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1849			mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1850					     context->devx_uid);
1851}
1852
1853static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master,
1854				struct mlx5_core_dev *slave,
1855				struct mlx5_ib_lb_state *lb_state)
1856{
1857	int err;
1858
1859	err = mlx5_nic_vport_update_local_lb(master, true);
1860	if (err)
1861		return err;
1862
1863	err = mlx5_nic_vport_update_local_lb(slave, true);
1864	if (err)
1865		goto out;
1866
1867	lb_state->force_enable = true;
1868	return 0;
1869
1870out:
1871	mlx5_nic_vport_update_local_lb(master, false);
1872	return err;
1873}
1874
1875static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master,
1876				  struct mlx5_core_dev *slave,
1877				  struct mlx5_ib_lb_state *lb_state)
1878{
1879	mlx5_nic_vport_update_local_lb(slave, false);
1880	mlx5_nic_vport_update_local_lb(master, false);
1881
1882	lb_state->force_enable = false;
1883}
1884
1885int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1886{
1887	int err = 0;
1888
1889	if (dev->lb.force_enable)
1890		return 0;
1891
1892	mutex_lock(&dev->lb.mutex);
1893	if (td)
1894		dev->lb.user_td++;
1895	if (qp)
1896		dev->lb.qps++;
1897
1898	if (dev->lb.user_td == 2 ||
1899	    dev->lb.qps == 1) {
1900		if (!dev->lb.enabled) {
1901			err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1902			dev->lb.enabled = true;
1903		}
1904	}
1905
1906	mutex_unlock(&dev->lb.mutex);
1907
1908	return err;
1909}
1910
1911void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1912{
1913	if (dev->lb.force_enable)
1914		return;
1915
1916	mutex_lock(&dev->lb.mutex);
1917	if (td)
1918		dev->lb.user_td--;
1919	if (qp)
1920		dev->lb.qps--;
1921
1922	if (dev->lb.user_td == 1 &&
1923	    dev->lb.qps == 0) {
1924		if (dev->lb.enabled) {
1925			mlx5_nic_vport_update_local_lb(dev->mdev, false);
1926			dev->lb.enabled = false;
1927		}
1928	}
1929
1930	mutex_unlock(&dev->lb.mutex);
1931}
1932
1933static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1934					  u16 uid)
1935{
1936	int err;
1937
1938	if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1939		return 0;
1940
1941	err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1942	if (err)
1943		return err;
1944
1945	if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1946	    (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1947	     !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1948		return err;
1949
1950	return mlx5_ib_enable_lb(dev, true, false);
1951}
1952
1953static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1954					     u16 uid)
1955{
1956	if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1957		return;
1958
1959	mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1960
1961	if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1962	    (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1963	     !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1964		return;
1965
1966	mlx5_ib_disable_lb(dev, true, false);
1967}
1968
1969static int set_ucontext_resp(struct ib_ucontext *uctx,
1970			     struct mlx5_ib_alloc_ucontext_resp *resp)
1971{
1972	struct ib_device *ibdev = uctx->device;
1973	struct mlx5_ib_dev *dev = to_mdev(ibdev);
1974	struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1975	struct mlx5_bfreg_info *bfregi = &context->bfregi;
1976
1977	if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1978		resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey;
1979		resp->comp_mask |=
1980			MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1981	}
1982
1983	resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1984	if (mlx5_wc_support_get(dev->mdev))
1985		resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1986						      log_bf_reg_size);
1987	resp->cache_line_size = cache_line_size();
1988	resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1989	resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1990	resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1991	resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1992	resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1993	resp->cqe_version = context->cqe_version;
1994	resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1995				MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1996	resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1997					MLX5_CAP_GEN(dev->mdev,
1998						     num_of_uars_per_page) : 1;
1999	resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
2000			bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
2001	resp->num_ports = dev->num_ports;
2002	resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
2003				      MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
2004
2005	if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
2006		mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
2007		resp->eth_min_inline++;
2008	}
2009
2010	if (dev->mdev->clock_info)
2011		resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
2012
2013	/*
2014	 * We don't want to expose information from the PCI bar that is located
2015	 * after 4096 bytes, so if the arch only supports larger pages, let's
2016	 * pretend we don't support reading the HCA's core clock. This is also
2017	 * forced by mmap function.
2018	 */
2019	if (PAGE_SIZE <= 4096) {
2020		resp->comp_mask |=
2021			MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
2022		resp->hca_core_clock_offset =
2023			offsetof(struct mlx5_init_seg,
2024				 internal_timer_h) % PAGE_SIZE;
2025	}
2026
2027	if (MLX5_CAP_GEN(dev->mdev, ece_support))
2028		resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
2029
2030	if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
2031	    rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
2032	    rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
2033		resp->comp_mask |=
2034			MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
2035
2036	resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
2037
2038	if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
2039		resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
2040
2041	resp->comp_mask |=
2042		MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
2043
2044	return 0;
2045}
2046
2047static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps)
2048{
2049	return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) ||
2050	       UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA);
2051}
2052
2053static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
2054				  struct ib_udata *udata)
2055{
2056	struct ib_device *ibdev = uctx->device;
2057	struct mlx5_ib_dev *dev = to_mdev(ibdev);
2058	struct mlx5_ib_alloc_ucontext_req_v2 req = {};
2059	struct mlx5_ib_alloc_ucontext_resp resp = {};
2060	struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2061	struct mlx5_bfreg_info *bfregi;
2062	int ver;
2063	int err;
2064	size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
2065				     max_cqe_version);
2066	bool lib_uar_4k;
2067	bool lib_uar_dyn;
2068
2069	if (!dev->ib_active)
2070		return -EAGAIN;
2071
2072	if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
2073		ver = 0;
2074	else if (udata->inlen >= min_req_v2)
2075		ver = 2;
2076	else
2077		return -EINVAL;
2078
2079	err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
2080	if (err)
2081		return err;
2082
2083	if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
2084		return -EOPNOTSUPP;
2085
2086	if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
2087		return -EOPNOTSUPP;
2088
2089	req.total_num_bfregs = ALIGN(req.total_num_bfregs,
2090				    MLX5_NON_FP_BFREGS_PER_UAR);
2091	if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
2092		return -EINVAL;
2093
2094	if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
2095		err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps);
2096		if (err < 0)
2097			goto out_ctx;
2098		context->devx_uid = err;
2099
2100		if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) {
2101			err = mlx5_cmd_add_privileged_uid(dev->mdev,
2102							  context->devx_uid);
2103			if (err)
2104				goto out_devx;
2105		}
2106	}
2107
2108	lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2109	lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
2110	bfregi = &context->bfregi;
2111
2112	if (lib_uar_dyn) {
2113		bfregi->lib_uar_dyn = lib_uar_dyn;
2114		goto uar_done;
2115	}
2116
2117	/* updates req->total_num_bfregs */
2118	err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
2119	if (err)
2120		goto out_ucap;
2121
2122	mutex_init(&bfregi->lock);
2123	bfregi->lib_uar_4k = lib_uar_4k;
2124	bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
2125				GFP_KERNEL);
2126	if (!bfregi->count) {
2127		err = -ENOMEM;
2128		goto out_ucap;
2129	}
2130
2131	bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
2132				    sizeof(*bfregi->sys_pages),
2133				    GFP_KERNEL);
2134	if (!bfregi->sys_pages) {
2135		err = -ENOMEM;
2136		goto out_count;
2137	}
2138
2139	err = allocate_uars(dev, context);
2140	if (err)
2141		goto out_sys_pages;
2142
2143uar_done:
2144	err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
2145					     context->devx_uid);
2146	if (err)
2147		goto out_uars;
2148
2149	INIT_LIST_HEAD(&context->db_page_list);
2150	mutex_init(&context->db_page_mutex);
2151
2152	context->cqe_version = min_t(__u8,
2153				 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
2154				 req.max_cqe_version);
2155
2156	err = set_ucontext_resp(uctx, &resp);
2157	if (err)
2158		goto out_mdev;
2159
2160	resp.response_length = min(udata->outlen, sizeof(resp));
2161	err = ib_copy_to_udata(udata, &resp, resp.response_length);
2162	if (err)
2163		goto out_mdev;
2164
2165	bfregi->ver = ver;
2166	bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
2167	context->lib_caps = req.lib_caps;
2168	print_lib_caps(dev, context->lib_caps);
2169
2170	if (mlx5_ib_lag_should_assign_affinity(dev)) {
2171		u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
2172
2173		atomic_set(&context->tx_port_affinity,
2174			   atomic_add_return(
2175				   1, &dev->port[port].roce.tx_port_affinity));
2176	}
2177
2178	return 0;
2179
2180out_mdev:
2181	mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2182
2183out_uars:
2184	deallocate_uars(dev, context);
2185
2186out_sys_pages:
2187	kfree(bfregi->sys_pages);
2188
2189out_count:
2190	kfree(bfregi->count);
2191
2192out_ucap:
2193	if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX &&
2194	    uctx_rdma_ctrl_is_enabled(uctx->enabled_caps))
2195		mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid);
2196
2197out_devx:
2198	if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
2199		mlx5_ib_devx_destroy(dev, context->devx_uid);
2200
2201out_ctx:
2202	return err;
2203}
2204
2205static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
2206				  struct uverbs_attr_bundle *attrs)
2207{
2208	struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
2209	int ret;
2210
2211	ret = set_ucontext_resp(ibcontext, &uctx_resp);
2212	if (ret)
2213		return ret;
2214
2215	uctx_resp.response_length =
2216		min_t(size_t,
2217		      uverbs_attr_get_len(attrs,
2218				MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
2219		      sizeof(uctx_resp));
2220
2221	ret = uverbs_copy_to_struct_or_zero(attrs,
2222					MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2223					&uctx_resp,
2224					sizeof(uctx_resp));
2225	return ret;
2226}
2227
2228static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2229{
2230	struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2231	struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2232	struct mlx5_bfreg_info *bfregi;
2233
2234	bfregi = &context->bfregi;
2235	mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2236
2237	deallocate_uars(dev, context);
2238	kfree(bfregi->sys_pages);
2239	kfree(bfregi->count);
2240
2241	if (context->devx_uid) {
2242		if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps))
2243			mlx5_cmd_remove_privileged_uid(dev->mdev,
2244						       context->devx_uid);
2245		mlx5_ib_devx_destroy(dev, context->devx_uid);
2246	}
2247}
2248
2249static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2250				 int uar_idx)
2251{
2252	int fw_uars_per_page;
2253
2254	fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2255
2256	return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2257}
2258
2259static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2260				 int uar_idx)
2261{
2262	unsigned int fw_uars_per_page;
2263
2264	fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2265				MLX5_UARS_IN_PAGE : 1;
2266
2267	return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2268}
2269
2270static int get_command(unsigned long offset)
2271{
2272	return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2273}
2274
2275static int get_arg(unsigned long offset)
2276{
2277	return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2278}
2279
2280static int get_index(unsigned long offset)
2281{
2282	return get_arg(offset);
2283}
2284
2285/* Index resides in an extra byte to enable larger values than 255 */
2286static int get_extended_index(unsigned long offset)
2287{
2288	return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2289}
2290
2291
2292static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2293{
2294}
2295
2296static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2297{
2298	switch (cmd) {
2299	case MLX5_IB_MMAP_WC_PAGE:
2300		return "WC";
2301	case MLX5_IB_MMAP_REGULAR_PAGE:
2302		return "best effort WC";
2303	case MLX5_IB_MMAP_NC_PAGE:
2304		return "NC";
2305	case MLX5_IB_MMAP_DEVICE_MEM:
2306		return "Device Memory";
2307	default:
2308		return "Unknown";
2309	}
2310}
2311
2312static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2313					struct vm_area_struct *vma,
2314					struct mlx5_ib_ucontext *context)
2315{
2316	if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2317	    !(vma->vm_flags & VM_SHARED))
2318		return -EINVAL;
2319
2320	if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2321		return -EOPNOTSUPP;
2322
2323	if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2324		return -EPERM;
2325	vm_flags_clear(vma, VM_MAYWRITE);
2326
2327	if (!dev->mdev->clock_info)
2328		return -EOPNOTSUPP;
2329
2330	return vm_insert_page(vma, vma->vm_start,
2331			      virt_to_page(dev->mdev->clock_info));
2332}
2333
2334static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2335{
2336	struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2337	struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2338	struct mlx5_var_table *var_table = &dev->var_table;
2339	struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
2340
2341	switch (mentry->mmap_flag) {
2342	case MLX5_IB_MMAP_TYPE_MEMIC:
2343	case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2344		mlx5_ib_dm_mmap_free(dev, mentry);
2345		break;
2346	case MLX5_IB_MMAP_TYPE_VAR:
2347		mutex_lock(&var_table->bitmap_lock);
2348		clear_bit(mentry->page_idx, var_table->bitmap);
2349		mutex_unlock(&var_table->bitmap_lock);
2350		kfree(mentry);
2351		break;
2352	case MLX5_IB_MMAP_TYPE_UAR_WC:
2353	case MLX5_IB_MMAP_TYPE_UAR_NC:
2354		mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2355				     context->devx_uid);
2356		kfree(mentry);
2357		break;
2358	default:
2359		WARN_ON(true);
2360	}
2361}
2362
2363static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2364		    struct vm_area_struct *vma,
2365		    struct mlx5_ib_ucontext *context)
2366{
2367	struct mlx5_bfreg_info *bfregi = &context->bfregi;
2368	int err;
2369	unsigned long idx;
2370	phys_addr_t pfn;
2371	pgprot_t prot;
2372	u32 bfreg_dyn_idx = 0;
2373	u32 uar_index;
2374	int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2375	int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2376				bfregi->num_static_sys_pages;
2377
2378	if (bfregi->lib_uar_dyn)
2379		return -EINVAL;
2380
2381	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2382		return -EINVAL;
2383
2384	if (dyn_uar)
2385		idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2386	else
2387		idx = get_index(vma->vm_pgoff);
2388
2389	if (idx >= max_valid_idx) {
2390		mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2391			     idx, max_valid_idx);
2392		return -EINVAL;
2393	}
2394
2395	switch (cmd) {
2396	case MLX5_IB_MMAP_WC_PAGE:
2397	case MLX5_IB_MMAP_ALLOC_WC:
2398	case MLX5_IB_MMAP_REGULAR_PAGE:
2399		/* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2400		prot = pgprot_writecombine(vma->vm_page_prot);
2401		break;
2402	case MLX5_IB_MMAP_NC_PAGE:
2403		prot = pgprot_noncached(vma->vm_page_prot);
2404		break;
2405	default:
2406		return -EINVAL;
2407	}
2408
2409	if (dyn_uar) {
2410		int uars_per_page;
2411
2412		uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2413		bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2414		if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2415			mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2416				     bfreg_dyn_idx, bfregi->total_num_bfregs);
2417			return -EINVAL;
2418		}
2419
2420		mutex_lock(&bfregi->lock);
2421		/* Fail if uar already allocated, first bfreg index of each
2422		 * page holds its count.
2423		 */
2424		if (bfregi->count[bfreg_dyn_idx]) {
2425			mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2426			mutex_unlock(&bfregi->lock);
2427			return -EINVAL;
2428		}
2429
2430		bfregi->count[bfreg_dyn_idx]++;
2431		mutex_unlock(&bfregi->lock);
2432
2433		err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2434					 context->devx_uid);
2435		if (err) {
2436			mlx5_ib_warn(dev, "UAR alloc failed\n");
2437			goto free_bfreg;
2438		}
2439	} else {
2440		uar_index = bfregi->sys_pages[idx];
2441	}
2442
2443	pfn = uar_index2pfn(dev, uar_index);
2444	mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2445
2446	err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2447				prot, NULL);
2448	if (err) {
2449		mlx5_ib_err(dev,
2450			    "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2451			    err, mmap_cmd2str(cmd));
2452		goto err;
2453	}
2454
2455	if (dyn_uar)
2456		bfregi->sys_pages[idx] = uar_index;
2457	return 0;
2458
2459err:
2460	if (!dyn_uar)
2461		return err;
2462
2463	mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
2464
2465free_bfreg:
2466	mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2467
2468	return err;
2469}
2470
2471static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2472{
2473	unsigned long idx;
2474	u8 command;
2475
2476	command = get_command(vma->vm_pgoff);
2477	idx = get_extended_index(vma->vm_pgoff);
2478
2479	return (command << 16 | idx);
2480}
2481
2482static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2483			       struct vm_area_struct *vma,
2484			       struct ib_ucontext *ucontext)
2485{
2486	struct mlx5_user_mmap_entry *mentry;
2487	struct rdma_user_mmap_entry *entry;
2488	unsigned long pgoff;
2489	pgprot_t prot;
2490	phys_addr_t pfn;
2491	int ret;
2492
2493	pgoff = mlx5_vma_to_pgoff(vma);
2494	entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2495	if (!entry)
2496		return -EINVAL;
2497
2498	mentry = to_mmmap(entry);
2499	pfn = (mentry->address >> PAGE_SHIFT);
2500	if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2501	    mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2502		prot = pgprot_noncached(vma->vm_page_prot);
2503	else
2504		prot = pgprot_writecombine(vma->vm_page_prot);
2505	ret = rdma_user_mmap_io(ucontext, vma, pfn,
2506				entry->npages * PAGE_SIZE,
2507				prot,
2508				entry);
2509	rdma_user_mmap_entry_put(&mentry->rdma_entry);
2510	return ret;
2511}
2512
2513static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2514{
2515	u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2516	u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2517
2518	return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2519		(index & 0xFF)) << PAGE_SHIFT;
2520}
2521
2522static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2523{
2524	struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2525	struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2526	unsigned long command;
2527	phys_addr_t pfn;
2528
2529	command = get_command(vma->vm_pgoff);
2530	switch (command) {
2531	case MLX5_IB_MMAP_WC_PAGE:
2532	case MLX5_IB_MMAP_ALLOC_WC:
2533		if (!mlx5_wc_support_get(dev->mdev))
2534			return -EPERM;
2535		fallthrough;
2536	case MLX5_IB_MMAP_NC_PAGE:
2537	case MLX5_IB_MMAP_REGULAR_PAGE:
2538		return uar_mmap(dev, command, vma, context);
2539
2540	case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2541		return -ENOSYS;
2542
2543	case MLX5_IB_MMAP_CORE_CLOCK:
2544		if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2545			return -EINVAL;
2546
2547		if (vma->vm_flags & VM_WRITE)
2548			return -EPERM;
2549		vm_flags_clear(vma, VM_MAYWRITE);
2550
2551		/* Don't expose to user-space information it shouldn't have */
2552		if (PAGE_SIZE > 4096)
2553			return -EOPNOTSUPP;
2554
2555		pfn = (dev->mdev->iseg_base +
2556		       offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2557			PAGE_SHIFT;
2558		return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2559					 PAGE_SIZE,
2560					 pgprot_noncached(vma->vm_page_prot),
2561					 NULL);
2562	case MLX5_IB_MMAP_CLOCK_INFO:
2563		return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2564
2565	default:
2566		return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2567	}
2568
2569	return 0;
2570}
2571
2572static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2573{
2574	struct mlx5_ib_pd *pd = to_mpd(ibpd);
2575	struct ib_device *ibdev = ibpd->device;
2576	struct mlx5_ib_alloc_pd_resp resp;
2577	int err;
2578	u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2579	u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2580	u16 uid = 0;
2581	struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2582		udata, struct mlx5_ib_ucontext, ibucontext);
2583
2584	uid = context ? context->devx_uid : 0;
2585	MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2586	MLX5_SET(alloc_pd_in, in, uid, uid);
2587	err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2588	if (err)
2589		return err;
2590
2591	pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2592	pd->uid = uid;
2593	if (udata) {
2594		resp.pdn = pd->pdn;
2595		if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2596			mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2597			return -EFAULT;
2598		}
2599	}
2600
2601	return 0;
2602}
2603
2604static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2605{
2606	struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2607	struct mlx5_ib_pd *mpd = to_mpd(pd);
2608
2609	return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2610}
2611
2612static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2613{
2614	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2615	struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2616	int err;
2617	u16 uid;
2618
2619	uid = ibqp->pd ?
2620		to_mpd(ibqp->pd)->uid : 0;
2621
2622	if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2623		mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2624		return -EOPNOTSUPP;
2625	}
2626
2627	err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2628	if (err)
2629		mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2630			     ibqp->qp_num, gid->raw);
2631
2632	return err;
2633}
2634
2635static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2636{
2637	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2638	int err;
2639	u16 uid;
2640
2641	uid = ibqp->pd ?
2642		to_mpd(ibqp->pd)->uid : 0;
2643	err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2644	if (err)
2645		mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2646			     ibqp->qp_num, gid->raw);
2647
2648	return err;
2649}
2650
2651static int init_node_data(struct mlx5_ib_dev *dev)
2652{
2653	int err;
2654
2655	err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2656	if (err)
2657		return err;
2658
2659	dev->mdev->rev_id = dev->mdev->pdev->revision;
2660
2661	return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2662}
2663
2664static ssize_t fw_pages_show(struct device *device,
2665			     struct device_attribute *attr, char *buf)
2666{
2667	struct mlx5_ib_dev *dev =
2668		rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2669
2670	return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2671}
2672static DEVICE_ATTR_RO(fw_pages);
2673
2674static ssize_t reg_pages_show(struct device *device,
2675			      struct device_attribute *attr, char *buf)
2676{
2677	struct mlx5_ib_dev *dev =
2678		rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2679
2680	return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2681}
2682static DEVICE_ATTR_RO(reg_pages);
2683
2684static ssize_t hca_type_show(struct device *device,
2685			     struct device_attribute *attr, char *buf)
2686{
2687	struct mlx5_ib_dev *dev =
2688		rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2689
2690	return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2691}
2692static DEVICE_ATTR_RO(hca_type);
2693
2694static ssize_t hw_rev_show(struct device *device,
2695			   struct device_attribute *attr, char *buf)
2696{
2697	struct mlx5_ib_dev *dev =
2698		rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2699
2700	return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2701}
2702static DEVICE_ATTR_RO(hw_rev);
2703
2704static ssize_t board_id_show(struct device *device,
2705			     struct device_attribute *attr, char *buf)
2706{
2707	struct mlx5_ib_dev *dev =
2708		rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2709
2710	return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2711			  dev->mdev->board_id);
2712}
2713static DEVICE_ATTR_RO(board_id);
2714
2715static struct attribute *mlx5_class_attributes[] = {
2716	&dev_attr_hw_rev.attr,
2717	&dev_attr_hca_type.attr,
2718	&dev_attr_board_id.attr,
2719	&dev_attr_fw_pages.attr,
2720	&dev_attr_reg_pages.attr,
2721	NULL,
2722};
2723
2724static const struct attribute_group mlx5_attr_group = {
2725	.attrs = mlx5_class_attributes,
2726};
2727
2728static void pkey_change_handler(struct work_struct *work)
2729{
2730	struct mlx5_ib_port_resources *ports =
2731		container_of(work, struct mlx5_ib_port_resources,
2732			     pkey_change_work);
2733
2734	if (!ports->gsi)
2735		/*
2736		 * We got this event before device was fully configured
2737		 * and MAD registration code wasn't called/finished yet.
2738		 */
2739		return;
2740
2741	mlx5_ib_gsi_pkey_change(ports->gsi);
2742}
2743
2744static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2745{
2746	struct mlx5_ib_qp *mqp;
2747	struct mlx5_ib_cq *send_mcq, *recv_mcq;
2748	struct mlx5_core_cq *mcq;
2749	struct list_head cq_armed_list;
2750	unsigned long flags_qp;
2751	unsigned long flags_cq;
2752	unsigned long flags;
2753
2754	INIT_LIST_HEAD(&cq_armed_list);
2755
2756	/* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2757	spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2758	list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2759		spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2760		if (mqp->sq.tail != mqp->sq.head) {
2761			send_mcq = to_mcq(mqp->ibqp.send_cq);
2762			spin_lock_irqsave(&send_mcq->lock, flags_cq);
2763			if (send_mcq->mcq.comp &&
2764			    mqp->ibqp.send_cq->comp_handler) {
2765				if (!send_mcq->mcq.reset_notify_added) {
2766					send_mcq->mcq.reset_notify_added = 1;
2767					list_add_tail(&send_mcq->mcq.reset_notify,
2768						      &cq_armed_list);
2769				}
2770			}
2771			spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2772		}
2773		spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2774		spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2775		/* no handling is needed for SRQ */
2776		if (!mqp->ibqp.srq) {
2777			if (mqp->rq.tail != mqp->rq.head) {
2778				recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2779				spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2780				if (recv_mcq->mcq.comp &&
2781				    mqp->ibqp.recv_cq->comp_handler) {
2782					if (!recv_mcq->mcq.reset_notify_added) {
2783						recv_mcq->mcq.reset_notify_added = 1;
2784						list_add_tail(&recv_mcq->mcq.reset_notify,
2785							      &cq_armed_list);
2786					}
2787				}
2788				spin_unlock_irqrestore(&recv_mcq->lock,
2789						       flags_cq);
2790			}
2791		}
2792		spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2793	}
2794	/*At that point all inflight post send were put to be executed as of we
2795	 * lock/unlock above locks Now need to arm all involved CQs.
2796	 */
2797	list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2798		mcq->comp(mcq, NULL);
2799	}
2800	spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2801}
2802
2803static void delay_drop_handler(struct work_struct *work)
2804{
2805	int err;
2806	struct mlx5_ib_delay_drop *delay_drop =
2807		container_of(work, struct mlx5_ib_delay_drop,
2808			     delay_drop_work);
2809
2810	atomic_inc(&delay_drop->events_cnt);
2811
2812	mutex_lock(&delay_drop->lock);
2813	err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2814	if (err) {
2815		mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2816			     delay_drop->timeout);
2817		delay_drop->activate = false;
2818	}
2819	mutex_unlock(&delay_drop->lock);
2820}
2821
2822static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2823				 struct ib_event *ibev)
2824{
2825	u32 port = (eqe->data.port.port >> 4) & 0xf;
2826
2827	switch (eqe->sub_type) {
2828	case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2829		if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2830					    IB_LINK_LAYER_ETHERNET)
2831			schedule_work(&ibdev->delay_drop.delay_drop_work);
2832		break;
2833	default: /* do nothing */
2834		return;
2835	}
2836}
2837
2838static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2839			      struct ib_event *ibev)
2840{
2841	u32 port = (eqe->data.port.port >> 4) & 0xf;
2842
2843	ibev->element.port_num = port;
2844
2845	switch (eqe->sub_type) {
2846	case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2847	case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2848	case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2849		/* In RoCE, port up/down events are handled in
2850		 * mlx5_netdev_event().
2851		 */
2852		if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2853					    IB_LINK_LAYER_ETHERNET)
2854			return -EINVAL;
2855
2856		ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2857				IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2858		break;
2859
2860	case MLX5_PORT_CHANGE_SUBTYPE_LID:
2861		ibev->event = IB_EVENT_LID_CHANGE;
2862		break;
2863
2864	case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2865		ibev->event = IB_EVENT_PKEY_CHANGE;
2866		schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2867		break;
2868
2869	case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2870		ibev->event = IB_EVENT_GID_CHANGE;
2871		break;
2872
2873	case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2874		ibev->event = IB_EVENT_CLIENT_REREGISTER;
2875		break;
2876	default:
2877		return -EINVAL;
2878	}
2879
2880	return 0;
2881}
2882
2883static void mlx5_ib_handle_event(struct work_struct *_work)
2884{
2885	struct mlx5_ib_event_work *work =
2886		container_of(_work, struct mlx5_ib_event_work, work);
2887	struct mlx5_ib_dev *ibdev;
2888	struct ib_event ibev;
2889
2890	if (work->is_slave) {
2891		ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2892		if (!ibdev)
2893			goto out;
2894	} else {
2895		ibdev = work->dev;
2896	}
2897
2898	switch (work->event) {
2899	case MLX5_EVENT_TYPE_PORT_CHANGE:
2900		if (handle_port_change(ibdev, work->param, &ibev))
2901			goto out;
2902		break;
2903	case MLX5_EVENT_TYPE_GENERAL_EVENT:
2904		handle_general_event(ibdev, work->param, &ibev);
2905		fallthrough;
2906	default:
2907		goto out;
2908	}
2909
2910	ibev.device = &ibdev->ib_dev;
2911
2912	if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2913		mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2914		goto out;
2915	}
2916
2917	if (ibdev->ib_active)
2918		ib_dispatch_event(&ibev);
2919
2920out:
2921	kfree(work);
2922}
2923
2924static int mlx5_ib_event(struct notifier_block *nb,
2925			 unsigned long event, void *param)
2926{
2927	struct mlx5_ib_event_work *work;
2928
2929	work = kmalloc(sizeof(*work), GFP_ATOMIC);
2930	if (!work)
2931		return NOTIFY_DONE;
2932
2933	INIT_WORK(&work->work, mlx5_ib_handle_event);
2934	work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2935	work->is_slave = false;
2936	work->param = param;
2937	work->event = event;
2938
2939	queue_work(mlx5_ib_event_wq, &work->work);
2940
2941	return NOTIFY_OK;
2942}
2943
2944static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2945				    unsigned long event, void *param)
2946{
2947	struct mlx5_ib_event_work *work;
2948
2949	work = kmalloc(sizeof(*work), GFP_ATOMIC);
2950	if (!work)
2951		return NOTIFY_DONE;
2952
2953	INIT_WORK(&work->work, mlx5_ib_handle_event);
2954	work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2955	work->is_slave = true;
2956	work->param = param;
2957	work->event = event;
2958	queue_work(mlx5_ib_event_wq, &work->work);
2959
2960	return NOTIFY_OK;
2961}
2962
2963static void mlx5_ib_handle_sys_error_event(struct work_struct *_work)
2964{
2965	struct mlx5_ib_event_work *work =
2966		container_of(_work, struct mlx5_ib_event_work, work);
2967	struct mlx5_ib_dev *ibdev = work->dev;
2968	struct ib_event ibev;
2969
2970	ibev.event = IB_EVENT_DEVICE_FATAL;
2971	mlx5_ib_handle_internal_error(ibdev);
2972	ibev.element.port_num = (u8)(unsigned long)work->param;
2973	ibev.device = &ibdev->ib_dev;
2974
2975	if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2976		mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2977		goto out;
2978	}
2979
2980	if (ibdev->ib_active)
2981		ib_dispatch_event(&ibev);
2982
2983	ibdev->ib_active = false;
2984out:
2985	kfree(work);
2986}
2987
2988static int mlx5_ib_sys_error_event(struct notifier_block *nb,
2989				   unsigned long event, void *param)
2990{
2991	struct mlx5_ib_event_work *work;
2992
2993	if (event != MLX5_DEV_EVENT_SYS_ERROR)
2994		return NOTIFY_DONE;
2995
2996	work = kmalloc(sizeof(*work), GFP_ATOMIC);
2997	if (!work)
2998		return NOTIFY_DONE;
2999
3000	INIT_WORK(&work->work, mlx5_ib_handle_sys_error_event);
3001	work->dev = container_of(nb, struct mlx5_ib_dev, sys_error_events);
3002	work->is_slave = false;
3003	work->param = param;
3004	work->event = event;
3005
3006	queue_work(mlx5_ib_event_wq, &work->work);
3007
3008	return NOTIFY_OK;
3009}
3010
3011static int mlx5_ib_stage_sys_error_notifier_init(struct mlx5_ib_dev *dev)
3012{
3013	dev->sys_error_events.notifier_call = mlx5_ib_sys_error_event;
3014	mlx5_notifier_register(dev->mdev, &dev->sys_error_events);
3015	return 0;
3016}
3017
3018static void mlx5_ib_stage_sys_error_notifier_cleanup(struct mlx5_ib_dev *dev)
3019{
3020	mlx5_notifier_unregister(dev->mdev, &dev->sys_error_events);
3021}
3022
3023static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane)
3024{
3025	struct mlx5_hca_vport_context vport_ctx;
3026	int err;
3027
3028	*num_plane = 0;
3029	if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane))
3030		return 0;
3031
3032	err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx);
3033	if (err)
3034		return err;
3035
3036	*num_plane = vport_ctx.num_plane;
3037	return 0;
3038}
3039
3040static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3041{
3042	struct mlx5_hca_vport_context vport_ctx;
3043	int err;
3044	int port;
3045
3046	if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
3047		return 0;
3048
3049	for (port = 1; port <= dev->num_ports; port++) {
3050		if (dev->num_plane) {
3051			dev->port_caps[port - 1].has_smi = false;
3052			continue;
3053		} else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) ||
3054			dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
3055			dev->port_caps[port - 1].has_smi = true;
3056			continue;
3057		}
3058
3059		err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
3060						   &vport_ctx);
3061		if (err) {
3062			mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3063				    port, err);
3064			return err;
3065		}
3066		dev->port_caps[port - 1].has_smi = vport_ctx.has_smi;
3067	}
3068
3069	return 0;
3070}
3071
3072static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3073{
3074	unsigned int port;
3075
3076	rdma_for_each_port (&dev->ib_dev, port)
3077		mlx5_query_ext_port_caps(dev, port);
3078}
3079
3080static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3081{
3082	switch (umr_fence_cap) {
3083	case MLX5_CAP_UMR_FENCE_NONE:
3084		return MLX5_FENCE_MODE_NONE;
3085	case MLX5_CAP_UMR_FENCE_SMALL:
3086		return MLX5_FENCE_MODE_INITIATOR_SMALL;
3087	default:
3088		return MLX5_FENCE_MODE_STRONG_ORDERING;
3089	}
3090}
3091
3092int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev)
3093{
3094	struct mlx5_ib_resources *devr = &dev->devr;
3095	struct ib_cq_init_attr cq_attr = {.cqe = 1};
3096	struct ib_device *ibdev;
3097	struct ib_pd *pd;
3098	struct ib_cq *cq;
3099	int ret = 0;
3100
3101
3102	/*
3103	 * devr->c0 is set once, never changed until device unload.
3104	 * Avoid taking the mutex if initialization is already done.
3105	 */
3106	if (devr->c0)
3107		return 0;
3108
3109	mutex_lock(&devr->cq_lock);
3110	if (devr->c0)
3111		goto unlock;
3112
3113	ibdev = &dev->ib_dev;
3114	pd = ib_alloc_pd(ibdev, 0);
3115	if (IS_ERR(pd)) {
3116		ret = PTR_ERR(pd);
3117		mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n",
3118			    pd);
3119		goto unlock;
3120	}
3121
3122	cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
3123	if (IS_ERR(cq)) {
3124		ret = PTR_ERR(cq);
3125		mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n",
3126			    cq);
3127		ib_dealloc_pd(pd);
3128		goto unlock;
3129	}
3130
3131	devr->p0 = pd;
3132	devr->c0 = cq;
3133
3134unlock:
3135	mutex_unlock(&devr->cq_lock);
3136	return ret;
3137}
3138
3139int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev)
3140{
3141	struct mlx5_ib_resources *devr = &dev->devr;
3142	struct ib_srq_init_attr attr;
3143	struct ib_srq *s0, *s1;
3144	int ret = 0;
3145
3146	/*
3147	 * devr->s1 is set once, never changed until device unload.
3148	 * Avoid taking the mutex if initialization is already done.
3149	 */
3150	if (devr->s1)
3151		return 0;
3152
3153	mutex_lock(&devr->srq_lock);
3154	if (devr->s1)
3155		goto unlock;
3156
3157	ret = mlx5_ib_dev_res_cq_init(dev);
3158	if (ret)
3159		goto unlock;
3160
3161	memset(&attr, 0, sizeof(attr));
3162	attr.attr.max_sge = 1;
3163	attr.attr.max_wr = 1;
3164	attr.srq_type = IB_SRQT_XRC;
3165	attr.ext.cq = devr->c0;
3166
3167	s0 = ib_create_srq(devr->p0, &attr);
3168	if (IS_ERR(s0)) {
3169		ret = PTR_ERR(s0);
3170		mlx5_ib_err(dev,
3171			    "Couldn't create SRQ 0 for res init, err=%pe\n",
3172			    s0);
3173		goto unlock;
3174	}
3175
3176	memset(&attr, 0, sizeof(attr));
3177	attr.attr.max_sge = 1;
3178	attr.attr.max_wr = 1;
3179	attr.srq_type = IB_SRQT_BASIC;
3180
3181	s1 = ib_create_srq(devr->p0, &attr);
3182	if (IS_ERR(s1)) {
3183		ret = PTR_ERR(s1);
3184		mlx5_ib_err(dev,
3185			    "Couldn't create SRQ 1 for res init, err=%pe\n",
3186			    s1);
3187		ib_destroy_srq(s0);
3188	}
3189
3190	devr->s0 = s0;
3191	devr->s1 = s1;
3192
3193unlock:
3194	mutex_unlock(&devr->srq_lock);
3195	return ret;
3196}
3197
3198static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
3199{
3200	struct mlx5_ib_resources *devr = &dev->devr;
3201	int ret;
3202
3203	if (!MLX5_CAP_GEN(dev->mdev, xrc))
3204		return -EOPNOTSUPP;
3205
3206	ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
3207	if (ret)
3208		return ret;
3209
3210	ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
3211	if (ret) {
3212		mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3213		return ret;
3214	}
3215
3216	mutex_init(&devr->cq_lock);
3217	mutex_init(&devr->srq_lock);
3218
3219	return 0;
3220}
3221
3222static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
3223{
3224	struct mlx5_ib_resources *devr = &dev->devr;
3225
3226	/* After s0/s1 init, they are not unset during the device lifetime. */
3227	if (devr->s1) {
3228		ib_destroy_srq(devr->s1);
3229		ib_destroy_srq(devr->s0);
3230	}
3231	mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3232	mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3233	/* After p0/c0 init, they are not unset during the device lifetime. */
3234	if (devr->c0) {
3235		ib_destroy_cq(devr->c0);
3236		ib_dealloc_pd(devr->p0);
3237	}
3238	mutex_destroy(&devr->cq_lock);
3239	mutex_destroy(&devr->srq_lock);
3240}
3241
3242static int
3243mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev)
3244{
3245	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3246	struct mlx5_core_dev *mdev = dev->mdev;
3247	bool ro_supp = false;
3248	void *mkc;
3249	u32 mkey;
3250	u32 pdn;
3251	u32 *in;
3252	int err;
3253
3254	err = mlx5_core_alloc_pd(mdev, &pdn);
3255	if (err)
3256		return err;
3257
3258	in = kvzalloc(inlen, GFP_KERNEL);
3259	if (!in) {
3260		err = -ENOMEM;
3261		goto err;
3262	}
3263
3264	MLX5_SET(create_mkey_in, in, data_direct, 1);
3265	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3266	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
3267	MLX5_SET(mkc, mkc, lw, 1);
3268	MLX5_SET(mkc, mkc, lr, 1);
3269	MLX5_SET(mkc, mkc, rw, 1);
3270	MLX5_SET(mkc, mkc, rr, 1);
3271	MLX5_SET(mkc, mkc, a, 1);
3272	MLX5_SET(mkc, mkc, pd, pdn);
3273	MLX5_SET(mkc, mkc, length64, 1);
3274	MLX5_SET(mkc, mkc, qpn, 0xffffff);
3275	err = mlx5_core_create_mkey(mdev, &mkey, in, inlen);
3276	if (err)
3277		goto err_mkey;
3278
3279	dev->ddr.mkey = mkey;
3280	dev->ddr.pdn = pdn;
3281
3282	/* create another mkey with RO support */
3283	if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) {
3284		MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
3285		ro_supp = true;
3286	}
3287
3288	if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) {
3289		MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);
3290		ro_supp = true;
3291	}
3292
3293	if (ro_supp) {
3294		err = mlx5_core_create_mkey(mdev, &mkey, in, inlen);
3295		/* RO is defined as best effort */
3296		if (!err) {
3297			dev->ddr.mkey_ro = mkey;
3298			dev->ddr.mkey_ro_valid = true;
3299		}
3300	}
3301
3302	kvfree(in);
3303	return 0;
3304
3305err_mkey:
3306	kvfree(in);
3307err:
3308	mlx5_core_dealloc_pd(mdev, pdn);
3309	return err;
3310}
3311
3312static void
3313mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev)
3314{
3315
3316	if (dev->ddr.mkey_ro_valid)
3317		mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro);
3318
3319	mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey);
3320	mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn);
3321}
3322
3323static u32 get_core_cap_flags(struct ib_device *ibdev,
3324			      struct mlx5_hca_vport_context *rep)
3325{
3326	struct mlx5_ib_dev *dev = to_mdev(ibdev);
3327	enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3328	u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3329	u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3330	bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3331	u32 ret = 0;
3332
3333	if (rep->grh_required)
3334		ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
3335
3336	if (dev->num_plane)
3337		return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD |
3338			RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA |
3339			RDMA_CORE_CAP_AF_IB;
3340	else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3341		return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI;
3342
3343	if (ll == IB_LINK_LAYER_INFINIBAND)
3344		return ret | RDMA_CORE_PORT_IBA_IB;
3345
3346	if (raw_support)
3347		ret |= RDMA_CORE_PORT_RAW_PACKET;
3348
3349	if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3350		return ret;
3351
3352	if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3353		return ret;
3354
3355	if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3356		ret |= RDMA_CORE_PORT_IBA_ROCE;
3357
3358	if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3359		ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3360
3361	return ret;
3362}
3363
3364static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
3365			       struct ib_port_immutable *immutable)
3366{
3367	struct ib_port_attr attr;
3368	struct mlx5_ib_dev *dev = to_mdev(ibdev);
3369	enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3370	struct mlx5_hca_vport_context rep = {0};
3371	int err;
3372
3373	err = ib_query_port(ibdev, port_num, &attr);
3374	if (err)
3375		return err;
3376
3377	if (ll == IB_LINK_LAYER_INFINIBAND) {
3378		if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3379			port_num = smi_to_native_portnum(dev, port_num);
3380
3381		err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3382						   &rep);
3383		if (err)
3384			return err;
3385	}
3386
3387	immutable->pkey_tbl_len = attr.pkey_tbl_len;
3388	immutable->gid_tbl_len = attr.gid_tbl_len;
3389	immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
3390	immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3391
3392	return 0;
3393}
3394
3395static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
3396				   struct ib_port_immutable *immutable)
3397{
3398	struct ib_port_attr attr;
3399	int err;
3400
3401	immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3402
3403	err = ib_query_port(ibdev, port_num, &attr);
3404	if (err)
3405		return err;
3406
3407	immutable->pkey_tbl_len = attr.pkey_tbl_len;
3408	immutable->gid_tbl_len = attr.gid_tbl_len;
3409	immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3410
3411	return 0;
3412}
3413
3414static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3415{
3416	struct mlx5_ib_dev *dev =
3417		container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3418	snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3419		 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3420		 fw_rev_sub(dev->mdev));
3421}
3422
3423static int lag_event(struct notifier_block *nb, unsigned long event, void *data)
3424{
3425	struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev,
3426					       lag_events);
3427	struct mlx5_core_dev *mdev = dev->mdev;
3428	struct ib_device *ibdev = &dev->ib_dev;
3429	struct net_device *old_ndev = NULL;
3430	struct mlx5_ib_port *port;
3431	struct net_device *ndev;
3432	u32 portnum = 0;
3433	int ret = 0;
3434	int i;
3435
3436	switch (event) {
3437	case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE:
3438		ndev = data;
3439		if (ndev) {
3440			if (!mlx5_lag_is_roce(mdev)) {
3441				// sriov lag
3442				for (i = 0; i < dev->num_ports; i++) {
3443					port = &dev->port[i];
3444					if (port->rep && port->rep->vport ==
3445					    MLX5_VPORT_UPLINK) {
3446						portnum = i;
3447						break;
3448					}
3449				}
3450			}
3451			old_ndev = ib_device_get_netdev(ibdev, portnum + 1);
3452			ret = ib_device_set_netdev(ibdev, ndev, portnum + 1);
3453			if (ret)
3454				goto out;
3455
3456			if (old_ndev)
3457				roce_del_all_netdev_gids(ibdev, portnum + 1,
3458							 old_ndev);
3459			rdma_roce_rescan_port(ibdev, portnum + 1);
3460		}
3461		break;
3462	default:
3463		return NOTIFY_DONE;
3464	}
3465
3466out:
3467	dev_put(old_ndev);
3468	return notifier_from_errno(ret);
3469}
3470
3471static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev)
3472{
3473	dev->lag_events.notifier_call = lag_event;
3474	blocking_notifier_chain_register(&dev->mdev->priv.lag_nh,
3475					 &dev->lag_events);
3476}
3477
3478static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev)
3479{
3480	blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh,
3481					   &dev->lag_events);
3482}
3483
3484static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3485{
3486	struct mlx5_core_dev *mdev = dev->mdev;
3487	struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3488								 MLX5_FLOW_NAMESPACE_LAG);
3489	struct mlx5_flow_table *ft;
3490	int err;
3491
3492	if (!ns || !mlx5_lag_is_active(mdev))
3493		return 0;
3494
3495	err = mlx5_cmd_create_vport_lag(mdev);
3496	if (err)
3497		return err;
3498
3499	ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3500	if (IS_ERR(ft)) {
3501		err = PTR_ERR(ft);
3502		goto err_destroy_vport_lag;
3503	}
3504
3505	mlx5e_lag_event_register(dev);
3506	dev->flow_db->lag_demux_ft = ft;
3507	dev->lag_ports = mlx5_lag_get_num_ports(mdev);
3508	dev->lag_active = true;
3509	return 0;
3510
3511err_destroy_vport_lag:
3512	mlx5_cmd_destroy_vport_lag(mdev);
3513	return err;
3514}
3515
3516static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3517{
3518	struct mlx5_core_dev *mdev = dev->mdev;
3519
3520	if (dev->lag_active) {
3521		dev->lag_active = false;
3522
3523		mlx5e_lag_event_unregister(dev);
3524		mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3525		dev->flow_db->lag_demux_ft = NULL;
3526
3527		mlx5_cmd_destroy_vport_lag(mdev);
3528	}
3529}
3530
3531static void mlx5_netdev_notifier_register(struct mlx5_roce *roce,
3532					  struct net_device *netdev)
3533{
3534	int err;
3535
3536	if (roce->tracking_netdev)
3537		return;
3538	roce->tracking_netdev = netdev;
3539	roce->nb.notifier_call = mlx5_netdev_event;
3540	err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn);
3541	WARN_ON(err);
3542}
3543
3544static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce)
3545{
3546	if (!roce->tracking_netdev)
3547		return;
3548	unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb,
3549					      &roce->nn);
3550	roce->tracking_netdev = NULL;
3551}
3552
3553static int mlx5e_mdev_notifier_event(struct notifier_block *nb,
3554				     unsigned long event, void *data)
3555{
3556	struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb);
3557	struct net_device *netdev = data;
3558
3559	switch (event) {
3560	case MLX5_DRIVER_EVENT_UPLINK_NETDEV:
3561		if (netdev)
3562			mlx5_netdev_notifier_register(roce, netdev);
3563		else
3564			mlx5_netdev_notifier_unregister(roce);
3565		break;
3566	default:
3567		return NOTIFY_DONE;
3568	}
3569
3570	return NOTIFY_OK;
3571}
3572
3573static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num)
3574{
3575	struct mlx5_roce *roce = &dev->port[port_num].roce;
3576
3577	roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event;
3578	mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb);
3579	mlx5_core_uplink_netdev_event_replay(dev->mdev);
3580}
3581
3582static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num)
3583{
3584	struct mlx5_roce *roce = &dev->port[port_num].roce;
3585
3586	mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb);
3587	mlx5_netdev_notifier_unregister(roce);
3588}
3589
3590static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3591{
3592	int err;
3593
3594	if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3595		err = mlx5_nic_vport_enable_roce(dev->mdev);
3596		if (err)
3597			return err;
3598	}
3599
3600	err = mlx5_eth_lag_init(dev);
3601	if (err)
3602		goto err_disable_roce;
3603
3604	return 0;
3605
3606err_disable_roce:
3607	if (!dev->is_rep && dev->profile != &raw_eth_profile)
3608		mlx5_nic_vport_disable_roce(dev->mdev);
3609
3610	return err;
3611}
3612
3613static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3614{
3615	mlx5_eth_lag_cleanup(dev);
3616	if (!dev->is_rep && dev->profile != &raw_eth_profile)
3617		mlx5_nic_vport_disable_roce(dev->mdev);
3618}
3619
3620static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3621				 enum rdma_netdev_t type,
3622				 struct rdma_netdev_alloc_params *params)
3623{
3624	if (type != RDMA_NETDEV_IPOIB)
3625		return -EOPNOTSUPP;
3626
3627	return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3628}
3629
3630static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3631				       size_t count, loff_t *pos)
3632{
3633	struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3634	char lbuf[20];
3635	int len;
3636
3637	len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3638	return simple_read_from_buffer(buf, count, pos, lbuf, len);
3639}
3640
3641static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3642					size_t count, loff_t *pos)
3643{
3644	struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3645	u32 timeout;
3646	u32 var;
3647
3648	if (kstrtouint_from_user(buf, count, 0, &var))
3649		return -EFAULT;
3650
3651	timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3652			1000);
3653	if (timeout != var)
3654		mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3655			    timeout);
3656
3657	delay_drop->timeout = timeout;
3658
3659	return count;
3660}
3661
3662static const struct file_operations fops_delay_drop_timeout = {
3663	.owner	= THIS_MODULE,
3664	.open	= simple_open,
3665	.write	= delay_drop_timeout_write,
3666	.read	= delay_drop_timeout_read,
3667};
3668
3669static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3670				      struct mlx5_ib_multiport_info *mpi)
3671{
3672	u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3673	struct mlx5_ib_port *port = &ibdev->port[port_num];
3674	int comps;
3675	int err;
3676	int i;
3677
3678	lockdep_assert_held(&mlx5_ib_multiport_mutex);
3679
3680	mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb);
3681
3682	mlx5_core_mp_event_replay(ibdev->mdev,
3683				  MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3684				  NULL);
3685	mlx5_core_mp_event_replay(mpi->mdev,
3686				  MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3687				  NULL);
3688
3689	mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3690
3691	spin_lock(&port->mp.mpi_lock);
3692	if (!mpi->ibdev) {
3693		spin_unlock(&port->mp.mpi_lock);
3694		return;
3695	}
3696
3697	mpi->ibdev = NULL;
3698
3699	spin_unlock(&port->mp.mpi_lock);
3700	if (mpi->mdev_events.notifier_call)
3701		mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3702	mpi->mdev_events.notifier_call = NULL;
3703	mlx5_mdev_netdev_untrack(ibdev, port_num);
3704	spin_lock(&port->mp.mpi_lock);
3705
3706	comps = mpi->mdev_refcnt;
3707	if (comps) {
3708		mpi->unaffiliate = true;
3709		init_completion(&mpi->unref_comp);
3710		spin_unlock(&port->mp.mpi_lock);
3711
3712		for (i = 0; i < comps; i++)
3713			wait_for_completion(&mpi->unref_comp);
3714
3715		spin_lock(&port->mp.mpi_lock);
3716		mpi->unaffiliate = false;
3717	}
3718
3719	port->mp.mpi = NULL;
3720
3721	spin_unlock(&port->mp.mpi_lock);
3722
3723	err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3724
3725	mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3726	/* Log an error, still needed to cleanup the pointers and add
3727	 * it back to the list.
3728	 */
3729	if (err)
3730		mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3731			    port_num + 1);
3732
3733	ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3734}
3735
3736static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3737				    struct mlx5_ib_multiport_info *mpi)
3738{
3739	u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3740	u64 key;
3741	int err;
3742
3743	lockdep_assert_held(&mlx5_ib_multiport_mutex);
3744
3745	spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3746	if (ibdev->port[port_num].mp.mpi) {
3747		mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3748			    port_num + 1);
3749		spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3750		return false;
3751	}
3752
3753	ibdev->port[port_num].mp.mpi = mpi;
3754	mpi->ibdev = ibdev;
3755	mpi->mdev_events.notifier_call = NULL;
3756	spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3757
3758	err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3759	if (err)
3760		goto unbind;
3761
3762	mlx5_mdev_netdev_track(ibdev, port_num);
3763
3764	mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3765	mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3766
3767	mlx5_ib_init_cong_debugfs(ibdev, port_num);
3768
3769	key = mpi->mdev->priv.adev_idx;
3770	mlx5_core_mp_event_replay(mpi->mdev,
3771				  MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3772				  &key);
3773	mlx5_core_mp_event_replay(ibdev->mdev,
3774				  MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3775				  &key);
3776
3777	err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb);
3778	if (err)
3779		goto unbind;
3780
3781	return true;
3782
3783unbind:
3784	mlx5_ib_unbind_slave_port(ibdev, mpi);
3785	return false;
3786}
3787
3788static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev)
3789{
3790	char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {};
3791	int ret;
3792
3793	if (!MLX5_CAP_GEN(dev->mdev, data_direct) ||
3794	    !MLX5_CAP_GEN_2(dev->mdev, query_vuid))
3795		return 0;
3796
3797	ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid);
3798	if (ret)
3799		return ret;
3800
3801	ret = mlx5_ib_create_data_direct_resources(dev);
3802	if (ret)
3803		return ret;
3804
3805	INIT_LIST_HEAD(&dev->data_direct_mr_list);
3806	ret = mlx5_data_direct_ib_reg(dev, vuid);
3807	if (ret)
3808		mlx5_ib_free_data_direct_resources(dev);
3809
3810	return ret;
3811}
3812
3813static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev)
3814{
3815	if (!MLX5_CAP_GEN(dev->mdev, data_direct) ||
3816	    !MLX5_CAP_GEN_2(dev->mdev, query_vuid))
3817		return;
3818
3819	mlx5_data_direct_ib_unreg(dev);
3820	mlx5_ib_free_data_direct_resources(dev);
3821}
3822
3823static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3824{
3825	u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3826	enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3827							  port_num + 1);
3828	struct mlx5_ib_multiport_info *mpi;
3829	int err;
3830	u32 i;
3831
3832	if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3833		return 0;
3834
3835	err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3836						     &dev->sys_image_guid);
3837	if (err)
3838		return err;
3839
3840	err = mlx5_nic_vport_enable_roce(dev->mdev);
3841	if (err)
3842		return err;
3843
3844	mutex_lock(&mlx5_ib_multiport_mutex);
3845	for (i = 0; i < dev->num_ports; i++) {
3846		bool bound = false;
3847
3848		/* build a stub multiport info struct for the native port. */
3849		if (i == port_num) {
3850			mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3851			if (!mpi) {
3852				mutex_unlock(&mlx5_ib_multiport_mutex);
3853				mlx5_nic_vport_disable_roce(dev->mdev);
3854				return -ENOMEM;
3855			}
3856
3857			mpi->is_master = true;
3858			mpi->mdev = dev->mdev;
3859			mpi->sys_image_guid = dev->sys_image_guid;
3860			dev->port[i].mp.mpi = mpi;
3861			mpi->ibdev = dev;
3862			mpi = NULL;
3863			continue;
3864		}
3865
3866		list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3867				    list) {
3868			if (dev->sys_image_guid == mpi->sys_image_guid &&
3869			    (mlx5_core_native_port_num(mpi->mdev) - 1) == i &&
3870			    mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) {
3871				bound = mlx5_ib_bind_slave_port(dev, mpi);
3872			}
3873
3874			if (bound) {
3875				dev_dbg(mpi->mdev->device,
3876					"removing port from unaffiliated list.\n");
3877				mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3878				list_del(&mpi->list);
3879				break;
3880			}
3881		}
3882		if (!bound)
3883			mlx5_ib_dbg(dev, "no free port found for port %d\n",
3884				    i + 1);
3885	}
3886
3887	list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3888	mutex_unlock(&mlx5_ib_multiport_mutex);
3889	return err;
3890}
3891
3892static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3893{
3894	u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3895	enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3896							  port_num + 1);
3897	u32 i;
3898
3899	if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3900		return;
3901
3902	mutex_lock(&mlx5_ib_multiport_mutex);
3903	for (i = 0; i < dev->num_ports; i++) {
3904		if (dev->port[i].mp.mpi) {
3905			/* Destroy the native port stub */
3906			if (i == port_num) {
3907				kfree(dev->port[i].mp.mpi);
3908				dev->port[i].mp.mpi = NULL;
3909			} else {
3910				mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3911					    i + 1);
3912				list_add_tail(&dev->port[i].mp.mpi->list,
3913					      &mlx5_ib_unaffiliated_port_list);
3914				mlx5_ib_unbind_slave_port(dev,
3915							  dev->port[i].mp.mpi);
3916			}
3917		}
3918	}
3919
3920	mlx5_ib_dbg(dev, "removing from devlist\n");
3921	list_del(&dev->ib_dev_list);
3922	mutex_unlock(&mlx5_ib_multiport_mutex);
3923
3924	mlx5_nic_vport_disable_roce(dev->mdev);
3925}
3926
3927static int mmap_obj_cleanup(struct ib_uobject *uobject,
3928			    enum rdma_remove_reason why,
3929			    struct uverbs_attr_bundle *attrs)
3930{
3931	struct mlx5_user_mmap_entry *obj = uobject->object;
3932
3933	rdma_user_mmap_entry_remove(&obj->rdma_entry);
3934	return 0;
3935}
3936
3937static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3938					    struct mlx5_user_mmap_entry *entry,
3939					    size_t length)
3940{
3941	return rdma_user_mmap_entry_insert_range(
3942		&c->ibucontext, &entry->rdma_entry, length,
3943		(MLX5_IB_MMAP_OFFSET_START << 16),
3944		((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3945}
3946
3947static struct mlx5_user_mmap_entry *
3948alloc_var_entry(struct mlx5_ib_ucontext *c)
3949{
3950	struct mlx5_user_mmap_entry *entry;
3951	struct mlx5_var_table *var_table;
3952	u32 page_idx;
3953	int err;
3954
3955	var_table = &to_mdev(c->ibucontext.device)->var_table;
3956	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3957	if (!entry)
3958		return ERR_PTR(-ENOMEM);
3959
3960	mutex_lock(&var_table->bitmap_lock);
3961	page_idx = find_first_zero_bit(var_table->bitmap,
3962				       var_table->num_var_hw_entries);
3963	if (page_idx >= var_table->num_var_hw_entries) {
3964		err = -ENOSPC;
3965		mutex_unlock(&var_table->bitmap_lock);
3966		goto end;
3967	}
3968
3969	set_bit(page_idx, var_table->bitmap);
3970	mutex_unlock(&var_table->bitmap_lock);
3971
3972	entry->address = var_table->hw_start_addr +
3973				(page_idx * var_table->stride_size);
3974	entry->page_idx = page_idx;
3975	entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3976
3977	err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3978					       var_table->stride_size);
3979	if (err)
3980		goto err_insert;
3981
3982	return entry;
3983
3984err_insert:
3985	mutex_lock(&var_table->bitmap_lock);
3986	clear_bit(page_idx, var_table->bitmap);
3987	mutex_unlock(&var_table->bitmap_lock);
3988end:
3989	kfree(entry);
3990	return ERR_PTR(err);
3991}
3992
3993static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3994	struct uverbs_attr_bundle *attrs)
3995{
3996	struct ib_uobject *uobj = uverbs_attr_get_uobject(
3997		attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3998	struct mlx5_ib_ucontext *c;
3999	struct mlx5_user_mmap_entry *entry;
4000	u64 mmap_offset;
4001	u32 length;
4002	int err;
4003
4004	c = to_mucontext(ib_uverbs_get_ucontext(attrs));
4005	if (IS_ERR(c))
4006		return PTR_ERR(c);
4007
4008	entry = alloc_var_entry(c);
4009	if (IS_ERR(entry))
4010		return PTR_ERR(entry);
4011
4012	mmap_offset = mlx5_entry_to_mmap_offset(entry);
4013	length = entry->rdma_entry.npages * PAGE_SIZE;
4014	uobj->object = entry;
4015	uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
4016
4017	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
4018			     &mmap_offset, sizeof(mmap_offset));
4019	if (err)
4020		return err;
4021
4022	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
4023			     &entry->page_idx, sizeof(entry->page_idx));
4024	if (err)
4025		return err;
4026
4027	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
4028			     &length, sizeof(length));
4029	return err;
4030}
4031
4032DECLARE_UVERBS_NAMED_METHOD(
4033	MLX5_IB_METHOD_VAR_OBJ_ALLOC,
4034	UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
4035			MLX5_IB_OBJECT_VAR,
4036			UVERBS_ACCESS_NEW,
4037			UA_MANDATORY),
4038	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
4039			   UVERBS_ATTR_TYPE(u32),
4040			   UA_MANDATORY),
4041	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
4042			   UVERBS_ATTR_TYPE(u32),
4043			   UA_MANDATORY),
4044	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
4045			    UVERBS_ATTR_TYPE(u64),
4046			    UA_MANDATORY));
4047
4048DECLARE_UVERBS_NAMED_METHOD_DESTROY(
4049	MLX5_IB_METHOD_VAR_OBJ_DESTROY,
4050	UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
4051			MLX5_IB_OBJECT_VAR,
4052			UVERBS_ACCESS_DESTROY,
4053			UA_MANDATORY));
4054
4055DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
4056			    UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
4057			    &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
4058			    &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
4059
4060static bool var_is_supported(struct ib_device *device)
4061{
4062	struct mlx5_ib_dev *dev = to_mdev(device);
4063
4064	return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4065			MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
4066}
4067
4068static struct mlx5_user_mmap_entry *
4069alloc_uar_entry(struct mlx5_ib_ucontext *c,
4070		enum mlx5_ib_uapi_uar_alloc_type alloc_type)
4071{
4072	struct mlx5_user_mmap_entry *entry;
4073	struct mlx5_ib_dev *dev;
4074	u32 uar_index;
4075	int err;
4076
4077	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
4078	if (!entry)
4079		return ERR_PTR(-ENOMEM);
4080
4081	dev = to_mdev(c->ibucontext.device);
4082	err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
4083	if (err)
4084		goto end;
4085
4086	entry->page_idx = uar_index;
4087	entry->address = uar_index2paddress(dev, uar_index);
4088	if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
4089		entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
4090	else
4091		entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
4092
4093	err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
4094	if (err)
4095		goto err_insert;
4096
4097	return entry;
4098
4099err_insert:
4100	mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
4101end:
4102	kfree(entry);
4103	return ERR_PTR(err);
4104}
4105
4106static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
4107	struct uverbs_attr_bundle *attrs)
4108{
4109	struct ib_uobject *uobj = uverbs_attr_get_uobject(
4110		attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
4111	enum mlx5_ib_uapi_uar_alloc_type alloc_type;
4112	struct mlx5_ib_ucontext *c;
4113	struct mlx5_user_mmap_entry *entry;
4114	u64 mmap_offset;
4115	u32 length;
4116	int err;
4117
4118	c = to_mucontext(ib_uverbs_get_ucontext(attrs));
4119	if (IS_ERR(c))
4120		return PTR_ERR(c);
4121
4122	err = uverbs_get_const(&alloc_type, attrs,
4123			       MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
4124	if (err)
4125		return err;
4126
4127	if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
4128	    alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
4129		return -EOPNOTSUPP;
4130
4131	if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) &&
4132	    alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
4133		return -EOPNOTSUPP;
4134
4135	entry = alloc_uar_entry(c, alloc_type);
4136	if (IS_ERR(entry))
4137		return PTR_ERR(entry);
4138
4139	mmap_offset = mlx5_entry_to_mmap_offset(entry);
4140	length = entry->rdma_entry.npages * PAGE_SIZE;
4141	uobj->object = entry;
4142	uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
4143
4144	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
4145			     &mmap_offset, sizeof(mmap_offset));
4146	if (err)
4147		return err;
4148
4149	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
4150			     &entry->page_idx, sizeof(entry->page_idx));
4151	if (err)
4152		return err;
4153
4154	err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
4155			     &length, sizeof(length));
4156	return err;
4157}
4158
4159DECLARE_UVERBS_NAMED_METHOD(
4160	MLX5_IB_METHOD_UAR_OBJ_ALLOC,
4161	UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
4162			MLX5_IB_OBJECT_UAR,
4163			UVERBS_ACCESS_NEW,
4164			UA_MANDATORY),
4165	UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
4166			     enum mlx5_ib_uapi_uar_alloc_type,
4167			     UA_MANDATORY),
4168	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
4169			   UVERBS_ATTR_TYPE(u32),
4170			   UA_MANDATORY),
4171	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
4172			   UVERBS_ATTR_TYPE(u32),
4173			   UA_MANDATORY),
4174	UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
4175			    UVERBS_ATTR_TYPE(u64),
4176			    UA_MANDATORY));
4177
4178DECLARE_UVERBS_NAMED_METHOD_DESTROY(
4179	MLX5_IB_METHOD_UAR_OBJ_DESTROY,
4180	UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
4181			MLX5_IB_OBJECT_UAR,
4182			UVERBS_ACCESS_DESTROY,
4183			UA_MANDATORY));
4184
4185DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
4186			    UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
4187			    &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
4188			    &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
4189
4190ADD_UVERBS_ATTRIBUTES_SIMPLE(
4191	mlx5_ib_query_context,
4192	UVERBS_OBJECT_DEVICE,
4193	UVERBS_METHOD_QUERY_CONTEXT,
4194	UVERBS_ATTR_PTR_OUT(
4195		MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
4196		UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
4197				   dump_fill_mkey),
4198		UA_MANDATORY));
4199
4200ADD_UVERBS_ATTRIBUTES_SIMPLE(
4201	mlx5_ib_reg_dmabuf_mr,
4202	UVERBS_OBJECT_MR,
4203	UVERBS_METHOD_REG_DMABUF_MR,
4204	UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS,
4205			     enum mlx5_ib_uapi_reg_dmabuf_flags,
4206			     UA_OPTIONAL));
4207
4208static const struct uapi_definition mlx5_ib_defs[] = {
4209	UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
4210	UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
4211	UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
4212	UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
4213	UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
4214	UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs),
4215
4216	UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
4217	UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr),
4218	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
4219				UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
4220	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
4221	{}
4222};
4223
4224static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
4225{
4226	mlx5_ib_data_direct_cleanup(dev);
4227	mlx5_ib_cleanup_multiport_master(dev);
4228	WARN_ON(!xa_empty(&dev->odp_mkeys));
4229	mutex_destroy(&dev->cap_mask_mutex);
4230	WARN_ON(!xa_empty(&dev->sig_mrs));
4231	WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
4232	mlx5r_macsec_dealloc_gids(dev);
4233}
4234
4235static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4236{
4237	struct mlx5_core_dev *mdev = dev->mdev;
4238	int err, i;
4239
4240	dev->ib_dev.node_type = RDMA_NODE_IB_CA;
4241	dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
4242	dev->ib_dev.dev.parent = mdev->device;
4243	dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
4244
4245	for (i = 0; i < dev->num_ports; i++) {
4246		spin_lock_init(&dev->port[i].mp.mpi_lock);
4247		dev->port[i].roce.dev = dev;
4248		dev->port[i].roce.native_port_num = i + 1;
4249		dev->port[i].roce.last_port_state = IB_PORT_DOWN;
4250	}
4251
4252	err = mlx5r_cmd_query_special_mkeys(dev);
4253	if (err)
4254		return err;
4255
4256	err = mlx5r_macsec_init_gids_and_devlist(dev);
4257	if (err)
4258		return err;
4259
4260	err = mlx5_ib_init_multiport_master(dev);
4261	if (err)
4262		goto err;
4263
4264	err = set_has_smi_cap(dev);
4265	if (err)
4266		goto err_mp;
4267
4268	err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
4269	if (err)
4270		goto err_mp;
4271
4272	if (mlx5_use_mad_ifc(dev))
4273		get_ext_port_caps(dev);
4274
4275	dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_max(mdev);
4276
4277	mutex_init(&dev->cap_mask_mutex);
4278	mutex_init(&dev->data_direct_lock);
4279	INIT_LIST_HEAD(&dev->qp_list);
4280	spin_lock_init(&dev->reset_flow_resource_lock);
4281	xa_init(&dev->odp_mkeys);
4282	xa_init(&dev->sig_mrs);
4283	atomic_set(&dev->mkey_var, 0);
4284
4285	spin_lock_init(&dev->dm.lock);
4286	dev->dm.dev = mdev;
4287	err = mlx5_ib_data_direct_init(dev);
4288	if (err)
4289		goto err_mp;
4290
4291	return 0;
4292err_mp:
4293	mlx5_ib_cleanup_multiport_master(dev);
4294err:
4295	mlx5r_macsec_dealloc_gids(dev);
4296	return err;
4297}
4298
4299static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4300					     enum rdma_nl_dev_type type,
4301					     const char *name);
4302static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev);
4303
4304static const struct ib_device_ops mlx5_ib_dev_ops = {
4305	.owner = THIS_MODULE,
4306	.driver_id = RDMA_DRIVER_MLX5,
4307	.uverbs_abi_ver	= MLX5_IB_UVERBS_ABI_VERSION,
4308
4309	.add_gid = mlx5_ib_add_gid,
4310	.add_sub_dev = mlx5_ib_add_sub_dev,
4311	.alloc_mr = mlx5_ib_alloc_mr,
4312	.alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
4313	.alloc_pd = mlx5_ib_alloc_pd,
4314	.alloc_ucontext = mlx5_ib_alloc_ucontext,
4315	.attach_mcast = mlx5_ib_mcg_attach,
4316	.check_mr_status = mlx5_ib_check_mr_status,
4317	.create_ah = mlx5_ib_create_ah,
4318	.create_cq = mlx5_ib_create_cq,
4319	.create_qp = mlx5_ib_create_qp,
4320	.create_srq = mlx5_ib_create_srq,
4321	.create_user_ah = mlx5_ib_create_ah,
4322	.dealloc_pd = mlx5_ib_dealloc_pd,
4323	.dealloc_ucontext = mlx5_ib_dealloc_ucontext,
4324	.del_gid = mlx5_ib_del_gid,
4325	.del_sub_dev = mlx5_ib_del_sub_dev,
4326	.dereg_mr = mlx5_ib_dereg_mr,
4327	.destroy_ah = mlx5_ib_destroy_ah,
4328	.destroy_cq = mlx5_ib_destroy_cq,
4329	.destroy_qp = mlx5_ib_destroy_qp,
4330	.destroy_srq = mlx5_ib_destroy_srq,
4331	.detach_mcast = mlx5_ib_mcg_detach,
4332	.disassociate_ucontext = mlx5_ib_disassociate_ucontext,
4333	.drain_rq = mlx5_ib_drain_rq,
4334	.drain_sq = mlx5_ib_drain_sq,
4335	.device_group = &mlx5_attr_group,
4336	.get_dev_fw_str = get_dev_fw_str,
4337	.get_dma_mr = mlx5_ib_get_dma_mr,
4338	.get_link_layer = mlx5_ib_port_link_layer,
4339	.map_mr_sg = mlx5_ib_map_mr_sg,
4340	.map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
4341	.mmap = mlx5_ib_mmap,
4342	.mmap_free = mlx5_ib_mmap_free,
4343	.modify_cq = mlx5_ib_modify_cq,
4344	.modify_device = mlx5_ib_modify_device,
4345	.modify_port = mlx5_ib_modify_port,
4346	.modify_qp = mlx5_ib_modify_qp,
4347	.modify_srq = mlx5_ib_modify_srq,
4348	.pre_destroy_cq = mlx5_ib_pre_destroy_cq,
4349	.poll_cq = mlx5_ib_poll_cq,
4350	.post_destroy_cq = mlx5_ib_post_destroy_cq,
4351	.post_recv = mlx5_ib_post_recv_nodrain,
4352	.post_send = mlx5_ib_post_send_nodrain,
4353	.post_srq_recv = mlx5_ib_post_srq_recv,
4354	.process_mad = mlx5_ib_process_mad,
4355	.query_ah = mlx5_ib_query_ah,
4356	.query_device = mlx5_ib_query_device,
4357	.query_gid = mlx5_ib_query_gid,
4358	.query_pkey = mlx5_ib_query_pkey,
4359	.query_qp = mlx5_ib_query_qp,
4360	.query_srq = mlx5_ib_query_srq,
4361	.query_ucontext = mlx5_ib_query_ucontext,
4362	.reg_user_mr = mlx5_ib_reg_user_mr,
4363	.reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
4364	.req_notify_cq = mlx5_ib_arm_cq,
4365	.rereg_user_mr = mlx5_ib_rereg_user_mr,
4366	.resize_cq = mlx5_ib_resize_cq,
4367	.ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup,
4368
4369	INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
4370	INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
4371	INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
4372	INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah),
4373	INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
4374	INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
4375	INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
4376	INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
4377};
4378
4379static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
4380	.rdma_netdev_get_params = mlx5_ib_rn_get_params,
4381};
4382
4383static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
4384	.get_vf_config = mlx5_ib_get_vf_config,
4385	.get_vf_guid = mlx5_ib_get_vf_guid,
4386	.get_vf_stats = mlx5_ib_get_vf_stats,
4387	.set_vf_guid = mlx5_ib_set_vf_guid,
4388	.set_vf_link_state = mlx5_ib_set_vf_link_state,
4389};
4390
4391static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
4392	.alloc_mw = mlx5_ib_alloc_mw,
4393	.dealloc_mw = mlx5_ib_dealloc_mw,
4394
4395	INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
4396};
4397
4398static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
4399	.alloc_xrcd = mlx5_ib_alloc_xrcd,
4400	.dealloc_xrcd = mlx5_ib_dealloc_xrcd,
4401
4402	INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
4403};
4404
4405static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
4406{
4407	struct mlx5_core_dev *mdev = dev->mdev;
4408	struct mlx5_var_table *var_table = &dev->var_table;
4409	u8 log_doorbell_bar_size;
4410	u8 log_doorbell_stride;
4411	u64 bar_size;
4412
4413	log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4414					log_doorbell_bar_size);
4415	log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4416					log_doorbell_stride);
4417	var_table->hw_start_addr = dev->mdev->bar_addr +
4418				MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4419					doorbell_bar_offset);
4420	bar_size = (1ULL << log_doorbell_bar_size) * 4096;
4421	var_table->stride_size = 1ULL << log_doorbell_stride;
4422	var_table->num_var_hw_entries = div_u64(bar_size,
4423						var_table->stride_size);
4424	mutex_init(&var_table->bitmap_lock);
4425	var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
4426					  GFP_KERNEL);
4427	return (var_table->bitmap) ? 0 : -ENOMEM;
4428}
4429
4430static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev)
4431{
4432	if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL)
4433		ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL);
4434
4435	if (MLX5_CAP_GEN(dev->mdev, uctx_cap) &
4436	    MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA)
4437		ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA);
4438}
4439
4440static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev)
4441{
4442	int ret;
4443
4444	if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) {
4445		ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL);
4446		if (ret)
4447			return ret;
4448	}
4449
4450	if (MLX5_CAP_GEN(dev->mdev, uctx_cap) &
4451	    MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) {
4452		ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA);
4453		if (ret)
4454			goto remove_local;
4455	}
4456
4457	return 0;
4458
4459remove_local:
4460	if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL)
4461		ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL);
4462	return ret;
4463}
4464
4465static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
4466{
4467	if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) &
4468	    MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL)
4469		mlx5_ib_cleanup_ucaps(dev);
4470
4471	bitmap_free(dev->var_table.bitmap);
4472}
4473
4474static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4475{
4476	struct mlx5_core_dev *mdev = dev->mdev;
4477	int err;
4478
4479	if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4480	    IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
4481		ib_set_device_ops(&dev->ib_dev,
4482				  &mlx5_ib_dev_ipoib_enhanced_ops);
4483
4484	if (mlx5_core_is_pf(mdev))
4485		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
4486
4487	dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4488
4489	if (MLX5_CAP_GEN(mdev, imaicl))
4490		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
4491
4492	if (MLX5_CAP_GEN(mdev, xrc))
4493		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
4494
4495	if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4496	    MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4497	    MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
4498		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
4499
4500	if (mdev->st)
4501		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops);
4502
4503	ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
4504
4505	if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
4506		dev->ib_dev.driver_def = mlx5_ib_defs;
4507
4508	err = init_node_data(dev);
4509	if (err)
4510		return err;
4511
4512	if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4513	    (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4514	     MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4515		mutex_init(&dev->lb.mutex);
4516
4517	if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4518			MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4519		err = mlx5_ib_init_var_table(dev);
4520		if (err)
4521			return err;
4522	}
4523
4524	if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) &
4525	    MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) {
4526		err = mlx5_ib_init_ucaps(dev);
4527		if (err)
4528			goto err_ucaps;
4529	}
4530
4531	dev->ib_dev.use_cq_dim = true;
4532
4533	return 0;
4534
4535err_ucaps:
4536	bitmap_free(dev->var_table.bitmap);
4537	return err;
4538}
4539
4540static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4541	.get_port_immutable = mlx5_port_immutable,
4542	.query_port = mlx5_ib_query_port,
4543};
4544
4545static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4546{
4547	ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
4548	return 0;
4549}
4550
4551static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4552	.get_port_immutable = mlx5_port_rep_immutable,
4553	.query_port = mlx5_ib_rep_query_port,
4554	.query_pkey = mlx5_ib_rep_query_pkey,
4555};
4556
4557static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
4558{
4559	ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
4560	return 0;
4561}
4562
4563static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4564	.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4565	.create_wq = mlx5_ib_create_wq,
4566	.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4567	.destroy_wq = mlx5_ib_destroy_wq,
4568	.modify_wq = mlx5_ib_modify_wq,
4569
4570	INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4571			   ib_rwq_ind_tbl),
4572};
4573
4574static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
4575{
4576	struct mlx5_core_dev *mdev = dev->mdev;
4577	enum rdma_link_layer ll;
4578	int port_type_cap;
4579	u32 port_num = 0;
4580	int err;
4581
4582	port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4583	ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4584
4585	if (ll == IB_LINK_LAYER_ETHERNET) {
4586		ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4587
4588		port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4589
4590		/* Register only for native ports */
4591		mlx5_mdev_netdev_track(dev, port_num);
4592
4593		err = mlx5_enable_eth(dev);
4594		if (err)
4595			goto cleanup;
4596	}
4597
4598	return 0;
4599cleanup:
4600	mlx5_mdev_netdev_untrack(dev, port_num);
4601	return err;
4602}
4603
4604static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
4605{
4606	struct mlx5_core_dev *mdev = dev->mdev;
4607	enum rdma_link_layer ll;
4608	int port_type_cap;
4609	u32 port_num;
4610
4611	port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4612	ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4613
4614	if (ll == IB_LINK_LAYER_ETHERNET) {
4615		mlx5_disable_eth(dev);
4616
4617		port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4618		mlx5_mdev_netdev_untrack(dev, port_num);
4619	}
4620}
4621
4622static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4623{
4624	mlx5_ib_init_cong_debugfs(dev,
4625				  mlx5_core_native_port_num(dev->mdev) - 1);
4626	return 0;
4627}
4628
4629static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4630{
4631	mlx5_ib_cleanup_cong_debugfs(dev,
4632				     mlx5_core_native_port_num(dev->mdev) - 1);
4633}
4634
4635static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4636{
4637	int err;
4638
4639	err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4640	if (err)
4641		return err;
4642
4643	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4644	if (err)
4645		mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4646
4647	return err;
4648}
4649
4650static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4651{
4652	mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4653	mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4654}
4655
4656static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4657{
4658	const char *name;
4659
4660	if (dev->sub_dev_name) {
4661		name = dev->sub_dev_name;
4662		ib_mark_name_assigned_by_user(&dev->ib_dev);
4663	} else if (!mlx5_lag_is_active(dev->mdev))
4664		name = "mlx5_%d";
4665	else
4666		name = "mlx5_bond_%d";
4667	return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4668}
4669
4670static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4671{
4672	mlx5_mkey_cache_cleanup(dev);
4673	mlx5r_umr_resource_cleanup(dev);
4674	mlx5r_umr_cleanup(dev);
4675}
4676
4677static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4678{
4679	ib_unregister_device(&dev->ib_dev);
4680}
4681
4682static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4683{
4684	int ret;
4685
4686	ret = mlx5r_umr_init(dev);
4687	if (ret)
4688		return ret;
4689
4690	ret = mlx5_mkey_cache_init(dev);
4691	if (ret)
4692		mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4693	return ret;
4694}
4695
4696static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4697{
4698	struct dentry *root;
4699
4700	if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4701		return 0;
4702
4703	mutex_init(&dev->delay_drop.lock);
4704	dev->delay_drop.dev = dev;
4705	dev->delay_drop.activate = false;
4706	dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4707	INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4708	atomic_set(&dev->delay_drop.rqs_cnt, 0);
4709	atomic_set(&dev->delay_drop.events_cnt, 0);
4710
4711	if (!mlx5_debugfs_root)
4712		return 0;
4713
4714	root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
4715	dev->delay_drop.dir_debugfs = root;
4716
4717	debugfs_create_atomic_t("num_timeout_events", 0400, root,
4718				&dev->delay_drop.events_cnt);
4719	debugfs_create_atomic_t("num_rqs", 0400, root,
4720				&dev->delay_drop.rqs_cnt);
4721	debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4722			    &fops_delay_drop_timeout);
4723	return 0;
4724}
4725
4726static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4727{
4728	if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4729		return;
4730
4731	cancel_work_sync(&dev->delay_drop.delay_drop_work);
4732	if (!dev->delay_drop.dir_debugfs)
4733		return;
4734
4735	debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4736	dev->delay_drop.dir_debugfs = NULL;
4737}
4738
4739static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4740{
4741	struct mlx5_ib_resources *devr = &dev->devr;
4742	int port;
4743
4744	for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4745		INIT_WORK(&devr->ports[port].pkey_change_work,
4746			  pkey_change_handler);
4747
4748	dev->mdev_events.notifier_call = mlx5_ib_event;
4749	mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4750
4751	mlx5r_macsec_event_register(dev);
4752
4753	return 0;
4754}
4755
4756static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4757{
4758	struct mlx5_ib_resources *devr = &dev->devr;
4759	int port;
4760
4761	mlx5r_macsec_event_unregister(dev);
4762	mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4763
4764	for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4765		cancel_work_sync(&devr->ports[port].pkey_change_work);
4766}
4767
4768void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev,
4769			      struct mlx5_data_direct_dev *dev)
4770{
4771	mutex_lock(&ibdev->data_direct_lock);
4772	ibdev->data_direct_dev = dev;
4773	mutex_unlock(&ibdev->data_direct_lock);
4774}
4775
4776void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev)
4777{
4778	mutex_lock(&ibdev->data_direct_lock);
4779	mlx5_ib_revoke_data_direct_mrs(ibdev);
4780	ibdev->data_direct_dev = NULL;
4781	mutex_unlock(&ibdev->data_direct_lock);
4782}
4783
4784void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4785		      const struct mlx5_ib_profile *profile,
4786		      int stage)
4787{
4788	dev->ib_active = false;
4789
4790	/* Number of stages to cleanup */
4791	while (stage) {
4792		stage--;
4793		if (profile->stage[stage].cleanup)
4794			profile->stage[stage].cleanup(dev);
4795	}
4796
4797	kfree(dev->port);
4798	ib_dealloc_device(&dev->ib_dev);
4799}
4800
4801int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4802		  const struct mlx5_ib_profile *profile)
4803{
4804	int err;
4805	int i;
4806
4807	dev->profile = profile;
4808
4809	for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4810		if (profile->stage[i].init) {
4811			err = profile->stage[i].init(dev);
4812			if (err)
4813				goto err_out;
4814		}
4815	}
4816
4817	dev->ib_active = true;
4818	return 0;
4819
4820err_out:
4821	/* Clean up stages which were initialized */
4822	while (i) {
4823		i--;
4824		if (profile->stage[i].cleanup)
4825			profile->stage[i].cleanup(dev);
4826	}
4827	return -ENOMEM;
4828}
4829
4830static const struct mlx5_ib_profile pf_profile = {
4831	STAGE_CREATE(MLX5_IB_STAGE_INIT,
4832		     mlx5_ib_stage_init_init,
4833		     mlx5_ib_stage_init_cleanup),
4834	STAGE_CREATE(MLX5_IB_STAGE_FS,
4835		     mlx5_ib_fs_init,
4836		     mlx5_ib_fs_cleanup),
4837	STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4838		     mlx5_ib_stage_caps_init,
4839		     mlx5_ib_stage_caps_cleanup),
4840	STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4841		     mlx5_ib_stage_non_default_cb,
4842		     NULL),
4843	STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4844		     mlx5_ib_roce_init,
4845		     mlx5_ib_roce_cleanup),
4846	STAGE_CREATE(MLX5_IB_STAGE_QP,
4847		     mlx5_init_qp_table,
4848		     mlx5_cleanup_qp_table),
4849	STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4850		     mlx5_init_srq_table,
4851		     mlx5_cleanup_srq_table),
4852	STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4853		     mlx5_ib_dev_res_init,
4854		     mlx5_ib_dev_res_cleanup),
4855	STAGE_CREATE(MLX5_IB_STAGE_ODP,
4856		     mlx5_ib_odp_init_one,
4857		     mlx5_ib_odp_cleanup_one),
4858	STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4859		     mlx5_ib_counters_init,
4860		     mlx5_ib_counters_cleanup),
4861	STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4862		     mlx5_ib_stage_cong_debugfs_init,
4863		     mlx5_ib_stage_cong_debugfs_cleanup),
4864	STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4865		     mlx5_ib_stage_bfrag_init,
4866		     mlx5_ib_stage_bfrag_cleanup),
4867	STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4868		     NULL,
4869		     mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4870	STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4871		     mlx5_ib_devx_init,
4872		     mlx5_ib_devx_cleanup),
4873	STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER,
4874		     mlx5_ib_stage_sys_error_notifier_init,
4875		     mlx5_ib_stage_sys_error_notifier_cleanup),
4876	STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4877		     mlx5_ib_stage_ib_reg_init,
4878		     mlx5_ib_stage_ib_reg_cleanup),
4879	STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4880		     mlx5_ib_stage_dev_notifier_init,
4881		     mlx5_ib_stage_dev_notifier_cleanup),
4882	STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4883		     mlx5_ib_stage_post_ib_reg_umr_init,
4884		     NULL),
4885	STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4886		     mlx5_ib_stage_delay_drop_init,
4887		     mlx5_ib_stage_delay_drop_cleanup),
4888	STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4889		     mlx5_ib_restrack_init,
4890		     NULL),
4891};
4892
4893const struct mlx5_ib_profile raw_eth_profile = {
4894	STAGE_CREATE(MLX5_IB_STAGE_INIT,
4895		     mlx5_ib_stage_init_init,
4896		     mlx5_ib_stage_init_cleanup),
4897	STAGE_CREATE(MLX5_IB_STAGE_FS,
4898		     mlx5_ib_fs_init,
4899		     mlx5_ib_fs_cleanup),
4900	STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4901		     mlx5_ib_stage_caps_init,
4902		     mlx5_ib_stage_caps_cleanup),
4903	STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4904		     mlx5_ib_stage_raw_eth_non_default_cb,
4905		     NULL),
4906	STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4907		     mlx5_ib_roce_init,
4908		     mlx5_ib_roce_cleanup),
4909	STAGE_CREATE(MLX5_IB_STAGE_QP,
4910		     mlx5_init_qp_table,
4911		     mlx5_cleanup_qp_table),
4912	STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4913		     mlx5_init_srq_table,
4914		     mlx5_cleanup_srq_table),
4915	STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4916		     mlx5_ib_dev_res_init,
4917		     mlx5_ib_dev_res_cleanup),
4918	STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4919		     mlx5_ib_counters_init,
4920		     mlx5_ib_counters_cleanup),
4921	STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4922		     mlx5_ib_stage_cong_debugfs_init,
4923		     mlx5_ib_stage_cong_debugfs_cleanup),
4924	STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4925		     mlx5_ib_stage_bfrag_init,
4926		     mlx5_ib_stage_bfrag_cleanup),
4927	STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4928		     NULL,
4929		     mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4930	STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4931		     mlx5_ib_devx_init,
4932		     mlx5_ib_devx_cleanup),
4933	STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER,
4934		     mlx5_ib_stage_sys_error_notifier_init,
4935		     mlx5_ib_stage_sys_error_notifier_cleanup),
4936	STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4937		     mlx5_ib_stage_ib_reg_init,
4938		     mlx5_ib_stage_ib_reg_cleanup),
4939	STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4940		     mlx5_ib_stage_dev_notifier_init,
4941		     mlx5_ib_stage_dev_notifier_cleanup),
4942	STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4943		     mlx5_ib_stage_post_ib_reg_umr_init,
4944		     NULL),
4945	STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4946		     mlx5_ib_stage_delay_drop_init,
4947		     mlx5_ib_stage_delay_drop_cleanup),
4948	STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4949		     mlx5_ib_restrack_init,
4950		     NULL),
4951};
4952
4953static const struct mlx5_ib_profile plane_profile = {
4954	STAGE_CREATE(MLX5_IB_STAGE_INIT,
4955		     mlx5_ib_stage_init_init,
4956		     mlx5_ib_stage_init_cleanup),
4957	STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4958		     mlx5_ib_stage_caps_init,
4959		     mlx5_ib_stage_caps_cleanup),
4960	STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4961		     mlx5_ib_stage_non_default_cb,
4962		     NULL),
4963	STAGE_CREATE(MLX5_IB_STAGE_QP,
4964		     mlx5_init_qp_table,
4965		     mlx5_cleanup_qp_table),
4966	STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4967		     mlx5_init_srq_table,
4968		     mlx5_cleanup_srq_table),
4969	STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4970		     mlx5_ib_dev_res_init,
4971		     mlx5_ib_dev_res_cleanup),
4972	STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4973		     mlx5_ib_stage_bfrag_init,
4974		     mlx5_ib_stage_bfrag_cleanup),
4975	STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4976		     mlx5_ib_stage_ib_reg_init,
4977		     mlx5_ib_stage_ib_reg_cleanup),
4978};
4979
4980static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4981					     enum rdma_nl_dev_type type,
4982					     const char *name)
4983{
4984	struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane;
4985	enum rdma_link_layer ll;
4986	int ret;
4987
4988	if (mparent->smi_dev)
4989		return ERR_PTR(-EEXIST);
4990
4991	ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev,
4992							port_type));
4993	if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane ||
4994	    ll != IB_LINK_LAYER_INFINIBAND ||
4995	    !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud))
4996		return ERR_PTR(-EOPNOTSUPP);
4997
4998	mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev,
4999					  mlx5_core_net(mparent->mdev));
5000	if (!mplane)
5001		return ERR_PTR(-ENOMEM);
5002
5003	mplane->port = kcalloc(mparent->num_plane * mparent->num_ports,
5004			       sizeof(*mplane->port), GFP_KERNEL);
5005	if (!mplane->port) {
5006		ret = -ENOMEM;
5007		goto fail_kcalloc;
5008	}
5009
5010	mplane->ib_dev.type = type;
5011	mplane->mdev = mparent->mdev;
5012	mplane->num_ports = mparent->num_plane;
5013	mplane->sub_dev_name = name;
5014	mplane->ib_dev.phys_port_cnt = mplane->num_ports;
5015
5016	ret = __mlx5_ib_add(mplane, &plane_profile);
5017	if (ret)
5018		goto fail_ib_add;
5019
5020	mparent->smi_dev = mplane;
5021	return &mplane->ib_dev;
5022
5023fail_ib_add:
5024	kfree(mplane->port);
5025fail_kcalloc:
5026	ib_dealloc_device(&mplane->ib_dev);
5027	return ERR_PTR(ret);
5028}
5029
5030static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev)
5031{
5032	struct mlx5_ib_dev *mdev = to_mdev(sub_dev);
5033
5034	to_mdev(sub_dev->parent)->smi_dev = NULL;
5035	__mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX);
5036}
5037
5038static int mlx5r_mp_probe(struct auxiliary_device *adev,
5039			  const struct auxiliary_device_id *id)
5040{
5041	struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
5042	struct mlx5_core_dev *mdev = idev->mdev;
5043	struct mlx5_ib_multiport_info *mpi;
5044	struct mlx5_ib_dev *dev;
5045	bool bound = false;
5046	int err;
5047
5048	mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5049	if (!mpi)
5050		return -ENOMEM;
5051
5052	mpi->mdev = mdev;
5053	err = mlx5_query_nic_vport_system_image_guid(mdev,
5054						     &mpi->sys_image_guid);
5055	if (err) {
5056		kfree(mpi);
5057		return err;
5058	}
5059
5060	mutex_lock(&mlx5_ib_multiport_mutex);
5061	list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5062		if (dev->sys_image_guid == mpi->sys_image_guid &&
5063		    mlx5_core_same_coredev_type(dev->mdev, mpi->mdev))
5064			bound = mlx5_ib_bind_slave_port(dev, mpi);
5065
5066		if (bound) {
5067			rdma_roce_rescan_device(&dev->ib_dev);
5068			mpi->ibdev->ib_active = true;
5069			break;
5070		}
5071	}
5072
5073	if (!bound) {
5074		list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5075		dev_dbg(mdev->device,
5076			"no suitable IB device found to bind to, added to unaffiliated list.\n");
5077	}
5078	mutex_unlock(&mlx5_ib_multiport_mutex);
5079
5080	auxiliary_set_drvdata(adev, mpi);
5081	return 0;
5082}
5083
5084static void mlx5r_mp_remove(struct auxiliary_device *adev)
5085{
5086	struct mlx5_ib_multiport_info *mpi;
5087
5088	mpi = auxiliary_get_drvdata(adev);
5089	mutex_lock(&mlx5_ib_multiport_mutex);
5090	if (mpi->ibdev)
5091		mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5092	else
5093		list_del(&mpi->list);
5094	mutex_unlock(&mlx5_ib_multiport_mutex);
5095	kfree(mpi);
5096}
5097
5098static int mlx5r_probe(struct auxiliary_device *adev,
5099		       const struct auxiliary_device_id *id)
5100{
5101	struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
5102	struct mlx5_core_dev *mdev = idev->mdev;
5103	const struct mlx5_ib_profile *profile;
5104	int port_type_cap, num_ports, ret;
5105	enum rdma_link_layer ll;
5106	struct mlx5_ib_dev *dev;
5107
5108	port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5109	ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5110
5111	num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5112			MLX5_CAP_GEN(mdev, num_vhca_ports));
5113	dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev,
5114				       mlx5_core_net(mdev));
5115	if (!dev)
5116		return -ENOMEM;
5117
5118	if (ll == IB_LINK_LAYER_INFINIBAND) {
5119		ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane);
5120		if (ret)
5121			goto fail;
5122	}
5123
5124	dev->port = kcalloc(num_ports, sizeof(*dev->port),
5125			     GFP_KERNEL);
5126	if (!dev->port) {
5127		ret = -ENOMEM;
5128		goto fail;
5129	}
5130
5131	dev->mdev = mdev;
5132	dev->num_ports = num_ports;
5133	dev->ib_dev.phys_port_cnt = num_ports;
5134
5135	if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev))
5136		profile = &raw_eth_profile;
5137	else
5138		profile = &pf_profile;
5139
5140	ret = __mlx5_ib_add(dev, profile);
5141	if (ret)
5142		goto fail_ib_add;
5143
5144	auxiliary_set_drvdata(adev, dev);
5145	return 0;
5146
5147fail_ib_add:
5148	kfree(dev->port);
5149fail:
5150	ib_dealloc_device(&dev->ib_dev);
5151	return ret;
5152}
5153
5154static void mlx5r_remove(struct auxiliary_device *adev)
5155{
5156	struct mlx5_ib_dev *dev;
5157
5158	dev = auxiliary_get_drvdata(adev);
5159	__mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5160}
5161
5162static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
5163	{ .name = MLX5_ADEV_NAME ".multiport", },
5164	{},
5165};
5166
5167static const struct auxiliary_device_id mlx5r_id_table[] = {
5168	{ .name = MLX5_ADEV_NAME ".rdma", },
5169	{},
5170};
5171
5172MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
5173MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
5174
5175static struct auxiliary_driver mlx5r_mp_driver = {
5176	.name = "multiport",
5177	.probe = mlx5r_mp_probe,
5178	.remove = mlx5r_mp_remove,
5179	.id_table = mlx5r_mp_id_table,
5180};
5181
5182static struct auxiliary_driver mlx5r_driver = {
5183	.name = "rdma",
5184	.probe = mlx5r_probe,
5185	.remove = mlx5r_remove,
5186	.id_table = mlx5r_id_table,
5187};
5188
5189static int __init mlx5_ib_init(void)
5190{
5191	int ret;
5192
5193	xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
5194	if (!xlt_emergency_page)
5195		return -ENOMEM;
5196
5197	mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5198	if (!mlx5_ib_event_wq) {
5199		free_page((unsigned long)xlt_emergency_page);
5200		return -ENOMEM;
5201	}
5202
5203	ret = mlx5_ib_qp_event_init();
5204	if (ret)
5205		goto qp_event_err;
5206
5207	mlx5_ib_odp_init();
5208	ret = mlx5r_rep_init();
5209	if (ret)
5210		goto rep_err;
5211	ret = mlx5_data_direct_driver_register();
5212	if (ret)
5213		goto dd_err;
5214	ret = auxiliary_driver_register(&mlx5r_mp_driver);
5215	if (ret)
5216		goto mp_err;
5217	ret = auxiliary_driver_register(&mlx5r_driver);
5218	if (ret)
5219		goto drv_err;
5220
5221	return 0;
5222
5223drv_err:
5224	auxiliary_driver_unregister(&mlx5r_mp_driver);
5225mp_err:
5226	mlx5_data_direct_driver_unregister();
5227dd_err:
5228	mlx5r_rep_cleanup();
5229rep_err:
5230	mlx5_ib_qp_event_cleanup();
5231qp_event_err:
5232	destroy_workqueue(mlx5_ib_event_wq);
5233	free_page((unsigned long)xlt_emergency_page);
5234	return ret;
5235}
5236
5237static void __exit mlx5_ib_cleanup(void)
5238{
5239	mlx5_data_direct_driver_unregister();
5240	auxiliary_driver_unregister(&mlx5r_driver);
5241	auxiliary_driver_unregister(&mlx5r_mp_driver);
5242	mlx5r_rep_cleanup();
5243
5244	mlx5_ib_qp_event_cleanup();
5245	destroy_workqueue(mlx5_ib_event_wq);
5246	free_page((unsigned long)xlt_emergency_page);
5247}
5248
5249module_init(mlx5_ib_init);
5250module_exit(mlx5_ib_cleanup);