qp.c

   1/*
   2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenIB.org BSD license below:
  10 *
  11 *     Redistribution and use in source and binary forms, with or
  12 *     without modification, are permitted provided that the following
  13 *     conditions are met:
  14 *
  15 *      - Redistributions of source code must retain the above
  16 *        copyright notice, this list of conditions and the following
  17 *        disclaimer.
  18 *
  19 *      - Redistributions in binary form must reproduce the above
  20 *        copyright notice, this list of conditions and the following
  21 *        disclaimer in the documentation and/or other materials
  22 *        provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 */
  33
  34#include <linux/log2.h>
  35#include <linux/etherdevice.h>
  36#include <net/ip.h>
  37#include <linux/slab.h>
  38#include <linux/netdevice.h>
  39
  40#include <rdma/ib_cache.h>
  41#include <rdma/ib_pack.h>
  42#include <rdma/ib_addr.h>
  43#include <rdma/ib_mad.h>
  44#include <rdma/uverbs_ioctl.h>
  45
  46#include <linux/mlx4/driver.h>
  47#include <linux/mlx4/qp.h>
  48
  49#include "mlx4_ib.h"
  50#include <rdma/mlx4-abi.h>
  51
  52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  53			     struct mlx4_ib_cq *recv_cq);
  54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  55			       struct mlx4_ib_cq *recv_cq);
  56static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
  57			      struct ib_udata *udata);
  58
  59enum {
  60	MLX4_IB_ACK_REQ_FREQ	= 8,
  61};
  62
  63enum {
  64	MLX4_IB_DEFAULT_SCHED_QUEUE	= 0x83,
  65	MLX4_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
  66	MLX4_IB_LINK_TYPE_IB		= 0,
  67	MLX4_IB_LINK_TYPE_ETH		= 1
  68};
  69
  70enum {
  71	MLX4_IB_MIN_SQ_STRIDE	= 6,
  72	MLX4_IB_CACHE_LINE_SIZE	= 64,
  73};
  74
  75enum {
  76	MLX4_RAW_QP_MTU		= 7,
  77	MLX4_RAW_QP_MSGMAX	= 31,
  78};
  79
  80#ifndef ETH_ALEN
  81#define ETH_ALEN        6
  82#endif
  83
  84static const __be32 mlx4_ib_opcode[] = {
  85	[IB_WR_SEND]				= cpu_to_be32(MLX4_OPCODE_SEND),
  86	[IB_WR_LSO]				= cpu_to_be32(MLX4_OPCODE_LSO),
  87	[IB_WR_SEND_WITH_IMM]			= cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  88	[IB_WR_RDMA_WRITE]			= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  89	[IB_WR_RDMA_WRITE_WITH_IMM]		= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  90	[IB_WR_RDMA_READ]			= cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  91	[IB_WR_ATOMIC_CMP_AND_SWP]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  92	[IB_WR_ATOMIC_FETCH_AND_ADD]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  93	[IB_WR_SEND_WITH_INV]			= cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
  94	[IB_WR_LOCAL_INV]			= cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
  95	[IB_WR_REG_MR]				= cpu_to_be32(MLX4_OPCODE_FMR),
  96	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
  97	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
  98};
  99
 100enum mlx4_ib_source_type {
 101	MLX4_IB_QP_SRC	= 0,
 102	MLX4_IB_RWQ_SRC	= 1,
 103};
 104
 105struct mlx4_ib_qp_event_work {
 106	struct work_struct work;
 107	struct mlx4_qp *qp;
 108	enum mlx4_event type;
 109};
 110
 111static struct workqueue_struct *mlx4_ib_qp_event_wq;
 112
 113static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 114{
 115	if (!mlx4_is_master(dev->dev))
 116		return 0;
 117
 118	return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 119	       qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 120		8 * MLX4_MFUNC_MAX;
 121}
 122
 123static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 124{
 125	int proxy_sqp = 0;
 126	int real_sqp = 0;
 127	int i;
 128	/* PPF or Native -- real SQP */
 129	real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 130		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 131		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 132	if (real_sqp)
 133		return 1;
 134	/* VF or PF -- proxy SQP */
 135	if (mlx4_is_mfunc(dev->dev)) {
 136		for (i = 0; i < dev->dev->caps.num_ports; i++) {
 137			if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
 138			    qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
 139				proxy_sqp = 1;
 140				break;
 141			}
 142		}
 143	}
 144	if (proxy_sqp)
 145		return 1;
 146
 147	return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 148}
 149
 150/* used for INIT/CLOSE port logic */
 151static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 152{
 153	int proxy_qp0 = 0;
 154	int real_qp0 = 0;
 155	int i;
 156	/* PPF or Native -- real QP0 */
 157	real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 158		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 159		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 160	if (real_qp0)
 161		return 1;
 162	/* VF or PF -- proxy QP0 */
 163	if (mlx4_is_mfunc(dev->dev)) {
 164		for (i = 0; i < dev->dev->caps.num_ports; i++) {
 165			if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
 166				proxy_qp0 = 1;
 167				break;
 168			}
 169		}
 170	}
 171	return proxy_qp0;
 172}
 173
 174static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 175{
 176	return mlx4_buf_offset(&qp->buf, offset);
 177}
 178
 179static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 180{
 181	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 182}
 183
 184static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 185{
 186	return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 187}
 188
 189/*
 190 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 191 * first four bytes of every 64 byte chunk with 0xffffffff, except for
 192 * the very first chunk of the WQE.
 193 */
 194static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
 195{
 196	__be32 *wqe;
 197	int i;
 198	int s;
 199	void *buf;
 200	struct mlx4_wqe_ctrl_seg *ctrl;
 201
 202	buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 203	ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
 204	s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 205	for (i = 64; i < s; i += 64) {
 206		wqe = buf + i;
 207		*wqe = cpu_to_be32(0xffffffff);
 208	}
 209}
 210
 211static void mlx4_ib_handle_qp_event(struct work_struct *_work)
 212{
 213	struct mlx4_ib_qp_event_work *qpe_work =
 214		container_of(_work, struct mlx4_ib_qp_event_work, work);
 215	struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp;
 216	struct ib_event event = {};
 217
 218	event.device = ibqp->device;
 219	event.element.qp = ibqp;
 220
 221	switch (qpe_work->type) {
 222	case MLX4_EVENT_TYPE_PATH_MIG:
 223		event.event = IB_EVENT_PATH_MIG;
 224		break;
 225	case MLX4_EVENT_TYPE_COMM_EST:
 226		event.event = IB_EVENT_COMM_EST;
 227		break;
 228	case MLX4_EVENT_TYPE_SQ_DRAINED:
 229		event.event = IB_EVENT_SQ_DRAINED;
 230		break;
 231	case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 232		event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 233		break;
 234	case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 235		event.event = IB_EVENT_QP_FATAL;
 236		break;
 237	case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 238		event.event = IB_EVENT_PATH_MIG_ERR;
 239		break;
 240	case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 241		event.event = IB_EVENT_QP_REQ_ERR;
 242		break;
 243	case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 244		event.event = IB_EVENT_QP_ACCESS_ERR;
 245		break;
 246	default:
 247		pr_warn("Unexpected event type %d on QP %06x\n",
 248			qpe_work->type, qpe_work->qp->qpn);
 249		goto out;
 250	}
 251
 252	ibqp->event_handler(&event, ibqp->qp_context);
 253
 254out:
 255	mlx4_put_qp(qpe_work->qp);
 256	kfree(qpe_work);
 257}
 258
 259static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 260{
 261	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 262	struct mlx4_ib_qp_event_work *qpe_work;
 263
 264	if (type == MLX4_EVENT_TYPE_PATH_MIG)
 265		to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 266
 267	if (!ibqp->event_handler)
 268		goto out_no_handler;
 269
 270	qpe_work = kzalloc(sizeof(*qpe_work), GFP_ATOMIC);
 271	if (!qpe_work)
 272		goto out_no_handler;
 273
 274	qpe_work->qp = qp;
 275	qpe_work->type = type;
 276	INIT_WORK(&qpe_work->work, mlx4_ib_handle_qp_event);
 277	queue_work(mlx4_ib_qp_event_wq, &qpe_work->work);
 278	return;
 279
 280out_no_handler:
 281	mlx4_put_qp(qp);
 282}
 283
 284static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
 285{
 286	pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
 287			    type, qp->qpn);
 288}
 289
 290static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 291{
 292	/*
 293	 * UD WQEs must have a datagram segment.
 294	 * RC and UC WQEs might have a remote address segment.
 295	 * MLX WQEs need two extra inline data segments (for the UD
 296	 * header and space for the ICRC).
 297	 */
 298	switch (type) {
 299	case MLX4_IB_QPT_UD:
 300		return sizeof (struct mlx4_wqe_ctrl_seg) +
 301			sizeof (struct mlx4_wqe_datagram_seg) +
 302			((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 303	case MLX4_IB_QPT_PROXY_SMI_OWNER:
 304	case MLX4_IB_QPT_PROXY_SMI:
 305	case MLX4_IB_QPT_PROXY_GSI:
 306		return sizeof (struct mlx4_wqe_ctrl_seg) +
 307			sizeof (struct mlx4_wqe_datagram_seg) + 64;
 308	case MLX4_IB_QPT_TUN_SMI_OWNER:
 309	case MLX4_IB_QPT_TUN_GSI:
 310		return sizeof (struct mlx4_wqe_ctrl_seg) +
 311			sizeof (struct mlx4_wqe_datagram_seg);
 312
 313	case MLX4_IB_QPT_UC:
 314		return sizeof (struct mlx4_wqe_ctrl_seg) +
 315			sizeof (struct mlx4_wqe_raddr_seg);
 316	case MLX4_IB_QPT_RC:
 317		return sizeof (struct mlx4_wqe_ctrl_seg) +
 318			sizeof (struct mlx4_wqe_masked_atomic_seg) +
 319			sizeof (struct mlx4_wqe_raddr_seg);
 320	case MLX4_IB_QPT_SMI:
 321	case MLX4_IB_QPT_GSI:
 322		return sizeof (struct mlx4_wqe_ctrl_seg) +
 323			ALIGN(MLX4_IB_UD_HEADER_SIZE +
 324			      DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 325					   MLX4_INLINE_ALIGN) *
 326			      sizeof (struct mlx4_wqe_inline_seg),
 327			      sizeof (struct mlx4_wqe_data_seg)) +
 328			ALIGN(4 +
 329			      sizeof (struct mlx4_wqe_inline_seg),
 330			      sizeof (struct mlx4_wqe_data_seg));
 331	default:
 332		return sizeof (struct mlx4_wqe_ctrl_seg);
 333	}
 334}
 335
 336static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 337		       bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
 338		       u32 inl_recv_sz)
 339{
 340	/* Sanity check RQ size before proceeding */
 341	if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 342	    cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 343		return -EINVAL;
 344
 345	if (!has_rq) {
 346		if (cap->max_recv_wr || inl_recv_sz)
 347			return -EINVAL;
 348
 349		qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 350	} else {
 351		u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
 352			sizeof(struct mlx4_wqe_data_seg);
 353		u32 wqe_size;
 354
 355		/* HW requires >= 1 RQ entry with >= 1 gather entry */
 356		if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
 357				inl_recv_sz > max_inl_recv_sz))
 358			return -EINVAL;
 359
 360		qp->rq.wqe_cnt	 = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 361		qp->rq.max_gs	 = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 362		wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
 363		qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
 364	}
 365
 366	/* leave userspace return values as they were, so as not to break ABI */
 367	if (is_user) {
 368		cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 369		cap->max_recv_sge = qp->rq.max_gs;
 370	} else {
 371		cap->max_recv_wr  = qp->rq.max_post =
 372			min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 373		cap->max_recv_sge = min(qp->rq.max_gs,
 374					min(dev->dev->caps.max_sq_sg,
 375					    dev->dev->caps.max_rq_sg));
 376	}
 377
 378	return 0;
 379}
 380
 381static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 382			      enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 383{
 384	int s;
 385
 386	/* Sanity check SQ size before proceeding */
 387	if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 388	    cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 389	    cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 390	    sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 391		return -EINVAL;
 392
 393	/*
 394	 * For MLX transport we need 2 extra S/G entries:
 395	 * one for the header and one for the checksum at the end
 396	 */
 397	if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 398	     type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 399	    cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 400		return -EINVAL;
 401
 402	s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 403		cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 404		send_wqe_overhead(type, qp->flags);
 405
 406	if (s > dev->dev->caps.max_sq_desc_sz)
 407		return -EINVAL;
 408
 409	qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 410
 411	/*
 412	 * We need to leave 2 KB + 1 WR of headroom in the SQ to
 413	 * allow HW to prefetch.
 414	 */
 415	qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
 416	qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
 417					    qp->sq_spare_wqes);
 418
 419	qp->sq.max_gs =
 420		(min(dev->dev->caps.max_sq_desc_sz,
 421		     (1 << qp->sq.wqe_shift)) -
 422		 send_wqe_overhead(type, qp->flags)) /
 423		sizeof (struct mlx4_wqe_data_seg);
 424
 425	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 426		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
 427	if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 428		qp->rq.offset = 0;
 429		qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 430	} else {
 431		qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 432		qp->sq.offset = 0;
 433	}
 434
 435	cap->max_send_wr  = qp->sq.max_post =
 436		qp->sq.wqe_cnt - qp->sq_spare_wqes;
 437	cap->max_send_sge = min(qp->sq.max_gs,
 438				min(dev->dev->caps.max_sq_sg,
 439				    dev->dev->caps.max_rq_sg));
 440	/* We don't support inline sends for kernel QPs (yet) */
 441	cap->max_inline_data = 0;
 442
 443	return 0;
 444}
 445
 446static int set_user_sq_size(struct mlx4_ib_dev *dev,
 447			    struct mlx4_ib_qp *qp,
 448			    struct mlx4_ib_create_qp *ucmd)
 449{
 450	u32 cnt;
 451
 452	/* Sanity check SQ size before proceeding */
 453	if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) ||
 454	    cnt > dev->dev->caps.max_wqes)
 455		return -EINVAL;
 456	if (ucmd->log_sq_stride >
 457		ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 458	    ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 459		return -EINVAL;
 460
 461	qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 462	qp->sq.wqe_shift = ucmd->log_sq_stride;
 463
 464	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 465		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
 466
 467	return 0;
 468}
 469
 470static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 471{
 472	int i;
 473
 474	qp->sqp_proxy_rcv =
 475		kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
 476			      GFP_KERNEL);
 477	if (!qp->sqp_proxy_rcv)
 478		return -ENOMEM;
 479	for (i = 0; i < qp->rq.wqe_cnt; i++) {
 480		qp->sqp_proxy_rcv[i].addr =
 481			kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 482				GFP_KERNEL);
 483		if (!qp->sqp_proxy_rcv[i].addr)
 484			goto err;
 485		qp->sqp_proxy_rcv[i].map =
 486			ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 487					  sizeof (struct mlx4_ib_proxy_sqp_hdr),
 488					  DMA_FROM_DEVICE);
 489		if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 490			kfree(qp->sqp_proxy_rcv[i].addr);
 491			goto err;
 492		}
 493	}
 494	return 0;
 495
 496err:
 497	while (i > 0) {
 498		--i;
 499		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 500				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
 501				    DMA_FROM_DEVICE);
 502		kfree(qp->sqp_proxy_rcv[i].addr);
 503	}
 504	kfree(qp->sqp_proxy_rcv);
 505	qp->sqp_proxy_rcv = NULL;
 506	return -ENOMEM;
 507}
 508
 509static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 510{
 511	int i;
 512
 513	for (i = 0; i < qp->rq.wqe_cnt; i++) {
 514		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 515				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
 516				    DMA_FROM_DEVICE);
 517		kfree(qp->sqp_proxy_rcv[i].addr);
 518	}
 519	kfree(qp->sqp_proxy_rcv);
 520}
 521
 522static bool qp_has_rq(struct ib_qp_init_attr *attr)
 523{
 524	if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 525		return false;
 526
 527	return !attr->srq;
 528}
 529
 530static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 531{
 532	int i;
 533	for (i = 0; i < dev->caps.num_ports; i++) {
 534		if (qpn == dev->caps.spec_qps[i].qp0_proxy)
 535			return !!dev->caps.spec_qps[i].qp0_qkey;
 536	}
 537	return 0;
 538}
 539
 540static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 541				    struct mlx4_ib_qp *qp)
 542{
 543	mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 544	mlx4_counter_free(dev->dev, qp->counter_index->index);
 545	list_del(&qp->counter_index->list);
 546	mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 547
 548	kfree(qp->counter_index);
 549	qp->counter_index = NULL;
 550}
 551
 552static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
 553		      struct ib_qp_init_attr *init_attr,
 554		      struct mlx4_ib_create_qp_rss *ucmd)
 555{
 556	rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
 557		(init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
 558
 559	if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
 560	    (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
 561		memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
 562		       MLX4_EN_RSS_KEY_SIZE);
 563	} else {
 564		pr_debug("RX Hash function is not supported\n");
 565		return (-EOPNOTSUPP);
 566	}
 567
 568	if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4	|
 569					       MLX4_IB_RX_HASH_DST_IPV4	|
 570					       MLX4_IB_RX_HASH_SRC_IPV6	|
 571					       MLX4_IB_RX_HASH_DST_IPV6	|
 572					       MLX4_IB_RX_HASH_SRC_PORT_TCP |
 573					       MLX4_IB_RX_HASH_DST_PORT_TCP |
 574					       MLX4_IB_RX_HASH_SRC_PORT_UDP |
 575					       MLX4_IB_RX_HASH_DST_PORT_UDP |
 576					       MLX4_IB_RX_HASH_INNER)) {
 577		pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
 578			 ucmd->rx_hash_fields_mask);
 579		return (-EOPNOTSUPP);
 580	}
 581
 582	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
 583	    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 584		rss_ctx->flags = MLX4_RSS_IPV4;
 585	} else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
 586		   (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 587		pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
 588		return (-EOPNOTSUPP);
 589	}
 590
 591	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
 592	    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 593		rss_ctx->flags |= MLX4_RSS_IPV6;
 594	} else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
 595		   (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 596		pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
 597		return (-EOPNOTSUPP);
 598	}
 599
 600	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
 601	    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 602		if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
 603			pr_debug("RX Hash fields_mask for UDP is not supported\n");
 604			return (-EOPNOTSUPP);
 605		}
 606
 607		if (rss_ctx->flags & MLX4_RSS_IPV4)
 608			rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
 609		if (rss_ctx->flags & MLX4_RSS_IPV6)
 610			rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
 611		if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 612			pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
 613			return (-EOPNOTSUPP);
 614		}
 615	} else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
 616		   (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 617		pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
 618		return (-EOPNOTSUPP);
 619	}
 620
 621	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
 622	    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 623		if (rss_ctx->flags & MLX4_RSS_IPV4)
 624			rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
 625		if (rss_ctx->flags & MLX4_RSS_IPV6)
 626			rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
 627		if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 628			pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
 629			return (-EOPNOTSUPP);
 630		}
 631	} else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
 632		   (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 633		pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
 634		return (-EOPNOTSUPP);
 635	}
 636
 637	if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
 638		if (dev->dev->caps.tunnel_offload_mode ==
 639		    MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
 640			/*
 641			 * Hash according to inner headers if exist, otherwise
 642			 * according to outer headers.
 643			 */
 644			rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
 645		} else {
 646			pr_debug("RSS Hash for inner headers isn't supported\n");
 647			return (-EOPNOTSUPP);
 648		}
 649	}
 650
 651	return 0;
 652}
 653
 654static int create_qp_rss(struct mlx4_ib_dev *dev,
 655			 struct ib_qp_init_attr *init_attr,
 656			 struct mlx4_ib_create_qp_rss *ucmd,
 657			 struct mlx4_ib_qp *qp)
 658{
 659	int qpn;
 660	int err;
 661
 662	qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 663
 664	err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
 665	if (err)
 666		return err;
 667
 668	err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 669	if (err)
 670		goto err_qpn;
 671
 672	INIT_LIST_HEAD(&qp->gid_list);
 673	INIT_LIST_HEAD(&qp->steering_rules);
 674
 675	qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 676	qp->state = IB_QPS_RESET;
 677
 678	/* Set dummy send resources to be compatible with HV and PRM */
 679	qp->sq_no_prefetch = 1;
 680	qp->sq.wqe_cnt = 1;
 681	qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 682	qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
 683	qp->mtt = (to_mqp(
 684		   (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
 685
 686	qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
 687	if (!qp->rss_ctx) {
 688		err = -ENOMEM;
 689		goto err_qp_alloc;
 690	}
 691
 692	err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
 693	if (err)
 694		goto err;
 695
 696	return 0;
 697
 698err:
 699	kfree(qp->rss_ctx);
 700
 701err_qp_alloc:
 702	mlx4_qp_remove(dev->dev, &qp->mqp);
 703	mlx4_qp_free(dev->dev, &qp->mqp);
 704
 705err_qpn:
 706	mlx4_qp_release_range(dev->dev, qpn, 1);
 707	return err;
 708}
 709
 710static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp,
 711				  struct ib_qp_init_attr *init_attr,
 712				  struct ib_udata *udata)
 713{
 714	struct mlx4_ib_create_qp_rss ucmd = {};
 715	size_t required_cmd_sz;
 716	int err;
 717
 718	if (!udata) {
 719		pr_debug("RSS QP with NULL udata\n");
 720		return -EINVAL;
 721	}
 722
 723	if (udata->outlen)
 724		return -EOPNOTSUPP;
 725
 726	required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
 727					sizeof(ucmd.reserved1);
 728	if (udata->inlen < required_cmd_sz) {
 729		pr_debug("invalid inlen\n");
 730		return -EINVAL;
 731	}
 732
 733	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
 734		pr_debug("copy failed\n");
 735		return -EFAULT;
 736	}
 737
 738	if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
 739		return -EOPNOTSUPP;
 740
 741	if (ucmd.comp_mask || ucmd.reserved1)
 742		return -EOPNOTSUPP;
 743
 744	if (udata->inlen > sizeof(ucmd) &&
 745	    !ib_is_udata_cleared(udata, sizeof(ucmd),
 746				 udata->inlen - sizeof(ucmd))) {
 747		pr_debug("inlen is not supported\n");
 748		return -EOPNOTSUPP;
 749	}
 750
 751	if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
 752		pr_debug("RSS QP with unsupported QP type %d\n",
 753			 init_attr->qp_type);
 754		return -EOPNOTSUPP;
 755	}
 756
 757	if (init_attr->create_flags) {
 758		pr_debug("RSS QP doesn't support create flags\n");
 759		return -EOPNOTSUPP;
 760	}
 761
 762	if (init_attr->send_cq || init_attr->cap.max_send_wr) {
 763		pr_debug("RSS QP with unsupported send attributes\n");
 764		return -EOPNOTSUPP;
 765	}
 766
 767	qp->pri.vid = 0xFFFF;
 768	qp->alt.vid = 0xFFFF;
 769
 770	err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
 771	if (err)
 772		return err;
 773
 774	qp->ibqp.qp_num = qp->mqp.qpn;
 775	return 0;
 776}
 777
 778/*
 779 * This function allocates a WQN from a range which is consecutive and aligned
 780 * to its size. In case the range is full, then it creates a new range and
 781 * allocates WQN from it. The new range will be used for following allocations.
 782 */
 783static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
 784			     struct mlx4_ib_qp *qp, int range_size, int *wqn)
 785{
 786	struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 787	struct mlx4_wqn_range *range;
 788	int err = 0;
 789
 790	mutex_lock(&context->wqn_ranges_mutex);
 791
 792	range = list_first_entry_or_null(&context->wqn_ranges_list,
 793					 struct mlx4_wqn_range, list);
 794
 795	if (!range || (range->refcount == range->size) || range->dirty) {
 796		range = kzalloc(sizeof(*range), GFP_KERNEL);
 797		if (!range) {
 798			err = -ENOMEM;
 799			goto out;
 800		}
 801
 802		err = mlx4_qp_reserve_range(dev->dev, range_size,
 803					    range_size, &range->base_wqn, 0,
 804					    qp->mqp.usage);
 805		if (err) {
 806			kfree(range);
 807			goto out;
 808		}
 809
 810		range->size = range_size;
 811		list_add(&range->list, &context->wqn_ranges_list);
 812	} else if (range_size != 1) {
 813		/*
 814		 * Requesting a new range (>1) when last range is still open, is
 815		 * not valid.
 816		 */
 817		err = -EINVAL;
 818		goto out;
 819	}
 820
 821	qp->wqn_range = range;
 822
 823	*wqn = range->base_wqn + range->refcount;
 824
 825	range->refcount++;
 826
 827out:
 828	mutex_unlock(&context->wqn_ranges_mutex);
 829
 830	return err;
 831}
 832
 833static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
 834				struct mlx4_ib_qp *qp, bool dirty_release)
 835{
 836	struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 837	struct mlx4_wqn_range *range;
 838
 839	mutex_lock(&context->wqn_ranges_mutex);
 840
 841	range = qp->wqn_range;
 842
 843	range->refcount--;
 844	if (!range->refcount) {
 845		mlx4_qp_release_range(dev->dev, range->base_wqn,
 846				      range->size);
 847		list_del(&range->list);
 848		kfree(range);
 849	} else if (dirty_release) {
 850	/*
 851	 * A range which one of its WQNs is destroyed, won't be able to be
 852	 * reused for further WQN allocations.
 853	 * The next created WQ will allocate a new range.
 854	 */
 855		range->dirty = true;
 856	}
 857
 858	mutex_unlock(&context->wqn_ranges_mutex);
 859}
 860
 861static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
 862		     struct ib_udata *udata, struct mlx4_ib_qp *qp)
 863{
 864	struct mlx4_ib_dev *dev = to_mdev(pd->device);
 865	int qpn;
 866	int err;
 867	struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
 868		udata, struct mlx4_ib_ucontext, ibucontext);
 869	struct mlx4_ib_cq *mcq;
 870	unsigned long flags;
 871	int range_size;
 872	struct mlx4_ib_create_wq wq;
 873	size_t copy_len;
 874	int shift;
 875	int n;
 876
 877	qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 878
 879	spin_lock_init(&qp->sq.lock);
 880	spin_lock_init(&qp->rq.lock);
 881	INIT_LIST_HEAD(&qp->gid_list);
 882	INIT_LIST_HEAD(&qp->steering_rules);
 883
 884	qp->state = IB_QPS_RESET;
 885
 886	copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
 887
 888	if (ib_copy_from_udata(&wq, udata, copy_len)) {
 889		err = -EFAULT;
 890		goto err;
 891	}
 892
 893	if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
 894	    wq.reserved[2]) {
 895		pr_debug("user command isn't supported\n");
 896		err = -EOPNOTSUPP;
 897		goto err;
 898	}
 899
 900	if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
 901		pr_debug("WQN range size must be equal or smaller than %d\n",
 902			 dev->dev->caps.max_rss_tbl_sz);
 903		err = -EOPNOTSUPP;
 904		goto err;
 905	}
 906	range_size = 1 << wq.log_range_size;
 907
 908	if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
 909		qp->flags |= MLX4_IB_QP_SCATTER_FCS;
 910
 911	err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
 912	if (err)
 913		goto err;
 914
 915	qp->sq_no_prefetch = 1;
 916	qp->sq.wqe_cnt = 1;
 917	qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 918	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 919		       (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 920
 921	qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
 922	if (IS_ERR(qp->umem)) {
 923		err = PTR_ERR(qp->umem);
 924		goto err;
 925	}
 926
 927	shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
 928	if (shift < 0) {
 929		err = shift;
 930		goto err_buf;
 931	}
 932
 933	err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
 934	if (err)
 935		goto err_buf;
 936
 937	err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 938	if (err)
 939		goto err_mtt;
 940
 941	err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
 942	if (err)
 943		goto err_mtt;
 944	qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 945
 946	err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
 947	if (err)
 948		goto err_wrid;
 949
 950	err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 951	if (err)
 952		goto err_qpn;
 953
 954	/*
 955	 * Hardware wants QPN written in big-endian order (after
 956	 * shifting) for send doorbell.  Precompute this value to save
 957	 * a little bit when posting sends.
 958	 */
 959	qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 960
 961	qp->mqp.event = mlx4_ib_wq_event;
 962
 963	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 964	mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 965			 to_mcq(init_attr->recv_cq));
 966	/* Maintain device to QPs access, needed for further handling
 967	 * via reset flow
 968	 */
 969	list_add_tail(&qp->qps_list, &dev->qp_list);
 970	/* Maintain CQ to QPs access, needed for further handling
 971	 * via reset flow
 972	 */
 973	mcq = to_mcq(init_attr->send_cq);
 974	list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 975	mcq = to_mcq(init_attr->recv_cq);
 976	list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 977	mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 978			   to_mcq(init_attr->recv_cq));
 979	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 980	return 0;
 981
 982err_qpn:
 983	mlx4_ib_release_wqn(context, qp, 0);
 984err_wrid:
 985	mlx4_ib_db_unmap_user(context, &qp->db);
 986
 987err_mtt:
 988	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 989err_buf:
 990	ib_umem_release(qp->umem);
 991err:
 992	return err;
 993}
 994
 995static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
 996			    struct ib_udata *udata, int sqpn,
 997			    struct mlx4_ib_qp *qp)
 998{
 999	struct mlx4_ib_dev *dev = to_mdev(pd->device);
1000	int qpn;
1001	int err;
1002	struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
1003		udata, struct mlx4_ib_ucontext, ibucontext);
1004	enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
1005	struct mlx4_ib_cq *mcq;
1006	unsigned long flags;
1007
1008	/* When tunneling special qps, we use a plain UD qp */
1009	if (sqpn) {
1010		if (mlx4_is_mfunc(dev->dev) &&
1011		    (!mlx4_is_master(dev->dev) ||
1012		     !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
1013			if (init_attr->qp_type == IB_QPT_GSI)
1014				qp_type = MLX4_IB_QPT_PROXY_GSI;
1015			else {
1016				if (mlx4_is_master(dev->dev) ||
1017				    qp0_enabled_vf(dev->dev, sqpn))
1018					qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
1019				else
1020					qp_type = MLX4_IB_QPT_PROXY_SMI;
1021			}
1022		}
1023		qpn = sqpn;
1024		/* add extra sg entry for tunneling */
1025		init_attr->cap.max_recv_sge++;
1026	} else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1027		struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1028			container_of(init_attr,
1029				     struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1030		if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1031		     tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
1032		    !mlx4_is_master(dev->dev))
1033			return -EINVAL;
1034		if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1035			qp_type = MLX4_IB_QPT_TUN_GSI;
1036		else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1037			 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1038					     tnl_init->port))
1039			qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1040		else
1041			qp_type = MLX4_IB_QPT_TUN_SMI;
1042		/* we are definitely in the PPF here, since we are creating
1043		 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1044		qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1045			+ tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1046		sqpn = qpn;
1047	}
1048
1049	if (init_attr->qp_type == IB_QPT_SMI ||
1050	    init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI ||
1051	    qp_type == MLX4_IB_QPT_GSI ||
1052	    (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1053			MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1054		qp->sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1055		if (!qp->sqp)
1056			return -ENOMEM;
1057	}
1058
1059	qp->mlx4_ib_qp_type = qp_type;
1060
1061	spin_lock_init(&qp->sq.lock);
1062	spin_lock_init(&qp->rq.lock);
1063	INIT_LIST_HEAD(&qp->gid_list);
1064	INIT_LIST_HEAD(&qp->steering_rules);
1065
1066	qp->state = IB_QPS_RESET;
1067	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1068		qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1069
1070	if (udata) {
1071		struct mlx4_ib_create_qp ucmd;
1072		size_t copy_len;
1073		int shift;
1074		int n;
1075
1076		copy_len = sizeof(struct mlx4_ib_create_qp);
1077
1078		if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1079			err = -EFAULT;
1080			goto err;
1081		}
1082
1083		qp->inl_recv_sz = ucmd.inl_recv_sz;
1084
1085		if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1086			if (!(dev->dev->caps.flags &
1087			      MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1088				pr_debug("scatter FCS is unsupported\n");
1089				err = -EOPNOTSUPP;
1090				goto err;
1091			}
1092
1093			qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1094		}
1095
1096		err = set_rq_size(dev, &init_attr->cap, udata,
1097				  qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1098		if (err)
1099			goto err;
1100
1101		qp->sq_no_prefetch = ucmd.sq_no_prefetch;
1102
1103		err = set_user_sq_size(dev, qp, &ucmd);
1104		if (err)
1105			goto err;
1106
1107		qp->umem =
1108			ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
1109		if (IS_ERR(qp->umem)) {
1110			err = PTR_ERR(qp->umem);
1111			goto err;
1112		}
1113
1114		shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1115		if (shift < 0) {
1116			err = shift;
1117			goto err_buf;
1118		}
1119
1120		err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1121		if (err)
1122			goto err_buf;
1123
1124		err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1125		if (err)
1126			goto err_mtt;
1127
1128		if (qp_has_rq(init_attr)) {
1129			err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
1130			if (err)
1131				goto err_mtt;
1132		}
1133		qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1134	} else {
1135		err = set_rq_size(dev, &init_attr->cap, udata,
1136				  qp_has_rq(init_attr), qp, 0);
1137		if (err)
1138			goto err;
1139
1140		qp->sq_no_prefetch = 0;
1141
1142		if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1143			qp->flags |= MLX4_IB_QP_LSO;
1144
1145		if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1146			if (dev->steering_support ==
1147			    MLX4_STEERING_MODE_DEVICE_MANAGED)
1148				qp->flags |= MLX4_IB_QP_NETIF;
1149			else {
1150				err = -EINVAL;
1151				goto err;
1152			}
1153		}
1154
1155		err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
1156		if (err)
1157			goto err;
1158
1159		if (qp_has_rq(init_attr)) {
1160			err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1161			if (err)
1162				goto err;
1163
1164			*qp->db.db = 0;
1165		}
1166
1167		if (mlx4_buf_alloc(dev->dev, qp->buf_size,  PAGE_SIZE * 2,
1168				   &qp->buf)) {
1169			err = -ENOMEM;
1170			goto err_db;
1171		}
1172
1173		err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1174				    &qp->mtt);
1175		if (err)
1176			goto err_buf;
1177
1178		err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1179		if (err)
1180			goto err_mtt;
1181
1182		qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1183					     sizeof(u64), GFP_KERNEL);
1184		qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1185					     sizeof(u64), GFP_KERNEL);
1186		if (!qp->sq.wrid || !qp->rq.wrid) {
1187			err = -ENOMEM;
1188			goto err_wrid;
1189		}
1190		qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1191	}
1192
1193	if (sqpn) {
1194		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1195		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1196			if (alloc_proxy_bufs(pd->device, qp)) {
1197				err = -ENOMEM;
1198				goto err_wrid;
1199			}
1200		}
1201	} else {
1202		/* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1203		 * otherwise, the WQE BlueFlame setup flow wrongly causes
1204		 * VLAN insertion. */
1205		if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1206			err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1207						    (init_attr->cap.max_send_wr ?
1208						     MLX4_RESERVE_ETH_BF_QP : 0) |
1209						    (init_attr->cap.max_recv_wr ?
1210						     MLX4_RESERVE_A0_QP : 0),
1211						    qp->mqp.usage);
1212		else
1213			if (qp->flags & MLX4_IB_QP_NETIF)
1214				err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1215			else
1216				err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1217							    &qpn, 0, qp->mqp.usage);
1218		if (err)
1219			goto err_proxy;
1220	}
1221
1222	if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1223		qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1224
1225	err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1226	if (err)
1227		goto err_qpn;
1228
1229	if (init_attr->qp_type == IB_QPT_XRC_TGT)
1230		qp->mqp.qpn |= (1 << 23);
1231
1232	/*
1233	 * Hardware wants QPN written in big-endian order (after
1234	 * shifting) for send doorbell.  Precompute this value to save
1235	 * a little bit when posting sends.
1236	 */
1237	qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1238
1239	qp->mqp.event = mlx4_ib_qp_event;
1240
1241	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1242	mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1243			 to_mcq(init_attr->recv_cq));
1244	/* Maintain device to QPs access, needed for further handling
1245	 * via reset flow
1246	 */
1247	list_add_tail(&qp->qps_list, &dev->qp_list);
1248	/* Maintain CQ to QPs access, needed for further handling
1249	 * via reset flow
1250	 */
1251	mcq = to_mcq(init_attr->send_cq);
1252	list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1253	mcq = to_mcq(init_attr->recv_cq);
1254	list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1255	mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1256			   to_mcq(init_attr->recv_cq));
1257	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1258	return 0;
1259
1260err_qpn:
1261	if (!sqpn) {
1262		if (qp->flags & MLX4_IB_QP_NETIF)
1263			mlx4_ib_steer_qp_free(dev, qpn, 1);
1264		else
1265			mlx4_qp_release_range(dev->dev, qpn, 1);
1266	}
1267err_proxy:
1268	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1269		free_proxy_bufs(pd->device, qp);
1270err_wrid:
1271	if (udata) {
1272		if (qp_has_rq(init_attr))
1273			mlx4_ib_db_unmap_user(context, &qp->db);
1274	} else {
1275		kvfree(qp->sq.wrid);
1276		kvfree(qp->rq.wrid);
1277	}
1278
1279err_mtt:
1280	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1281
1282err_buf:
1283	if (!qp->umem)
1284		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1285	ib_umem_release(qp->umem);
1286
1287err_db:
1288	if (!udata && qp_has_rq(init_attr))
1289		mlx4_db_free(dev->dev, &qp->db);
1290
1291err:
1292	kfree(qp->sqp);
1293	return err;
1294}
1295
1296static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1297{
1298	switch (state) {
1299	case IB_QPS_RESET:	return MLX4_QP_STATE_RST;
1300	case IB_QPS_INIT:	return MLX4_QP_STATE_INIT;
1301	case IB_QPS_RTR:	return MLX4_QP_STATE_RTR;
1302	case IB_QPS_RTS:	return MLX4_QP_STATE_RTS;
1303	case IB_QPS_SQD:	return MLX4_QP_STATE_SQD;
1304	case IB_QPS_SQE:	return MLX4_QP_STATE_SQER;
1305	case IB_QPS_ERR:	return MLX4_QP_STATE_ERR;
1306	default:		return -1;
1307	}
1308}
1309
1310static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1311	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1312{
1313	if (send_cq == recv_cq) {
1314		spin_lock(&send_cq->lock);
1315		__acquire(&recv_cq->lock);
1316	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1317		spin_lock(&send_cq->lock);
1318		spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1319	} else {
1320		spin_lock(&recv_cq->lock);
1321		spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1322	}
1323}
1324
1325static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1326	__releases(&send_cq->lock) __releases(&recv_cq->lock)
1327{
1328	if (send_cq == recv_cq) {
1329		__release(&recv_cq->lock);
1330		spin_unlock(&send_cq->lock);
1331	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1332		spin_unlock(&recv_cq->lock);
1333		spin_unlock(&send_cq->lock);
1334	} else {
1335		spin_unlock(&send_cq->lock);
1336		spin_unlock(&recv_cq->lock);
1337	}
1338}
1339
1340static void del_gid_entries(struct mlx4_ib_qp *qp)
1341{
1342	struct mlx4_ib_gid_entry *ge, *tmp;
1343
1344	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1345		list_del(&ge->list);
1346		kfree(ge);
1347	}
1348}
1349
1350static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1351{
1352	if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1353		return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1354	else
1355		return to_mpd(qp->ibqp.pd);
1356}
1357
1358static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1359		    struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1360{
1361	switch (qp->ibqp.qp_type) {
1362	case IB_QPT_XRC_TGT:
1363		*send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1364		*recv_cq = *send_cq;
1365		break;
1366	case IB_QPT_XRC_INI:
1367		*send_cq = to_mcq(qp->ibqp.send_cq);
1368		*recv_cq = *send_cq;
1369		break;
1370	default:
1371		*recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1372						     to_mcq(qp->ibwq.cq);
1373		*send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1374						     *recv_cq;
1375		break;
1376	}
1377}
1378
1379static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1380{
1381	if (qp->state != IB_QPS_RESET) {
1382		int i;
1383
1384		for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1385		     i++) {
1386			struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1387			struct mlx4_ib_qp *wq =	to_mqp((struct ib_qp *)ibwq);
1388
1389			mutex_lock(&wq->mutex);
1390
1391			wq->rss_usecnt--;
1392
1393			mutex_unlock(&wq->mutex);
1394		}
1395
1396		if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1397				   MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1398			pr_warn("modify QP %06x to RESET failed.\n",
1399				qp->mqp.qpn);
1400	}
1401
1402	mlx4_qp_remove(dev->dev, &qp->mqp);
1403	mlx4_qp_free(dev->dev, &qp->mqp);
1404	mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1405	del_gid_entries(qp);
1406}
1407
1408static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1409			      enum mlx4_ib_source_type src,
1410			      struct ib_udata *udata)
1411{
1412	struct mlx4_ib_cq *send_cq, *recv_cq;
1413	unsigned long flags;
1414
1415	if (qp->state != IB_QPS_RESET) {
1416		if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1417				   MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1418			pr_warn("modify QP %06x to RESET failed.\n",
1419			       qp->mqp.qpn);
1420		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1421			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1422			qp->pri.smac = 0;
1423			qp->pri.smac_port = 0;
1424		}
1425		if (qp->alt.smac) {
1426			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1427			qp->alt.smac = 0;
1428		}
1429		if (qp->pri.vid < 0x1000) {
1430			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1431			qp->pri.vid = 0xFFFF;
1432			qp->pri.candidate_vid = 0xFFFF;
1433			qp->pri.update_vid = 0;
1434		}
1435		if (qp->alt.vid < 0x1000) {
1436			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1437			qp->alt.vid = 0xFFFF;
1438			qp->alt.candidate_vid = 0xFFFF;
1439			qp->alt.update_vid = 0;
1440		}
1441	}
1442
1443	get_cqs(qp, src, &send_cq, &recv_cq);
1444
1445	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1446	mlx4_ib_lock_cqs(send_cq, recv_cq);
1447
1448	/* del from lists under both locks above to protect reset flow paths */
1449	list_del(&qp->qps_list);
1450	list_del(&qp->cq_send_list);
1451	list_del(&qp->cq_recv_list);
1452	if (!udata) {
1453		__mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1454				 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1455		if (send_cq != recv_cq)
1456			__mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1457	}
1458
1459	mlx4_qp_remove(dev->dev, &qp->mqp);
1460
1461	mlx4_ib_unlock_cqs(send_cq, recv_cq);
1462	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1463
1464	mlx4_qp_free(dev->dev, &qp->mqp);
1465
1466	if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1467		if (qp->flags & MLX4_IB_QP_NETIF)
1468			mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1469		else if (src == MLX4_IB_RWQ_SRC)
1470			mlx4_ib_release_wqn(
1471				rdma_udata_to_drv_context(
1472					udata,
1473					struct mlx4_ib_ucontext,
1474					ibucontext),
1475				qp, 1);
1476		else
1477			mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1478	}
1479
1480	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1481
1482	if (udata) {
1483		if (qp->rq.wqe_cnt) {
1484			struct mlx4_ib_ucontext *mcontext =
1485				rdma_udata_to_drv_context(
1486					udata,
1487					struct mlx4_ib_ucontext,
1488					ibucontext);
1489
1490			mlx4_ib_db_unmap_user(mcontext, &qp->db);
1491		}
1492	} else {
1493		kvfree(qp->sq.wrid);
1494		kvfree(qp->rq.wrid);
1495		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1496		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1497			free_proxy_bufs(&dev->ib_dev, qp);
1498		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1499		if (qp->rq.wqe_cnt)
1500			mlx4_db_free(dev->dev, &qp->db);
1501	}
1502	ib_umem_release(qp->umem);
1503
1504	del_gid_entries(qp);
1505}
1506
1507static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1508{
1509	/* Native or PPF */
1510	if (!mlx4_is_mfunc(dev->dev) ||
1511	    (mlx4_is_master(dev->dev) &&
1512	     attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1513		return  dev->dev->phys_caps.base_sqpn +
1514			(attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1515			attr->port_num - 1;
1516	}
1517	/* PF or VF -- creating proxies */
1518	if (attr->qp_type == IB_QPT_SMI)
1519		return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1520	else
1521		return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1522}
1523
1524static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp,
1525			      struct ib_qp_init_attr *init_attr,
1526			      struct ib_udata *udata)
1527{
1528	int err;
1529	int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1530	u16 xrcdn = 0;
1531
1532	if (init_attr->rwq_ind_tbl)
1533		return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata);
1534
1535	/*
1536	 * We only support LSO, vendor flag1, and multicast loopback blocking,
1537	 * and only for kernel UD QPs.
1538	 */
1539	if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1540					MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1541					MLX4_IB_SRIOV_TUNNEL_QP |
1542					MLX4_IB_SRIOV_SQP |
1543					MLX4_IB_QP_NETIF |
1544					MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1545		return -EOPNOTSUPP;
1546
1547	if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1548		if (init_attr->qp_type != IB_QPT_UD)
1549			return -EINVAL;
1550	}
1551
1552	if (init_attr->create_flags) {
1553		if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1554			return -EINVAL;
1555
1556		if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1557						 MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1558						 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1559		     init_attr->qp_type != IB_QPT_UD) ||
1560		    (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1561		     init_attr->qp_type > IB_QPT_GSI) ||
1562		    (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1563		     init_attr->qp_type != IB_QPT_GSI))
1564			return -EINVAL;
1565	}
1566
1567	switch (init_attr->qp_type) {
1568	case IB_QPT_XRC_TGT:
1569		pd = to_mxrcd(init_attr->xrcd)->pd;
1570		xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1571		init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1572		fallthrough;
1573	case IB_QPT_XRC_INI:
1574		if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1575			return -ENOSYS;
1576		init_attr->recv_cq = init_attr->send_cq;
1577		fallthrough;
1578	case IB_QPT_RC:
1579	case IB_QPT_UC:
1580	case IB_QPT_RAW_PACKET:
1581	case IB_QPT_UD:
1582		qp->pri.vid = 0xFFFF;
1583		qp->alt.vid = 0xFFFF;
1584		err = create_qp_common(pd, init_attr, udata, 0, qp);
1585		if (err)
1586			return err;
1587
1588		qp->ibqp.qp_num = qp->mqp.qpn;
1589		qp->xrcdn = xrcdn;
1590		break;
1591	case IB_QPT_SMI:
1592	case IB_QPT_GSI:
1593	{
1594		int sqpn;
1595
1596		if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1597			int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1598							1, 1, &sqpn, 0,
1599							MLX4_RES_USAGE_DRIVER);
1600
1601			if (res)
1602				return res;
1603		} else {
1604			sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1605		}
1606
1607		qp->pri.vid = 0xFFFF;
1608		qp->alt.vid = 0xFFFF;
1609		err = create_qp_common(pd, init_attr, udata, sqpn, qp);
1610		if (err)
1611			return err;
1612
1613		if (init_attr->create_flags &
1614		    (MLX4_IB_SRIOV_SQP | MLX4_IB_SRIOV_TUNNEL_QP))
1615			/* Internal QP created with ib_create_qp */
1616			rdma_restrack_no_track(&qp->ibqp.res);
1617
1618		qp->port	= init_attr->port_num;
1619		qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1620			init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1621		break;
1622	}
1623	default:
1624		/* Don't support raw QPs */
1625		return -EOPNOTSUPP;
1626	}
1627	return 0;
1628}
1629
1630int mlx4_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *init_attr,
1631		      struct ib_udata *udata)
1632{
1633	struct ib_device *device = ibqp->device;
1634	struct mlx4_ib_dev *dev = to_mdev(device);
1635	struct mlx4_ib_qp *qp = to_mqp(ibqp);
1636	struct ib_pd *pd = ibqp->pd;
1637	int ret;
1638
1639	mutex_init(&qp->mutex);
1640	ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata);
1641	if (ret)
1642		return ret;
1643
1644	if (init_attr->qp_type == IB_QPT_GSI &&
1645	    !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1646		struct mlx4_ib_sqp *sqp = qp->sqp;
1647		int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1648
1649		if (is_eth &&
1650		    dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1651			init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1652			sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1653
1654			if (IS_ERR(sqp->roce_v2_gsi)) {
1655				pr_err("Failed to create GSI QP for RoCEv2 (%pe)\n",
1656				       sqp->roce_v2_gsi);
1657				sqp->roce_v2_gsi = NULL;
1658			} else {
1659				to_mqp(sqp->roce_v2_gsi)->flags |=
1660					MLX4_IB_ROCE_V2_GSI_QP;
1661			}
1662
1663			init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1664		}
1665	}
1666	return 0;
1667}
1668
1669static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
1670{
1671	struct mlx4_ib_dev *dev = to_mdev(qp->device);
1672	struct mlx4_ib_qp *mqp = to_mqp(qp);
1673
1674	if (is_qp0(dev, mqp))
1675		mlx4_CLOSE_PORT(dev->dev, mqp->port);
1676
1677	if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1678	    dev->qp1_proxy[mqp->port - 1] == mqp) {
1679		mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1680		dev->qp1_proxy[mqp->port - 1] = NULL;
1681		mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1682	}
1683
1684	if (mqp->counter_index)
1685		mlx4_ib_free_qp_counter(dev, mqp);
1686
1687	if (qp->rwq_ind_tbl) {
1688		destroy_qp_rss(dev, mqp);
1689	} else {
1690		destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
1691	}
1692
1693	kfree(mqp->sqp);
1694	return 0;
1695}
1696
1697int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
1698{
1699	struct mlx4_ib_qp *mqp = to_mqp(qp);
1700
1701	if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1702		struct mlx4_ib_sqp *sqp = mqp->sqp;
1703
1704		if (sqp->roce_v2_gsi)
1705			ib_destroy_qp(sqp->roce_v2_gsi);
1706	}
1707
1708	return _mlx4_ib_destroy_qp(qp, udata);
1709}
1710
1711static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1712{
1713	switch (type) {
1714	case MLX4_IB_QPT_RC:		return MLX4_QP_ST_RC;
1715	case MLX4_IB_QPT_UC:		return MLX4_QP_ST_UC;
1716	case MLX4_IB_QPT_UD:		return MLX4_QP_ST_UD;
1717	case MLX4_IB_QPT_XRC_INI:
1718	case MLX4_IB_QPT_XRC_TGT:	return MLX4_QP_ST_XRC;
1719	case MLX4_IB_QPT_SMI:
1720	case MLX4_IB_QPT_GSI:
1721	case MLX4_IB_QPT_RAW_PACKET:	return MLX4_QP_ST_MLX;
1722
1723	case MLX4_IB_QPT_PROXY_SMI_OWNER:
1724	case MLX4_IB_QPT_TUN_SMI_OWNER:	return (mlx4_is_mfunc(dev->dev) ?
1725						MLX4_QP_ST_MLX : -1);
1726	case MLX4_IB_QPT_PROXY_SMI:
1727	case MLX4_IB_QPT_TUN_SMI:
1728	case MLX4_IB_QPT_PROXY_GSI:
1729	case MLX4_IB_QPT_TUN_GSI:	return (mlx4_is_mfunc(dev->dev) ?
1730						MLX4_QP_ST_UD : -1);
1731	default:			return -1;
1732	}
1733}
1734
1735static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1736				   int attr_mask)
1737{
1738	u8 dest_rd_atomic;
1739	u32 access_flags;
1740	u32 hw_access_flags = 0;
1741
1742	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1743		dest_rd_atomic = attr->max_dest_rd_atomic;
1744	else
1745		dest_rd_atomic = qp->resp_depth;
1746
1747	if (attr_mask & IB_QP_ACCESS_FLAGS)
1748		access_flags = attr->qp_access_flags;
1749	else
1750		access_flags = qp->atomic_rd_en;
1751
1752	if (!dest_rd_atomic)
1753		access_flags &= IB_ACCESS_REMOTE_WRITE;
1754
1755	if (access_flags & IB_ACCESS_REMOTE_READ)
1756		hw_access_flags |= MLX4_QP_BIT_RRE;
1757	if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1758		hw_access_flags |= MLX4_QP_BIT_RAE;
1759	if (access_flags & IB_ACCESS_REMOTE_WRITE)
1760		hw_access_flags |= MLX4_QP_BIT_RWE;
1761
1762	return cpu_to_be32(hw_access_flags);
1763}
1764
1765static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1766			    int attr_mask)
1767{
1768	if (attr_mask & IB_QP_PKEY_INDEX)
1769		sqp->pkey_index = attr->pkey_index;
1770	if (attr_mask & IB_QP_QKEY)
1771		sqp->qkey = attr->qkey;
1772	if (attr_mask & IB_QP_SQ_PSN)
1773		sqp->send_psn = attr->sq_psn;
1774}
1775
1776static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1777{
1778	path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1779}
1780
1781static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1782			  const struct rdma_ah_attr *ah,
1783			  u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1784			  struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1785{
1786	int vidx;
1787	int smac_index;
1788	int err;
1789
1790	path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1791	path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1792	if (rdma_ah_get_static_rate(ah)) {
1793		path->static_rate = rdma_ah_get_static_rate(ah) +
1794				    MLX4_STAT_RATE_OFFSET;
1795		while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1796		       !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1797			--path->static_rate;
1798	} else
1799		path->static_rate = 0;
1800
1801	if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1802		const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1803		int real_sgid_index =
1804			mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
1805
1806		if (real_sgid_index < 0)
1807			return real_sgid_index;
1808		if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1809			pr_err("sgid_index (%u) too large. max is %d\n",
1810			       real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1811			return -1;
1812		}
1813
1814		path->grh_mylmc |= 1 << 7;
1815		path->mgid_index = real_sgid_index;
1816		path->hop_limit  = grh->hop_limit;
1817		path->tclass_flowlabel =
1818			cpu_to_be32((grh->traffic_class << 20) |
1819				    (grh->flow_label));
1820		memcpy(path->rgid, grh->dgid.raw, 16);
1821	}
1822
1823	if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1824		if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1825			return -1;
1826
1827		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1828			((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1829
1830		path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1831		if (vlan_tag < 0x1000) {
1832			if (smac_info->vid < 0x1000) {
1833				/* both valid vlan ids */
1834				if (smac_info->vid != vlan_tag) {
1835					/* different VIDs.  unreg old and reg new */
1836					err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1837					if (err)
1838						return err;
1839					smac_info->candidate_vid = vlan_tag;
1840					smac_info->candidate_vlan_index = vidx;
1841					smac_info->candidate_vlan_port = port;
1842					smac_info->update_vid = 1;
1843					path->vlan_index = vidx;
1844				} else {
1845					path->vlan_index = smac_info->vlan_index;
1846				}
1847			} else {
1848				/* no current vlan tag in qp */
1849				err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1850				if (err)
1851					return err;
1852				smac_info->candidate_vid = vlan_tag;
1853				smac_info->candidate_vlan_index = vidx;
1854				smac_info->candidate_vlan_port = port;
1855				smac_info->update_vid = 1;
1856				path->vlan_index = vidx;
1857			}
1858			path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1859			path->fl = 1 << 6;
1860		} else {
1861			/* have current vlan tag. unregister it at modify-qp success */
1862			if (smac_info->vid < 0x1000) {
1863				smac_info->candidate_vid = 0xFFFF;
1864				smac_info->update_vid = 1;
1865			}
1866		}
1867
1868		/* get smac_index for RoCE use.
1869		 * If no smac was yet assigned, register one.
1870		 * If one was already assigned, but the new mac differs,
1871		 * unregister the old one and register the new one.
1872		*/
1873		if ((!smac_info->smac && !smac_info->smac_port) ||
1874		    smac_info->smac != smac) {
1875			/* register candidate now, unreg if needed, after success */
1876			smac_index = mlx4_register_mac(dev->dev, port, smac);
1877			if (smac_index >= 0) {
1878				smac_info->candidate_smac_index = smac_index;
1879				smac_info->candidate_smac = smac;
1880				smac_info->candidate_smac_port = port;
1881			} else {
1882				return -EINVAL;
1883			}
1884		} else {
1885			smac_index = smac_info->smac_index;
1886		}
1887		memcpy(path->dmac, ah->roce.dmac, 6);
1888		path->ackto = MLX4_IB_LINK_TYPE_ETH;
1889		/* put MAC table smac index for IBoE */
1890		path->grh_mylmc = (u8) (smac_index) | 0x80;
1891	} else {
1892		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1893			((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1894	}
1895
1896	return 0;
1897}
1898
1899static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1900			 enum ib_qp_attr_mask qp_attr_mask,
1901			 struct mlx4_ib_qp *mqp,
1902			 struct mlx4_qp_path *path, u8 port,
1903			 u16 vlan_id, u8 *smac)
1904{
1905	return _mlx4_set_path(dev, &qp->ah_attr,
1906			      ether_addr_to_u64(smac),
1907			      vlan_id,
1908			      path, &mqp->pri, port);
1909}
1910
1911static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1912			     const struct ib_qp_attr *qp,
1913			     enum ib_qp_attr_mask qp_attr_mask,
1914			     struct mlx4_ib_qp *mqp,
1915			     struct mlx4_qp_path *path, u8 port)
1916{
1917	return _mlx4_set_path(dev, &qp->alt_ah_attr,
1918			      0,
1919			      0xffff,
1920			      path, &mqp->alt, port);
1921}
1922
1923static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1924{
1925	struct mlx4_ib_gid_entry *ge, *tmp;
1926
1927	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1928		if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1929			ge->added = 1;
1930			ge->port = qp->port;
1931		}
1932	}
1933}
1934
1935static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1936				    struct mlx4_ib_qp *qp,
1937				    struct mlx4_qp_context *context)
1938{
1939	u64 u64_mac;
1940	int smac_index;
1941
1942	u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1943
1944	context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1945	if (!qp->pri.smac && !qp->pri.smac_port) {
1946		smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1947		if (smac_index >= 0) {
1948			qp->pri.candidate_smac_index = smac_index;
1949			qp->pri.candidate_smac = u64_mac;
1950			qp->pri.candidate_smac_port = qp->port;
1951			context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1952		} else {
1953			return -ENOENT;
1954		}
1955	}
1956	return 0;
1957}
1958
1959static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1960{
1961	struct counter_index *new_counter_index;
1962	int err;
1963	u32 tmp_idx;
1964
1965	if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1966	    IB_LINK_LAYER_ETHERNET ||
1967	    !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1968	    !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1969		return 0;
1970
1971	err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
1972	if (err)
1973		return err;
1974
1975	new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1976	if (!new_counter_index) {
1977		mlx4_counter_free(dev->dev, tmp_idx);
1978		return -ENOMEM;
1979	}
1980
1981	new_counter_index->index = tmp_idx;
1982	new_counter_index->allocated = 1;
1983	qp->counter_index = new_counter_index;
1984
1985	mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1986	list_add_tail(&new_counter_index->list,
1987		      &dev->counters_table[qp->port - 1].counters_list);
1988	mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1989
1990	return 0;
1991}
1992
1993enum {
1994	MLX4_QPC_ROCE_MODE_1 = 0,
1995	MLX4_QPC_ROCE_MODE_2 = 2,
1996	MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1997};
1998
1999static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2000{
2001	switch (gid_type) {
2002	case IB_GID_TYPE_ROCE:
2003		return MLX4_QPC_ROCE_MODE_1;
2004	case IB_GID_TYPE_ROCE_UDP_ENCAP:
2005		return MLX4_QPC_ROCE_MODE_2;
2006	default:
2007		return MLX4_QPC_ROCE_MODE_UNDEFINED;
2008	}
2009}
2010
2011/*
2012 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2013 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2014 */
2015static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
2016			    struct ib_udata *udata)
2017{
2018	int err = 0;
2019	int i;
2020
2021	for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2022		struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2023		struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2024
2025		mutex_lock(&wq->mutex);
2026
2027		/* Mlx4_ib restrictions:
2028		 * WQ's is associated to a port according to the RSS QP it is
2029		 * associates to.
2030		 * In case the WQ is associated to a different port by another
2031		 * RSS QP, return a failure.
2032		 */
2033		if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2034			err = -EINVAL;
2035			mutex_unlock(&wq->mutex);
2036			break;
2037		}
2038		wq->port = port_num;
2039		if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2040			err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
2041			if (err) {
2042				mutex_unlock(&wq->mutex);
2043				break;
2044			}
2045		}
2046		wq->rss_usecnt++;
2047
2048		mutex_unlock(&wq->mutex);
2049	}
2050
2051	if (i && err) {
2052		int j;
2053
2054		for (j = (i - 1); j >= 0; j--) {
2055			struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2056			struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2057
2058			mutex_lock(&wq->mutex);
2059
2060			if ((wq->rss_usecnt == 1) &&
2061			    (ibwq->state == IB_WQS_RDY))
2062				if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2063						       udata))
2064					pr_warn("failed to reverse WQN=0x%06x\n",
2065						ibwq->wq_num);
2066			wq->rss_usecnt--;
2067
2068			mutex_unlock(&wq->mutex);
2069		}
2070	}
2071
2072	return err;
2073}
2074
2075static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2076				struct ib_udata *udata)
2077{
2078	int i;
2079
2080	for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2081		struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2082		struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2083
2084		mutex_lock(&wq->mutex);
2085
2086		if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2087			if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
2088				pr_warn("failed to reverse WQN=%x\n",
2089					ibwq->wq_num);
2090		wq->rss_usecnt--;
2091
2092		mutex_unlock(&wq->mutex);
2093	}
2094}
2095
2096static void fill_qp_rss_context(struct mlx4_qp_context *context,
2097				struct mlx4_ib_qp *qp)
2098{
2099	struct mlx4_rss_context *rss_context;
2100
2101	rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2102			pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2103
2104	rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2105	rss_context->default_qpn =
2106		cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2107	if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2108		rss_context->base_qpn_udp = rss_context->default_qpn;
2109	rss_context->flags = qp->rss_ctx->flags;
2110	/* Currently support just toeplitz */
2111	rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2112
2113	memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2114	       MLX4_EN_RSS_KEY_SIZE);
2115}
2116
2117static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2118			       const struct ib_qp_attr *attr, int attr_mask,
2119			       enum ib_qp_state cur_state,
2120			       enum ib_qp_state new_state,
2121			       struct ib_udata *udata)
2122{
2123	struct ib_srq  *ibsrq;
2124	const struct ib_gid_attr *gid_attr = NULL;
2125	struct ib_rwq_ind_table *rwq_ind_tbl;
2126	enum ib_qp_type qp_type;
2127	struct mlx4_ib_dev *dev;
2128	struct mlx4_ib_qp *qp;
2129	struct mlx4_ib_pd *pd;
2130	struct mlx4_ib_cq *send_cq, *recv_cq;
2131	struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2132		udata, struct mlx4_ib_ucontext, ibucontext);
2133	struct mlx4_qp_context *context;
2134	enum mlx4_qp_optpar optpar = 0;
2135	int sqd_event;
2136	int steer_qp = 0;
2137	int err = -EINVAL;
2138	int counter_index;
2139
2140	if (src_type == MLX4_IB_RWQ_SRC) {
2141		struct ib_wq *ibwq;
2142
2143		ibwq	    = (struct ib_wq *)src;
2144		ibsrq	    = NULL;
2145		rwq_ind_tbl = NULL;
2146		qp_type     = IB_QPT_RAW_PACKET;
2147		qp	    = to_mqp((struct ib_qp *)ibwq);
2148		dev	    = to_mdev(ibwq->device);
2149		pd	    = to_mpd(ibwq->pd);
2150	} else {
2151		struct ib_qp *ibqp;
2152
2153		ibqp	    = (struct ib_qp *)src;
2154		ibsrq	    = ibqp->srq;
2155		rwq_ind_tbl = ibqp->rwq_ind_tbl;
2156		qp_type     = ibqp->qp_type;
2157		qp	    = to_mqp(ibqp);
2158		dev	    = to_mdev(ibqp->device);
2159		pd	    = get_pd(qp);
2160	}
2161
2162	/* APM is not supported under RoCE */
2163	if (attr_mask & IB_QP_ALT_PATH &&
2164	    rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2165	    IB_LINK_LAYER_ETHERNET)
2166		return -ENOTSUPP;
2167
2168	context = kzalloc(sizeof *context, GFP_KERNEL);
2169	if (!context)
2170		return -ENOMEM;
2171
2172	context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2173				     (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2174
2175	if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2176		context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2177	else {
2178		optpar |= MLX4_QP_OPTPAR_PM_STATE;
2179		switch (attr->path_mig_state) {
2180		case IB_MIG_MIGRATED:
2181			context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2182			break;
2183		case IB_MIG_REARM:
2184			context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2185			break;
2186		case IB_MIG_ARMED:
2187			context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2188			break;
2189		}
2190	}
2191
2192	if (qp->inl_recv_sz)
2193		context->param3 |= cpu_to_be32(1 << 25);
2194
2195	if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2196		context->param3 |= cpu_to_be32(1 << 29);
2197
2198	if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2199		context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2200	else if (qp_type == IB_QPT_RAW_PACKET)
2201		context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2202	else if (qp_type == IB_QPT_UD) {
2203		if (qp->flags & MLX4_IB_QP_LSO)
2204			context->mtu_msgmax = (IB_MTU_4096 << 5) |
2205					      ilog2(dev->dev->caps.max_gso_sz);
2206		else
2207			context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2208	} else if (attr_mask & IB_QP_PATH_MTU) {
2209		if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2210			pr_err("path MTU (%u) is invalid\n",
2211			       attr->path_mtu);
2212			goto out;
2213		}
2214		context->mtu_msgmax = (attr->path_mtu << 5) |
2215			ilog2(dev->dev->caps.max_msg_sz);
2216	}
2217
2218	if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2219		if (qp->rq.wqe_cnt)
2220			context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2221		context->rq_size_stride |= qp->rq.wqe_shift - 4;
2222	}
2223
2224	if (qp->sq.wqe_cnt)
2225		context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2226	context->sq_size_stride |= qp->sq.wqe_shift - 4;
2227
2228	if (new_state == IB_QPS_RESET && qp->counter_index)
2229		mlx4_ib_free_qp_counter(dev, qp);
2230
2231	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2232		context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2233		context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2234		if (qp_type == IB_QPT_RAW_PACKET)
2235			context->param3 |= cpu_to_be32(1 << 30);
2236	}
2237
2238	if (ucontext)
2239		context->usr_page = cpu_to_be32(
2240			mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
2241	else
2242		context->usr_page = cpu_to_be32(
2243			mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2244
2245	if (attr_mask & IB_QP_DEST_QPN)
2246		context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2247
2248	if (attr_mask & IB_QP_PORT) {
2249		if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2250		    !(attr_mask & IB_QP_AV)) {
2251			mlx4_set_sched(&context->pri_path, attr->port_num);
2252			optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2253		}
2254	}
2255
2256	if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2257		err = create_qp_lb_counter(dev, qp);
2258		if (err)
2259			goto out;
2260
2261		counter_index =
2262			dev->counters_table[qp->port - 1].default_counter;
2263		if (qp->counter_index)
2264			counter_index = qp->counter_index->index;
2265
2266		if (counter_index != -1) {
2267			context->pri_path.counter_index = counter_index;
2268			optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2269			if (qp->counter_index) {
2270				context->pri_path.fl |=
2271					MLX4_FL_ETH_SRC_CHECK_MC_LB;
2272				context->pri_path.vlan_control |=
2273					MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2274			}
2275		} else
2276			context->pri_path.counter_index =
2277				MLX4_SINK_COUNTER_INDEX(dev->dev);
2278
2279		if (qp->flags & MLX4_IB_QP_NETIF) {
2280			mlx4_ib_steer_qp_reg(dev, qp, 1);
2281			steer_qp = 1;
2282		}
2283
2284		if (qp_type == IB_QPT_GSI) {
2285			enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2286				IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2287			u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2288
2289			context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2290		}
2291	}
2292
2293	if (attr_mask & IB_QP_PKEY_INDEX) {
2294		if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2295			context->pri_path.disable_pkey_check = 0x40;
2296		context->pri_path.pkey_index = attr->pkey_index;
2297		optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2298	}
2299
2300	if (attr_mask & IB_QP_AV) {
2301		u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2302			attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2303		u16 vlan = 0xffff;
2304		u8 smac[ETH_ALEN];
2305		int is_eth =
2306			rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2307			rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2308
2309		if (is_eth) {
2310			gid_attr = attr->ah_attr.grh.sgid_attr;
2311			err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2312						      &smac[0]);
2313			if (err)
2314				goto out;
2315		}
2316
2317		if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2318				  port_num, vlan, smac))
2319			goto out;
2320
2321		optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2322			   MLX4_QP_OPTPAR_SCHED_QUEUE);
2323
2324		if (is_eth &&
2325		    (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2326			u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
2327
2328			if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2329				err = -EINVAL;
2330				goto out;
2331			}
2332			context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2333		}
2334
2335	}
2336
2337	if (attr_mask & IB_QP_TIMEOUT) {
2338		context->pri_path.ackto |= attr->timeout << 3;
2339		optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2340	}
2341
2342	if (attr_mask & IB_QP_ALT_PATH) {
2343		if (attr->alt_port_num == 0 ||
2344		    attr->alt_port_num > dev->dev->caps.num_ports)
2345			goto out;
2346
2347		if (attr->alt_pkey_index >=
2348		    dev->dev->caps.pkey_table_len[attr->alt_port_num])
2349			goto out;
2350
2351		if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2352				      &context->alt_path,
2353				      attr->alt_port_num))
2354			goto out;
2355
2356		context->alt_path.pkey_index = attr->alt_pkey_index;
2357		context->alt_path.ackto = attr->alt_timeout << 3;
2358		optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2359	}
2360
2361	context->pd = cpu_to_be32(pd->pdn);
2362
2363	if (!rwq_ind_tbl) {
2364		context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2365		get_cqs(qp, src_type, &send_cq, &recv_cq);
2366	} else { /* Set dummy CQs to be compatible with HV and PRM */
2367		send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2368		recv_cq = send_cq;
2369	}
2370	context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2371	context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2372
2373	/* Set "fast registration enabled" for all kernel QPs */
2374	if (!ucontext)
2375		context->params1 |= cpu_to_be32(1 << 11);
2376
2377	if (attr_mask & IB_QP_RNR_RETRY) {
2378		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2379		optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2380	}
2381
2382	if (attr_mask & IB_QP_RETRY_CNT) {
2383		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2384		optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2385	}
2386
2387	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2388		if (attr->max_rd_atomic)
2389			context->params1 |=
2390				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2391		optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2392	}
2393
2394	if (attr_mask & IB_QP_SQ_PSN)
2395		context->next_send_psn = cpu_to_be32(attr->sq_psn);
2396
2397	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2398		if (attr->max_dest_rd_atomic)
2399			context->params2 |=
2400				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2401		optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2402	}
2403
2404	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2405		context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2406		optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2407	}
2408
2409	if (ibsrq)
2410		context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2411
2412	if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2413		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2414		optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2415	}
2416	if (attr_mask & IB_QP_RQ_PSN)
2417		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2418
2419	/* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2420	if (attr_mask & IB_QP_QKEY) {
2421		if (qp->mlx4_ib_qp_type &
2422		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2423			context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2424		else {
2425			if (mlx4_is_mfunc(dev->dev) &&
2426			    !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2427			    (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2428			    MLX4_RESERVED_QKEY_BASE) {
2429				pr_err("Cannot use reserved QKEY"
2430				       " 0x%x (range 0xffff0000..0xffffffff"
2431				       " is reserved)\n", attr->qkey);
2432				err = -EINVAL;
2433				goto out;
2434			}
2435			context->qkey = cpu_to_be32(attr->qkey);
2436		}
2437		optpar |= MLX4_QP_OPTPAR_Q_KEY;
2438	}
2439
2440	if (ibsrq)
2441		context->srqn = cpu_to_be32(1 << 24 |
2442					    to_msrq(ibsrq)->msrq.srqn);
2443
2444	if (qp->rq.wqe_cnt &&
2445	    cur_state == IB_QPS_RESET &&
2446	    new_state == IB_QPS_INIT)
2447		context->db_rec_addr = cpu_to_be64(qp->db.dma);
2448
2449	if (cur_state == IB_QPS_INIT &&
2450	    new_state == IB_QPS_RTR  &&
2451	    (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2452	     qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2453		context->pri_path.sched_queue = (qp->port - 1) << 6;
2454		if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2455		    qp->mlx4_ib_qp_type &
2456		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2457			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2458			if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2459				context->pri_path.fl = 0x80;
2460		} else {
2461			if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2462				context->pri_path.fl = 0x80;
2463			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2464		}
2465		if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2466		    IB_LINK_LAYER_ETHERNET) {
2467			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2468			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2469				context->pri_path.feup = 1 << 7; /* don't fsm */
2470			/* handle smac_index */
2471			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2472			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2473			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2474				err = handle_eth_ud_smac_index(dev, qp, context);
2475				if (err) {
2476					err = -EINVAL;
2477					goto out;
2478				}
2479				if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2480					dev->qp1_proxy[qp->port - 1] = qp;
2481			}
2482		}
2483	}
2484
2485	if (qp_type == IB_QPT_RAW_PACKET) {
2486		context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2487					MLX4_IB_LINK_TYPE_ETH;
2488		if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2489			/* set QP to receive both tunneled & non-tunneled packets */
2490			if (!rwq_ind_tbl)
2491				context->srqn = cpu_to_be32(7 << 28);
2492		}
2493	}
2494
2495	if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2496		int is_eth = rdma_port_get_link_layer(
2497				&dev->ib_dev, qp->port) ==
2498				IB_LINK_LAYER_ETHERNET;
2499		if (is_eth) {
2500			context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2501			optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2502		}
2503	}
2504
2505	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
2506	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2507		sqd_event = 1;
2508	else
2509		sqd_event = 0;
2510
2511	if (!ucontext &&
2512	    cur_state == IB_QPS_RESET &&
2513	    new_state == IB_QPS_INIT)
2514		context->rlkey_roce_mode |= (1 << 4);
2515
2516	/*
2517	 * Before passing a kernel QP to the HW, make sure that the
2518	 * ownership bits of the send queue are set and the SQ
2519	 * headroom is stamped so that the hardware doesn't start
2520	 * processing stale work requests.
2521	 */
2522	if (!ucontext &&
2523	    cur_state == IB_QPS_RESET &&
2524	    new_state == IB_QPS_INIT) {
2525		struct mlx4_wqe_ctrl_seg *ctrl;
2526		int i;
2527
2528		for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2529			ctrl = get_send_wqe(qp, i);
2530			ctrl->owner_opcode = cpu_to_be32(1 << 31);
2531			ctrl->qpn_vlan.fence_size =
2532				1 << (qp->sq.wqe_shift - 4);
2533			stamp_send_wqe(qp, i);
2534		}
2535	}
2536
2537	if (rwq_ind_tbl	&&
2538	    cur_state == IB_QPS_RESET &&
2539	    new_state == IB_QPS_INIT) {
2540		fill_qp_rss_context(context, qp);
2541		context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2542	}
2543
2544	err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2545			     to_mlx4_state(new_state), context, optpar,
2546			     sqd_event, &qp->mqp);
2547	if (err)
2548		goto out;
2549
2550	qp->state = new_state;
2551
2552	if (attr_mask & IB_QP_ACCESS_FLAGS)
2553		qp->atomic_rd_en = attr->qp_access_flags;
2554	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2555		qp->resp_depth = attr->max_dest_rd_atomic;
2556	if (attr_mask & IB_QP_PORT) {
2557		qp->port = attr->port_num;
2558		update_mcg_macs(dev, qp);
2559	}
2560	if (attr_mask & IB_QP_ALT_PATH)
2561		qp->alt_port = attr->alt_port_num;
2562
2563	if (is_sqp(dev, qp))
2564		store_sqp_attrs(qp->sqp, attr, attr_mask);
2565
2566	/*
2567	 * If we moved QP0 to RTR, bring the IB link up; if we moved
2568	 * QP0 to RESET or ERROR, bring the link back down.
2569	 */
2570	if (is_qp0(dev, qp)) {
2571		if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2572			if (mlx4_INIT_PORT(dev->dev, qp->port))
2573				pr_warn("INIT_PORT failed for port %d\n",
2574				       qp->port);
2575
2576		if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2577		    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2578			mlx4_CLOSE_PORT(dev->dev, qp->port);
2579	}
2580
2581	/*
2582	 * If we moved a kernel QP to RESET, clean up all old CQ
2583	 * entries and reinitialize the QP.
2584	 */
2585	if (new_state == IB_QPS_RESET) {
2586		if (!ucontext) {
2587			mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2588					 ibsrq ? to_msrq(ibsrq) : NULL);
2589			if (send_cq != recv_cq)
2590				mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2591
2592			qp->rq.head = 0;
2593			qp->rq.tail = 0;
2594			qp->sq.head = 0;
2595			qp->sq.tail = 0;
2596			qp->sq_next_wqe = 0;
2597			if (qp->rq.wqe_cnt)
2598				*qp->db.db  = 0;
2599
2600			if (qp->flags & MLX4_IB_QP_NETIF)
2601				mlx4_ib_steer_qp_reg(dev, qp, 0);
2602		}
2603		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2604			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2605			qp->pri.smac = 0;
2606			qp->pri.smac_port = 0;
2607		}
2608		if (qp->alt.smac) {
2609			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2610			qp->alt.smac = 0;
2611		}
2612		if (qp->pri.vid < 0x1000) {
2613			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2614			qp->pri.vid = 0xFFFF;
2615			qp->pri.candidate_vid = 0xFFFF;
2616			qp->pri.update_vid = 0;
2617		}
2618
2619		if (qp->alt.vid < 0x1000) {
2620			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2621			qp->alt.vid = 0xFFFF;
2622			qp->alt.candidate_vid = 0xFFFF;
2623			qp->alt.update_vid = 0;
2624		}
2625	}
2626out:
2627	if (err && qp->counter_index)
2628		mlx4_ib_free_qp_counter(dev, qp);
2629	if (err && steer_qp)
2630		mlx4_ib_steer_qp_reg(dev, qp, 0);
2631	kfree(context);
2632	if (qp->pri.candidate_smac ||
2633	    (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2634		if (err) {
2635			mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2636		} else {
2637			if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2638				mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2639			qp->pri.smac = qp->pri.candidate_smac;
2640			qp->pri.smac_index = qp->pri.candidate_smac_index;
2641			qp->pri.smac_port = qp->pri.candidate_smac_port;
2642		}
2643		qp->pri.candidate_smac = 0;
2644		qp->pri.candidate_smac_index = 0;
2645		qp->pri.candidate_smac_port = 0;
2646	}
2647	if (qp->alt.candidate_smac) {
2648		if (err) {
2649			mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2650		} else {
2651			if (qp->alt.smac)
2652				mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2653			qp->alt.smac = qp->alt.candidate_smac;
2654			qp->alt.smac_index = qp->alt.candidate_smac_index;
2655			qp->alt.smac_port = qp->alt.candidate_smac_port;
2656		}
2657		qp->alt.candidate_smac = 0;
2658		qp->alt.candidate_smac_index = 0;
2659		qp->alt.candidate_smac_port = 0;
2660	}
2661
2662	if (qp->pri.update_vid) {
2663		if (err) {
2664			if (qp->pri.candidate_vid < 0x1000)
2665				mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2666						     qp->pri.candidate_vid);
2667		} else {
2668			if (qp->pri.vid < 0x1000)
2669				mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2670						     qp->pri.vid);
2671			qp->pri.vid = qp->pri.candidate_vid;
2672			qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2673			qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2674		}
2675		qp->pri.candidate_vid = 0xFFFF;
2676		qp->pri.update_vid = 0;
2677	}
2678
2679	if (qp->alt.update_vid) {
2680		if (err) {
2681			if (qp->alt.candidate_vid < 0x1000)
2682				mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2683						     qp->alt.candidate_vid);
2684		} else {
2685			if (qp->alt.vid < 0x1000)
2686				mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2687						     qp->alt.vid);
2688			qp->alt.vid = qp->alt.candidate_vid;
2689			qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2690			qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2691		}
2692		qp->alt.candidate_vid = 0xFFFF;
2693		qp->alt.update_vid = 0;
2694	}
2695
2696	return err;
2697}
2698
2699enum {
2700	MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE	|
2701					      IB_QP_PORT),
2702};
2703
2704static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2705			      int attr_mask, struct ib_udata *udata)
2706{
2707	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2708	struct mlx4_ib_qp *qp = to_mqp(ibqp);
2709	enum ib_qp_state cur_state, new_state;
2710	int err = -EINVAL;
2711	mutex_lock(&qp->mutex);
2712
2713	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2714	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2715
2716	if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2717				attr_mask)) {
2718		pr_debug("qpn 0x%x: invalid attribute mask specified "
2719			 "for transition %d to %d. qp_type %d,"
2720			 " attr_mask 0x%x\n",
2721			 ibqp->qp_num, cur_state, new_state,
2722			 ibqp->qp_type, attr_mask);
2723		goto out;
2724	}
2725
2726	if (ibqp->rwq_ind_tbl) {
2727		if (!(((cur_state == IB_QPS_RESET) &&
2728		       (new_state == IB_QPS_INIT)) ||
2729		      ((cur_state == IB_QPS_INIT)  &&
2730		       (new_state == IB_QPS_RTR)))) {
2731			pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2732				 ibqp->qp_num, cur_state, new_state);
2733
2734			err = -EOPNOTSUPP;
2735			goto out;
2736		}
2737
2738		if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2739			pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2740				 ibqp->qp_num, attr_mask, cur_state, new_state);
2741
2742			err = -EOPNOTSUPP;
2743			goto out;
2744		}
2745	}
2746
2747	if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2748		if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2749			if ((ibqp->qp_type == IB_QPT_RC) ||
2750			    (ibqp->qp_type == IB_QPT_UD) ||
2751			    (ibqp->qp_type == IB_QPT_UC) ||
2752			    (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2753			    (ibqp->qp_type == IB_QPT_XRC_INI)) {
2754				attr->port_num = mlx4_ib_bond_next_port(dev);
2755			}
2756		} else {
2757			/* no sense in changing port_num
2758			 * when ports are bonded */
2759			attr_mask &= ~IB_QP_PORT;
2760		}
2761	}
2762
2763	if ((attr_mask & IB_QP_PORT) &&
2764	    (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2765		pr_debug("qpn 0x%x: invalid port number (%d) specified "
2766			 "for transition %d to %d. qp_type %d\n",
2767			 ibqp->qp_num, attr->port_num, cur_state,
2768			 new_state, ibqp->qp_type);
2769		goto out;
2770	}
2771
2772	if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2773	    (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2774	     IB_LINK_LAYER_ETHERNET))
2775		goto out;
2776
2777	if (attr_mask & IB_QP_PKEY_INDEX) {
2778		int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2779		if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2780			pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2781				 "for transition %d to %d. qp_type %d\n",
2782				 ibqp->qp_num, attr->pkey_index, cur_state,
2783				 new_state, ibqp->qp_type);
2784			goto out;
2785		}
2786	}
2787
2788	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2789	    attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2790		pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2791			 "Transition %d to %d. qp_type %d\n",
2792			 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2793			 new_state, ibqp->qp_type);
2794		goto out;
2795	}
2796
2797	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2798	    attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2799		pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2800			 "Transition %d to %d. qp_type %d\n",
2801			 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2802			 new_state, ibqp->qp_type);
2803		goto out;
2804	}
2805
2806	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2807		err = 0;
2808		goto out;
2809	}
2810
2811	if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2812		err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2813				       udata);
2814		if (err)
2815			goto out;
2816	}
2817
2818	err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2819				  cur_state, new_state, udata);
2820
2821	if (ibqp->rwq_ind_tbl && err)
2822		bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
2823
2824	if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2825		attr->port_num = 1;
2826
2827out:
2828	mutex_unlock(&qp->mutex);
2829	return err;
2830}
2831
2832int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2833		      int attr_mask, struct ib_udata *udata)
2834{
2835	struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2836	int ret;
2837
2838	if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
2839		return -EOPNOTSUPP;
2840
2841	ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2842
2843	if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2844		struct mlx4_ib_sqp *sqp = mqp->sqp;
2845		int err = 0;
2846
2847		if (sqp->roce_v2_gsi)
2848			err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2849		if (err)
2850			pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2851			       err);
2852	}
2853	return ret;
2854}
2855
2856static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2857{
2858	int i;
2859	for (i = 0; i < dev->caps.num_ports; i++) {
2860		if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2861		    qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2862			*qkey = dev->caps.spec_qps[i].qp0_qkey;
2863			return 0;
2864		}
2865	}
2866	return -EINVAL;
2867}
2868
2869static int build_sriov_qp0_header(struct mlx4_ib_qp *qp,
2870				  const struct ib_ud_wr *wr,
2871				  void *wqe, unsigned *mlx_seg_len)
2872{
2873	struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device);
2874	struct mlx4_ib_sqp *sqp = qp->sqp;
2875	struct ib_device *ib_dev = qp->ibqp.device;
2876	struct mlx4_wqe_mlx_seg *mlx = wqe;
2877	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2878	struct mlx4_ib_ah *ah = to_mah(wr->ah);
2879	u16 pkey;
2880	u32 qkey;
2881	int send_size;
2882	int header_size;
2883	int spc;
2884	int err;
2885	int i;
2886
2887	if (wr->wr.opcode != IB_WR_SEND)
2888		return -EINVAL;
2889
2890	send_size = 0;
2891
2892	for (i = 0; i < wr->wr.num_sge; ++i)
2893		send_size += wr->wr.sg_list[i].length;
2894
2895	/* for proxy-qp0 sends, need to add in size of tunnel header */
2896	/* for tunnel-qp0 sends, tunnel header is already in s/g list */
2897	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2898		send_size += sizeof (struct mlx4_ib_tunnel_header);
2899
2900	ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2901
2902	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2903		sqp->ud_header.lrh.service_level =
2904			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2905		sqp->ud_header.lrh.destination_lid =
2906			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2907		sqp->ud_header.lrh.source_lid =
2908			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2909	}
2910
2911	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2912
2913	/* force loopback */
2914	mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2915	mlx->rlid = sqp->ud_header.lrh.destination_lid;
2916
2917	sqp->ud_header.lrh.virtual_lane    = 0;
2918	sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2919	err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey);
2920	if (err)
2921		return err;
2922	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2923	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2924		sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2925	else
2926		sqp->ud_header.bth.destination_qpn =
2927			cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel);
2928
2929	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2930	if (mlx4_is_master(mdev->dev)) {
2931		if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey))
2932			return -EINVAL;
2933	} else {
2934		if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey))
2935			return -EINVAL;
2936	}
2937	sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2938	sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn);
2939
2940	sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2941	sqp->ud_header.immediate_present = 0;
2942
2943	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2944
2945	/*
2946	 * Inline data segments may not cross a 64 byte boundary.  If
2947	 * our UD header is bigger than the space available up to the
2948	 * next 64 byte boundary in the WQE, use two inline data
2949	 * segments to hold the UD header.
2950	 */
2951	spc = MLX4_INLINE_ALIGN -
2952	      ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2953	if (header_size <= spc) {
2954		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2955		memcpy(inl + 1, sqp->header_buf, header_size);
2956		i = 1;
2957	} else {
2958		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2959		memcpy(inl + 1, sqp->header_buf, spc);
2960
2961		inl = (void *) (inl + 1) + spc;
2962		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2963		/*
2964		 * Need a barrier here to make sure all the data is
2965		 * visible before the byte_count field is set.
2966		 * Otherwise the HCA prefetcher could grab the 64-byte
2967		 * chunk with this inline segment and get a valid (!=
2968		 * 0xffffffff) byte count but stale data, and end up
2969		 * generating a packet with bad headers.
2970		 *
2971		 * The first inline segment's byte_count field doesn't
2972		 * need a barrier, because it comes after a
2973		 * control/MLX segment and therefore is at an offset
2974		 * of 16 mod 64.
2975		 */
2976		wmb();
2977		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2978		i = 2;
2979	}
2980
2981	*mlx_seg_len =
2982	ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2983	return 0;
2984}
2985
2986static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2987{
2988	union sl2vl_tbl_to_u64 tmp_vltab;
2989	u8 vl;
2990
2991	if (sl > 15)
2992		return 0xf;
2993	tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2994	vl = tmp_vltab.sl8[sl >> 1];
2995	if (sl & 1)
2996		vl &= 0x0f;
2997	else
2998		vl >>= 4;
2999	return vl;
3000}
3001
3002static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3003				int index, union ib_gid *gid,
3004				enum ib_gid_type *gid_type)
3005{
3006	struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3007	struct mlx4_port_gid_table *port_gid_table;
3008	unsigned long flags;
3009
3010	port_gid_table = &iboe->gids[port_num - 1];
3011	spin_lock_irqsave(&iboe->lock, flags);
3012	memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3013	*gid_type = port_gid_table->gids[index].gid_type;
3014	spin_unlock_irqrestore(&iboe->lock, flags);
3015	if (rdma_is_zero_gid(gid))
3016		return -ENOENT;
3017
3018	return 0;
3019}
3020
3021#define MLX4_ROCEV2_QP1_SPORT 0xC000
3022static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr,
3023			    void *wqe, unsigned *mlx_seg_len)
3024{
3025	struct mlx4_ib_sqp *sqp = qp->sqp;
3026	struct ib_device *ib_dev = qp->ibqp.device;
3027	struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
3028	struct mlx4_wqe_mlx_seg *mlx = wqe;
3029	struct mlx4_wqe_ctrl_seg *ctrl = wqe;
3030	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
3031	struct mlx4_ib_ah *ah = to_mah(wr->ah);
3032	union ib_gid sgid;
3033	u16 pkey;
3034	int send_size;
3035	int header_size;
3036	int spc;
3037	int i;
3038	int err = 0;
3039	u16 vlan = 0xffff;
3040	bool is_eth;
3041	bool is_vlan = false;
3042	bool is_grh;
3043	bool is_udp = false;
3044	int ip_version = 0;
3045
3046	send_size = 0;
3047	for (i = 0; i < wr->wr.num_sge; ++i)
3048		send_size += wr->wr.sg_list[i].length;
3049
3050	is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET;
3051	is_grh = mlx4_ib_ah_grh_present(ah);
3052	if (is_eth) {
3053		enum ib_gid_type gid_type;
3054		if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3055			/* When multi-function is enabled, the ib_core gid
3056			 * indexes don't necessarily match the hw ones, so
3057			 * we must use our own cache */
3058			err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3059							   be32_to_cpu(ah->av.ib.port_pd) >> 24,
3060							   ah->av.ib.gid_index, &sgid.raw[0]);
3061			if (err)
3062				return err;
3063		} else  {
3064			err = fill_gid_by_hw_index(ibdev, qp->port,
3065						   ah->av.ib.gid_index, &sgid,
3066						   &gid_type);
3067			if (!err) {
3068				is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3069				if (is_udp) {
3070					if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3071						ip_version = 4;
3072					else
3073						ip_version = 6;
3074					is_grh = false;
3075				}
3076			} else {
3077				return err;
3078			}
3079		}
3080		if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3081			vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3082			is_vlan = true;
3083		}
3084	}
3085	err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3086			  ip_version, is_udp, 0, &sqp->ud_header);
3087	if (err)
3088		return err;
3089
3090	if (!is_eth) {
3091		sqp->ud_header.lrh.service_level =
3092			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3093		sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3094		sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3095	}
3096
3097	if (is_grh || (ip_version == 6)) {
3098		sqp->ud_header.grh.traffic_class =
3099			(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3100		sqp->ud_header.grh.flow_label    =
3101			ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3102		sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
3103		if (is_eth) {
3104			memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3105		} else {
3106			if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3107				/* When multi-function is enabled, the ib_core gid
3108				 * indexes don't necessarily match the hw ones, so
3109				 * we must use our own cache
3110				 */
3111				sqp->ud_header.grh.source_gid.global
3112					.subnet_prefix =
3113					cpu_to_be64(atomic64_read(
3114						&(to_mdev(ib_dev)
3115							  ->sriov
3116							  .demux[qp->port - 1]
3117							  .subnet_prefix)));
3118				sqp->ud_header.grh.source_gid.global
3119					.interface_id =
3120					to_mdev(ib_dev)
3121						->sriov.demux[qp->port - 1]
3122						.guid_cache[ah->av.ib.gid_index];
3123			} else {
3124				sqp->ud_header.grh.source_gid =
3125					ah->ibah.sgid_attr->gid;
3126			}
3127		}
3128		memcpy(sqp->ud_header.grh.destination_gid.raw,
3129		       ah->av.ib.dgid, 16);
3130	}
3131
3132	if (ip_version == 4) {
3133		sqp->ud_header.ip4.tos =
3134			(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3135		sqp->ud_header.ip4.id = 0;
3136		sqp->ud_header.ip4.frag_off = htons(IP_DF);
3137		sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3138
3139		memcpy(&sqp->ud_header.ip4.saddr,
3140		       sgid.raw + 12, 4);
3141		memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3142		sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3143	}
3144
3145	if (is_udp) {
3146		sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3147		sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3148		sqp->ud_header.udp.csum = 0;
3149	}
3150
3151	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3152
3153	if (!is_eth) {
3154		mlx->flags |=
3155			cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3156				    (sqp->ud_header.lrh.destination_lid ==
3157						     IB_LID_PERMISSIVE ?
3158					     MLX4_WQE_MLX_SLR :
3159					     0) |
3160				    (sqp->ud_header.lrh.service_level << 8));
3161		if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3162			mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3163		mlx->rlid = sqp->ud_header.lrh.destination_lid;
3164	}
3165
3166	switch (wr->wr.opcode) {
3167	case IB_WR_SEND:
3168		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY;
3169		sqp->ud_header.immediate_present = 0;
3170		break;
3171	case IB_WR_SEND_WITH_IMM:
3172		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3173		sqp->ud_header.immediate_present = 1;
3174		sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
3175		break;
3176	default:
3177		return -EINVAL;
3178	}
3179
3180	if (is_eth) {
3181		u16 ether_type;
3182		u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3183
3184		ether_type = (!is_udp) ? ETH_P_IBOE:
3185			(ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3186
3187		mlx->sched_prio = cpu_to_be16(pcp);
3188
3189		ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3190		ether_addr_copy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac);
3191		memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3192		memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3193
3194		if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3195			mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3196		if (!is_vlan) {
3197			sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3198		} else {
3199			sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3200			sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3201		}
3202	} else {
3203		sqp->ud_header.lrh.virtual_lane =
3204			!qp->ibqp.qp_num ?
3205				15 :
3206				sl_to_vl(to_mdev(ib_dev),
3207					 sqp->ud_header.lrh.service_level,
3208					 qp->port);
3209		if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3210			return -EINVAL;
3211		if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3212			sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3213	}
3214	sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3215	if (!qp->ibqp.qp_num)
3216		err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index,
3217					 &pkey);
3218	else
3219		err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index,
3220					 &pkey);
3221	if (err)
3222		return err;
3223
3224	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3225	sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3226	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3227	sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3228					       sqp->qkey : wr->remote_qkey);
3229	sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num);
3230
3231	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3232
3233	if (0) {
3234		pr_err("built UD header of size %d:\n", header_size);
3235		for (i = 0; i < header_size / 4; ++i) {
3236			if (i % 8 == 0)
3237				pr_err("  [%02x] ", i * 4);
3238			pr_cont(" %08x",
3239				be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3240			if ((i + 1) % 8 == 0)
3241				pr_cont("\n");
3242		}
3243		pr_err("\n");
3244	}
3245
3246	/*
3247	 * Inline data segments may not cross a 64 byte boundary.  If
3248	 * our UD header is bigger than the space available up to the
3249	 * next 64 byte boundary in the WQE, use two inline data
3250	 * segments to hold the UD header.
3251	 */
3252	spc = MLX4_INLINE_ALIGN -
3253		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3254	if (header_size <= spc) {
3255		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3256		memcpy(inl + 1, sqp->header_buf, header_size);
3257		i = 1;
3258	} else {
3259		inl->byte_count = cpu_to_be32(1 << 31 | spc);
3260		memcpy(inl + 1, sqp->header_buf, spc);
3261
3262		inl = (void *) (inl + 1) + spc;
3263		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3264		/*
3265		 * Need a barrier here to make sure all the data is
3266		 * visible before the byte_count field is set.
3267		 * Otherwise the HCA prefetcher could grab the 64-byte
3268		 * chunk with this inline segment and get a valid (!=
3269		 * 0xffffffff) byte count but stale data, and end up
3270		 * generating a packet with bad headers.
3271		 *
3272		 * The first inline segment's byte_count field doesn't
3273		 * need a barrier, because it comes after a
3274		 * control/MLX segment and therefore is at an offset
3275		 * of 16 mod 64.
3276		 */
3277		wmb();
3278		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3279		i = 2;
3280	}
3281
3282	*mlx_seg_len =
3283		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3284	return 0;
3285}
3286
3287static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3288{
3289	unsigned cur;
3290	struct mlx4_ib_cq *cq;
3291
3292	cur = wq->head - wq->tail;
3293	if (likely(cur + nreq < wq->max_post))
3294		return 0;
3295
3296	cq = to_mcq(ib_cq);
3297	spin_lock(&cq->lock);
3298	cur = wq->head - wq->tail;
3299	spin_unlock(&cq->lock);
3300
3301	return cur + nreq >= wq->max_post;
3302}
3303
3304static __be32 convert_access(int acc)
3305{
3306	return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3307		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
3308	       (acc & IB_ACCESS_REMOTE_WRITE  ?
3309		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3310	       (acc & IB_ACCESS_REMOTE_READ   ?
3311		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
3312	       (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
3313		cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3314}
3315
3316static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3317			const struct ib_reg_wr *wr)
3318{
3319	struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3320
3321	fseg->flags		= convert_access(wr->access);
3322	fseg->mem_key		= cpu_to_be32(wr->key);
3323	fseg->buf_list		= cpu_to_be64(mr->page_map);
3324	fseg->start_addr	= cpu_to_be64(mr->ibmr.iova);
3325	fseg->reg_len		= cpu_to_be64(mr->ibmr.length);
3326	fseg->offset		= 0; /* XXX -- is this just for ZBVA? */
3327	fseg->page_size		= cpu_to_be32(ilog2(mr->ibmr.page_size));
3328	fseg->reserved[0]	= 0;
3329	fseg->reserved[1]	= 0;
3330}
3331
3332static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3333{
3334	memset(iseg, 0, sizeof(*iseg));
3335	iseg->mem_key = cpu_to_be32(rkey);
3336}
3337
3338static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3339					  u64 remote_addr, u32 rkey)
3340{
3341	rseg->raddr    = cpu_to_be64(remote_addr);
3342	rseg->rkey     = cpu_to_be32(rkey);
3343	rseg->reserved = 0;
3344}
3345
3346static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3347			   const struct ib_atomic_wr *wr)
3348{
3349	if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3350		aseg->swap_add = cpu_to_be64(wr->swap);
3351		aseg->compare  = cpu_to_be64(wr->compare_add);
3352	} else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3353		aseg->swap_add = cpu_to_be64(wr->compare_add);
3354		aseg->compare  = cpu_to_be64(wr->compare_add_mask);
3355	} else {
3356		aseg->swap_add = cpu_to_be64(wr->compare_add);
3357		aseg->compare  = 0;
3358	}
3359
3360}
3361
3362static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3363				  const struct ib_atomic_wr *wr)
3364{
3365	aseg->swap_add		= cpu_to_be64(wr->swap);
3366	aseg->swap_add_mask	= cpu_to_be64(wr->swap_mask);
3367	aseg->compare		= cpu_to_be64(wr->compare_add);
3368	aseg->compare_mask	= cpu_to_be64(wr->compare_add_mask);
3369}
3370
3371static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3372			     const struct ib_ud_wr *wr)
3373{
3374	memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3375	dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3376	dseg->qkey = cpu_to_be32(wr->remote_qkey);
3377	dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3378	memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3379}
3380
3381static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3382				    struct mlx4_wqe_datagram_seg *dseg,
3383				    const struct ib_ud_wr *wr,
3384				    enum mlx4_ib_qp_type qpt)
3385{
3386	union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3387	struct mlx4_av sqp_av = {0};
3388	int port = *((u8 *) &av->ib.port_pd) & 0x3;
3389
3390	/* force loopback */
3391	sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3392	sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3393	sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3394			cpu_to_be32(0xf0000000);
3395
3396	memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3397	if (qpt == MLX4_IB_QPT_PROXY_GSI)
3398		dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3399	else
3400		dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3401	/* Use QKEY from the QP context, which is set by master */
3402	dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3403}
3404
3405static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3406				unsigned *mlx_seg_len)
3407{
3408	struct mlx4_wqe_inline_seg *inl = wqe;
3409	struct mlx4_ib_tunnel_header hdr;
3410	struct mlx4_ib_ah *ah = to_mah(wr->ah);
3411	int spc;
3412	int i;
3413
3414	memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3415	hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3416	hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3417	hdr.qkey = cpu_to_be32(wr->remote_qkey);
3418	memcpy(hdr.mac, ah->av.eth.mac, 6);
3419	hdr.vlan = ah->av.eth.vlan;
3420
3421	spc = MLX4_INLINE_ALIGN -
3422		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3423	if (sizeof (hdr) <= spc) {
3424		memcpy(inl + 1, &hdr, sizeof (hdr));
3425		wmb();
3426		inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3427		i = 1;
3428	} else {
3429		memcpy(inl + 1, &hdr, spc);
3430		wmb();
3431		inl->byte_count = cpu_to_be32(1 << 31 | spc);
3432
3433		inl = (void *) (inl + 1) + spc;
3434		memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3435		wmb();
3436		inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3437		i = 2;
3438	}
3439
3440	*mlx_seg_len =
3441		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3442}
3443
3444static void set_mlx_icrc_seg(void *dseg)
3445{
3446	u32 *t = dseg;
3447	struct mlx4_wqe_inline_seg *iseg = dseg;
3448
3449	t[1] = 0;
3450
3451	/*
3452	 * Need a barrier here before writing the byte_count field to
3453	 * make sure that all the data is visible before the
3454	 * byte_count field is set.  Otherwise, if the segment begins
3455	 * a new cacheline, the HCA prefetcher could grab the 64-byte
3456	 * chunk and get a valid (!= * 0xffffffff) byte count but
3457	 * stale data, and end up sending the wrong data.
3458	 */
3459	wmb();
3460
3461	iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3462}
3463
3464static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3465{
3466	dseg->lkey       = cpu_to_be32(sg->lkey);
3467	dseg->addr       = cpu_to_be64(sg->addr);
3468
3469	/*
3470	 * Need a barrier here before writing the byte_count field to
3471	 * make sure that all the data is visible before the
3472	 * byte_count field is set.  Otherwise, if the segment begins
3473	 * a new cacheline, the HCA prefetcher could grab the 64-byte
3474	 * chunk and get a valid (!= * 0xffffffff) byte count but
3475	 * stale data, and end up sending the wrong data.
3476	 */
3477	wmb();
3478
3479	dseg->byte_count = cpu_to_be32(sg->length);
3480}
3481
3482static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3483{
3484	dseg->byte_count = cpu_to_be32(sg->length);
3485	dseg->lkey       = cpu_to_be32(sg->lkey);
3486	dseg->addr       = cpu_to_be64(sg->addr);
3487}
3488
3489static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3490			 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3491			 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
3492{
3493	unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3494
3495	if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3496		*blh = cpu_to_be32(1 << 6);
3497
3498	if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3499		     wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3500		return -EINVAL;
3501
3502	memcpy(wqe->header, wr->header, wr->hlen);
3503
3504	*lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
3505	*lso_seg_len = halign;
3506	return 0;
3507}
3508
3509static __be32 send_ieth(const struct ib_send_wr *wr)
3510{
3511	switch (wr->opcode) {
3512	case IB_WR_SEND_WITH_IMM:
3513	case IB_WR_RDMA_WRITE_WITH_IMM:
3514		return wr->ex.imm_data;
3515
3516	case IB_WR_SEND_WITH_INV:
3517		return cpu_to_be32(wr->ex.invalidate_rkey);
3518
3519	default:
3520		return 0;
3521	}
3522}
3523
3524static void add_zero_len_inline(void *wqe)
3525{
3526	struct mlx4_wqe_inline_seg *inl = wqe;
3527	memset(wqe, 0, 16);
3528	inl->byte_count = cpu_to_be32(1 << 31);
3529}
3530
3531static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3532			      const struct ib_send_wr **bad_wr, bool drain)
3533{
3534	struct mlx4_ib_qp *qp = to_mqp(ibqp);
3535	void *wqe;
3536	struct mlx4_wqe_ctrl_seg *ctrl;
3537	struct mlx4_wqe_data_seg *dseg;
3538	unsigned long flags;
3539	int nreq;
3540	int err = 0;
3541	unsigned ind;
3542	int size;
3543	unsigned seglen;
3544	__be32 dummy;
3545	__be32 *lso_wqe;
3546	__be32 lso_hdr_sz;
3547	__be32 blh;
3548	int i;
3549	struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3550
3551	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3552		struct mlx4_ib_sqp *sqp = qp->sqp;
3553
3554		if (sqp->roce_v2_gsi) {
3555			struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3556			enum ib_gid_type gid_type;
3557			union ib_gid gid;
3558
3559			if (!fill_gid_by_hw_index(mdev, qp->port,
3560					   ah->av.ib.gid_index,
3561					   &gid, &gid_type))
3562				qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3563						to_mqp(sqp->roce_v2_gsi) : qp;
3564			else
3565				pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3566				       ah->av.ib.gid_index);
3567		}
3568	}
3569
3570	spin_lock_irqsave(&qp->sq.lock, flags);
3571	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3572	    !drain) {
3573		err = -EIO;
3574		*bad_wr = wr;
3575		nreq = 0;
3576		goto out;
3577	}
3578
3579	ind = qp->sq_next_wqe;
3580
3581	for (nreq = 0; wr; ++nreq, wr = wr->next) {
3582		lso_wqe = &dummy;
3583		blh = 0;
3584
3585		if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3586			err = -ENOMEM;
3587			*bad_wr = wr;
3588			goto out;
3589		}
3590
3591		if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3592			err = -EINVAL;
3593			*bad_wr = wr;
3594			goto out;
3595		}
3596
3597		ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3598		qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3599
3600		ctrl->srcrb_flags =
3601			(wr->send_flags & IB_SEND_SIGNALED ?
3602			 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3603			(wr->send_flags & IB_SEND_SOLICITED ?
3604			 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3605			((wr->send_flags & IB_SEND_IP_CSUM) ?
3606			 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3607				     MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3608			qp->sq_signal_bits;
3609
3610		ctrl->imm = send_ieth(wr);
3611
3612		wqe += sizeof *ctrl;
3613		size = sizeof *ctrl / 16;
3614
3615		switch (qp->mlx4_ib_qp_type) {
3616		case MLX4_IB_QPT_RC:
3617		case MLX4_IB_QPT_UC:
3618			switch (wr->opcode) {
3619			case IB_WR_ATOMIC_CMP_AND_SWP:
3620			case IB_WR_ATOMIC_FETCH_AND_ADD:
3621			case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3622				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3623					      atomic_wr(wr)->rkey);
3624				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3625
3626				set_atomic_seg(wqe, atomic_wr(wr));
3627				wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3628
3629				size += (sizeof (struct mlx4_wqe_raddr_seg) +
3630					 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3631
3632				break;
3633
3634			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3635				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3636					      atomic_wr(wr)->rkey);
3637				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3638
3639				set_masked_atomic_seg(wqe, atomic_wr(wr));
3640				wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3641
3642				size += (sizeof (struct mlx4_wqe_raddr_seg) +
3643					 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3644
3645				break;
3646
3647			case IB_WR_RDMA_READ:
3648			case IB_WR_RDMA_WRITE:
3649			case IB_WR_RDMA_WRITE_WITH_IMM:
3650				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3651					      rdma_wr(wr)->rkey);
3652				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3653				size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3654				break;
3655
3656			case IB_WR_LOCAL_INV:
3657				ctrl->srcrb_flags |=
3658					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3659				set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3660				wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3661				size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3662				break;
3663
3664			case IB_WR_REG_MR:
3665				ctrl->srcrb_flags |=
3666					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3667				set_reg_seg(wqe, reg_wr(wr));
3668				wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3669				size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3670				break;
3671
3672			default:
3673				/* No extra segments required for sends */
3674				break;
3675			}
3676			break;
3677
3678		case MLX4_IB_QPT_TUN_SMI_OWNER:
3679			err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3680						     &seglen);
3681			if (unlikely(err)) {
3682				*bad_wr = wr;
3683				goto out;
3684			}
3685			wqe  += seglen;
3686			size += seglen / 16;
3687			break;
3688		case MLX4_IB_QPT_TUN_SMI:
3689		case MLX4_IB_QPT_TUN_GSI:
3690			/* this is a UD qp used in MAD responses to slaves. */
3691			set_datagram_seg(wqe, ud_wr(wr));
3692			/* set the forced-loopback bit in the data seg av */
3693			*(__be32 *) wqe |= cpu_to_be32(0x80000000);
3694			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3695			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3696			break;
3697		case MLX4_IB_QPT_UD:
3698			set_datagram_seg(wqe, ud_wr(wr));
3699			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3700			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3701
3702			if (wr->opcode == IB_WR_LSO) {
3703				err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3704						&lso_hdr_sz, &blh);
3705				if (unlikely(err)) {
3706					*bad_wr = wr;
3707					goto out;
3708				}
3709				lso_wqe = (__be32 *) wqe;
3710				wqe  += seglen;
3711				size += seglen / 16;
3712			}
3713			break;
3714
3715		case MLX4_IB_QPT_PROXY_SMI_OWNER:
3716			err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3717						     &seglen);
3718			if (unlikely(err)) {
3719				*bad_wr = wr;
3720				goto out;
3721			}
3722			wqe  += seglen;
3723			size += seglen / 16;
3724			/* to start tunnel header on a cache-line boundary */
3725			add_zero_len_inline(wqe);
3726			wqe += 16;
3727			size++;
3728			build_tunnel_header(ud_wr(wr), wqe, &seglen);
3729			wqe  += seglen;
3730			size += seglen / 16;
3731			break;
3732		case MLX4_IB_QPT_PROXY_SMI:
3733		case MLX4_IB_QPT_PROXY_GSI:
3734			/* If we are tunneling special qps, this is a UD qp.
3735			 * In this case we first add a UD segment targeting
3736			 * the tunnel qp, and then add a header with address
3737			 * information */
3738			set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3739						ud_wr(wr),
3740						qp->mlx4_ib_qp_type);
3741			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3742			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3743			build_tunnel_header(ud_wr(wr), wqe, &seglen);
3744			wqe  += seglen;
3745			size += seglen / 16;
3746			break;
3747
3748		case MLX4_IB_QPT_SMI:
3749		case MLX4_IB_QPT_GSI:
3750			err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen);
3751			if (unlikely(err)) {
3752				*bad_wr = wr;
3753				goto out;
3754			}
3755			wqe  += seglen;
3756			size += seglen / 16;
3757			break;
3758
3759		default:
3760			break;
3761		}
3762
3763		/*
3764		 * Write data segments in reverse order, so as to
3765		 * overwrite cacheline stamp last within each
3766		 * cacheline.  This avoids issues with WQE
3767		 * prefetching.
3768		 */
3769
3770		dseg = wqe;
3771		dseg += wr->num_sge - 1;
3772		size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3773
3774		/* Add one more inline data segment for ICRC for MLX sends */
3775		if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3776			     qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3777			     qp->mlx4_ib_qp_type &
3778			     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3779			set_mlx_icrc_seg(dseg + 1);
3780			size += sizeof (struct mlx4_wqe_data_seg) / 16;
3781		}
3782
3783		for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3784			set_data_seg(dseg, wr->sg_list + i);
3785
3786		/*
3787		 * Possibly overwrite stamping in cacheline with LSO
3788		 * segment only after making sure all data segments
3789		 * are written.
3790		 */
3791		wmb();
3792		*lso_wqe = lso_hdr_sz;
3793
3794		ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3795					     MLX4_WQE_CTRL_FENCE : 0) | size;
3796
3797		/*
3798		 * Make sure descriptor is fully written before
3799		 * setting ownership bit (because HW can start
3800		 * executing as soon as we do).
3801		 */
3802		wmb();
3803
3804		if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3805			*bad_wr = wr;
3806			err = -EINVAL;
3807			goto out;
3808		}
3809
3810		ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3811			(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3812
3813		/*
3814		 * We can improve latency by not stamping the last
3815		 * send queue WQE until after ringing the doorbell, so
3816		 * only stamp here if there are still more WQEs to post.
3817		 */
3818		if (wr->next)
3819			stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3820		ind++;
3821	}
3822
3823out:
3824	if (likely(nreq)) {
3825		qp->sq.head += nreq;
3826
3827		/*
3828		 * Make sure that descriptors are written before
3829		 * doorbell record.
3830		 */
3831		wmb();
3832
3833		writel_relaxed(qp->doorbell_qpn,
3834			to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3835
3836		stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
3837
3838		qp->sq_next_wqe = ind;
3839	}
3840
3841	spin_unlock_irqrestore(&qp->sq.lock, flags);
3842
3843	return err;
3844}
3845
3846int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3847		      const struct ib_send_wr **bad_wr)
3848{
3849	return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3850}
3851
3852static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3853			      const struct ib_recv_wr **bad_wr, bool drain)
3854{
3855	struct mlx4_ib_qp *qp = to_mqp(ibqp);
3856	struct mlx4_wqe_data_seg *scat;
3857	unsigned long flags;
3858	int err = 0;
3859	int nreq;
3860	int ind;
3861	int max_gs;
3862	int i;
3863	struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3864
3865	max_gs = qp->rq.max_gs;
3866	spin_lock_irqsave(&qp->rq.lock, flags);
3867
3868	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3869	    !drain) {
3870		err = -EIO;
3871		*bad_wr = wr;
3872		nreq = 0;
3873		goto out;
3874	}
3875
3876	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3877
3878	for (nreq = 0; wr; ++nreq, wr = wr->next) {
3879		if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3880			err = -ENOMEM;
3881			*bad_wr = wr;
3882			goto out;
3883		}
3884
3885		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3886			err = -EINVAL;
3887			*bad_wr = wr;
3888			goto out;
3889		}
3890
3891		scat = get_recv_wqe(qp, ind);
3892
3893		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3894		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3895			ib_dma_sync_single_for_device(ibqp->device,
3896						      qp->sqp_proxy_rcv[ind].map,
3897						      sizeof (struct mlx4_ib_proxy_sqp_hdr),
3898						      DMA_FROM_DEVICE);
3899			scat->byte_count =
3900				cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3901			/* use dma lkey from upper layer entry */
3902			scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3903			scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3904			scat++;
3905			max_gs--;
3906		}
3907
3908		for (i = 0; i < wr->num_sge; ++i)
3909			__set_data_seg(scat + i, wr->sg_list + i);
3910
3911		if (i < max_gs) {
3912			scat[i].byte_count = 0;
3913			scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3914			scat[i].addr       = 0;
3915		}
3916
3917		qp->rq.wrid[ind] = wr->wr_id;
3918
3919		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3920	}
3921
3922out:
3923	if (likely(nreq)) {
3924		qp->rq.head += nreq;
3925
3926		/*
3927		 * Make sure that descriptors are written before
3928		 * doorbell record.
3929		 */
3930		wmb();
3931
3932		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3933	}
3934
3935	spin_unlock_irqrestore(&qp->rq.lock, flags);
3936
3937	return err;
3938}
3939
3940int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3941		      const struct ib_recv_wr **bad_wr)
3942{
3943	return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3944}
3945
3946static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3947{
3948	switch (mlx4_state) {
3949	case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3950	case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3951	case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3952	case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3953	case MLX4_QP_STATE_SQ_DRAINING:
3954	case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3955	case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3956	case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3957	default:		     return -1;
3958	}
3959}
3960
3961static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3962{
3963	switch (mlx4_mig_state) {
3964	case MLX4_QP_PM_ARMED:		return IB_MIG_ARMED;
3965	case MLX4_QP_PM_REARM:		return IB_MIG_REARM;
3966	case MLX4_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
3967	default: return -1;
3968	}
3969}
3970
3971static int to_ib_qp_access_flags(int mlx4_flags)
3972{
3973	int ib_flags = 0;
3974
3975	if (mlx4_flags & MLX4_QP_BIT_RRE)
3976		ib_flags |= IB_ACCESS_REMOTE_READ;
3977	if (mlx4_flags & MLX4_QP_BIT_RWE)
3978		ib_flags |= IB_ACCESS_REMOTE_WRITE;
3979	if (mlx4_flags & MLX4_QP_BIT_RAE)
3980		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3981
3982	return ib_flags;
3983}
3984
3985static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
3986			    struct rdma_ah_attr *ah_attr,
3987			    struct mlx4_qp_path *path)
3988{
3989	struct mlx4_dev *dev = ibdev->dev;
3990	u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
3991
3992	memset(ah_attr, 0, sizeof(*ah_attr));
3993	if (port_num == 0 || port_num > dev->caps.num_ports)
3994		return;
3995	ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
3996
3997	if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
3998		rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3999			       ((path->sched_queue & 4) << 1));
4000	else
4001		rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
4002	rdma_ah_set_port_num(ah_attr, port_num);
4003
4004	rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4005	rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4006	rdma_ah_set_static_rate(ah_attr,
4007				path->static_rate ? path->static_rate - 5 : 0);
4008	if (path->grh_mylmc & (1 << 7)) {
4009		rdma_ah_set_grh(ah_attr, NULL,
4010				be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4011				path->mgid_index,
4012				path->hop_limit,
4013				(be32_to_cpu(path->tclass_flowlabel)
4014				 >> 20) & 0xff);
4015		rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4016	}
4017}
4018
4019int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4020		     struct ib_qp_init_attr *qp_init_attr)
4021{
4022	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4023	struct mlx4_ib_qp *qp = to_mqp(ibqp);
4024	struct mlx4_qp_context context;
4025	int mlx4_state;
4026	int err = 0;
4027
4028	if (ibqp->rwq_ind_tbl)
4029		return -EOPNOTSUPP;
4030
4031	mutex_lock(&qp->mutex);
4032
4033	if (qp->state == IB_QPS_RESET) {
4034		qp_attr->qp_state = IB_QPS_RESET;
4035		goto done;
4036	}
4037
4038	err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
4039	if (err) {
4040		err = -EINVAL;
4041		goto out;
4042	}
4043
4044	mlx4_state = be32_to_cpu(context.flags) >> 28;
4045
4046	qp->state		     = to_ib_qp_state(mlx4_state);
4047	qp_attr->qp_state	     = qp->state;
4048	qp_attr->path_mtu	     = context.mtu_msgmax >> 5;
4049	qp_attr->path_mig_state	     =
4050		to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4051	qp_attr->qkey		     = be32_to_cpu(context.qkey);
4052	qp_attr->rq_psn		     = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4053	qp_attr->sq_psn		     = be32_to_cpu(context.next_send_psn) & 0xffffff;
4054	qp_attr->dest_qp_num	     = be32_to_cpu(context.remote_qpn) & 0xffffff;
4055	qp_attr->qp_access_flags     =
4056		to_ib_qp_access_flags(be32_to_cpu(context.params2));
4057
4058	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC ||
4059	    qp->ibqp.qp_type == IB_QPT_XRC_INI ||
4060	    qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
4061		to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4062		to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4063		qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4064		qp_attr->alt_port_num	=
4065			rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4066	}
4067
4068	qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4069	if (qp_attr->qp_state == IB_QPS_INIT)
4070		qp_attr->port_num = qp->port;
4071	else
4072		qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4073
4074	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4075	qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4076
4077	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4078
4079	qp_attr->max_dest_rd_atomic =
4080		1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4081	qp_attr->min_rnr_timer	    =
4082		(be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4083	qp_attr->timeout	    = context.pri_path.ackto >> 3;
4084	qp_attr->retry_cnt	    = (be32_to_cpu(context.params1) >> 16) & 0x7;
4085	qp_attr->rnr_retry	    = (be32_to_cpu(context.params1) >> 13) & 0x7;
4086	qp_attr->alt_timeout	    = context.alt_path.ackto >> 3;
4087
4088done:
4089	qp_attr->cur_qp_state	     = qp_attr->qp_state;
4090	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4091	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4092
4093	if (!ibqp->uobject) {
4094		qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
4095		qp_attr->cap.max_send_sge = qp->sq.max_gs;
4096	} else {
4097		qp_attr->cap.max_send_wr  = 0;
4098		qp_attr->cap.max_send_sge = 0;
4099	}
4100
4101	/*
4102	 * We don't support inline sends for kernel QPs (yet), and we
4103	 * don't know what userspace's value should be.
4104	 */
4105	qp_attr->cap.max_inline_data = 0;
4106
4107	qp_init_attr->cap	     = qp_attr->cap;
4108
4109	qp_init_attr->create_flags = 0;
4110	if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4111		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4112
4113	if (qp->flags & MLX4_IB_QP_LSO)
4114		qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4115
4116	if (qp->flags & MLX4_IB_QP_NETIF)
4117		qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4118
4119	qp_init_attr->sq_sig_type =
4120		qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4121		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4122
4123out:
4124	mutex_unlock(&qp->mutex);
4125	return err;
4126}
4127
4128struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4129				struct ib_wq_init_attr *init_attr,
4130				struct ib_udata *udata)
4131{
4132	struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4133	struct ib_qp_init_attr ib_qp_init_attr = {};
4134	struct mlx4_ib_qp *qp;
4135	struct mlx4_ib_create_wq ucmd;
4136	int err, required_cmd_sz;
4137
4138	if (!udata)
4139		return ERR_PTR(-EINVAL);
4140
4141	required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4142			  sizeof(ucmd.comp_mask);
4143	if (udata->inlen < required_cmd_sz) {
4144		pr_debug("invalid inlen\n");
4145		return ERR_PTR(-EINVAL);
4146	}
4147
4148	if (udata->inlen > sizeof(ucmd) &&
4149	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4150				 udata->inlen - sizeof(ucmd))) {
4151		pr_debug("inlen is not supported\n");
4152		return ERR_PTR(-EOPNOTSUPP);
4153	}
4154
4155	if (udata->outlen)
4156		return ERR_PTR(-EOPNOTSUPP);
4157
4158	if (init_attr->wq_type != IB_WQT_RQ) {
4159		pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4160		return ERR_PTR(-EOPNOTSUPP);
4161	}
4162
4163	if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4164	    !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
4165		pr_debug("unsupported create_flags %u\n",
4166			 init_attr->create_flags);
4167		return ERR_PTR(-EOPNOTSUPP);
4168	}
4169
4170	qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4171	if (!qp)
4172		return ERR_PTR(-ENOMEM);
4173
4174	mutex_init(&qp->mutex);
4175	qp->pri.vid = 0xFFFF;
4176	qp->alt.vid = 0xFFFF;
4177
4178	ib_qp_init_attr.qp_context = init_attr->wq_context;
4179	ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4180	ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4181	ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4182	ib_qp_init_attr.recv_cq = init_attr->cq;
4183	ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4184
4185	if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4186		ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4187
4188	err = create_rq(pd, &ib_qp_init_attr, udata, qp);
4189	if (err) {
4190		kfree(qp);
4191		return ERR_PTR(err);
4192	}
4193
4194	qp->ibwq.event_handler = init_attr->event_handler;
4195	qp->ibwq.wq_num = qp->mqp.qpn;
4196	qp->ibwq.state = IB_WQS_RESET;
4197
4198	return &qp->ibwq;
4199}
4200
4201static int ib_wq2qp_state(enum ib_wq_state state)
4202{
4203	switch (state) {
4204	case IB_WQS_RESET:
4205		return IB_QPS_RESET;
4206	case IB_WQS_RDY:
4207		return IB_QPS_RTR;
4208	default:
4209		return IB_QPS_ERR;
4210	}
4211}
4212
4213static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4214			      struct ib_udata *udata)
4215{
4216	struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4217	enum ib_qp_state qp_cur_state;
4218	enum ib_qp_state qp_new_state;
4219	int attr_mask;
4220	int err;
4221
4222	/* ib_qp.state represents the WQ HW state while ib_wq.state represents
4223	 * the WQ logic state.
4224	 */
4225	qp_cur_state = qp->state;
4226	qp_new_state = ib_wq2qp_state(new_state);
4227
4228	if (ib_wq2qp_state(new_state) == qp_cur_state)
4229		return 0;
4230
4231	if (new_state == IB_WQS_RDY) {
4232		struct ib_qp_attr attr = {};
4233
4234		attr.port_num = qp->port;
4235		attr_mask = IB_QP_PORT;
4236
4237		err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4238					  attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4239					  udata);
4240		if (err) {
4241			pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4242				 ibwq->wq_num);
4243			return err;
4244		}
4245
4246		qp_cur_state = IB_QPS_INIT;
4247	}
4248
4249	attr_mask = 0;
4250	err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4251				  qp_cur_state,  qp_new_state, udata);
4252
4253	if (err && (qp_cur_state == IB_QPS_INIT)) {
4254		qp_new_state = IB_QPS_RESET;
4255		if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4256					attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4257					udata)) {
4258			pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4259				ibwq->wq_num);
4260			qp_new_state = IB_QPS_INIT;
4261		}
4262	}
4263
4264	qp->state = qp_new_state;
4265
4266	return err;
4267}
4268
4269int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4270		      u32 wq_attr_mask, struct ib_udata *udata)
4271{
4272	struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4273	struct mlx4_ib_modify_wq ucmd = {};
4274	size_t required_cmd_sz;
4275	enum ib_wq_state cur_state, new_state;
4276	int err = 0;
4277
4278	required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4279				   sizeof(ucmd.reserved);
4280	if (udata->inlen < required_cmd_sz)
4281		return -EINVAL;
4282
4283	if (udata->inlen > sizeof(ucmd) &&
4284	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4285				 udata->inlen - sizeof(ucmd)))
4286		return -EOPNOTSUPP;
4287
4288	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4289		return -EFAULT;
4290
4291	if (ucmd.comp_mask || ucmd.reserved)
4292		return -EOPNOTSUPP;
4293
4294	if (wq_attr_mask & IB_WQ_FLAGS)
4295		return -EOPNOTSUPP;
4296
4297	cur_state = wq_attr->curr_wq_state;
4298	new_state = wq_attr->wq_state;
4299
4300	if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4301		return -EINVAL;
4302
4303	if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4304		return -EINVAL;
4305
4306	/* Need to protect against the parent RSS which also may modify WQ
4307	 * state.
4308	 */
4309	mutex_lock(&qp->mutex);
4310
4311	/* Can update HW state only if a RSS QP has already associated to this
4312	 * WQ, so we can apply its port on the WQ.
4313	 */
4314	if (qp->rss_usecnt)
4315		err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
4316
4317	if (!err)
4318		ibwq->state = new_state;
4319
4320	mutex_unlock(&qp->mutex);
4321
4322	return err;
4323}
4324
4325int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
4326{
4327	struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4328	struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4329
4330	if (qp->counter_index)
4331		mlx4_ib_free_qp_counter(dev, qp);
4332
4333	destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
4334
4335	kfree(qp);
4336	return 0;
4337}
4338
4339int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table,
4340				 struct ib_rwq_ind_table_init_attr *init_attr,
4341				 struct ib_udata *udata)
4342{
4343	struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4344	unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4345	struct ib_device *device = rwq_ind_table->device;
4346	unsigned int base_wqn;
4347	size_t min_resp_len;
4348	int i, err = 0;
4349
4350	if (udata->inlen > 0 &&
4351	    !ib_is_udata_cleared(udata, 0,
4352				 udata->inlen))
4353		return -EOPNOTSUPP;
4354
4355	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4356	if (udata->outlen && udata->outlen < min_resp_len)
4357		return -EINVAL;
4358
4359	if (ind_tbl_size >
4360	    device->attrs.rss_caps.max_rwq_indirection_table_size) {
4361		pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4362			 ind_tbl_size,
4363			 device->attrs.rss_caps.max_rwq_indirection_table_size);
4364		return -EINVAL;
4365	}
4366
4367	base_wqn = init_attr->ind_tbl[0]->wq_num;
4368
4369	if (base_wqn % ind_tbl_size) {
4370		pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4371			 base_wqn);
4372		return -EINVAL;
4373	}
4374
4375	for (i = 1; i < ind_tbl_size; i++) {
4376		if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4377			pr_debug("indirection table's WQNs aren't consecutive\n");
4378			return -EINVAL;
4379		}
4380	}
4381
4382	if (udata->outlen) {
4383		resp.response_length = offsetof(typeof(resp), response_length) +
4384					sizeof(resp.response_length);
4385		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4386	}
4387
4388	return err;
4389}
4390
4391struct mlx4_ib_drain_cqe {
4392	struct ib_cqe cqe;
4393	struct completion done;
4394};
4395
4396static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4397{
4398	struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4399						     struct mlx4_ib_drain_cqe,
4400						     cqe);
4401
4402	complete(&cqe->done);
4403}
4404
4405/* This function returns only once the drained WR was completed */
4406static void handle_drain_completion(struct ib_cq *cq,
4407				    struct mlx4_ib_drain_cqe *sdrain,
4408				    struct mlx4_ib_dev *dev)
4409{
4410	struct mlx4_dev *mdev = dev->dev;
4411
4412	if (cq->poll_ctx == IB_POLL_DIRECT) {
4413		while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4414			ib_process_cq_direct(cq, -1);
4415		return;
4416	}
4417
4418	if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4419		struct mlx4_ib_cq *mcq = to_mcq(cq);
4420		bool triggered = false;
4421		unsigned long flags;
4422
4423		spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4424		/* Make sure that the CQ handler won't run if wasn't run yet */
4425		if (!mcq->mcq.reset_notify_added)
4426			mcq->mcq.reset_notify_added = 1;
4427		else
4428			triggered = true;
4429		spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4430
4431		if (triggered) {
4432			/* Wait for any scheduled/running task to be ended */
4433			switch (cq->poll_ctx) {
4434			case IB_POLL_SOFTIRQ:
4435				irq_poll_disable(&cq->iop);
4436				irq_poll_enable(&cq->iop);
4437				break;
4438			case IB_POLL_WORKQUEUE:
4439				cancel_work_sync(&cq->work);
4440				break;
4441			default:
4442				WARN_ON_ONCE(1);
4443			}
4444		}
4445
4446		/* Run the CQ handler - this makes sure that the drain WR will
4447		 * be processed if wasn't processed yet.
4448		 */
4449		mcq->mcq.comp(&mcq->mcq);
4450	}
4451
4452	wait_for_completion(&sdrain->done);
4453}
4454
4455void mlx4_ib_drain_sq(struct ib_qp *qp)
4456{
4457	struct ib_cq *cq = qp->send_cq;
4458	struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4459	struct mlx4_ib_drain_cqe sdrain;
4460	const struct ib_send_wr *bad_swr;
4461	struct ib_rdma_wr swr = {
4462		.wr = {
4463			.next = NULL,
4464			{ .wr_cqe	= &sdrain.cqe, },
4465			.opcode	= IB_WR_RDMA_WRITE,
4466		},
4467	};
4468	int ret;
4469	struct mlx4_ib_dev *dev = to_mdev(qp->device);
4470	struct mlx4_dev *mdev = dev->dev;
4471
4472	ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4473	if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4474		WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4475		return;
4476	}
4477
4478	sdrain.cqe.done = mlx4_ib_drain_qp_done;
4479	init_completion(&sdrain.done);
4480
4481	ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4482	if (ret) {
4483		WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4484		return;
4485	}
4486
4487	handle_drain_completion(cq, &sdrain, dev);
4488}
4489
4490void mlx4_ib_drain_rq(struct ib_qp *qp)
4491{
4492	struct ib_cq *cq = qp->recv_cq;
4493	struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4494	struct mlx4_ib_drain_cqe rdrain;
4495	struct ib_recv_wr rwr = {};
4496	const struct ib_recv_wr *bad_rwr;
4497	int ret;
4498	struct mlx4_ib_dev *dev = to_mdev(qp->device);
4499	struct mlx4_dev *mdev = dev->dev;
4500
4501	ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4502	if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4503		WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4504		return;
4505	}
4506
4507	rwr.wr_cqe = &rdrain.cqe;
4508	rdrain.cqe.done = mlx4_ib_drain_qp_done;
4509	init_completion(&rdrain.done);
4510
4511	ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4512	if (ret) {
4513		WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4514		return;
4515	}
4516
4517	handle_drain_completion(cq, &rdrain, dev);
4518}
4519
4520int mlx4_ib_qp_event_init(void)
4521{
4522	mlx4_ib_qp_event_wq = alloc_ordered_workqueue("mlx4_ib_qp_event_wq", 0);
4523	if (!mlx4_ib_qp_event_wq)
4524		return -ENOMEM;
4525
4526	return 0;
4527}
4528
4529void mlx4_ib_qp_event_cleanup(void)
4530{
4531	destroy_workqueue(mlx4_ib_qp_event_wq);
4532}