defs.h

   1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
   2/* Copyright (c) 2015 - 2021 Intel Corporation */
   3#ifndef IRDMA_DEFS_H
   4#define IRDMA_DEFS_H
   5
   6#define IRDMA_FIRST_USER_QP_ID	3
   7
   8#define ECN_CODE_PT_VAL	2
   9
  10#define IRDMA_PUSH_OFFSET		(8 * 1024 * 1024)
  11#define IRDMA_PF_FIRST_PUSH_PAGE_INDEX	16
  12#define IRDMA_PF_BAR_RSVD		(60 * 1024)
  13
  14#define IRDMA_PE_DB_SIZE_4M	1
  15#define IRDMA_PE_DB_SIZE_8M	2
  16
  17#define IRDMA_IRD_HW_SIZE_4_GEN3	0
  18#define IRDMA_IRD_HW_SIZE_8_GEN3	1
  19#define IRDMA_IRD_HW_SIZE_16_GEN3	2
  20#define IRDMA_IRD_HW_SIZE_32_GEN3	3
  21#define IRDMA_IRD_HW_SIZE_64_GEN3	4
  22#define IRDMA_IRD_HW_SIZE_128_GEN3	5
  23#define IRDMA_IRD_HW_SIZE_256_GEN3	6
  24#define IRDMA_IRD_HW_SIZE_512_GEN3	7
  25#define IRDMA_IRD_HW_SIZE_1024_GEN3	8
  26#define IRDMA_IRD_HW_SIZE_2048_GEN3	9
  27#define IRDMA_IRD_HW_SIZE_4096_GEN3	10
  28
  29#define IRDMA_IRD_HW_SIZE_4	0
  30#define IRDMA_IRD_HW_SIZE_16	1
  31#define IRDMA_IRD_HW_SIZE_64	2
  32#define IRDMA_IRD_HW_SIZE_128	3
  33#define IRDMA_IRD_HW_SIZE_256	4
  34
  35enum irdma_protocol_used {
  36	IRDMA_ANY_PROTOCOL = 0,
  37	IRDMA_IWARP_PROTOCOL_ONLY = 1,
  38	IRDMA_ROCE_PROTOCOL_ONLY = 2,
  39};
  40
  41#define IRDMA_QP_STATE_INVALID		0
  42#define IRDMA_QP_STATE_IDLE		1
  43#define IRDMA_QP_STATE_RTS		2
  44#define IRDMA_QP_STATE_CLOSING		3
  45#define IRDMA_QP_STATE_SQD		3
  46#define IRDMA_QP_STATE_RTR		4
  47#define IRDMA_QP_STATE_TERMINATE	5
  48#define IRDMA_QP_STATE_ERROR		6
  49
  50#define IRDMA_MAX_TRAFFIC_CLASS		8
  51#define	IRDMA_MAX_STATS_COUNT_GEN_1	12
  52#define IRDMA_MAX_USER_PRIORITY		8
  53#define IRDMA_MAX_APPS			8
  54#define IRDMA_MAX_STATS_COUNT		128
  55#define IRDMA_FIRST_NON_PF_STAT		4
  56
  57#define IRDMA_MIN_MTU_IPV4	576
  58#define IRDMA_MIN_MTU_IPV6	1280
  59#define IRDMA_MTU_TO_MSS_IPV4	40
  60#define IRDMA_MTU_TO_MSS_IPV6	60
  61#define IRDMA_DEFAULT_MTU	1500
  62
  63#define Q2_FPSN_OFFSET		64
  64#define TERM_DDP_LEN_TAGGED	14
  65#define TERM_DDP_LEN_UNTAGGED	18
  66#define TERM_RDMA_LEN		28
  67#define RDMA_OPCODE_M		0x0f
  68#define RDMA_READ_REQ_OPCODE	1
  69#define Q2_BAD_FRAME_OFFSET	72
  70#define CQE_MAJOR_DRV		0x8000
  71
  72#define IRDMA_TERM_SENT		1
  73#define IRDMA_TERM_RCVD		2
  74#define IRDMA_TERM_DONE		4
  75#define IRDMA_MAC_HLEN		14
  76
  77#define IRDMA_CQP_WAIT_POLL_REGS	1
  78#define IRDMA_CQP_WAIT_POLL_CQ		2
  79#define IRDMA_CQP_WAIT_EVENT		3
  80
  81#define IRDMA_AE_SOURCE_RSVD		0x0
  82#define IRDMA_AE_SOURCE_RQ		0x1
  83#define IRDMA_AE_SOURCE_RQ_0011		0x3
  84
  85#define IRDMA_AE_SOURCE_CQ		0x2
  86#define IRDMA_AE_SOURCE_CQ_0110		0x6
  87#define IRDMA_AE_SOURCE_CQ_1010		0xa
  88#define IRDMA_AE_SOURCE_CQ_1110		0xe
  89
  90#define IRDMA_AE_SOURCE_SQ		0x5
  91#define IRDMA_AE_SOURCE_SQ_0111		0x7
  92
  93#define IRDMA_AE_SOURCE_IN_RR_WR	0x9
  94#define IRDMA_AE_SOURCE_IN_RR_WR_1011	0xb
  95#define IRDMA_AE_SOURCE_OUT_RR		0xd
  96#define IRDMA_AE_SOURCE_OUT_RR_1111	0xf
  97
  98#define IRDMA_TCP_STATE_NON_EXISTENT	0
  99#define IRDMA_TCP_STATE_CLOSED		1
 100#define IRDMA_TCP_STATE_LISTEN		2
 101#define IRDMA_STATE_SYN_SEND		3
 102#define IRDMA_TCP_STATE_SYN_RECEIVED	4
 103#define IRDMA_TCP_STATE_ESTABLISHED	5
 104#define IRDMA_TCP_STATE_CLOSE_WAIT	6
 105#define IRDMA_TCP_STATE_FIN_WAIT_1	7
 106#define IRDMA_TCP_STATE_CLOSING		8
 107#define IRDMA_TCP_STATE_LAST_ACK	9
 108#define IRDMA_TCP_STATE_FIN_WAIT_2	10
 109#define IRDMA_TCP_STATE_TIME_WAIT	11
 110#define IRDMA_TCP_STATE_RESERVED_1	12
 111#define IRDMA_TCP_STATE_RESERVED_2	13
 112#define IRDMA_TCP_STATE_RESERVED_3	14
 113#define IRDMA_TCP_STATE_RESERVED_4	15
 114
 115#define IRDMA_CQP_SW_SQSIZE_4		4
 116#define IRDMA_CQP_SW_SQSIZE_2048	2048
 117
 118#define IRDMA_CQ_TYPE_IWARP	1
 119#define IRDMA_CQ_TYPE_ILQ	2
 120#define IRDMA_CQ_TYPE_IEQ	3
 121#define IRDMA_CQ_TYPE_CQP	4
 122
 123#define IRDMA_DONE_COUNT	1000
 124#define IRDMA_SLEEP_COUNT	10
 125
 126#define IRDMA_UPDATE_SD_BUFF_SIZE	128
 127#define IRDMA_FEATURE_BUF_SIZE		(8 * IRDMA_MAX_FEATURES)
 128
 129#define ENABLE_LOC_MEM			63
 130#define IRDMA_ATOMICS_ALLOWED_BIT	1
 131#define MAX_PBLE_PER_SD			0x40000
 132#define MAX_PBLE_SD_PER_FCN		0x400
 133#define MAX_MR_PER_SD			0x8000
 134#define MAX_MR_SD_PER_FCN		0x80
 135#define IRDMA_PBLE_COMMIT_OFFSET	112
 136#define IRDMA_MAX_QUANTA_PER_WR	8
 137
 138#define IRDMA_QP_SW_MAX_WQ_QUANTA	32768
 139#define IRDMA_QP_SW_MAX_SQ_QUANTA	32768
 140#define IRDMA_QP_SW_MAX_RQ_QUANTA	32768
 141#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \
 142	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
 143#define IRDMA_SRQ_MIN_QUANTA 8
 144#define IRDMA_SRQ_MAX_QUANTA 262144
 145#define IRDMA_MAX_SRQ_WRS \
 146	((IRDMA_SRQ_MAX_QUANTA - IRDMA_RQ_RSVD) / IRDMA_MAX_QUANTA_PER_WR)
 147
 148#define IRDMAQP_TERM_SEND_TERM_AND_FIN		0
 149#define IRDMAQP_TERM_SEND_TERM_ONLY		1
 150#define IRDMAQP_TERM_SEND_FIN_ONLY		2
 151#define IRDMAQP_TERM_DONOT_SEND_TERM_OR_FIN	3
 152
 153#define IRDMA_QP_TYPE_IWARP	1
 154#define IRDMA_QP_TYPE_UDA	2
 155#define IRDMA_QP_TYPE_ROCE_RC	3
 156#define IRDMA_QP_TYPE_ROCE_UD	4
 157
 158#define IRDMA_HW_PAGE_SIZE	4096
 159#define IRDMA_HW_PAGE_SHIFT	12
 160#define IRDMA_CQE_QTYPE_RQ	0
 161#define IRDMA_CQE_QTYPE_SQ	1
 162
 163#define IRDMA_QP_SW_MIN_WQSIZE	8u /* in WRs*/
 164#define IRDMA_QP_WQE_MIN_SIZE	32
 165#define IRDMA_QP_WQE_MAX_SIZE	256
 166#define IRDMA_QP_WQE_MIN_QUANTA 1
 167#define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2
 168#define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3
 169
 170#define IRDMA_SQ_RSVD	258
 171#define IRDMA_RQ_RSVD	1
 172
 173#define IRDMA_FEATURE_RTS_AE			BIT_ULL(0)
 174#define IRDMA_FEATURE_CQ_RESIZE			BIT_ULL(1)
 175#define IRDMA_FEATURE_64_BYTE_CQE		BIT_ULL(5)
 176#define IRDMA_FEATURE_ATOMIC_OPS		BIT_ULL(6)
 177#define IRDMA_FEATURE_SRQ			BIT_ULL(7)
 178#define IRDMA_FEATURE_CQE_TIMESTAMPING		BIT_ULL(8)
 179
 180#define IRDMAQP_OP_RDMA_WRITE			0x00
 181#define IRDMAQP_OP_RDMA_READ			0x01
 182#define IRDMAQP_OP_RDMA_SEND			0x03
 183#define IRDMAQP_OP_RDMA_SEND_INV		0x04
 184#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT		0x05
 185#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV	0x06
 186#define IRDMAQP_OP_BIND_MW			0x08
 187#define IRDMAQP_OP_FAST_REGISTER		0x09
 188#define IRDMAQP_OP_LOCAL_INVALIDATE		0x0a
 189#define IRDMAQP_OP_RDMA_READ_LOC_INV		0x0b
 190#define IRDMAQP_OP_NOP				0x0c
 191#define IRDMAQP_OP_RDMA_WRITE_SOL		0x0d
 192#define IRDMAQP_OP_ATOMIC_FETCH_ADD		0x0f
 193#define IRDMAQP_OP_ATOMIC_COMPARE_SWAP_ADD	0x11
 194#define IRDMAQP_OP_GEN_RTS_AE			0x30
 195
 196enum irdma_cqp_op_type {
 197	IRDMA_OP_CEQ_DESTROY			= 1,
 198	IRDMA_OP_AEQ_DESTROY			= 2,
 199	IRDMA_OP_DELETE_ARP_CACHE_ENTRY		= 3,
 200	IRDMA_OP_MANAGE_APBVT_ENTRY		= 4,
 201	IRDMA_OP_CEQ_CREATE			= 5,
 202	IRDMA_OP_AEQ_CREATE			= 6,
 203	IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY	= 7,
 204	IRDMA_OP_QP_MODIFY			= 8,
 205	IRDMA_OP_QP_UPLOAD_CONTEXT		= 9,
 206	IRDMA_OP_CQ_CREATE			= 10,
 207	IRDMA_OP_CQ_DESTROY			= 11,
 208	IRDMA_OP_QP_CREATE			= 12,
 209	IRDMA_OP_QP_DESTROY			= 13,
 210	IRDMA_OP_ALLOC_STAG			= 14,
 211	IRDMA_OP_MR_REG_NON_SHARED		= 15,
 212	IRDMA_OP_DEALLOC_STAG			= 16,
 213	IRDMA_OP_MW_ALLOC			= 17,
 214	IRDMA_OP_QP_FLUSH_WQES			= 18,
 215	IRDMA_OP_ADD_ARP_CACHE_ENTRY		= 19,
 216	IRDMA_OP_MANAGE_PUSH_PAGE		= 20,
 217	IRDMA_OP_UPDATE_PE_SDS			= 21,
 218	IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE	= 22,
 219	IRDMA_OP_SUSPEND			= 23,
 220	IRDMA_OP_RESUME				= 24,
 221	IRDMA_OP_MANAGE_VF_PBLE_BP		= 25,
 222	IRDMA_OP_QUERY_FPM_VAL			= 26,
 223	IRDMA_OP_COMMIT_FPM_VAL			= 27,
 224	IRDMA_OP_AH_CREATE			= 28,
 225	IRDMA_OP_AH_MODIFY			= 29,
 226	IRDMA_OP_AH_DESTROY			= 30,
 227	IRDMA_OP_MC_CREATE			= 31,
 228	IRDMA_OP_MC_DESTROY			= 32,
 229	IRDMA_OP_MC_MODIFY			= 33,
 230	IRDMA_OP_STATS_ALLOCATE			= 34,
 231	IRDMA_OP_STATS_FREE			= 35,
 232	IRDMA_OP_STATS_GATHER			= 36,
 233	IRDMA_OP_WS_ADD_NODE			= 37,
 234	IRDMA_OP_WS_MODIFY_NODE			= 38,
 235	IRDMA_OP_WS_DELETE_NODE			= 39,
 236	IRDMA_OP_WS_FAILOVER_START		= 40,
 237	IRDMA_OP_WS_FAILOVER_COMPLETE		= 41,
 238	IRDMA_OP_SET_UP_MAP			= 42,
 239	IRDMA_OP_GEN_AE				= 43,
 240	IRDMA_OP_QUERY_RDMA_FEATURES		= 44,
 241	IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY		= 45,
 242	IRDMA_OP_ADD_LOCAL_MAC_ENTRY		= 46,
 243	IRDMA_OP_DELETE_LOCAL_MAC_ENTRY		= 47,
 244	IRDMA_OP_CQ_MODIFY			= 48,
 245	IRDMA_OP_SRQ_CREATE			= 49,
 246	IRDMA_OP_SRQ_MODIFY			= 50,
 247	IRDMA_OP_SRQ_DESTROY			= 51,
 248
 249	/* Must be last entry*/
 250	IRDMA_MAX_CQP_OPS			= 52,
 251};
 252
 253/* CQP SQ WQES */
 254#define IRDMA_CQP_OP_CREATE_QP				0
 255#define IRDMA_CQP_OP_MODIFY_QP				0x1
 256#define IRDMA_CQP_OP_DESTROY_QP				0x02
 257#define IRDMA_CQP_OP_CREATE_CQ				0x03
 258#define IRDMA_CQP_OP_MODIFY_CQ				0x04
 259#define IRDMA_CQP_OP_DESTROY_CQ				0x05
 260#define IRDMA_CQP_OP_CREATE_SRQ				0x06
 261#define IRDMA_CQP_OP_MODIFY_SRQ				0x07
 262#define IRDMA_CQP_OP_DESTROY_SRQ			0x08
 263#define IRDMA_CQP_OP_ALLOC_STAG				0x09
 264#define IRDMA_CQP_OP_REG_MR				0x0a
 265#define IRDMA_CQP_OP_QUERY_STAG				0x0b
 266#define IRDMA_CQP_OP_REG_SMR				0x0c
 267#define IRDMA_CQP_OP_DEALLOC_STAG			0x0d
 268#define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE		0x0e
 269#define IRDMA_CQP_OP_MANAGE_ARP				0x0f
 270#define IRDMA_CQP_OP_MANAGE_VF_PBLE_BP			0x10
 271#define IRDMA_CQP_OP_MANAGE_PUSH_PAGES			0x11
 272#define IRDMA_CQP_OP_QUERY_RDMA_FEATURES		0x12
 273#define IRDMA_CQP_OP_UPLOAD_CONTEXT			0x13
 274#define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY	0x14
 275#define IRDMA_CQP_OP_UPLOAD_CONTEXT			0x13
 276#define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE		0x15
 277#define IRDMA_CQP_OP_CREATE_CEQ				0x16
 278#define IRDMA_CQP_OP_DESTROY_CEQ			0x18
 279#define IRDMA_CQP_OP_CREATE_AEQ				0x19
 280#define IRDMA_CQP_OP_DESTROY_AEQ			0x1b
 281#define IRDMA_CQP_OP_CREATE_ADDR_HANDLE			0x1c
 282#define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE			0x1d
 283#define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE		0x1e
 284#define IRDMA_CQP_OP_UPDATE_PE_SDS			0x1f
 285#define IRDMA_CQP_OP_QUERY_FPM_VAL			0x20
 286#define IRDMA_CQP_OP_COMMIT_FPM_VAL			0x21
 287#define IRDMA_CQP_OP_FLUSH_WQES				0x22
 288/* IRDMA_CQP_OP_GEN_AE is the same value as IRDMA_CQP_OP_FLUSH_WQES */
 289#define IRDMA_CQP_OP_GEN_AE				0x22
 290#define IRDMA_CQP_OP_MANAGE_APBVT			0x23
 291#define IRDMA_CQP_OP_NOP				0x24
 292#define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY	0x25
 293#define IRDMA_CQP_OP_CREATE_MCAST_GRP			0x26
 294#define IRDMA_CQP_OP_MODIFY_MCAST_GRP			0x27
 295#define IRDMA_CQP_OP_DESTROY_MCAST_GRP			0x28
 296#define IRDMA_CQP_OP_SUSPEND_QP				0x29
 297#define IRDMA_CQP_OP_RESUME_QP				0x2a
 298#define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED		0x2b
 299#define IRDMA_CQP_OP_WORK_SCHED_NODE			0x2c
 300#define IRDMA_CQP_OP_MANAGE_STATS			0x2d
 301#define IRDMA_CQP_OP_GATHER_STATS			0x2e
 302#define IRDMA_CQP_OP_UP_MAP				0x2f
 303
 304#define FLD_LS_64(dev, val, field)	\
 305	(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
 306#define FLD_RS_64(dev, val, field)	\
 307	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
 308#define FLD_LS_32(dev, val, field)	\
 309	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
 310#define FLD_RS_32(dev, val, field)	\
 311	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
 312
 313#define IRDMA_MAX_STATS_24	0xffffffULL
 314#define IRDMA_MAX_STATS_32	0xffffffffULL
 315#define IRDMA_MAX_STATS_48	0xffffffffffffULL
 316#define IRDMA_MAX_STATS_56	0xffffffffffffffULL
 317#define IRDMA_MAX_STATS_64	0xffffffffffffffffULL
 318
 319#define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
 320#define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
 321#define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
 322#define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
 323#define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
 324#define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
 325#define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
 326#define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
 327#define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
 328#define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
 329#define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
 330#define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
 331#define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
 332#define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
 333#define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
 334#define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
 335#define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
 336#define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
 337#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
 338#define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
 339#define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
 340#define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
 341#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)
 342#define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
 343#define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52)
 344#define IRDMA_SD_MAX GENMASK_ULL(15, 0)
 345#define IRDMA_MEM_MAX GENMASK_ULL(15, 0)
 346#define IRDMA_QP_MEM_LOC GENMASK_ULL(47, 44)
 347#define IRDMA_MR_MEM_LOC GENMASK_ULL(27, 24)
 348
 349#define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
 350#define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
 351#define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
 352#define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
 353#define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
 354#define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
 355#define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
 356#define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(29, 16)
 357#define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(13, 0)
 358#define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(63, 48)
 359#define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
 360
 361#define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
 362#define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)
 363#define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)
 364#define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
 365#define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(15, 0)
 366#define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
 367#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
 368#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
 369#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
 370#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
 371#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
 372#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
 373#define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
 374#define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
 375#define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)
 376#define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
 377#define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
 378#define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
 379#define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
 380#define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
 381#define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
 382#define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
 383#define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
 384#define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)
 385#define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
 386#define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
 387
 388#define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
 389#define IRDMA_CQPHC_HW_MAJVER_GEN_2 1
 390#define IRDMA_CQPHC_HW_MAJVER_GEN_3 2
 391#define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
 392#define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
 393
 394#define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
 395
 396#define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
 397#define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
 398#define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
 399
 400#define IRDMA_CQPHC_TIMESTAMP_OVERRIDE BIT_ULL(5)
 401#define IRDMA_CQPHC_TS_SHIFT GENMASK_ULL(12, 8)
 402#define IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS BIT_ULL(0)
 403
 404#define IRDMA_CQPHC_OOISC_BLKSIZE GENMASK_ULL(63, 60)
 405#define IRDMA_CQPHC_RRSP_BLKSIZE GENMASK_ULL(59, 56)
 406#define IRDMA_CQPHC_Q1_BLKSIZE GENMASK_ULL(55, 52)
 407#define IRDMA_CQPHC_XMIT_BLKSIZE GENMASK_ULL(51, 48)
 408#define IRDMA_CQPHC_BLKSIZES_VALID BIT_ULL(4)
 409
 410#define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
 411#define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
 412#define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
 413#define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
 414#define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
 415#define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
 416#define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
 417
 418/* CQP and iWARP Completion Queue */
 419#define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX
 420
 421#define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
 422
 423#define IRDMA_CCQ_DEFINFO GENMASK_ULL(63, 32)
 424
 425#define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
 426#define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
 427#define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
 428#define IRDMA_CQ_EXTCQE BIT_ULL(50)
 429#define IRDMA_OOO_CMPL BIT_ULL(54)
 430#define IRDMA_CQ_ERROR BIT_ULL(55)
 431#define IRDMA_CQ_SQ BIT_ULL(62)
 432
 433#define IRDMA_CQ_SRQ BIT_ULL(52)
 434#define IRDMA_CQ_VALID BIT_ULL(63)
 435#define IRDMA_CQ_IMMVALID BIT_ULL(62)
 436#define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
 437#define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
 438#define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
 439#define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
 440
 441#define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
 442#define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
 443#define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
 444#define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
 445#define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
 446#define IRDMACQ_QPID GENMASK_ULL(55, 32)
 447
 448#define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
 449#define IRDMACQ_PSHDROP BIT_ULL(51)
 450#define IRDMACQ_STAG BIT_ULL(53)
 451#define IRDMACQ_IPV4 BIT_ULL(53)
 452#define IRDMACQ_SOEVENT BIT_ULL(54)
 453#define IRDMACQ_OP GENMASK_ULL(61, 56)
 454
 455#define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
 456#define IRDMA_CEQE_VALID BIT_ULL(63)
 457
 458/* AEQE format */
 459#define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX
 460#define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
 461#define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)
 462#define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
 463#define IRDMA_AEQE_OVERFLOW BIT_ULL(33)
 464#define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
 465#define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
 466#define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
 467#define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
 468#define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
 469#define IRDMA_AEQE_VALID BIT_ULL(63)
 470
 471#define IRDMA_AEQE_Q2DATA_GEN_3 GENMASK_ULL(5, 4)
 472#define IRDMA_AEQE_TCPSTATE_GEN_3 GENMASK_ULL(3, 0)
 473#define IRDMA_AEQE_QPCQID_GEN_3 GENMASK_ULL(24, 0)
 474#define IRDMA_AEQE_AECODE_GEN_3 GENMASK_ULL(61, 50)
 475#define IRDMA_AEQE_OVERFLOW_GEN_3 BIT_ULL(62)
 476#define IRDMA_AEQE_WQDESCIDX_GEN_3 GENMASK_ULL(49, 32)
 477#define IRDMA_AEQE_IWSTATE_GEN_3 GENMASK_ULL(31, 29)
 478#define IRDMA_AEQE_AESRC_GEN_3 GENMASK_ULL(28, 25)
 479#define IRDMA_AEQE_CMPL_CTXT_S 6
 480#define IRDMA_AEQE_CMPL_CTXT GENMASK_ULL(63, 6)
 481
 482#define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
 483#define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
 484#define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
 485#define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
 486#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
 487#define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
 488#define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)
 489#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
 490#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
 491#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
 492#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
 493#define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
 494#define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
 495#define IRDMA_VLAN_TAG_VALID BIT_ULL(50)
 496#define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
 497#define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
 498#define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)
 499#define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
 500#define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
 501#define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
 502#define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
 503
 504#define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(23, 8)
 505#define IRDMA_CQPSQ_TPHEN BIT_ULL(60)
 506
 507#define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX
 508
 509#define IRDMA_CQPSQ_PASID GENMASK_ULL(51, 32)
 510#define IRDMA_CQPSQ_PASID_VALID BIT_ULL(62)
 511
 512/* Create/Modify/Destroy QP */
 513
 514#define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
 515#define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
 516
 517#define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX
 518
 519#define IRDMA_CQPSQ_QP_QPID_S 0
 520#define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
 521
 522#define IRDMA_CQPSQ_QP_OP_S 32
 523#define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M
 524#define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)
 525#define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)
 526#define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)
 527#define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)
 528#define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)
 529#define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
 530#define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
 531#define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)
 532#define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)
 533
 534#define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)
 535#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)
 536#define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
 537#define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)
 538#define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)
 539#define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
 540
 541#define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX
 542
 543#define IRDMA_CQPSQ_SRQ_RQSIZE GENMASK_ULL(3, 0)
 544#define IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE GENMASK_ULL(5, 4)
 545#define IRDMA_CQPSQ_SRQ_SRQ_LIMIT GENMASK_ULL(43, 32)
 546#define IRDMA_CQPSQ_SRQ_SRQCTX GENMASK_ULL(63, 6)
 547#define IRDMA_CQPSQ_SRQ_PD_ID GENMASK_ULL(39, 16)
 548#define IRDMA_CQPSQ_SRQ_SRQ_ID GENMASK_ULL(15, 0)
 549#define IRDMA_CQPSQ_SRQ_OP GENMASK_ULL(37, 32)
 550#define IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE GENMASK_ULL(45, 44)
 551#define IRDMA_CQPSQ_SRQ_VIRTMAP BIT_ULL(47)
 552#define IRDMA_CQPSQ_SRQ_TPH_EN BIT_ULL(60)
 553#define IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT BIT_ULL(61)
 554#define IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX GENMASK_ULL(27, 0)
 555#define IRDMA_CQPSQ_SRQ_TPH_VALUE GENMASK_ULL(7, 0)
 556#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S 8
 557#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR GENMASK_ULL(63, 8)
 558#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S 6
 559#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR GENMASK_ULL(63, 6)
 560
 561#define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
 562#define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
 563#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
 564
 565#define IRDMA_CQPSQ_CQ_CQID_HIGH GENMASK_ULL(52, 50)
 566#define IRDMA_CQPSQ_CQ_CEQID_HIGH GENMASK_ULL(59, 54)
 567#define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
 568#define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)
 569#define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
 570#define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)
 571#define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
 572#define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
 573#define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)
 574#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)
 575#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
 576
 577/* Allocate/Register/Register Shared/Deallocate Stag */
 578#define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX
 579#define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
 580#define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
 581#define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
 582#define IRDMA_CQPSQ_STAG_IDX_S 8
 583#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
 584#define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)
 585#define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)
 586#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)
 587#define IRDMA_CQPSQ_STAG_PDID_HI GENMASK_ULL(59, 54)
 588
 589#define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
 590#define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
 591#define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
 592#define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)
 593#define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)
 594#define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)
 595#define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61)
 596
 597#define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX
 598#define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(15, 0)
 599#define IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN BIT_ULL(61)
 600
 601#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
 602#define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX
 603#define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
 604#define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)
 605#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)
 606#define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
 607#define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
 608#define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
 609#define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
 610#define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
 611#define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
 612#define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
 613#define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
 614#define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
 615#define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)
 616#define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)
 617#define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)
 618#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
 619#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
 620#define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
 621#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)
 622#define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
 623
 624/* Manage Push Page - MPP */
 625#define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
 626#define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
 627#define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(31, 0)
 628#define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
 629#define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)
 630
 631/* Upload Context - UCTX */
 632#define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX
 633#define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
 634#define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
 635
 636#define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)
 637#define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)
 638
 639#define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
 640#define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)
 641
 642#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
 643#define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
 644#define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
 645#define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
 646
 647#define IRDMA_CQPSQ_CEQ_CEQID_HIGH GENMASK_ULL(15, 10)
 648
 649#define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
 650#define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
 651#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)
 652#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
 653#define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
 654#define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
 655#define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
 656#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
 657
 658#define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(20, 0)
 659#define IRDMA_COMMIT_FPM_BASE_S 32
 660#define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(15, 0)
 661
 662#define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
 663#define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
 664#define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
 665#define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
 666#define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
 667#define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
 668#define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
 669#define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)
 670#define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)
 671#define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)
 672#define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)
 673#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID BIT_ULL(42)
 674#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX GENMASK_ULL(49, 32)
 675#define IRDMA_CQPSQ_FWQE_ERR_RQ_IDX_VALID BIT_ULL(43)
 676#define IRDMA_CQPSQ_FWQE_ERR_RQ_IDX GENMASK_ULL(46, 32)
 677#define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
 678#define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)
 679#define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
 680#define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
 681#define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
 682#define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
 683#define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
 684
 685#define IRDMA_CQPSQ_UPESD_BM_PF 0
 686#define IRDMA_CQPSQ_UPESD_BM_CP_LM 1
 687#define IRDMA_CQPSQ_UPESD_BM_AXF 2
 688#define IRDMA_CQPSQ_UPESD_BM_LM 4
 689#define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
 690#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
 691#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)
 692#define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
 693#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
 694#define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0)
 695#define IRDMA_MANAGE_RSRC_VER2 BIT_ULL(2)
 696
 697#define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
 698#define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
 699#define IRDMA_CQPSQ_MIN_DEF_CMPL 0x0006
 700#define IRDMA_CQPSQ_MIN_OOO_CMPL 0x0007
 701
 702#define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000
 703#define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
 704#define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
 705#define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
 706#define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
 707#define IRDMAQPC_IBRDENABLE BIT_ULL(2)
 708#define IRDMAQPC_IPV4 BIT_ULL(3)
 709#define IRDMAQPC_NONAGLE BIT_ULL(4)
 710#define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)
 711#define IRDMAQPC_ISQP1 BIT_ULL(6)
 712#define IRDMAQPC_TIMESTAMP BIT_ULL(7)
 713#define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
 714#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)
 715#define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
 716
 717#define IRDMAQPC_USE_SRQ BIT_ULL(10)
 718#define IRDMAQPC_SRQ_ID GENMASK_ULL(15, 0)
 719#define IRDMAQPC_PASID GENMASK_ULL(19, 0)
 720#define IRDMAQPC_PASID_VALID BIT_ULL(11)
 721
 722#define IRDMAQPC_ECN_EN BIT_ULL(14)
 723#define IRDMAQPC_DROPOOOSEG BIT_ULL(15)
 724#define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
 725#define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)
 726#define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
 727#define IRDMAQPC_DC_TCP_EN BIT_ULL(25)
 728#define IRDMAQPC_RCVTPHEN BIT_ULL(28)
 729#define IRDMAQPC_XMITTPHEN BIT_ULL(29)
 730#define IRDMAQPC_RQTPHEN BIT_ULL(30)
 731#define IRDMAQPC_SQTPHEN BIT_ULL(31)
 732#define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
 733#define IRDMAQPC_PMENA BIT_ULL(47)
 734#define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
 735#define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
 736
 737#define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX
 738#define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX
 739#define IRDMAQPC_TTL GENMASK_ULL(7, 0)
 740#define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
 741#define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
 742#define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16)
 743#define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)
 744#define IRDMAQPC_TOS GENMASK_ULL(31, 24)
 745#define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
 746#define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
 747#define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
 748#define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
 749#define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
 750#define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
 751#define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
 752#define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
 753#define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
 754#define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
 755#define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
 756#define IRDMAQPC_WSCALE BIT_ULL(20)
 757#define IRDMAQPC_KEEPALIVE BIT_ULL(21)
 758#define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)
 759#define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)
 760#define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
 761#define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
 762#define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
 763#define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
 764#define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
 765#define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
 766#define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
 767#define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
 768#define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
 769#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
 770#define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
 771#define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
 772#define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
 773#define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
 774#define IRDMAQPC_ISN GENMASK_ULL(55, 32)
 775#define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
 776#define IRDMAQPC_LSN GENMASK_ULL(55, 32)
 777#define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
 778#define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
 779#define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
 780#define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
 781#define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
 782#define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
 783#define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
 784#define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
 785#define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
 786#define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
 787#define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
 788#define IRDMAQPC_CWND GENMASK_ULL(63, 32)
 789#define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
 790#define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
 791#define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
 792#define IRDMAQPC_MINRNR_TIMER GENMASK_ULL(4, 0)
 793#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
 794#define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
 795#define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
 796#define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
 797#define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
 798#define IRDMAQPC_TXCQNUM GENMASK_ULL(24, 0)
 799#define IRDMAQPC_RXCQNUM GENMASK_ULL(56, 32)
 800#define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
 801#define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
 802#define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
 803#define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
 804#define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
 805
 806#define IRDMAQPC_LOCALACKTIMEOUT GENMASK_ULL(12, 8)
 807#define IRDMAQPC_RNRNAK_TMR GENMASK_ULL(4, 0)
 808#define IRDMAQPC_ORDSIZE_GEN3 GENMASK_ULL(10, 0)
 809#define IRDMAQPC_REMOTE_ATOMIC_EN BIT_ULL(18)
 810#define IRDMAQPC_STAT_INDEX_GEN3 GENMASK_ULL(47, 32)
 811#define IRDMAQPC_PKT_LIMIT GENMASK_ULL(55, 48)
 812
 813#define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
 814
 815#define IRDMAQPC_IRDSIZE_GEN3 GENMASK_ULL(17, 14)
 816
 817#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
 818#define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
 819#define IRDMAQPC_RDOK BIT_ULL(21)
 820#define IRDMAQPC_SNDMARKERS BIT_ULL(22)
 821#define IRDMAQPC_DCQCNENABLE BIT_ULL(22)
 822#define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)
 823#define IRDMAQPC_RCVNOICRC BIT_ULL(31)
 824#define IRDMAQPC_BINDEN BIT_ULL(23)
 825#define IRDMAQPC_FASTREGEN BIT_ULL(24)
 826#define IRDMAQPC_PRIVEN BIT_ULL(25)
 827#define IRDMAQPC_TIMELYENABLE BIT_ULL(27)
 828#define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
 829#define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
 830#define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
 831#define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)
 832#define IRDMAQPC_IWARPMODE BIT_ULL(28)
 833#define IRDMAQPC_RCVMARKERS BIT_ULL(29)
 834#define IRDMAQPC_ALIGNHDRS BIT_ULL(30)
 835#define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)
 836#define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
 837#define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
 838
 839#define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX
 840#define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
 841#define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
 842#define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
 843#define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
 844#define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
 845#define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
 846#define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
 847#define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
 848#define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
 849#define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
 850#define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
 851#define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
 852#define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
 853#define IRDMA_FEATURE_RSRC_MAX GENMASK_ULL(31, 0)
 854
 855#define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
 856#define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
 857#define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
 858#define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
 859#define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
 860#define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
 861#define IRDMAQPSQ_READFENCE BIT_ULL(60)
 862#define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
 863#define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
 864#define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
 865#define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
 866#define IRDMAQPSQ_VALID BIT_ULL(63)
 867
 868#define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX
 869#define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
 870#define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
 871#define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
 872#define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
 873#define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
 874#define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
 875#define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
 876#define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
 877#define IRDMAQPSQ_AHID GENMASK_ULL(24, 0)
 878#define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
 879
 880#define IRDMA_INLINE_VALID_S 7
 881#define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
 882#define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
 883#define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
 884
 885#define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
 886#define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
 887
 888#define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX
 889
 890#define IRDMAQPSQ_STAG GENMASK_ULL(31, 0)
 891#define IRDMAQPSQ_REMOTE_STAG GENMASK_ULL(31, 0)
 892
 893#define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
 894#define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
 895#define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
 896
 897#define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX
 898#define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
 899#define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
 900
 901#define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX
 902
 903#define IRDMAQPSQ_REMOTE_ATOMICS_EN BIT_ULL(55)
 904
 905#define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
 906
 907#define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
 908#define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
 909#define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)
 910#define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
 911#define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
 912#define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
 913#define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
 914#define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
 915#define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
 916
 917/* iwarp QP RQ WQE common fields */
 918#define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT
 919#define IRDMAQPRQ_VALID IRDMAQPSQ_VALID
 920#define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX
 921#define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN
 922#define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG
 923#define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO
 924
 925#define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
 926#define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
 927#define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
 928
 929#define IRDMA_QUERY_FPM_LOC_MEM_PAGES GENMASK_ULL(63, 32)
 930#define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(31, 0)
 931#define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(31, 0)
 932#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
 933#define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(44, 32)
 934#define IRDMA_QUERY_FPM_MAX_PE_SDS_GEN3 GENMASK_ULL(47, 32)
 935#define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
 936#define IRDMA_QUERY_FPM_MAX_IRD GENMASK_ULL(53, 50)
 937#define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
 938#define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
 939#define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
 940#define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
 941#define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
 942#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
 943#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
 944#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)
 945
 946#define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \
 947	( \
 948		(_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
 949	)
 950
 951#define IRDMA_GET_CURRENT_CEQ_ELEM(_ceq) \
 952	( \
 953		(_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
 954	)
 955
 956#define IRDMA_GET_CEQ_ELEM_AT_POS(_ceq, _pos) \
 957	( \
 958		(_ceq)->ceqe_base[_pos].buf  \
 959	)
 960
 961#define IRDMA_RING_GET_NEXT_TAIL(_ring, _idx) \
 962	( \
 963		((_ring).tail + (_idx)) % (_ring).size \
 964	)
 965
 966#define IRDMA_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)
 967
 968#define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \
 969	( \
 970		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
 971	)
 972#define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \
 973	( \
 974		((struct irdma_extended_cqe *) \
 975		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
 976	)
 977
 978#define IRDMA_RING_INIT(_ring, _size) \
 979	{ \
 980		(_ring).head = 0; \
 981		(_ring).tail = 0; \
 982		(_ring).size = (_size); \
 983	}
 984#define IRDMA_RING_SIZE(_ring) ((_ring).size)
 985#define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)
 986#define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)
 987
 988#define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \
 989	{ \
 990		register u32 size; \
 991		size = (_ring).size;  \
 992		if (!IRDMA_RING_FULL_ERR(_ring)) { \
 993			(_ring).head = ((_ring).head + 1) % size; \
 994			(_retcode) = 0; \
 995		} else { \
 996			(_retcode) = -ENOMEM; \
 997		} \
 998	}
 999#define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1000	{ \
1001		register u32 size; \
1002		size = (_ring).size; \
1003		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \
1004			(_ring).head = ((_ring).head + (_count)) % size; \
1005			(_retcode) = 0; \
1006		} else { \
1007			(_retcode) = -ENOMEM; \
1008		} \
1009	}
1010#define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
1011	{ \
1012		register u32 size; \
1013		size = (_ring).size;  \
1014		if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \
1015			(_ring).head = ((_ring).head + 1) % size; \
1016			(_retcode) = 0; \
1017		} else { \
1018			(_retcode) = -ENOMEM; \
1019		} \
1020	}
1021#define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1022	{ \
1023		register u32 size; \
1024		size = (_ring).size; \
1025		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1026			(_ring).head = ((_ring).head + (_count)) % size; \
1027			(_retcode) = 0; \
1028		} else { \
1029			(_retcode) = -ENOMEM; \
1030		} \
1031	}
1032#define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \
1033	(_ring).head = ((_ring).head + (_count)) % (_ring).size
1034
1035#define IRDMA_RING_MOVE_TAIL(_ring) \
1036	(_ring).tail = ((_ring).tail + 1) % (_ring).size
1037
1038#define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \
1039	(_ring).head = ((_ring).head + 1) % (_ring).size
1040
1041#define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
1042	(_ring).tail = ((_ring).tail + (_count)) % (_ring).size
1043
1044#define IRDMA_RING_SET_TAIL(_ring, _pos) \
1045	(_ring).tail = (_pos) % (_ring).size
1046
1047#define IRDMA_RING_FULL_ERR(_ring) \
1048	( \
1049		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
1050	)
1051
1052#define IRDMA_ERR_RING_FULL2(_ring) \
1053	( \
1054		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
1055	)
1056
1057#define IRDMA_ERR_RING_FULL3(_ring) \
1058	( \
1059		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
1060	)
1061
1062#define IRDMA_SQ_RING_FULL_ERR(_ring) \
1063	( \
1064		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
1065	)
1066
1067#define IRDMA_ERR_SQ_RING_FULL2(_ring) \
1068	( \
1069		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
1070	)
1071#define IRDMA_ERR_SQ_RING_FULL3(_ring) \
1072	( \
1073		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
1074	)
1075#define IRDMA_RING_MORE_WORK(_ring) \
1076	( \
1077		(IRDMA_RING_USED_QUANTA(_ring) != 0) \
1078	)
1079
1080#define IRDMA_RING_USED_QUANTA(_ring) \
1081	( \
1082		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1083	)
1084
1085#define IRDMA_RING_FREE_QUANTA(_ring) \
1086	( \
1087		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1088	)
1089
1090#define IRDMA_SQ_RING_FREE_QUANTA(_ring) \
1091	( \
1092		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1093	)
1094
1095#define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
1096	{ \
1097		index = IRDMA_RING_CURRENT_HEAD(_ring); \
1098		IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
1099	}
1100
1101enum irdma_qp_wqe_size {
1102	IRDMA_WQE_SIZE_32  = 32,
1103	IRDMA_WQE_SIZE_64  = 64,
1104	IRDMA_WQE_SIZE_96  = 96,
1105	IRDMA_WQE_SIZE_128 = 128,
1106	IRDMA_WQE_SIZE_256 = 256,
1107};
1108
1109enum irdma_ws_node_op {
1110	IRDMA_ADD_NODE = 0,
1111	IRDMA_MODIFY_NODE,
1112	IRDMA_DEL_NODE,
1113};
1114
1115enum {	IRDMA_Q_ALIGNMENT_M		 = (128 - 1),
1116	IRDMA_AEQ_ALIGNMENT_M		 = (256 - 1),
1117	IRDMA_Q2_ALIGNMENT_M		 = (256 - 1),
1118	IRDMA_CEQ_ALIGNMENT_M		 = (256 - 1),
1119	IRDMA_CQ0_ALIGNMENT_M		 = (256 - 1),
1120	IRDMA_HOST_CTX_ALIGNMENT_M	 = (4 - 1),
1121	IRDMA_SHADOWAREA_M		 = (128 - 1),
1122	IRDMA_FPM_QUERY_BUF_ALIGNMENT_M	 = (4 - 1),
1123	IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1124};
1125
1126enum irdma_alignment {
1127	IRDMA_CQP_ALIGNMENT	    = 0x200,
1128	IRDMA_AEQ_ALIGNMENT	    = 0x100,
1129	IRDMA_CEQ_ALIGNMENT	    = 0x100,
1130	IRDMA_CQ0_ALIGNMENT	    = 0x100,
1131	IRDMA_SD_BUF_ALIGNMENT      = 0x80,
1132	IRDMA_FEATURE_BUF_ALIGNMENT = 0x10,
1133};
1134
1135enum icrdma_protocol_used {
1136	ICRDMA_ANY_PROTOCOL	   = 0,
1137	ICRDMA_IWARP_PROTOCOL_ONLY = 1,
1138	ICRDMA_ROCE_PROTOCOL_ONLY  = 2,
1139};
1140
1141/**
1142 * set_64bit_val - set 64 bit value to hw wqe
1143 * @wqe_words: wqe addr to write
1144 * @byte_index: index in wqe
1145 * @val: value to write
1146 **/
1147static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)
1148{
1149	wqe_words[byte_index >> 3] = cpu_to_le64(val);
1150}
1151
1152/**
1153 * set_32bit_val - set 32 bit value to hw wqe
1154 * @wqe_words: wqe addr to write
1155 * @byte_index: index in wqe
1156 * @val: value to write
1157 **/
1158static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)
1159{
1160	wqe_words[byte_index >> 2] = cpu_to_le32(val);
1161}
1162
1163/**
1164 * get_64bit_val - read 64 bit value from wqe
1165 * @wqe_words: wqe addr
1166 * @byte_index: index to read from
1167 * @val: read value
1168 **/
1169static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)
1170{
1171	*val = le64_to_cpu(wqe_words[byte_index >> 3]);
1172}
1173
1174/**
1175 * get_32bit_val - read 32 bit value from wqe
1176 * @wqe_words: wqe addr
1177 * @byte_index: index to reaad from
1178 * @val: return 32 bit value
1179 **/
1180static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)
1181{
1182	*val = le32_to_cpu(wqe_words[byte_index >> 2]);
1183}
1184#endif /* IRDMA_DEFS_H */