hns_roce_qp.c

   1/*
   2 * Copyright (c) 2016 Hisilicon Limited.
   3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenIB.org BSD license below:
  10 *
  11 *     Redistribution and use in source and binary forms, with or
  12 *     without modification, are permitted provided that the following
  13 *     conditions are met:
  14 *
  15 *      - Redistributions of source code must retain the above
  16 *        copyright notice, this list of conditions and the following
  17 *        disclaimer.
  18 *
  19 *      - Redistributions in binary form must reproduce the above
  20 *        copyright notice, this list of conditions and the following
  21 *        disclaimer in the documentation and/or other materials
  22 *        provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 */
  33
  34#include <rdma/ib_addr.h>
  35#include <rdma/ib_umem.h>
  36#include <rdma/uverbs_ioctl.h>
  37#include "hns_roce_common.h"
  38#include "hns_roce_device.h"
  39#include "hns_roce_hem.h"
  40
  41static struct hns_roce_qp *hns_roce_qp_lookup(struct hns_roce_dev *hr_dev,
  42					      u32 qpn)
  43{
  44	struct device *dev = hr_dev->dev;
  45	struct hns_roce_qp *qp;
  46	unsigned long flags;
  47
  48	xa_lock_irqsave(&hr_dev->qp_table_xa, flags);
  49	qp = __hns_roce_qp_lookup(hr_dev, qpn);
  50	if (qp)
  51		refcount_inc(&qp->refcount);
  52	xa_unlock_irqrestore(&hr_dev->qp_table_xa, flags);
  53
  54	if (!qp)
  55		dev_warn(dev, "async event for bogus QP %08x\n", qpn);
  56
  57	return qp;
  58}
  59
  60static void flush_work_handle(struct work_struct *work)
  61{
  62	struct hns_roce_work *flush_work = container_of(work,
  63					struct hns_roce_work, work);
  64	struct hns_roce_qp *hr_qp = container_of(flush_work,
  65					struct hns_roce_qp, flush_work);
  66	struct device *dev = flush_work->hr_dev->dev;
  67	struct ib_qp_attr attr;
  68	int attr_mask;
  69	int ret;
  70
  71	attr_mask = IB_QP_STATE;
  72	attr.qp_state = IB_QPS_ERR;
  73
  74	if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) {
  75		ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL);
  76		if (ret)
  77			dev_err(dev, "modify QP to error state failed(%d) during CQE flush\n",
  78				ret);
  79	}
  80
  81	/*
  82	 * make sure we signal QP destroy leg that flush QP was completed
  83	 * so that it can safely proceed ahead now and destroy QP
  84	 */
  85	if (refcount_dec_and_test(&hr_qp->refcount))
  86		complete(&hr_qp->free);
  87}
  88
  89void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  90{
  91	struct hns_roce_work *flush_work = &hr_qp->flush_work;
  92	unsigned long flags;
  93
  94	spin_lock_irqsave(&hr_qp->flush_lock, flags);
  95	/* Exit directly after destroy_qp() */
  96	if (test_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag)) {
  97		spin_unlock_irqrestore(&hr_qp->flush_lock, flags);
  98		return;
  99	}
 100
 101	refcount_inc(&hr_qp->refcount);
 102	queue_work(hr_dev->irq_workq, &flush_work->work);
 103	spin_unlock_irqrestore(&hr_qp->flush_lock, flags);
 104}
 105
 106void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp)
 107{
 108	/*
 109	 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state
 110	 * gets into errored mode. Hence, as a workaround to this
 111	 * hardware limitation, driver needs to assist in flushing. But
 112	 * the flushing operation uses mailbox to convey the QP state to
 113	 * the hardware and which can sleep due to the mutex protection
 114	 * around the mailbox calls. Hence, use the deferred flush for
 115	 * now.
 116	 */
 117	if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
 118		init_flush_work(dev, qp);
 119}
 120
 121void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
 122{
 123	struct hns_roce_qp *qp;
 124
 125	qp = hns_roce_qp_lookup(hr_dev, qpn);
 126	if (!qp)
 127		return;
 128
 129	qp->event(qp, (enum hns_roce_event)event_type);
 130
 131	if (refcount_dec_and_test(&qp->refcount))
 132		complete(&qp->free);
 133}
 134
 135void hns_roce_flush_cqe(struct hns_roce_dev *hr_dev, u32 qpn)
 136{
 137	struct hns_roce_qp *qp;
 138
 139	qp = hns_roce_qp_lookup(hr_dev, qpn);
 140	if (!qp)
 141		return;
 142
 143	qp->state = IB_QPS_ERR;
 144	flush_cqe(hr_dev, qp);
 145
 146	if (refcount_dec_and_test(&qp->refcount))
 147		complete(&qp->free);
 148}
 149
 150static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
 151				 enum hns_roce_event type)
 152{
 153	struct ib_qp *ibqp = &hr_qp->ibqp;
 154	struct ib_event event;
 155
 156	if (ibqp->event_handler) {
 157		event.device = ibqp->device;
 158		event.element.qp = ibqp;
 159		switch (type) {
 160		case HNS_ROCE_EVENT_TYPE_PATH_MIG:
 161			event.event = IB_EVENT_PATH_MIG;
 162			break;
 163		case HNS_ROCE_EVENT_TYPE_COMM_EST:
 164			event.event = IB_EVENT_COMM_EST;
 165			break;
 166		case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
 167			event.event = IB_EVENT_SQ_DRAINED;
 168			break;
 169		case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
 170			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 171			break;
 172		case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
 173			event.event = IB_EVENT_QP_FATAL;
 174			break;
 175		case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
 176			event.event = IB_EVENT_PATH_MIG_ERR;
 177			break;
 178		case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
 179			event.event = IB_EVENT_QP_REQ_ERR;
 180			break;
 181		case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
 182		case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
 183		case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
 184			event.event = IB_EVENT_QP_ACCESS_ERR;
 185			break;
 186		default:
 187			dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
 188				type, hr_qp->qpn);
 189			return;
 190		}
 191		ibqp->event_handler(&event, ibqp->qp_context);
 192	}
 193}
 194
 195static u8 get_affinity_cq_bank(u8 qp_bank)
 196{
 197	return (qp_bank >> 1) & CQ_BANKID_MASK;
 198}
 199
 200static u8 get_least_load_bankid_for_qp(struct ib_qp_init_attr *init_attr,
 201					struct hns_roce_bank *bank)
 202{
 203#define INVALID_LOAD_QPNUM 0xFFFFFFFF
 204	struct ib_cq *scq = init_attr->send_cq;
 205	u32 least_load = INVALID_LOAD_QPNUM;
 206	unsigned long cqn = 0;
 207	u8 bankid = 0;
 208	u32 bankcnt;
 209	u8 i;
 210
 211	if (scq)
 212		cqn = to_hr_cq(scq)->cqn;
 213
 214	for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) {
 215		if (scq && (get_affinity_cq_bank(i) != (cqn & CQ_BANKID_MASK)))
 216			continue;
 217
 218		bankcnt = bank[i].inuse;
 219		if (bankcnt < least_load) {
 220			least_load = bankcnt;
 221			bankid = i;
 222		}
 223	}
 224
 225	return bankid;
 226}
 227
 228static int alloc_qpn_with_bankid(struct hns_roce_bank *bank, u8 bankid,
 229				 unsigned long *qpn)
 230{
 231	int id;
 232
 233	id = ida_alloc_range(&bank->ida, bank->next, bank->max, GFP_KERNEL);
 234	if (id < 0) {
 235		id = ida_alloc_range(&bank->ida, bank->min, bank->max,
 236				     GFP_KERNEL);
 237		if (id < 0)
 238			return id;
 239	}
 240
 241	/* the QPN should keep increasing until the max value is reached. */
 242	bank->next = (id + 1) > bank->max ? bank->min : id + 1;
 243
 244	/* the lower 3 bits is bankid */
 245	*qpn = (id << 3) | bankid;
 246
 247	return 0;
 248}
 249static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 250		     struct ib_qp_init_attr *init_attr)
 251{
 252	struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 253	unsigned long num = 0;
 254	u8 bankid;
 255	int ret;
 256
 257	if (hr_qp->ibqp.qp_type == IB_QPT_GSI) {
 258		num = 1;
 259	} else {
 260		mutex_lock(&qp_table->bank_mutex);
 261		bankid = get_least_load_bankid_for_qp(init_attr, qp_table->bank);
 262
 263		ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid,
 264					    &num);
 265		if (ret) {
 266			ibdev_err(&hr_dev->ib_dev,
 267				  "failed to alloc QPN, ret = %d\n", ret);
 268			mutex_unlock(&qp_table->bank_mutex);
 269			return ret;
 270		}
 271
 272		qp_table->bank[bankid].inuse++;
 273		mutex_unlock(&qp_table->bank_mutex);
 274	}
 275
 276	hr_qp->qpn = num;
 277
 278	return 0;
 279}
 280
 281static void add_qp_to_list(struct hns_roce_dev *hr_dev,
 282			   struct hns_roce_qp *hr_qp,
 283			   struct ib_cq *send_cq, struct ib_cq *recv_cq)
 284{
 285	struct hns_roce_cq *hr_send_cq, *hr_recv_cq;
 286	unsigned long flags;
 287
 288	hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL;
 289	hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL;
 290
 291	spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
 292	hns_roce_lock_cqs(hr_send_cq, hr_recv_cq);
 293
 294	list_add_tail(&hr_qp->node, &hr_dev->qp_list);
 295	if (hr_send_cq)
 296		list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list);
 297	if (hr_recv_cq)
 298		list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list);
 299
 300	hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq);
 301	spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
 302}
 303
 304static int hns_roce_qp_store(struct hns_roce_dev *hr_dev,
 305			     struct hns_roce_qp *hr_qp,
 306			     struct ib_qp_init_attr *init_attr)
 307{
 308	struct xarray *xa = &hr_dev->qp_table_xa;
 309	int ret;
 310
 311	if (!hr_qp->qpn)
 312		return -EINVAL;
 313
 314	ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL));
 315	if (ret)
 316		dev_err(hr_dev->dev, "failed to xa store for QPC\n");
 317	else
 318		/* add QP to device's QP list for softwc */
 319		add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq,
 320			       init_attr->recv_cq);
 321
 322	return ret;
 323}
 324
 325static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 326{
 327	struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 328	struct device *dev = hr_dev->dev;
 329	int ret;
 330
 331	if (!hr_qp->qpn)
 332		return -EINVAL;
 333
 334	/* Alloc memory for QPC */
 335	ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
 336	if (ret) {
 337		dev_err(dev, "failed to get QPC table\n");
 338		goto err_out;
 339	}
 340
 341	/* Alloc memory for IRRL */
 342	ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 343	if (ret) {
 344		dev_err(dev, "failed to get IRRL table\n");
 345		goto err_put_qp;
 346	}
 347
 348	if (hr_dev->caps.trrl_entry_sz) {
 349		/* Alloc memory for TRRL */
 350		ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
 351					 hr_qp->qpn);
 352		if (ret) {
 353			dev_err(dev, "failed to get TRRL table\n");
 354			goto err_put_irrl;
 355		}
 356	}
 357
 358	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 359		/* Alloc memory for SCC CTX */
 360		ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table,
 361					 hr_qp->qpn);
 362		if (ret) {
 363			dev_err(dev, "failed to get SCC CTX table\n");
 364			goto err_put_trrl;
 365		}
 366	}
 367
 368	return 0;
 369
 370err_put_trrl:
 371	if (hr_dev->caps.trrl_entry_sz)
 372		hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
 373
 374err_put_irrl:
 375	hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 376
 377err_put_qp:
 378	hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
 379
 380err_out:
 381	return ret;
 382}
 383
 384static void qp_user_mmap_entry_remove(struct hns_roce_qp *hr_qp)
 385{
 386	rdma_user_mmap_entry_remove(&hr_qp->dwqe_mmap_entry->rdma_entry);
 387}
 388
 389void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 390{
 391	struct xarray *xa = &hr_dev->qp_table_xa;
 392	unsigned long flags;
 393
 394	list_del(&hr_qp->node);
 395
 396	if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT)
 397		list_del(&hr_qp->sq_node);
 398
 399	if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI &&
 400	    hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT)
 401		list_del(&hr_qp->rq_node);
 402
 403	xa_lock_irqsave(xa, flags);
 404	__xa_erase(xa, hr_qp->qpn);
 405	xa_unlock_irqrestore(xa, flags);
 406}
 407
 408static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 409{
 410	struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
 411
 412	if (hr_dev->caps.trrl_entry_sz)
 413		hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
 414	hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 415}
 416
 417static inline u8 get_qp_bankid(unsigned long qpn)
 418{
 419	/* The lower 3 bits of QPN are used to hash to different banks */
 420	return (u8)(qpn & GENMASK(2, 0));
 421}
 422
 423static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 424{
 425	u8 bankid;
 426
 427	if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
 428		return;
 429
 430	if (hr_qp->qpn < hr_dev->caps.reserved_qps)
 431		return;
 432
 433	bankid = get_qp_bankid(hr_qp->qpn);
 434
 435	ida_free(&hr_dev->qp_table.bank[bankid].ida,
 436		 hr_qp->qpn / HNS_ROCE_QP_BANK_NUM);
 437
 438	mutex_lock(&hr_dev->qp_table.bank_mutex);
 439	hr_dev->qp_table.bank[bankid].inuse--;
 440	mutex_unlock(&hr_dev->qp_table.bank_mutex);
 441}
 442
 443static u32 proc_rq_sge(struct hns_roce_dev *dev, struct hns_roce_qp *hr_qp,
 444		       bool user)
 445{
 446	u32 max_sge = dev->caps.max_rq_sg;
 447
 448	if (dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 449		return max_sge;
 450
 451	/* Reserve SGEs only for HIP08 in kernel; The userspace driver will
 452	 * calculate number of max_sge with reserved SGEs when allocating wqe
 453	 * buf, so there is no need to do this again in kernel. But the number
 454	 * may exceed the capacity of SGEs recorded in the firmware, so the
 455	 * kernel driver should just adapt the value accordingly.
 456	 */
 457	if (user)
 458		max_sge = roundup_pow_of_two(max_sge + 1);
 459	else
 460		hr_qp->rq.rsv_sge = 1;
 461
 462	return max_sge;
 463}
 464
 465static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap,
 466		       struct hns_roce_qp *hr_qp, int has_rq, bool user)
 467{
 468	u32 max_sge = proc_rq_sge(hr_dev, hr_qp, user);
 469	u32 cnt;
 470
 471	/* If srq exist, set zero for relative number of rq */
 472	if (!has_rq) {
 473		hr_qp->rq.wqe_cnt = 0;
 474		hr_qp->rq.max_gs = 0;
 475		cap->max_recv_wr = 0;
 476		cap->max_recv_sge = 0;
 477
 478		return 0;
 479	}
 480
 481	/* Check the validity of QP support capacity */
 482	if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes ||
 483	    cap->max_recv_sge > max_sge) {
 484		ibdev_err(&hr_dev->ib_dev,
 485			  "RQ config error, depth = %u, sge = %u\n",
 486			  cap->max_recv_wr, cap->max_recv_sge);
 487		return -EINVAL;
 488	}
 489
 490	cnt = roundup_pow_of_two(max(cap->max_recv_wr, hr_dev->caps.min_wqes));
 491	if (cnt > hr_dev->caps.max_wqes) {
 492		ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n",
 493			  cap->max_recv_wr);
 494		return -EINVAL;
 495	}
 496
 497	hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge) +
 498					      hr_qp->rq.rsv_sge);
 499
 500	hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz *
 501				    hr_qp->rq.max_gs);
 502
 503	hr_qp->rq.wqe_cnt = cnt;
 504
 505	cap->max_recv_wr = cnt;
 506	cap->max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
 507
 508	return 0;
 509}
 510
 511static u32 get_max_inline_data(struct hns_roce_dev *hr_dev,
 512			       struct ib_qp_cap *cap)
 513{
 514	if (cap->max_inline_data) {
 515		cap->max_inline_data = roundup_pow_of_two(cap->max_inline_data);
 516		return min(cap->max_inline_data,
 517			   hr_dev->caps.max_sq_inline);
 518	}
 519
 520	return 0;
 521}
 522
 523static void update_inline_data(struct hns_roce_qp *hr_qp,
 524			       struct ib_qp_cap *cap)
 525{
 526	u32 sge_num = hr_qp->sq.ext_sge_cnt;
 527
 528	if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) {
 529		if (!(hr_qp->ibqp.qp_type == IB_QPT_GSI ||
 530		      hr_qp->ibqp.qp_type == IB_QPT_UD))
 531			sge_num = max((u32)HNS_ROCE_SGE_IN_WQE, sge_num);
 532
 533		cap->max_inline_data = max(cap->max_inline_data,
 534					   sge_num * HNS_ROCE_SGE_SIZE);
 535	}
 536
 537	hr_qp->max_inline_data = cap->max_inline_data;
 538}
 539
 540static u32 get_sge_num_from_max_send_sge(bool is_ud_or_gsi,
 541					 u32 max_send_sge)
 542{
 543	unsigned int std_sge_num;
 544	unsigned int min_sge;
 545
 546	std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE;
 547	min_sge = is_ud_or_gsi ? 1 : 0;
 548	return max_send_sge > std_sge_num ? (max_send_sge - std_sge_num) :
 549				min_sge;
 550}
 551
 552static unsigned int get_sge_num_from_max_inl_data(bool is_ud_or_gsi,
 553						  u32 max_inline_data)
 554{
 555	unsigned int inline_sge;
 556
 557	if (!max_inline_data)
 558		return 0;
 559
 560	/*
 561	 * if max_inline_data less than
 562	 * HNS_ROCE_SGE_IN_WQE * HNS_ROCE_SGE_SIZE,
 563	 * In addition to ud's mode, no need to extend sge.
 564	 */
 565	inline_sge = roundup_pow_of_two(max_inline_data) / HNS_ROCE_SGE_SIZE;
 566	if (!is_ud_or_gsi && inline_sge <= HNS_ROCE_SGE_IN_WQE)
 567		inline_sge = 0;
 568
 569	return inline_sge;
 570}
 571
 572static void set_ext_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt,
 573			      struct hns_roce_qp *hr_qp, struct ib_qp_cap *cap)
 574{
 575	bool is_ud_or_gsi = (hr_qp->ibqp.qp_type == IB_QPT_GSI ||
 576				hr_qp->ibqp.qp_type == IB_QPT_UD);
 577	unsigned int std_sge_num;
 578	u32 inline_ext_sge = 0;
 579	u32 ext_wqe_sge_cnt;
 580	u32 total_sge_cnt;
 581
 582	cap->max_inline_data = get_max_inline_data(hr_dev, cap);
 583
 584	hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT;
 585	std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE;
 586	ext_wqe_sge_cnt = get_sge_num_from_max_send_sge(is_ud_or_gsi,
 587							cap->max_send_sge);
 588
 589	if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) {
 590		inline_ext_sge = max(ext_wqe_sge_cnt,
 591				     get_sge_num_from_max_inl_data(is_ud_or_gsi,
 592							 cap->max_inline_data));
 593		hr_qp->sq.ext_sge_cnt = inline_ext_sge ?
 594					roundup_pow_of_two(inline_ext_sge) : 0;
 595
 596		hr_qp->sq.max_gs = max(1U, (hr_qp->sq.ext_sge_cnt + std_sge_num));
 597		hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg);
 598
 599		ext_wqe_sge_cnt = hr_qp->sq.ext_sge_cnt;
 600	} else {
 601		hr_qp->sq.max_gs = max(1U, cap->max_send_sge);
 602		hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg);
 603		hr_qp->sq.ext_sge_cnt = hr_qp->sq.max_gs;
 604	}
 605
 606	/* If the number of extended sge is not zero, they MUST use the
 607	 * space of HNS_HW_PAGE_SIZE at least.
 608	 */
 609	if (ext_wqe_sge_cnt) {
 610		total_sge_cnt = roundup_pow_of_two(sq_wqe_cnt * ext_wqe_sge_cnt);
 611		hr_qp->sge.sge_cnt = max(total_sge_cnt,
 612				(u32)HNS_HW_PAGE_SIZE / HNS_ROCE_SGE_SIZE);
 613	}
 614
 615	update_inline_data(hr_qp, cap);
 616}
 617
 618static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev,
 619					struct ib_qp_cap *cap,
 620					struct hns_roce_ib_create_qp *ucmd)
 621{
 622	u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
 623	u8 max_sq_stride = ilog2(roundup_sq_stride);
 624
 625	/* Sanity check SQ size before proceeding */
 626	if (ucmd->log_sq_stride > max_sq_stride ||
 627	    ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
 628		ibdev_err(&hr_dev->ib_dev, "failed to check SQ stride size.\n");
 629		return -EINVAL;
 630	}
 631
 632	if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
 633		ibdev_err(&hr_dev->ib_dev, "failed to check SQ SGE size %u.\n",
 634			  cap->max_send_sge);
 635		return -EINVAL;
 636	}
 637
 638	return 0;
 639}
 640
 641static int set_user_sq_size(struct hns_roce_dev *hr_dev,
 642			    struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp,
 643			    struct hns_roce_ib_create_qp *ucmd)
 644{
 645	struct ib_device *ibdev = &hr_dev->ib_dev;
 646	u32 cnt = 0;
 647	int ret;
 648
 649	if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) ||
 650	    cnt > hr_dev->caps.max_wqes)
 651		return -EINVAL;
 652
 653	ret = check_sq_size_with_integrity(hr_dev, cap, ucmd);
 654	if (ret) {
 655		ibdev_err(ibdev, "failed to check user SQ size, ret = %d.\n",
 656			  ret);
 657		return ret;
 658	}
 659
 660	set_ext_sge_param(hr_dev, cnt, hr_qp, cap);
 661
 662	hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
 663	hr_qp->sq.wqe_cnt = cnt;
 664
 665	return 0;
 666}
 667
 668static int set_wqe_buf_attr(struct hns_roce_dev *hr_dev,
 669			    struct hns_roce_qp *hr_qp,
 670			    struct hns_roce_buf_attr *buf_attr)
 671{
 672	int buf_size;
 673	int idx = 0;
 674
 675	hr_qp->buff_size = 0;
 676
 677	/* SQ WQE */
 678	hr_qp->sq.offset = 0;
 679	buf_size = to_hr_hem_entries_size(hr_qp->sq.wqe_cnt,
 680					  hr_qp->sq.wqe_shift);
 681	if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 682		buf_attr->region[idx].size = buf_size;
 683		buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sq_hop_num;
 684		idx++;
 685		hr_qp->buff_size += buf_size;
 686	}
 687
 688	/* extend SGE WQE in SQ */
 689	hr_qp->sge.offset = hr_qp->buff_size;
 690	buf_size = to_hr_hem_entries_size(hr_qp->sge.sge_cnt,
 691					  hr_qp->sge.sge_shift);
 692	if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 693		buf_attr->region[idx].size = buf_size;
 694		buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sge_hop_num;
 695		idx++;
 696		hr_qp->buff_size += buf_size;
 697	}
 698
 699	/* RQ WQE */
 700	hr_qp->rq.offset = hr_qp->buff_size;
 701	buf_size = to_hr_hem_entries_size(hr_qp->rq.wqe_cnt,
 702					  hr_qp->rq.wqe_shift);
 703	if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) {
 704		buf_attr->region[idx].size = buf_size;
 705		buf_attr->region[idx].hopnum = hr_dev->caps.wqe_rq_hop_num;
 706		idx++;
 707		hr_qp->buff_size += buf_size;
 708	}
 709
 710	if (hr_qp->buff_size < 1)
 711		return -EINVAL;
 712
 713	buf_attr->page_shift = HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
 714	buf_attr->region_count = idx;
 715
 716	return 0;
 717}
 718
 719static int set_kernel_sq_size(struct hns_roce_dev *hr_dev,
 720			      struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp)
 721{
 722	struct ib_device *ibdev = &hr_dev->ib_dev;
 723	u32 cnt;
 724
 725	if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes ||
 726	    cap->max_send_sge > hr_dev->caps.max_sq_sg) {
 727		ibdev_err(ibdev, "failed to check SQ WR or SGE num.\n");
 728		return -EINVAL;
 729	}
 730
 731	cnt = roundup_pow_of_two(max(cap->max_send_wr, hr_dev->caps.min_wqes));
 732	if (cnt > hr_dev->caps.max_wqes) {
 733		ibdev_err(ibdev, "failed to check WQE num, WQE num = %u.\n",
 734			  cnt);
 735		return -EINVAL;
 736	}
 737
 738	hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
 739	hr_qp->sq.wqe_cnt = cnt;
 740
 741	set_ext_sge_param(hr_dev, cnt, hr_qp, cap);
 742
 743	/* sync the parameters of kernel QP to user's configuration */
 744	cap->max_send_wr = cnt;
 745
 746	return 0;
 747}
 748
 749static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
 750{
 751	if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr)
 752		return 0;
 753
 754	return 1;
 755}
 756
 757static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
 758{
 759	if (attr->qp_type == IB_QPT_XRC_INI ||
 760	    attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 761	    !attr->cap.max_recv_wr)
 762		return 0;
 763
 764	return 1;
 765}
 766
 767static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 768			struct ib_qp_init_attr *init_attr,
 769			struct ib_udata *udata, unsigned long addr)
 770{
 771	struct ib_device *ibdev = &hr_dev->ib_dev;
 772	struct hns_roce_buf_attr buf_attr = {};
 773	int ret;
 774
 775	ret = set_wqe_buf_attr(hr_dev, hr_qp, &buf_attr);
 776	if (ret) {
 777		ibdev_err(ibdev, "failed to split WQE buf, ret = %d.\n", ret);
 778		goto err_inline;
 779	}
 780	ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr,
 781				  PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz,
 782				  udata, addr);
 783	if (ret) {
 784		ibdev_err(ibdev, "failed to create WQE mtr, ret = %d.\n", ret);
 785		goto err_inline;
 786	}
 787
 788	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_DIRECT_WQE)
 789		hr_qp->en_flags |= HNS_ROCE_QP_CAP_DIRECT_WQE;
 790
 791	return 0;
 792
 793err_inline:
 794
 795	return ret;
 796}
 797
 798static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
 799{
 800	hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr);
 801}
 802
 803static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev,
 804				   struct ib_qp_init_attr *init_attr,
 805				   struct ib_udata *udata,
 806				   struct hns_roce_ib_create_qp_resp *resp,
 807				   struct hns_roce_ib_create_qp *ucmd)
 808{
 809	return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 810		udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
 811		hns_roce_qp_has_sq(init_attr) &&
 812		udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr));
 813}
 814
 815static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev,
 816				   struct ib_qp_init_attr *init_attr,
 817				   struct ib_udata *udata,
 818				   struct hns_roce_ib_create_qp_resp *resp)
 819{
 820	return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 821		udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
 822		hns_roce_qp_has_rq(init_attr));
 823}
 824
 825static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev,
 826				     struct ib_qp_init_attr *init_attr)
 827{
 828	return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) &&
 829		hns_roce_qp_has_rq(init_attr));
 830}
 831
 832static int qp_mmap_entry(struct hns_roce_qp *hr_qp,
 833			 struct hns_roce_dev *hr_dev,
 834			 struct ib_udata *udata,
 835			 struct hns_roce_ib_create_qp_resp *resp)
 836{
 837	struct hns_roce_ucontext *uctx =
 838		rdma_udata_to_drv_context(udata,
 839			struct hns_roce_ucontext, ibucontext);
 840	struct rdma_user_mmap_entry *rdma_entry;
 841	u64 address;
 842
 843	address = hr_dev->dwqe_page + hr_qp->qpn * HNS_ROCE_DWQE_SIZE;
 844
 845	hr_qp->dwqe_mmap_entry =
 846		hns_roce_user_mmap_entry_insert(&uctx->ibucontext, address,
 847						HNS_ROCE_DWQE_SIZE,
 848						HNS_ROCE_MMAP_TYPE_DWQE);
 849
 850	if (!hr_qp->dwqe_mmap_entry) {
 851		ibdev_err(&hr_dev->ib_dev, "failed to get dwqe mmap entry.\n");
 852		return -ENOMEM;
 853	}
 854
 855	rdma_entry = &hr_qp->dwqe_mmap_entry->rdma_entry;
 856	resp->dwqe_mmap_key = rdma_user_mmap_get_offset(rdma_entry);
 857
 858	return 0;
 859}
 860
 861static int alloc_user_qp_db(struct hns_roce_dev *hr_dev,
 862			    struct hns_roce_qp *hr_qp,
 863			    struct ib_qp_init_attr *init_attr,
 864			    struct ib_udata *udata,
 865			    struct hns_roce_ib_create_qp *ucmd,
 866			    struct hns_roce_ib_create_qp_resp *resp)
 867{
 868	bool has_sdb = user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd);
 869	struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
 870		struct hns_roce_ucontext, ibucontext);
 871	bool has_rdb = user_qp_has_rdb(hr_dev, init_attr, udata, resp);
 872	struct ib_device *ibdev = &hr_dev->ib_dev;
 873	int ret;
 874
 875	if (has_sdb) {
 876		ret = hns_roce_db_map_user(uctx, ucmd->sdb_addr, &hr_qp->sdb);
 877		if (ret) {
 878			ibdev_err(ibdev,
 879				  "failed to map user SQ doorbell, ret = %d.\n",
 880				  ret);
 881			goto err_out;
 882		}
 883		hr_qp->en_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB;
 884	}
 885
 886	if (has_rdb) {
 887		ret = hns_roce_db_map_user(uctx, ucmd->db_addr, &hr_qp->rdb);
 888		if (ret) {
 889			ibdev_err(ibdev,
 890				  "failed to map user RQ doorbell, ret = %d.\n",
 891				  ret);
 892			goto err_sdb;
 893		}
 894		hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB;
 895	}
 896
 897	return 0;
 898
 899err_sdb:
 900	if (has_sdb)
 901		hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
 902err_out:
 903	return ret;
 904}
 905
 906static int alloc_kernel_qp_db(struct hns_roce_dev *hr_dev,
 907			      struct hns_roce_qp *hr_qp,
 908			      struct ib_qp_init_attr *init_attr)
 909{
 910	struct ib_device *ibdev = &hr_dev->ib_dev;
 911	int ret;
 912
 913	if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
 914		hr_qp->sq.db_reg = hr_dev->mem_base +
 915				   HNS_ROCE_DWQE_SIZE * hr_qp->qpn;
 916	else
 917		hr_qp->sq.db_reg = hr_dev->reg_base + hr_dev->sdb_offset +
 918				   DB_REG_OFFSET * hr_dev->priv_uar.index;
 919
 920	hr_qp->rq.db_reg = hr_dev->reg_base + hr_dev->odb_offset +
 921			   DB_REG_OFFSET * hr_dev->priv_uar.index;
 922
 923	if (kernel_qp_has_rdb(hr_dev, init_attr)) {
 924		ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
 925		if (ret) {
 926			ibdev_err(ibdev,
 927				  "failed to alloc kernel RQ doorbell, ret = %d.\n",
 928				  ret);
 929			return ret;
 930		}
 931		*hr_qp->rdb.db_record = 0;
 932		hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB;
 933	}
 934
 935	return 0;
 936}
 937
 938static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 939		       struct ib_qp_init_attr *init_attr,
 940		       struct ib_udata *udata,
 941		       struct hns_roce_ib_create_qp *ucmd,
 942		       struct hns_roce_ib_create_qp_resp *resp)
 943{
 944	int ret;
 945
 946	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SDI_MODE)
 947		hr_qp->en_flags |= HNS_ROCE_QP_CAP_OWNER_DB;
 948
 949	if (udata) {
 950		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) {
 951			ret = qp_mmap_entry(hr_qp, hr_dev, udata, resp);
 952			if (ret)
 953				return ret;
 954		}
 955
 956		ret = alloc_user_qp_db(hr_dev, hr_qp, init_attr, udata, ucmd,
 957				       resp);
 958		if (ret)
 959			goto err_remove_qp;
 960	} else {
 961		ret = alloc_kernel_qp_db(hr_dev, hr_qp, init_attr);
 962		if (ret)
 963			return ret;
 964	}
 965
 966	return 0;
 967
 968err_remove_qp:
 969	if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)
 970		qp_user_mmap_entry_remove(hr_qp);
 971
 972	return ret;
 973}
 974
 975static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
 976		       struct ib_udata *udata)
 977{
 978	struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(
 979		udata, struct hns_roce_ucontext, ibucontext);
 980
 981	if (udata) {
 982		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
 983			hns_roce_db_unmap_user(uctx, &hr_qp->rdb);
 984		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB)
 985			hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
 986		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)
 987			qp_user_mmap_entry_remove(hr_qp);
 988	} else {
 989		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
 990			hns_roce_free_db(hr_dev, &hr_qp->rdb);
 991	}
 992}
 993
 994static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev,
 995			     struct hns_roce_qp *hr_qp)
 996{
 997	struct ib_device *ibdev = &hr_dev->ib_dev;
 998	u64 *sq_wrid = NULL;
 999	u64 *rq_wrid = NULL;
1000	int ret;
1001
1002	sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL);
1003	if (!sq_wrid) {
1004		ibdev_err(ibdev, "failed to alloc SQ wrid.\n");
1005		return -ENOMEM;
1006	}
1007
1008	if (hr_qp->rq.wqe_cnt) {
1009		rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL);
1010		if (!rq_wrid) {
1011			ibdev_err(ibdev, "failed to alloc RQ wrid.\n");
1012			ret = -ENOMEM;
1013			goto err_sq;
1014		}
1015	}
1016
1017	hr_qp->sq.wrid = sq_wrid;
1018	hr_qp->rq.wrid = rq_wrid;
1019	return 0;
1020err_sq:
1021	kfree(sq_wrid);
1022
1023	return ret;
1024}
1025
1026static void free_kernel_wrid(struct hns_roce_qp *hr_qp)
1027{
1028	kfree(hr_qp->rq.wrid);
1029	kfree(hr_qp->sq.wrid);
1030}
1031
1032static void default_congest_type(struct hns_roce_dev *hr_dev,
1033				 struct hns_roce_qp *hr_qp)
1034{
1035	if (hr_qp->ibqp.qp_type == IB_QPT_UD ||
1036	    hr_qp->ibqp.qp_type == IB_QPT_GSI)
1037		hr_qp->cong_type = CONG_TYPE_DCQCN;
1038	else
1039		hr_qp->cong_type = hr_dev->caps.default_cong_type;
1040}
1041
1042static int set_congest_type(struct hns_roce_qp *hr_qp,
1043			    struct hns_roce_ib_create_qp *ucmd)
1044{
1045	struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1046
1047	switch (ucmd->cong_type_flags) {
1048	case HNS_ROCE_CREATE_QP_FLAGS_DCQCN:
1049		hr_qp->cong_type = CONG_TYPE_DCQCN;
1050		break;
1051	case HNS_ROCE_CREATE_QP_FLAGS_LDCP:
1052		hr_qp->cong_type = CONG_TYPE_LDCP;
1053		break;
1054	case HNS_ROCE_CREATE_QP_FLAGS_HC3:
1055		hr_qp->cong_type = CONG_TYPE_HC3;
1056		break;
1057	case HNS_ROCE_CREATE_QP_FLAGS_DIP:
1058		hr_qp->cong_type = CONG_TYPE_DIP;
1059		break;
1060	default:
1061		return -EINVAL;
1062	}
1063
1064	if (!test_bit(hr_qp->cong_type, (unsigned long *)&hr_dev->caps.cong_cap))
1065		return -EOPNOTSUPP;
1066
1067	if (hr_qp->ibqp.qp_type == IB_QPT_UD &&
1068	    hr_qp->cong_type != CONG_TYPE_DCQCN)
1069		return -EOPNOTSUPP;
1070
1071	return 0;
1072}
1073
1074static int set_congest_param(struct hns_roce_dev *hr_dev,
1075			     struct hns_roce_qp *hr_qp,
1076			     struct hns_roce_ib_create_qp *ucmd)
1077{
1078	if (ucmd->comp_mask & HNS_ROCE_CREATE_QP_MASK_CONGEST_TYPE)
1079		return set_congest_type(hr_qp, ucmd);
1080
1081	default_congest_type(hr_dev, hr_qp);
1082
1083	return 0;
1084}
1085
1086static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1087			struct ib_qp_init_attr *init_attr,
1088			struct ib_udata *udata,
1089			struct hns_roce_ib_create_qp *ucmd)
1090{
1091	struct ib_device *ibdev = &hr_dev->ib_dev;
1092	struct hns_roce_ucontext *uctx;
1093	int ret;
1094
1095	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1096		hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR;
1097	else
1098		hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR;
1099
1100	ret = set_rq_size(hr_dev, &init_attr->cap, hr_qp,
1101			  hns_roce_qp_has_rq(init_attr), !!udata);
1102	if (ret) {
1103		ibdev_err(ibdev, "failed to set user RQ size, ret = %d.\n",
1104			  ret);
1105		return ret;
1106	}
1107
1108	if (udata) {
1109		ret = ib_copy_from_udata(ucmd, udata,
1110					 min(udata->inlen, sizeof(*ucmd)));
1111		if (ret) {
1112			ibdev_err(ibdev,
1113				  "failed to copy QP ucmd, ret = %d\n", ret);
1114			return ret;
1115		}
1116
1117		uctx = rdma_udata_to_drv_context(udata, struct hns_roce_ucontext,
1118						 ibucontext);
1119		hr_qp->config = uctx->config;
1120		ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd);
1121		if (ret) {
1122			ibdev_err(ibdev,
1123				  "failed to set user SQ size, ret = %d.\n",
1124				  ret);
1125			return ret;
1126		}
1127
1128		ret = set_congest_param(hr_dev, hr_qp, ucmd);
1129	} else {
1130		if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
1131			hr_qp->config = HNS_ROCE_EXSGE_FLAGS;
1132		default_congest_type(hr_dev, hr_qp);
1133		ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp);
1134		if (ret)
1135			ibdev_err(ibdev,
1136				  "failed to set kernel SQ size, ret = %d.\n",
1137				  ret);
1138	}
1139
1140	return ret;
1141}
1142
1143static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
1144				     struct ib_qp_init_attr *init_attr,
1145				     struct ib_udata *udata,
1146				     struct hns_roce_qp *hr_qp)
1147{
1148	struct hns_roce_work *flush_work = &hr_qp->flush_work;
1149	struct hns_roce_ib_create_qp_resp resp = {};
1150	struct ib_device *ibdev = &hr_dev->ib_dev;
1151	struct hns_roce_ib_create_qp ucmd = {};
1152	int ret;
1153
1154	mutex_init(&hr_qp->mutex);
1155	spin_lock_init(&hr_qp->sq.lock);
1156	spin_lock_init(&hr_qp->rq.lock);
1157	spin_lock_init(&hr_qp->flush_lock);
1158
1159	hr_qp->state = IB_QPS_RESET;
1160	hr_qp->flush_flag = 0;
1161	flush_work->hr_dev = hr_dev;
1162	INIT_WORK(&flush_work->work, flush_work_handle);
1163
1164	if (init_attr->create_flags)
1165		return -EOPNOTSUPP;
1166
1167	ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd);
1168	if (ret) {
1169		ibdev_err(ibdev, "failed to set QP param, ret = %d.\n", ret);
1170		goto err_out;
1171	}
1172
1173	if (!udata) {
1174		ret = alloc_kernel_wrid(hr_dev, hr_qp);
1175		if (ret) {
1176			ibdev_err(ibdev, "failed to alloc wrid, ret = %d.\n",
1177				  ret);
1178			goto err_out;
1179		}
1180	}
1181
1182	ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr);
1183	if (ret) {
1184		ibdev_err(ibdev, "failed to alloc QP buffer, ret = %d.\n", ret);
1185		goto err_buf;
1186	}
1187
1188	ret = alloc_qpn(hr_dev, hr_qp, init_attr);
1189	if (ret) {
1190		ibdev_err(ibdev, "failed to alloc QPN, ret = %d.\n", ret);
1191		goto err_qpn;
1192	}
1193
1194	ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp);
1195	if (ret) {
1196		ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n",
1197			  ret);
1198		goto err_db;
1199	}
1200
1201	ret = alloc_qpc(hr_dev, hr_qp);
1202	if (ret) {
1203		ibdev_err(ibdev, "failed to alloc QP context, ret = %d.\n",
1204			  ret);
1205		goto err_qpc;
1206	}
1207
1208	ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr);
1209	if (ret) {
1210		ibdev_err(ibdev, "failed to store QP, ret = %d.\n", ret);
1211		goto err_store;
1212	}
1213
1214	if (udata) {
1215		resp.cap_flags = hr_qp->en_flags;
1216		ret = ib_copy_to_udata(udata, &resp,
1217				       min(udata->outlen, sizeof(resp)));
1218		if (ret) {
1219			ibdev_err(ibdev, "copy qp resp failed!\n");
1220			goto err_flow_ctrl;
1221		}
1222	}
1223
1224	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
1225		ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp);
1226		if (ret)
1227			goto err_flow_ctrl;
1228	}
1229
1230	hr_qp->ibqp.qp_num = hr_qp->qpn;
1231	hr_qp->event = hns_roce_ib_qp_event;
1232	refcount_set(&hr_qp->refcount, 1);
1233	init_completion(&hr_qp->free);
1234
1235	return 0;
1236
1237err_flow_ctrl:
1238	hns_roce_qp_remove(hr_dev, hr_qp);
1239err_store:
1240	free_qpc(hr_dev, hr_qp);
1241err_qpc:
1242	free_qp_db(hr_dev, hr_qp, udata);
1243err_db:
1244	free_qpn(hr_dev, hr_qp);
1245err_qpn:
1246	free_qp_buf(hr_dev, hr_qp);
1247err_buf:
1248	free_kernel_wrid(hr_qp);
1249err_out:
1250	mutex_destroy(&hr_qp->mutex);
1251	return ret;
1252}
1253
1254void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1255			 struct ib_udata *udata)
1256{
1257	if (refcount_dec_and_test(&hr_qp->refcount))
1258		complete(&hr_qp->free);
1259	wait_for_completion(&hr_qp->free);
1260
1261	free_qpc(hr_dev, hr_qp);
1262	free_qpn(hr_dev, hr_qp);
1263	free_qp_buf(hr_dev, hr_qp);
1264	free_kernel_wrid(hr_qp);
1265	free_qp_db(hr_dev, hr_qp, udata);
1266	mutex_destroy(&hr_qp->mutex);
1267}
1268
1269static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type,
1270			 bool is_user)
1271{
1272	switch (type) {
1273	case IB_QPT_XRC_INI:
1274	case IB_QPT_XRC_TGT:
1275		if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC))
1276			goto out;
1277		break;
1278	case IB_QPT_UD:
1279		if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 &&
1280		    is_user)
1281			goto out;
1282		break;
1283	case IB_QPT_RC:
1284	case IB_QPT_GSI:
1285		break;
1286	default:
1287		goto out;
1288	}
1289
1290	return 0;
1291
1292out:
1293	ibdev_err(&hr_dev->ib_dev, "not support QP type %d\n", type);
1294
1295	return -EOPNOTSUPP;
1296}
1297
1298int hns_roce_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
1299		       struct ib_udata *udata)
1300{
1301	struct ib_device *ibdev = qp->device;
1302	struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
1303	struct hns_roce_qp *hr_qp = to_hr_qp(qp);
1304	int ret;
1305
1306	ret = check_qp_type(hr_dev, init_attr->qp_type, !!udata);
1307	if (ret)
1308		goto err_out;
1309
1310	if (init_attr->qp_type == IB_QPT_XRC_TGT)
1311		hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn;
1312
1313	if (init_attr->qp_type == IB_QPT_GSI) {
1314		hr_qp->port = init_attr->port_num - 1;
1315		hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
1316	}
1317
1318	ret = hns_roce_create_qp_common(hr_dev, init_attr, udata, hr_qp);
1319	if (ret)
1320		ibdev_err(ibdev, "create QP type %d failed(%d)\n",
1321			  init_attr->qp_type, ret);
1322
1323err_out:
1324	if (ret)
1325		atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_QP_CREATE_ERR_CNT]);
1326
1327	return ret;
1328}
1329
1330int to_hr_qp_type(int qp_type)
1331{
1332	switch (qp_type) {
1333	case IB_QPT_RC:
1334		return SERV_TYPE_RC;
1335	case IB_QPT_UD:
1336	case IB_QPT_GSI:
1337		return SERV_TYPE_UD;
1338	case IB_QPT_XRC_INI:
1339	case IB_QPT_XRC_TGT:
1340		return SERV_TYPE_XRC;
1341	default:
1342		return -1;
1343	}
1344}
1345
1346static int check_mtu_validate(struct hns_roce_dev *hr_dev,
1347			      struct hns_roce_qp *hr_qp,
1348			      struct ib_qp_attr *attr, int attr_mask)
1349{
1350	struct net_device *net_dev;
1351	enum ib_mtu active_mtu;
1352	int p;
1353
1354	p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1355	net_dev = get_hr_netdev(hr_dev, p);
1356	active_mtu = iboe_get_mtu(net_dev->mtu);
1357
1358	if ((hr_dev->caps.max_mtu >= IB_MTU_2048 &&
1359	    attr->path_mtu > hr_dev->caps.max_mtu) ||
1360	    attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) {
1361		ibdev_err(&hr_dev->ib_dev,
1362			"attr path_mtu(%d)invalid while modify qp",
1363			attr->path_mtu);
1364		return -EINVAL;
1365	}
1366
1367	return 0;
1368}
1369
1370static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1371				  int attr_mask)
1372{
1373	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1374	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1375	int p;
1376
1377	if ((attr_mask & IB_QP_PORT) &&
1378	    (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
1379		ibdev_err(&hr_dev->ib_dev, "invalid attr, port_num = %u.\n",
1380			  attr->port_num);
1381		return -EINVAL;
1382	}
1383
1384	if (attr_mask & IB_QP_PKEY_INDEX) {
1385		p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1386		if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
1387			ibdev_err(&hr_dev->ib_dev,
1388				  "invalid attr, pkey_index = %u.\n",
1389				  attr->pkey_index);
1390			return -EINVAL;
1391		}
1392	}
1393
1394	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1395	    attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
1396		ibdev_err(&hr_dev->ib_dev,
1397			  "invalid attr, max_rd_atomic = %u.\n",
1398			  attr->max_rd_atomic);
1399		return -EINVAL;
1400	}
1401
1402	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1403	    attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
1404		ibdev_err(&hr_dev->ib_dev,
1405			  "invalid attr, max_dest_rd_atomic = %u.\n",
1406			  attr->max_dest_rd_atomic);
1407		return -EINVAL;
1408	}
1409
1410	if (attr_mask & IB_QP_PATH_MTU)
1411		return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask);
1412
1413	return 0;
1414}
1415
1416int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1417		       int attr_mask, struct ib_udata *udata)
1418{
1419	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1420	struct hns_roce_ib_modify_qp_resp resp = {};
1421	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1422	enum ib_qp_state cur_state, new_state;
1423	int ret = -EINVAL;
1424
1425	mutex_lock(&hr_qp->mutex);
1426
1427	if (attr_mask & IB_QP_CUR_STATE && attr->cur_qp_state != hr_qp->state)
1428		goto out;
1429
1430	cur_state = hr_qp->state;
1431	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1432
1433	if (ibqp->uobject &&
1434	    (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
1435		if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) {
1436			hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
1437
1438			if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
1439				hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
1440		} else {
1441			ibdev_warn(&hr_dev->ib_dev,
1442				  "flush cqe is not supported in userspace!\n");
1443			goto out;
1444		}
1445	}
1446
1447	if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1448				attr_mask)) {
1449		ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n");
1450		goto out;
1451	}
1452
1453	ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask);
1454	if (ret)
1455		goto out;
1456
1457	if (cur_state == new_state && cur_state == IB_QPS_RESET)
1458		goto out;
1459
1460	ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
1461				    new_state, udata);
1462	if (ret)
1463		goto out;
1464
1465	if (udata && udata->outlen) {
1466		resp.tc_mode = hr_qp->tc_mode;
1467		resp.priority = hr_qp->sl;
1468		ret = ib_copy_to_udata(udata, &resp,
1469				       min(udata->outlen, sizeof(resp)));
1470		if (ret)
1471			ibdev_err_ratelimited(&hr_dev->ib_dev,
1472					      "failed to copy modify qp resp.\n");
1473	}
1474
1475out:
1476	mutex_unlock(&hr_qp->mutex);
1477	if (ret)
1478		atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_QP_MODIFY_ERR_CNT]);
1479
1480	return ret;
1481}
1482
1483void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
1484		       __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1485{
1486	if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1487		__acquire(&send_cq->lock);
1488		__acquire(&recv_cq->lock);
1489	} else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1490		spin_lock(&send_cq->lock);
1491		__acquire(&recv_cq->lock);
1492	} else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1493		spin_lock(&recv_cq->lock);
1494		__acquire(&send_cq->lock);
1495	} else if (send_cq == recv_cq) {
1496		spin_lock(&send_cq->lock);
1497		__acquire(&recv_cq->lock);
1498	} else if (send_cq->cqn < recv_cq->cqn) {
1499		spin_lock(&send_cq->lock);
1500		spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1501	} else {
1502		spin_lock(&recv_cq->lock);
1503		spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1504	}
1505}
1506
1507void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1508			 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
1509			 __releases(&recv_cq->lock)
1510{
1511	if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1512		__release(&recv_cq->lock);
1513		__release(&send_cq->lock);
1514	} else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1515		__release(&recv_cq->lock);
1516		spin_unlock(&send_cq->lock);
1517	} else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1518		__release(&send_cq->lock);
1519		spin_unlock(&recv_cq->lock);
1520	} else if (send_cq == recv_cq) {
1521		__release(&recv_cq->lock);
1522		spin_unlock(&send_cq->lock);
1523	} else if (send_cq->cqn < recv_cq->cqn) {
1524		spin_unlock(&recv_cq->lock);
1525		spin_unlock(&send_cq->lock);
1526	} else {
1527		spin_unlock(&send_cq->lock);
1528		spin_unlock(&recv_cq->lock);
1529	}
1530}
1531
1532static inline void *get_wqe(struct hns_roce_qp *hr_qp, u32 offset)
1533{
1534	return hns_roce_buf_offset(hr_qp->mtr.kmem, offset);
1535}
1536
1537void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
1538{
1539	return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
1540}
1541
1542void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
1543{
1544	return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
1545}
1546
1547void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n)
1548{
1549	return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift));
1550}
1551
1552bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1553			  struct ib_cq *ib_cq)
1554{
1555	struct hns_roce_cq *hr_cq;
1556	u32 cur;
1557
1558	cur = hr_wq->head - hr_wq->tail;
1559	if (likely(cur + nreq < hr_wq->wqe_cnt))
1560		return false;
1561
1562	hr_cq = to_hr_cq(ib_cq);
1563	spin_lock(&hr_cq->lock);
1564	cur = hr_wq->head - hr_wq->tail;
1565	spin_unlock(&hr_cq->lock);
1566
1567	return cur + nreq >= hr_wq->wqe_cnt;
1568}
1569
1570int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
1571{
1572	struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
1573	unsigned int reserved_from_bot;
1574	unsigned int i;
1575
1576	mutex_init(&qp_table->scc_mutex);
1577	mutex_init(&qp_table->bank_mutex);
1578	xa_init(&hr_dev->qp_table_xa);
1579	xa_init(&qp_table->dip_xa);
1580
1581	reserved_from_bot = hr_dev->caps.reserved_qps;
1582
1583	for (i = 0; i < reserved_from_bot; i++) {
1584		hr_dev->qp_table.bank[get_qp_bankid(i)].inuse++;
1585		hr_dev->qp_table.bank[get_qp_bankid(i)].min++;
1586	}
1587
1588	for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) {
1589		ida_init(&hr_dev->qp_table.bank[i].ida);
1590		hr_dev->qp_table.bank[i].max = hr_dev->caps.num_qps /
1591					       HNS_ROCE_QP_BANK_NUM - 1;
1592		hr_dev->qp_table.bank[i].next = hr_dev->qp_table.bank[i].min;
1593	}
1594
1595	return 0;
1596}
1597
1598void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
1599{
1600	int i;
1601
1602	for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++)
1603		ida_destroy(&hr_dev->qp_table.bank[i].ida);
1604	xa_destroy(&hr_dev->qp_table.dip_xa);
1605	xa_destroy(&hr_dev->qp_table_xa);
1606	mutex_destroy(&hr_dev->qp_table.bank_mutex);
1607	mutex_destroy(&hr_dev->qp_table.scc_mutex);
1608}