qplib_rcfw.h

  1/*
  2 * Broadcom NetXtreme-E RoCE driver.
  3 *
  4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
  5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
  6 *
  7 * This software is available to you under a choice of one of two
  8 * licenses.  You may choose to be licensed under the terms of the GNU
  9 * General Public License (GPL) Version 2, available from the file
 10 * COPYING in the main directory of this source tree, or the
 11 * BSD license below:
 12 *
 13 * Redistribution and use in source and binary forms, with or without
 14 * modification, are permitted provided that the following conditions
 15 * are met:
 16 *
 17 * 1. Redistributions of source code must retain the above copyright
 18 *    notice, this list of conditions and the following disclaimer.
 19 * 2. Redistributions in binary form must reproduce the above copyright
 20 *    notice, this list of conditions and the following disclaimer in
 21 *    the documentation and/or other materials provided with the
 22 *    distribution.
 23 *
 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 35 *
 36 * Description: RDMA Controller HW interface (header)
 37 */
 38
 39#ifndef __BNXT_QPLIB_RCFW_H__
 40#define __BNXT_QPLIB_RCFW_H__
 41
 42#include "qplib_tlv.h"
 43
 44#define RCFW_CMDQ_TRIG_VAL		1
 45#define RCFW_COMM_PCI_BAR_REGION	0
 46#define RCFW_COMM_CONS_PCI_BAR_REGION	2
 47#define RCFW_COMM_BASE_OFFSET		0x600
 48#define RCFW_PF_VF_COMM_PROD_OFFSET	0xc
 49#define RCFW_COMM_TRIG_OFFSET		0x100
 50#define RCFW_COMM_SIZE			0x104
 51
 52#define RCFW_DBR_PCI_BAR_REGION		2
 53#define RCFW_DBR_BASE_PAGE_SHIFT	12
 54#define RCFW_FW_STALL_MAX_TIMEOUT	40
 55
 56/* Cmdq contains a fix number of a 16-Byte slots */
 57struct bnxt_qplib_cmdqe {
 58	u8		data[16];
 59};
 60
 61#define BNXT_QPLIB_CMDQE_UNITS		sizeof(struct bnxt_qplib_cmdqe)
 62
 63static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req,
 64					    u8 opcode, u8 cmd_size)
 65{
 66	req->opcode = opcode;
 67	req->cmd_size = cmd_size;
 68}
 69
 70/* Shadow queue depth for non blocking command */
 71#define RCFW_CMD_NON_BLOCKING_SHADOW_QD	64
 72#define RCFW_CMD_WAIT_TIME_MS		20000 /* 20 Seconds timeout */
 73
 74/* CMDQ elements */
 75#define BNXT_QPLIB_CMDQE_MAX_CNT	8192
 76#define BNXT_QPLIB_CMDQE_BYTES(depth)	((depth) * BNXT_QPLIB_CMDQE_UNITS)
 77
 78static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
 79{
 80	u32 npages;
 81
 82	npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
 83	if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
 84		npages++;
 85	return npages;
 86}
 87
 88static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
 89{
 90	return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
 91}
 92
 93/* Get the number of command units required for the req. The
 94 * function returns correct value only if called before
 95 * setting using bnxt_qplib_set_cmd_slots
 96 */
 97static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req)
 98{
 99	u32 cmd_units = 0;
100
101	if (HAS_TLV_HEADER(req)) {
102		struct roce_tlv *tlv_req = (struct roce_tlv *)req;
103
104		cmd_units = tlv_req->total_size;
105	} else {
106		cmd_units = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
107			    BNXT_QPLIB_CMDQE_UNITS;
108	}
109
110	return cmd_units;
111}
112
113static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
114{
115	u32 cmd_byte = 0;
116
117	if (HAS_TLV_HEADER(req)) {
118		struct roce_tlv *tlv_req = (struct roce_tlv *)req;
119
120		cmd_byte = tlv_req->total_size * BNXT_QPLIB_CMDQE_UNITS;
121	} else {
122		cmd_byte = req->cmd_size;
123		req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
124				 BNXT_QPLIB_CMDQE_UNITS;
125	}
126
127	return cmd_byte;
128}
129
130#define RCFW_MAX_COOKIE_VALUE		(BNXT_QPLIB_CMDQE_MAX_CNT - 1)
131#define RCFW_CMD_IS_BLOCKING		0x8000
132
133#define HWRM_VERSION_DEV_ATTR_MAX_DPI  0x1000A0000000DULL
134/* HWRM version 1.10.3.18 */
135#define HWRM_VERSION_READ_CTX           0x1000A00030012
136
137/* Crsq buf is 1024-Byte */
138struct bnxt_qplib_crsbe {
139	u8			data[1024];
140};
141
142/* CREQ */
143/* Allocate 1 per QP for async error notification for now */
144#define BNXT_QPLIB_CREQE_MAX_CNT	(64 * 1024)
145#define BNXT_QPLIB_CREQE_UNITS		16	/* 16-Bytes per prod unit */
146#define CREQ_CMP_VALID(hdr, pass)			\
147	(!!((hdr)->v & CREQ_BASE_V) ==				\
148	   !((pass) & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))
149#define CREQ_ENTRY_POLL_BUDGET		0x100
150
151/* HWQ */
152typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *);
153
154struct bnxt_qplib_crsqe {
155	struct creq_qp_event	*resp;
156	u32			req_size;
157	/* Free slots at the time of submission */
158	u32			free_slots;
159	u8			opcode;
160	bool			is_waiter_alive;
161	bool			is_internal_cmd;
162	bool			is_in_used;
163};
164
165struct bnxt_qplib_rcfw_sbuf {
166	void *sb;
167	dma_addr_t dma_addr;
168	u32 size;
169};
170
171struct bnxt_qplib_qp_node {
172	u32 qp_id;              /* QP id */
173	void *qp_handle;        /* ptr to qplib_qp */
174};
175
176#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
177
178#define FIRMWARE_INITIALIZED_FLAG	(0)
179#define FIRMWARE_FIRST_FLAG		(31)
180#define FIRMWARE_STALL_DETECTED		(3)
181#define ERR_DEVICE_DETACHED             (4)
182
183struct bnxt_qplib_cmdq_mbox {
184	struct bnxt_qplib_reg_desc	reg;
185	void __iomem			*prod;
186	void __iomem			*db;
187};
188
189struct bnxt_qplib_cmdq_ctx {
190	struct bnxt_qplib_hwq		hwq;
191	struct bnxt_qplib_cmdq_mbox	cmdq_mbox;
192	wait_queue_head_t		waitq;
193	unsigned long			flags;
194	unsigned long			last_seen;
195	u32				seq_num;
196};
197
198struct bnxt_qplib_creq_db {
199	struct bnxt_qplib_reg_desc	reg;
200	struct bnxt_qplib_db_info	dbinfo;
201};
202
203struct bnxt_qplib_creq_stat {
204	u64	creq_qp_event_processed;
205	u64	creq_func_event_processed;
206};
207
208struct bnxt_qplib_creq_ctx {
209	struct bnxt_qplib_hwq		hwq;
210	struct bnxt_qplib_creq_db	creq_db;
211	struct bnxt_qplib_creq_stat	stats;
212	struct tasklet_struct		creq_tasklet;
213	aeq_handler_t			aeq_handler;
214	u16				ring_id;
215	int				msix_vec;
216	bool				requested; /*irq handler installed */
217	char				*irq_name;
218};
219
220/* RCFW Communication Channels */
221struct bnxt_qplib_rcfw {
222	struct pci_dev		*pdev;
223	struct bnxt_qplib_res	*res;
224	struct bnxt_qplib_cmdq_ctx	cmdq;
225	struct bnxt_qplib_creq_ctx	creq;
226	struct bnxt_qplib_crsqe		*crsqe_tbl;
227	int qp_tbl_size;
228	struct bnxt_qplib_qp_node *qp_tbl;
229	/* To synchronize the qp-handle hash table */
230	spinlock_t			tbl_lock;
231	u64 oos_prev;
232	u32 init_oos_stats;
233	u32 cmdq_depth;
234	atomic_t rcfw_intr_enabled;
235	struct semaphore rcfw_inflight;
236	atomic_t timeout_send;
237	/* cached from chip cctx for quick reference in slow path */
238	u16 max_timeout;
239	bool roce_mirror;
240};
241
242struct bnxt_qplib_cmdqmsg {
243	struct cmdq_base	*req;
244	struct creq_base	*resp;
245	void			*sb;
246	u32			req_sz;
247	u32			res_sz;
248	u8			block;
249};
250
251static inline void bnxt_qplib_fill_cmdqmsg(struct bnxt_qplib_cmdqmsg *msg,
252					   void *req, void *resp, void *sb,
253					   u32 req_sz, u32 res_sz, u8 block)
254{
255	msg->req = req;
256	msg->resp = resp;
257	msg->sb = sb;
258	msg->req_sz = req_sz;
259	msg->res_sz = res_sz;
260	msg->block = block;
261}
262
263void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
264int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
265				  struct bnxt_qplib_rcfw *rcfw,
266				  struct bnxt_qplib_ctx *ctx);
267void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
268void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
269int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
270			      bool need_init);
271int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
272				   int msix_vector,
273				   int cp_bar_reg_off,
274				   aeq_handler_t aeq_handler);
275
276struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
277				struct bnxt_qplib_rcfw *rcfw,
278				u32 size);
279void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
280			       struct bnxt_qplib_rcfw_sbuf *sbuf);
281int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
282				 struct bnxt_qplib_cmdqmsg *msg);
283
284int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
285int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
286			 struct bnxt_qplib_ctx *ctx, int is_virtfn);
287void bnxt_qplib_mark_qp_error(void *qp_handle);
288
289static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw)
290{
291	/* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/
292	return (qid == 1) ? rcfw->qp_tbl_size - 1 : (qid % (rcfw->qp_tbl_size - 2));
293}
294#endif /* __BNXT_QPLIB_RCFW_H__ */