qplib_fp.h

  1/*
  2 * Broadcom NetXtreme-E RoCE driver.
  3 *
  4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
  5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
  6 *
  7 * This software is available to you under a choice of one of two
  8 * licenses.  You may choose to be licensed under the terms of the GNU
  9 * General Public License (GPL) Version 2, available from the file
 10 * COPYING in the main directory of this source tree, or the
 11 * BSD license below:
 12 *
 13 * Redistribution and use in source and binary forms, with or without
 14 * modification, are permitted provided that the following conditions
 15 * are met:
 16 *
 17 * 1. Redistributions of source code must retain the above copyright
 18 *    notice, this list of conditions and the following disclaimer.
 19 * 2. Redistributions in binary form must reproduce the above copyright
 20 *    notice, this list of conditions and the following disclaimer in
 21 *    the documentation and/or other materials provided with the
 22 *    distribution.
 23 *
 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 35 *
 36 * Description: Fast Path Operators (header)
 37 */
 38
 39#ifndef __BNXT_QPLIB_FP_H__
 40#define __BNXT_QPLIB_FP_H__
 41
 42#include <rdma/bnxt_re-abi.h>
 43
 44/* Few helper structures temporarily defined here
 45 * should get rid of these when roce_hsi.h is updated
 46 * in original code base
 47 */
 48struct sq_ud_ext_hdr {
 49	__le32 dst_qp;
 50	__le32 avid;
 51	__le64 rsvd;
 52};
 53
 54struct sq_raw_ext_hdr {
 55	__le32 cfa_meta;
 56	__le32 rsvd0;
 57	__le64 rsvd1;
 58};
 59
 60struct sq_rdma_ext_hdr {
 61	__le64 remote_va;
 62	__le32 remote_key;
 63	__le32 rsvd;
 64};
 65
 66struct sq_atomic_ext_hdr {
 67	__le64 swap_data;
 68	__le64 cmp_data;
 69};
 70
 71struct sq_fr_pmr_ext_hdr {
 72	__le64 pblptr;
 73	__le64 va;
 74};
 75
 76struct sq_bind_ext_hdr {
 77	__le64 va;
 78	__le32 length_lo;
 79	__le32 length_hi;
 80};
 81
 82struct rq_ext_hdr {
 83	__le64 rsvd1;
 84	__le64 rsvd2;
 85};
 86
 87/* Helper structures end */
 88
 89struct bnxt_qplib_srq {
 90	struct bnxt_qplib_pd		*pd;
 91	struct bnxt_qplib_dpi		*dpi;
 92	struct bnxt_qplib_db_info	dbinfo;
 93	u64				srq_handle;
 94	u32				id;
 95	u16				wqe_size;
 96	u32				max_wqe;
 97	u32				max_sge;
 98	u32				threshold;
 99	bool				arm_req;
100	struct bnxt_qplib_cq		*cq;
101	struct bnxt_qplib_hwq		hwq;
102	struct bnxt_qplib_swq		*swq;
103	int				start_idx;
104	int				last_idx;
105	struct bnxt_qplib_sg_info	sg_info;
106	u16				eventq_hw_ring_id;
107	spinlock_t			lock; /* protect SRQE link list */
108	u8				toggle;
109};
110
111struct bnxt_qplib_sge {
112	u64				addr;
113	u32				lkey;
114	u32				size;
115};
116
117struct bnxt_qplib_swq {
118	u64				wr_id;
119	int				next_idx;
120	u8				type;
121	u8				flags;
122	u32				start_psn;
123	u32				next_psn;
124	u32				slot_idx;
125	u8				slots;
126	struct sq_psn_search		*psn_search;
127	struct sq_psn_search_ext	*psn_ext;
128};
129
130struct bnxt_qplib_swqe {
131	/* General */
132#define	BNXT_QPLIB_FENCE_WRID	0x46454E43	/* "FENC" */
133	u64				wr_id;
134	u8				reqs_type;
135	u8				type;
136#define BNXT_QPLIB_SWQE_TYPE_SEND			0
137#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM		1
138#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV		2
139#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE			4
140#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM	5
141#define BNXT_QPLIB_SWQE_TYPE_RDMA_READ			6
142#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP		8
143#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD	11
144#define BNXT_QPLIB_SWQE_TYPE_LOCAL_INV			12
145#define BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR		13
146#define BNXT_QPLIB_SWQE_TYPE_REG_MR			13
147#define BNXT_QPLIB_SWQE_TYPE_BIND_MW			14
148#define BNXT_QPLIB_SWQE_TYPE_RECV			128
149#define BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM		129
150	u8				flags;
151#define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP		BIT(0)
152#define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE		BIT(1)
153#define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE			BIT(2)
154#define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT		BIT(3)
155#define BNXT_QPLIB_SWQE_FLAGS_INLINE			BIT(4)
156	struct bnxt_qplib_sge		sg_list[BNXT_VAR_MAX_SGE];
157	int				num_sge;
158	/* Max inline data is 96 bytes */
159	u32				inline_len;
160#define BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH		96
161	u8		inline_data[BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH];
162
163	union {
164		/* Send, with imm, inval key */
165		struct {
166			union {
167				u32	imm_data;
168				u32	inv_key;
169			};
170			u32		q_key;
171			u32		dst_qp;
172			u32		avid;
173		} send;
174
175		/* Send Raw Ethernet and QP1 */
176		struct {
177			u16		lflags;
178			u16		cfa_action;
179			u32		cfa_meta;
180		} rawqp1;
181
182		/* RDMA write, with imm, read */
183		struct {
184			union {
185				u32	imm_data;
186				u32	inv_key;
187			};
188			u64		remote_va;
189			u32		r_key;
190		} rdma;
191
192		/* Atomic cmp/swap, fetch/add */
193		struct {
194			u64		remote_va;
195			u32		r_key;
196			u64		swap_data;
197			u64		cmp_data;
198		} atomic;
199
200		/* Local Invalidate */
201		struct {
202			u32		inv_l_key;
203		} local_inv;
204
205		/* FR-PMR */
206		struct {
207			u8		access_cntl;
208			u8		pg_sz_log;
209			bool		zero_based;
210			u32		l_key;
211			u32		length;
212			u8		pbl_pg_sz_log;
213#define BNXT_QPLIB_SWQE_PAGE_SIZE_4K			0
214#define BNXT_QPLIB_SWQE_PAGE_SIZE_8K			1
215#define BNXT_QPLIB_SWQE_PAGE_SIZE_64K			4
216#define BNXT_QPLIB_SWQE_PAGE_SIZE_256K			6
217#define BNXT_QPLIB_SWQE_PAGE_SIZE_1M			8
218#define BNXT_QPLIB_SWQE_PAGE_SIZE_2M			9
219#define BNXT_QPLIB_SWQE_PAGE_SIZE_4M			10
220#define BNXT_QPLIB_SWQE_PAGE_SIZE_1G			18
221			u8		levels;
222#define PAGE_SHIFT_4K	12
223			__le64		*pbl_ptr;
224			dma_addr_t	pbl_dma_ptr;
225			u64		*page_list;
226			u16		page_list_len;
227			u64		va;
228		} frmr;
229
230		/* Bind */
231		struct {
232			u8		access_cntl;
233#define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE		BIT(0)
234#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ		BIT(1)
235#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE	BIT(2)
236#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC	BIT(3)
237#define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND		BIT(4)
238			bool		zero_based;
239			u8		mw_type;
240			u32		parent_l_key;
241			u32		r_key;
242			u64		va;
243			u32		length;
244		} bind;
245	};
246};
247
248struct bnxt_qplib_q {
249	struct bnxt_qplib_hwq		hwq;
250	struct bnxt_qplib_swq		*swq;
251	struct bnxt_qplib_db_info	dbinfo;
252	struct bnxt_qplib_sg_info	sg_info;
253	u32				max_wqe;
254	u32				max_sw_wqe;
255	u16				wqe_size;
256	u16				q_full_delta;
257	u16				max_sge;
258	u32				psn;
259	bool				condition;
260	bool				single;
261	bool				send_phantom;
262	u32				phantom_wqe_cnt;
263	u32				phantom_cqe_cnt;
264	u32				next_cq_cons;
265	bool				flushed;
266	u32				swq_start;
267	u32				swq_last;
268};
269
270struct bnxt_qplib_qp {
271	struct bnxt_qplib_pd		*pd;
272	struct bnxt_qplib_dpi		*dpi;
273	struct bnxt_qplib_chip_ctx	*cctx;
274	u64				qp_handle;
275#define BNXT_QPLIB_QP_ID_INVALID        0xFFFFFFFF
276	u32				id;
277	u8				type;
278	u8				sig_type;
279	u8				wqe_mode;
280	u8				state;
281	u8				cur_qp_state;
282	u64				modify_flags;
283	u32				max_inline_data;
284	u32				mtu;
285	u8				path_mtu;
286	bool				en_sqd_async_notify;
287	u16				pkey_index;
288	u32				qkey;
289	u32				dest_qp_id;
290	u8				access;
291	u8				timeout;
292	u8				retry_cnt;
293	u8				rnr_retry;
294	u64				wqe_cnt;
295	u32				min_rnr_timer;
296	u32				max_rd_atomic;
297	u32				max_dest_rd_atomic;
298	u32				dest_qpn;
299	u8				smac[6];
300	u16				vlan_id;
301	u16				port_id;
302	u16				udp_sport;
303	u8				nw_type;
304	struct bnxt_qplib_ah		ah;
305
306#define BTH_PSN_MASK			((1 << 24) - 1)
307	/* SQ */
308	struct bnxt_qplib_q		sq;
309	/* RQ */
310	struct bnxt_qplib_q		rq;
311	/* SRQ */
312	struct bnxt_qplib_srq		*srq;
313	/* CQ */
314	struct bnxt_qplib_cq		*scq;
315	struct bnxt_qplib_cq		*rcq;
316	/* IRRQ and ORRQ */
317	struct bnxt_qplib_hwq		irrq;
318	struct bnxt_qplib_hwq		orrq;
319	/* Header buffer for QP1 */
320	int				sq_hdr_buf_size;
321	int				rq_hdr_buf_size;
322/*
323 * Buffer space for ETH(14), IP or GRH(40), UDP header(8)
324 * and ib_bth + ib_deth (20).
325 * Max required is 82 when RoCE V2 is enabled
326 */
327#define BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2	86
328	/* Ethernet header	=  14 */
329	/* ib_grh		=  40 (provided by MAD) */
330	/* ib_bth + ib_deth	=  20 */
331	/* MAD			= 256 (provided by MAD) */
332	/* iCRC			=   4 */
333#define BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE	14
334#define BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2	512
335#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4	20
336#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6	40
337#define BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE	20
338	void				*sq_hdr_buf;
339	dma_addr_t			sq_hdr_buf_map;
340	void				*rq_hdr_buf;
341	dma_addr_t			rq_hdr_buf_map;
342	struct list_head		sq_flush;
343	struct list_head		rq_flush;
344	u32				msn;
345	u32				msn_tbl_sz;
346	bool				is_host_msn_tbl;
347	u8				tos_dscp;
348	u32				ugid_index;
349};
350
351#define BNXT_RE_MAX_MSG_SIZE	0x80000000
352#define BNXT_RE_INVAL_MSG_SIZE	0xFFFFFFFF
353
354#define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE	sizeof(struct cq_base)
355
356#define CQE_CNT_PER_PG		(PAGE_SIZE / BNXT_QPLIB_MAX_CQE_ENTRY_SIZE)
357#define CQE_MAX_IDX_PER_PG	(CQE_CNT_PER_PG - 1)
358#define CQE_PG(x)		(((x) & ~CQE_MAX_IDX_PER_PG) / CQE_CNT_PER_PG)
359#define CQE_IDX(x)		((x) & CQE_MAX_IDX_PER_PG)
360
361#define ROCE_CQE_CMP_V			0
362#define CQE_CMP_VALID(hdr, pass)			\
363	(!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) ==		\
364	   !((pass) & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))
365
366static inline u32 __bnxt_qplib_get_avail(struct bnxt_qplib_hwq *hwq)
367{
368	int cons, prod, avail;
369
370	cons = hwq->cons;
371	prod = hwq->prod;
372	avail = cons - prod;
373	if (cons <= prod)
374		avail += hwq->depth;
375	return avail;
376}
377
378static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *que,
379					 u8 slots)
380{
381	struct bnxt_qplib_hwq *hwq;
382	int avail;
383
384	hwq = &que->hwq;
385	/* False full is possible, retrying post-send makes sense */
386	avail = hwq->cons - hwq->prod;
387	if (hwq->cons <= hwq->prod)
388		avail += hwq->depth;
389	return avail <= slots;
390}
391
392/* CQ coalescing parameters */
393struct bnxt_qplib_cq_coal_param {
394	u16 buf_maxtime;
395	u8 normal_maxbuf;
396	u8 during_maxbuf;
397	u8 en_ring_idle_mode;
398	u8 enable;
399};
400
401#define BNXT_QPLIB_CQ_COAL_DEF_BUF_MAXTIME		0x1
402#define BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P7		0x8
403#define BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P7		0x8
404#define BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P5		0x1
405#define BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P5		0x1
406#define BNXT_QPLIB_CQ_COAL_DEF_EN_RING_IDLE_MODE	0x1
407#define BNXT_QPLIB_CQ_COAL_MAX_BUF_MAXTIME		0x1bf
408#define BNXT_QPLIB_CQ_COAL_MAX_NORMAL_MAXBUF		0x1f
409#define BNXT_QPLIB_CQ_COAL_MAX_DURING_MAXBUF		0x1f
410#define BNXT_QPLIB_CQ_COAL_MAX_EN_RING_IDLE_MODE	0x1
411
412struct bnxt_qplib_cqe {
413	u8				status;
414	u8				type;
415	u8				opcode;
416	u32				length;
417	u16				cfa_meta;
418	u64				wr_id;
419	union {
420		u32			immdata;
421		u32			invrkey;
422	};
423	u64				qp_handle;
424	u64				mr_handle;
425	u16				flags;
426	u8				smac[6];
427	u32				src_qp;
428	u16				raweth_qp1_flags;
429	u16				raweth_qp1_errors;
430	u16				raweth_qp1_cfa_code;
431	u32				raweth_qp1_flags2;
432	u32				raweth_qp1_metadata;
433	u8				raweth_qp1_payload_offset;
434	u16				pkey_index;
435};
436
437#define BNXT_QPLIB_QUEUE_START_PERIOD		0x01
438struct bnxt_qplib_cq {
439	struct bnxt_qplib_dpi		*dpi;
440	struct bnxt_qplib_db_info	dbinfo;
441	u32				max_wqe;
442	u32				id;
443	u16				count;
444	u16				period;
445	struct bnxt_qplib_hwq		hwq;
446	struct bnxt_qplib_hwq		resize_hwq;
447	u32				cnq_hw_ring_id;
448	struct bnxt_qplib_nq		*nq;
449	bool				resize_in_progress;
450	struct bnxt_qplib_sg_info	sg_info;
451	u64				cq_handle;
452	u8				toggle;
453
454#define CQ_RESIZE_WAIT_TIME_MS		500
455	unsigned long			flags;
456#define CQ_FLAGS_RESIZE_IN_PROG		1
457	wait_queue_head_t		waitq;
458	struct list_head		sqf_head, rqf_head;
459	atomic_t			arm_state;
460	spinlock_t			compl_lock; /* synch CQ handlers */
461/* Locking Notes:
462 * QP can move to error state from modify_qp, async error event or error
463 * CQE as part of poll_cq. When QP is moved to error state, it gets added
464 * to two flush lists, one each for SQ and RQ.
465 * Each flush list is protected by qplib_cq->flush_lock. Both scq and rcq
466 * flush_locks should be acquired when QP is moved to error. The control path
467 * operations(modify_qp and async error events) are synchronized with poll_cq
468 * using upper level CQ locks (bnxt_re_cq->cq_lock) of both SCQ and RCQ.
469 * The qplib_cq->flush_lock is required to synchronize two instances of poll_cq
470 * of the same QP while manipulating the flush list.
471 */
472	spinlock_t			flush_lock; /* QP flush management */
473	u16				cnq_events;
474	struct bnxt_qplib_cq_coal_param	*coalescing;
475};
476
477#define BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE	sizeof(struct xrrq_irrq)
478#define BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE	sizeof(struct xrrq_orrq)
479#define IRD_LIMIT_TO_IRRQ_SLOTS(x)	(2 * (x) + 2)
480#define IRRQ_SLOTS_TO_IRD_LIMIT(s)	(((s) >> 1) - 1)
481#define ORD_LIMIT_TO_ORRQ_SLOTS(x)	((x) + 1)
482#define ORRQ_SLOTS_TO_ORD_LIMIT(s)	((s) - 1)
483
484#define BNXT_QPLIB_MAX_NQE_ENTRY_SIZE	sizeof(struct nq_base)
485
486#define NQE_CNT_PER_PG		(PAGE_SIZE / BNXT_QPLIB_MAX_NQE_ENTRY_SIZE)
487#define NQE_MAX_IDX_PER_PG	(NQE_CNT_PER_PG - 1)
488#define NQE_PG(x)		(((x) & ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG)
489#define NQE_IDX(x)		((x) & NQE_MAX_IDX_PER_PG)
490
491#define NQE_CMP_VALID(hdr, pass)			\
492	(!!(le32_to_cpu((hdr)->info63_v[0]) & NQ_BASE_V) ==	\
493	   !((pass) & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))
494
495#define BNXT_QPLIB_NQE_MAX_CNT		(128 * 1024)
496
497#define NQ_CONS_PCI_BAR_REGION		2
498#define NQ_DB_KEY_CP			(0x2 << CMPL_DOORBELL_KEY_SFT)
499#define NQ_DB_IDX_VALID			CMPL_DOORBELL_IDX_VALID
500#define NQ_DB_IRQ_DIS			CMPL_DOORBELL_MASK
501#define NQ_DB_CP_FLAGS_REARM		(NQ_DB_KEY_CP |		\
502					 NQ_DB_IDX_VALID)
503#define NQ_DB_CP_FLAGS			(NQ_DB_KEY_CP    |	\
504					 NQ_DB_IDX_VALID |	\
505					 NQ_DB_IRQ_DIS)
506
507struct bnxt_qplib_nq_db {
508	struct bnxt_qplib_reg_desc	reg;
509	struct bnxt_qplib_db_info	dbinfo;
510};
511
512typedef int (*cqn_handler_t)(struct bnxt_qplib_nq *nq,
513		struct bnxt_qplib_cq *cq);
514typedef int (*srqn_handler_t)(struct bnxt_qplib_nq *nq,
515		struct bnxt_qplib_srq *srq, u8 event);
516
517struct bnxt_qplib_nq {
518	struct pci_dev			*pdev;
519	struct bnxt_qplib_res		*res;
520	char				*name;
521	struct bnxt_qplib_hwq		hwq;
522	struct bnxt_qplib_nq_db		nq_db;
523	u16				ring_id;
524	int				msix_vec;
525	cpumask_t			mask;
526	struct tasklet_struct		nq_tasklet;
527	bool				requested;
528	int				budget;
529	u32				load;
530
531	cqn_handler_t			cqn_handler;
532	srqn_handler_t			srqn_handler;
533	struct workqueue_struct		*cqn_wq;
534};
535
536struct bnxt_qplib_nq_work {
537	struct work_struct      work;
538	struct bnxt_qplib_nq    *nq;
539	struct bnxt_qplib_cq    *cq;
540};
541
542void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill);
543void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq);
544int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
545			    int msix_vector, bool need_init);
546int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
547			 int nq_idx, int msix_vector, int bar_reg_offset,
548			 cqn_handler_t cqn_handler,
549			 srqn_handler_t srq_handler);
550int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
551			  struct bnxt_qplib_srq *srq);
552int bnxt_qplib_query_srq(struct bnxt_qplib_res *res,
553			 struct bnxt_qplib_srq *srq);
554void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
555			    struct bnxt_qplib_srq *srq);
556int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,
557			     struct bnxt_qplib_swqe *wqe);
558int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
559int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
560int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
561int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
562int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
563void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp);
564void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
565			    struct bnxt_qplib_qp *qp);
566void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
567				struct bnxt_qplib_sge *sge);
568void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
569				struct bnxt_qplib_sge *sge);
570u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp);
571dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp,
572					    u32 index);
573void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp);
574int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
575			 struct bnxt_qplib_swqe *wqe);
576void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp);
577int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
578			 struct bnxt_qplib_swqe *wqe);
579int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
580int bnxt_qplib_resize_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq,
581			 int new_cqes);
582void bnxt_qplib_resize_cq_complete(struct bnxt_qplib_res *res,
583				   struct bnxt_qplib_cq *cq);
584int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
585int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
586		       int num, struct bnxt_qplib_qp **qp);
587bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq);
588void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
589void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
590int bnxt_qplib_alloc_nq(struct bnxt_qplib_res *res, struct bnxt_qplib_nq *nq);
591void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp);
592void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp,
593				 unsigned long *flags);
594void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
595				 unsigned long *flags);
596int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
597				  struct bnxt_qplib_cqe *cqe,
598				  int num_cqes);
599void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp);
600void bnxt_re_synchronize_nq(struct bnxt_qplib_nq *nq);
601
602static inline void *bnxt_qplib_get_swqe(struct bnxt_qplib_q *que, u32 *swq_idx)
603{
604	u32 idx;
605
606	idx = que->swq_start;
607	if (swq_idx)
608		*swq_idx = idx;
609	return &que->swq[idx];
610}
611
612static inline void bnxt_qplib_swq_mod_start(struct bnxt_qplib_q *que, u32 idx)
613{
614	que->swq_start = que->swq[idx].next_idx;
615}
616
617static inline u32 bnxt_qplib_get_depth(struct bnxt_qplib_q *que, u8 wqe_mode, bool is_sq)
618{
619	u32 slots;
620
621	/* Queue depth is the number of slots. */
622	slots = (que->wqe_size * que->max_wqe) / sizeof(struct sq_sge);
623	/* For variable WQE mode, need to align the slots to 256 */
624	if (wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE && is_sq)
625		slots = ALIGN(slots, BNXT_VAR_MAX_SLOT_ALIGN);
626	return slots;
627}
628
629static inline u32 bnxt_qplib_set_sq_size(struct bnxt_qplib_q *que, u8 wqe_mode)
630{
631	return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
632		que->max_wqe : bnxt_qplib_get_depth(que, wqe_mode, true);
633}
634
635static inline u32 bnxt_qplib_set_sq_max_slot(u8 wqe_mode)
636{
637	return (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
638		sizeof(struct sq_send) / sizeof(struct sq_sge) : 1;
639}
640
641static inline u32 bnxt_qplib_set_rq_max_slot(u32 wqe_size)
642{
643	return (wqe_size / sizeof(struct sq_sge));
644}
645
646static inline u16 __xlate_qfd(u16 delta, u16 wqe_bytes)
647{
648	/* For Cu/Wh delta = 128, stride = 16, wqe_bytes = 128
649	 * For Gen-p5 B/C mode delta = 0, stride = 16, wqe_bytes = 128.
650	 * For Gen-p5 delta = 0, stride = 16, 32 <= wqe_bytes <= 512.
651	 * when 8916 is disabled.
652	 */
653	return (delta * wqe_bytes) / sizeof(struct sq_sge);
654}
655
656static inline u16 bnxt_qplib_calc_ilsize(struct bnxt_qplib_swqe *wqe, u16 max)
657{
658	u16 size = 0;
659	int indx;
660
661	for (indx = 0; indx < wqe->num_sge; indx++)
662		size += wqe->sg_list[indx].size;
663	if (size > max)
664		size = max;
665
666	return size;
667}
668
669/* MSN table update inlin */
670static inline __le64 bnxt_re_update_msn_tbl(u32 st_idx, u32 npsn, u32 start_psn)
671{
672	return cpu_to_le64((((u64)(st_idx) << SQ_MSN_SEARCH_START_IDX_SFT) &
673		SQ_MSN_SEARCH_START_IDX_MASK) |
674		(((u64)(npsn) << SQ_MSN_SEARCH_NEXT_PSN_SFT) &
675		SQ_MSN_SEARCH_NEXT_PSN_MASK) |
676		(((start_psn) << SQ_MSN_SEARCH_START_PSN_SFT) &
677		SQ_MSN_SEARCH_START_PSN_MASK));
678}
679
680static inline bool __is_var_wqe(struct bnxt_qplib_qp *qp)
681{
682	return (qp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE);
683}
684
685static inline bool __is_err_cqe_for_var_wqe(struct bnxt_qplib_qp *qp, u8 status)
686{
687	return (status != CQ_REQ_STATUS_OK) && __is_var_wqe(qp);
688}
689#endif /* __BNXT_QPLIB_FP_H__ */