bnxt_re.h

  1/*
  2 * Broadcom NetXtreme-E RoCE driver.
  3 *
  4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
  5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
  6 *
  7 * This software is available to you under a choice of one of two
  8 * licenses.  You may choose to be licensed under the terms of the GNU
  9 * General Public License (GPL) Version 2, available from the file
 10 * COPYING in the main directory of this source tree, or the
 11 * BSD license below:
 12 *
 13 * Redistribution and use in source and binary forms, with or without
 14 * modification, are permitted provided that the following conditions
 15 * are met:
 16 *
 17 * 1. Redistributions of source code must retain the above copyright
 18 *    notice, this list of conditions and the following disclaimer.
 19 * 2. Redistributions in binary form must reproduce the above copyright
 20 *    notice, this list of conditions and the following disclaimer in
 21 *    the documentation and/or other materials provided with the
 22 *    distribution.
 23 *
 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 35 *
 36 * Description: Slow Path Operators (header)
 37 *
 38 */
 39
 40#ifndef __BNXT_RE_H__
 41#define __BNXT_RE_H__
 42#include <rdma/uverbs_ioctl.h>
 43#include "hw_counters.h"
 44#include <linux/hashtable.h>
 45#define ROCE_DRV_MODULE_NAME		"bnxt_re"
 46
 47#define BNXT_RE_DESC	"Broadcom NetXtreme-C/E RoCE Driver"
 48
 49#define BNXT_RE_PAGE_SHIFT_1G		(30)
 50#define BNXT_RE_PAGE_SIZE_SUPPORTED	0x7FFFF000 /* 4kb - 1G */
 51
 52#define BNXT_RE_MAX_MR_SIZE_LOW		BIT_ULL(BNXT_RE_PAGE_SHIFT_1G)
 53#define BNXT_RE_MAX_MR_SIZE_HIGH	BIT_ULL(39)
 54#define BNXT_RE_MAX_MR_SIZE		BNXT_RE_MAX_MR_SIZE_HIGH
 55
 56
 57/* Number of MRs to reserve for PF, leaving remainder for VFs */
 58#define BNXT_RE_RESVD_MR_FOR_PF         (32 * 1024)
 59#define BNXT_RE_MAX_GID_PER_VF          128
 60
 61/*
 62 * Percentage of resources of each type reserved for PF.
 63 * Remaining resources are divided equally among VFs.
 64 * [0, 100]
 65 */
 66#define BNXT_RE_PCT_RSVD_FOR_PF         50
 67
 68#define BNXT_RE_UD_QP_HW_STALL		0x400000
 69
 70#define BNXT_RE_RQ_WQE_THRESHOLD	32
 71
 72/*
 73 * Setting the default ack delay value to 16, which means
 74 * the default timeout is approx. 260ms(4 usec * 2 ^(timeout))
 75 */
 76
 77#define BNXT_RE_DEFAULT_ACK_DELAY	16
 78
 79struct bnxt_re_ring_attr {
 80	dma_addr_t	*dma_arr;
 81	int		pages;
 82	int		type;
 83	u32		depth;
 84	u32		lrid; /* Logical ring id */
 85	u8		mode;
 86};
 87
 88/*
 89 * Data structure and defines to handle
 90 * recovery
 91 */
 92#define BNXT_RE_PRE_RECOVERY_REMOVE 0x1
 93#define BNXT_RE_COMPLETE_REMOVE 0x2
 94#define BNXT_RE_POST_RECOVERY_INIT 0x4
 95#define BNXT_RE_COMPLETE_INIT 0x8
 96
 97struct bnxt_re_sqp_entries {
 98	struct bnxt_qplib_sge sge;
 99	u64 wrid;
100	/* For storing the actual qp1 cqe */
101	struct bnxt_qplib_cqe cqe;
102	struct bnxt_re_qp *qp1_qp;
103};
104
105#define BNXT_RE_MAX_GSI_SQP_ENTRIES	1024
106struct bnxt_re_gsi_context {
107	struct	bnxt_re_qp *gsi_qp;
108	struct	bnxt_re_qp *gsi_sqp;
109	struct	bnxt_re_ah *gsi_sah;
110	struct	bnxt_re_sqp_entries *sqp_tbl;
111};
112
113struct bnxt_re_en_dev_info {
114	struct bnxt_en_dev *en_dev;
115	struct bnxt_re_dev *rdev;
116};
117
118#define BNXT_RE_AEQ_IDX			0
119#define BNXT_RE_NQ_IDX			1
120#define BNXT_RE_GEN_P5_MAX_VF		64
121
122struct bnxt_re_pacing {
123	u64 dbr_db_fifo_reg_off;
124	void *dbr_page;
125	u64 dbr_bar_addr;
126	u32 pacing_algo_th;
127	u32 do_pacing_save;
128	u32 dbq_pacing_time; /* ms */
129	u32 dbr_def_do_pacing;
130	bool dbr_pacing;
131	struct mutex dbq_lock; /* synchronize db pacing algo */
132};
133
134#define BNXT_RE_MAX_DBR_DO_PACING 0xFFFF
135#define BNXT_RE_DBR_PACING_TIME 5 /* ms */
136#define BNXT_RE_PACING_ALGO_THRESHOLD 250 /* Entries in DB FIFO */
137#define BNXT_RE_PACING_ALARM_TH_MULTIPLE 2 /* Multiple of pacing algo threshold */
138/* Default do_pacing value when there is no congestion */
139#define BNXT_RE_DBR_DO_PACING_NO_CONGESTION 0x7F /* 1 in 512 probability */
140
141#define BNXT_RE_MAX_FIFO_DEPTH_P5       0x2c00
142#define BNXT_RE_MAX_FIFO_DEPTH_P7       0x8000
143
144#define BNXT_RE_MAX_FIFO_DEPTH(ctx)	\
145	(bnxt_qplib_is_chip_gen_p7((ctx)) ? \
146	 BNXT_RE_MAX_FIFO_DEPTH_P7 :\
147	 BNXT_RE_MAX_FIFO_DEPTH_P5)
148
149#define BNXT_RE_GRC_FIFO_REG_BASE 0x2000
150
151#define BNXT_RE_MIN_MSIX		2
152#define BNXT_RE_MAX_MSIX		BNXT_MAX_ROCE_MSIX
153struct bnxt_re_nq_record {
154	struct bnxt_msix_entry	msix_entries[BNXT_RE_MAX_MSIX];
155	struct bnxt_qplib_nq	nq[BNXT_RE_MAX_MSIX];
156	int			num_msix;
157	/* serialize NQ access */
158	struct mutex		load_lock;
159};
160
161#define MAX_CQ_HASH_BITS		(16)
162#define MAX_SRQ_HASH_BITS		(16)
163
164static inline bool bnxt_re_chip_gen_p7(u16 chip_num)
165{
166	return (chip_num == CHIP_NUM_58818 ||
167		chip_num == CHIP_NUM_57608);
168}
169
170struct bnxt_re_dev {
171	struct ib_device		ibdev;
172	struct list_head		list;
173	unsigned long			flags;
174#define BNXT_RE_FLAG_NETDEV_REGISTERED		0
175#define BNXT_RE_FLAG_STATS_CTX3_ALLOC		1
176#define BNXT_RE_FLAG_HAVE_L2_REF		3
177#define BNXT_RE_FLAG_RCFW_CHANNEL_EN		4
178#define BNXT_RE_FLAG_RESOURCES_ALLOCATED	7
179#define BNXT_RE_FLAG_RESOURCES_INITIALIZED	8
180#define BNXT_RE_FLAG_ERR_DEVICE_DETACHED       17
181#define BNXT_RE_FLAG_ISSUE_ROCE_STATS          29
182	struct net_device		*netdev;
183	struct auxiliary_device         *adev;
184	unsigned int			version, major, minor;
185	struct bnxt_qplib_chip_ctx	*chip_ctx;
186	struct bnxt_en_dev		*en_dev;
187
188	int				id;
189
190	/* RCFW Channel */
191	struct bnxt_qplib_rcfw		rcfw;
192
193	/* NQ record */
194	struct bnxt_re_nq_record	*nqr;
195
196	/* Device Resources */
197	struct bnxt_qplib_dev_attr	*dev_attr;
198	struct bnxt_qplib_ctx		qplib_ctx;
199	struct bnxt_qplib_res		qplib_res;
200	struct bnxt_qplib_dpi		dpi_privileged;
201	struct bnxt_qplib_cq_coal_param	cq_coalescing;
202
203	struct mutex			qp_lock;	/* protect qp list */
204	struct list_head		qp_list;
205
206	/* Max of 2 lossless traffic class supported per port */
207	u16				cosq[2];
208
209	/* QP for handling QP1 packets */
210	struct bnxt_re_gsi_context	gsi_ctx;
211	struct bnxt_re_stats		stats;
212	atomic_t nq_alloc_cnt;
213	u32 is_virtfn;
214	u32 num_vfs;
215	struct bnxt_re_pacing pacing;
216	struct work_struct dbq_fifo_check_work;
217	struct delayed_work dbq_pacing_work;
218	DECLARE_HASHTABLE(cq_hash, MAX_CQ_HASH_BITS);
219	DECLARE_HASHTABLE(srq_hash, MAX_SRQ_HASH_BITS);
220	struct dentry			*dbg_root;
221	struct dentry			*qp_debugfs;
222	unsigned long			event_bitmap;
223	struct bnxt_qplib_cc_param	cc_param;
224	struct workqueue_struct		*dcb_wq;
225	struct dentry                   *cc_config;
226	struct bnxt_re_dbg_cc_config_params *cc_config_params;
227	struct dentry			*cq_coal_cfg;
228	struct bnxt_re_dbg_cq_coal_params *cq_coal_cfg_params;
229#define BNXT_VPD_FLD_LEN		32
230	char board_partno[BNXT_VPD_FLD_LEN];
231	/* RoCE mirror */
232	u16 mirror_vnic_id;
233	union ib_gid ugid;
234	u32 ugid_index;
235	u8 sniffer_flow_created : 1;
236};
237
238#define to_bnxt_re_dev(ptr, member)	\
239	container_of((ptr), struct bnxt_re_dev, member)
240
241#define BNXT_RE_ROCE_V1_PACKET		0
242#define BNXT_RE_ROCEV2_IPV4_PACKET	2
243#define BNXT_RE_ROCEV2_IPV6_PACKET	3
244
245#define BNXT_RE_CHECK_RC(x) ((x) && ((x) != -ETIMEDOUT))
246void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev);
247
248int bnxt_re_assign_pma_port_counters(struct bnxt_re_dev *rdev, struct ib_mad *out_mad);
249int bnxt_re_assign_pma_port_ext_counters(struct bnxt_re_dev *rdev,
250					 struct ib_mad *out_mad);
251
252void bnxt_re_hwrm_free_vnic(struct bnxt_re_dev *rdev);
253int bnxt_re_hwrm_alloc_vnic(struct bnxt_re_dev *rdev);
254int bnxt_re_hwrm_cfg_vnic(struct bnxt_re_dev *rdev, u32 qp_id);
255
256static inline struct device *rdev_to_dev(struct bnxt_re_dev *rdev)
257{
258	if (rdev)
259		return  &rdev->ibdev.dev;
260	return NULL;
261}
262
263extern const struct uapi_definition bnxt_re_uapi_defs[];
264
265static inline void bnxt_re_set_pacing_dev_state(struct bnxt_re_dev *rdev)
266{
267	rdev->qplib_res.pacing_data->dev_err_state =
268		test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
269}
270
271static inline int bnxt_re_read_context_allowed(struct bnxt_re_dev *rdev)
272{
273	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ||
274	    rdev->rcfw.res->cctx->hwrm_intf_ver < HWRM_VERSION_READ_CTX)
275		return -EOPNOTSUPP;
276	return 0;
277}
278
279#define BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5	1088
280#define BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5		128
281#define BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5	128
282#define BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5	192
283
284#define BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7	1088
285#define BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7		192
286#define BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7	192
287#define BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7	192
288
289#define BNXT_RE_HWRM_CMD_TIMEOUT(rdev)		\
290		((rdev)->chip_ctx->hwrm_cmd_max_timeout * 1000)
291
292#endif