stm32-timer-trigger.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) STMicroelectronics 2016
  4 *
  5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
  6 *
  7 */
  8
  9#include <linux/export.h>
 10#include <linux/iio/iio.h>
 11#include <linux/iio/sysfs.h>
 12#include <linux/iio/timer/stm32-timer-trigger.h>
 13#include <linux/iio/trigger.h>
 14#include <linux/mfd/stm32-timers.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/module.h>
 17#include <linux/platform_device.h>
 18#include <linux/property.h>
 19
 20#define MAX_TRIGGERS 7
 21#define MAX_VALIDS 5
 22
 23/* List the triggers created by each timer */
 24static const void *triggers_table[][MAX_TRIGGERS] = {
 25	{ TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
 26	{ TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
 27	{ TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
 28	{ TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
 29	{ TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
 30	{ TIM6_TRGO,},
 31	{ TIM7_TRGO,},
 32	{ TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
 33	{ TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
 34	{ TIM10_OC1,},
 35	{ TIM11_OC1,},
 36	{ TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
 37	{ TIM13_OC1,},
 38	{ TIM14_OC1,},
 39	{ TIM15_TRGO,},
 40	{ TIM16_OC1,},
 41	{ TIM17_OC1,},
 42	{ }, /* timer 18 */
 43	{ }, /* timer 19 */
 44	{ TIM20_TRGO, TIM20_TRGO2, TIM20_OC1, TIM20_OC2, TIM20_OC3, },
 45};
 46
 47/* List the triggers accepted by each timer */
 48static const void *valids_table[][MAX_VALIDS] = {
 49	{ TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
 50	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
 51	{ TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
 52	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
 53	{ TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
 54	{ }, /* timer 6 */
 55	{ }, /* timer 7 */
 56	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
 57	{ TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
 58	{ }, /* timer 10 */
 59	{ }, /* timer 11 */
 60	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
 61};
 62
 63static const void *stm32h7_valids_table[][MAX_VALIDS] = {
 64	{ TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
 65	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
 66	{ TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
 67	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
 68	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
 69	{ }, /* timer 6 */
 70	{ }, /* timer 7 */
 71	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
 72	{ }, /* timer 9 */
 73	{ }, /* timer 10 */
 74	{ }, /* timer 11 */
 75	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
 76	{ }, /* timer 13 */
 77	{ }, /* timer 14 */
 78	{ TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
 79	{ }, /* timer 16 */
 80	{ }, /* timer 17 */
 81};
 82
 83struct stm32_timer_trigger_regs {
 84	u32 cr1;
 85	u32 cr2;
 86	u32 psc;
 87	u32 arr;
 88	u32 cnt;
 89	u32 smcr;
 90};
 91
 92struct stm32_timer_trigger {
 93	struct device *dev;
 94	struct regmap *regmap;
 95	struct clk *clk;
 96	bool enabled;
 97	u32 max_arr;
 98	const void *triggers;
 99	const void *valids;
100	bool has_trgo2;
101	struct mutex lock; /* concurrent sysfs configuration */
102	struct list_head tr_list;
103	struct stm32_timer_trigger_regs bak;
104};
105
106struct stm32_timer_trigger_cfg {
107	const void *(*valids_table)[MAX_VALIDS];
108	const unsigned int num_valids_table;
109};
110
111static bool stm32_timer_is_trgo2_name(const char *name)
112{
113	return !!strstr(name, "trgo2");
114}
115
116static bool stm32_timer_is_trgo_name(const char *name)
117{
118	return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
119}
120
121static int stm32_timer_start(struct stm32_timer_trigger *priv,
122			     struct iio_trigger *trig,
123			     unsigned int frequency)
124{
125	unsigned long long prd, div;
126	int prescaler = 0, ret;
127	u32 ccer;
128
129	/* Period and prescaler values depends of clock rate */
130	div = (unsigned long long)clk_get_rate(priv->clk);
131
132	do_div(div, frequency);
133
134	prd = div;
135
136	/*
137	 * Increase prescaler value until we get a result that fit
138	 * with auto reload register maximum value.
139	 */
140	while (div > priv->max_arr) {
141		prescaler++;
142		div = prd;
143		do_div(div, (prescaler + 1));
144	}
145	prd = div;
146
147	if (prescaler > MAX_TIM_PSC) {
148		dev_err(priv->dev, "prescaler exceeds the maximum value\n");
149		return -EINVAL;
150	}
151
152	/* Check if nobody else use the timer */
153	regmap_read(priv->regmap, TIM_CCER, &ccer);
154	if (ccer & TIM_CCER_CCXE)
155		return -EBUSY;
156
157	guard(mutex)(&priv->lock);
158	if (!priv->enabled) {
159		priv->enabled = true;
160		ret = clk_enable(priv->clk);
161		if (ret)
162			return ret;
163	}
164
165	regmap_write(priv->regmap, TIM_PSC, prescaler);
166	regmap_write(priv->regmap, TIM_ARR, prd - 1);
167	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
168
169	/* Force master mode to update mode */
170	if (stm32_timer_is_trgo2_name(trig->name))
171		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
172				   0x2 << TIM_CR2_MMS2_SHIFT);
173	else
174		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
175				   0x2 << TIM_CR2_MMS_SHIFT);
176
177	/* Make sure that registers are updated */
178	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
179
180	/* Enable controller */
181	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
182
183	return 0;
184}
185
186static void stm32_timer_stop(struct stm32_timer_trigger *priv,
187			     struct iio_trigger *trig)
188{
189	u32 ccer;
190
191	regmap_read(priv->regmap, TIM_CCER, &ccer);
192	if (ccer & TIM_CCER_CCXE)
193		return;
194
195	mutex_lock(&priv->lock);
196	/* Stop timer */
197	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
198	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
199	regmap_write(priv->regmap, TIM_PSC, 0);
200	regmap_write(priv->regmap, TIM_ARR, 0);
201
202	/* Force disable master mode */
203	if (stm32_timer_is_trgo2_name(trig->name))
204		regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
205	else
206		regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);
207
208	/* Make sure that registers are updated */
209	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
210
211	if (priv->enabled) {
212		priv->enabled = false;
213		clk_disable(priv->clk);
214	}
215	mutex_unlock(&priv->lock);
216}
217
218static ssize_t stm32_tt_store_frequency(struct device *dev,
219					struct device_attribute *attr,
220					const char *buf, size_t len)
221{
222	struct iio_trigger *trig = to_iio_trigger(dev);
223	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
224	unsigned int freq;
225	int ret;
226
227	ret = kstrtouint(buf, 10, &freq);
228	if (ret)
229		return ret;
230
231	if (freq == 0) {
232		stm32_timer_stop(priv, trig);
233	} else {
234		ret = stm32_timer_start(priv, trig, freq);
235		if (ret)
236			return ret;
237	}
238
239	return len;
240}
241
242static ssize_t stm32_tt_read_frequency(struct device *dev,
243				       struct device_attribute *attr, char *buf)
244{
245	struct iio_trigger *trig = to_iio_trigger(dev);
246	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
247	u32 psc, arr, cr1;
248	unsigned long long freq = 0;
249
250	regmap_read(priv->regmap, TIM_CR1, &cr1);
251	regmap_read(priv->regmap, TIM_PSC, &psc);
252	regmap_read(priv->regmap, TIM_ARR, &arr);
253
254	if (cr1 & TIM_CR1_CEN) {
255		freq = (unsigned long long)clk_get_rate(priv->clk);
256		do_div(freq, psc + 1);
257		do_div(freq, arr + 1);
258	}
259
260	return sprintf(buf, "%d\n", (unsigned int)freq);
261}
262
263static IIO_DEV_ATTR_SAMP_FREQ(0660,
264			      stm32_tt_read_frequency,
265			      stm32_tt_store_frequency);
266
267#define MASTER_MODE_MAX		7
268#define MASTER_MODE2_MAX	15
269
270static char *master_mode_table[] = {
271	"reset",
272	"enable",
273	"update",
274	"compare_pulse",
275	"OC1REF",
276	"OC2REF",
277	"OC3REF",
278	"OC4REF",
279	/* Master mode selection 2 only */
280	"OC5REF",
281	"OC6REF",
282	"compare_pulse_OC4REF",
283	"compare_pulse_OC6REF",
284	"compare_pulse_OC4REF_r_or_OC6REF_r",
285	"compare_pulse_OC4REF_r_or_OC6REF_f",
286	"compare_pulse_OC5REF_r_or_OC6REF_r",
287	"compare_pulse_OC5REF_r_or_OC6REF_f",
288};
289
290static ssize_t stm32_tt_show_master_mode(struct device *dev,
291					 struct device_attribute *attr,
292					 char *buf)
293{
294	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
295	struct iio_trigger *trig = to_iio_trigger(dev);
296	u32 cr2;
297
298	regmap_read(priv->regmap, TIM_CR2, &cr2);
299
300	if (stm32_timer_is_trgo2_name(trig->name))
301		cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
302	else
303		cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
304
305	return sysfs_emit(buf, "%s\n", master_mode_table[cr2]);
306}
307
308static ssize_t stm32_tt_store_master_mode(struct device *dev,
309					  struct device_attribute *attr,
310					  const char *buf, size_t len)
311{
312	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
313	struct iio_trigger *trig = to_iio_trigger(dev);
314	u32 mask, shift, master_mode_max;
315	int i, ret;
316
317	if (stm32_timer_is_trgo2_name(trig->name)) {
318		mask = TIM_CR2_MMS2;
319		shift = TIM_CR2_MMS2_SHIFT;
320		master_mode_max = MASTER_MODE2_MAX;
321	} else {
322		mask = TIM_CR2_MMS;
323		shift = TIM_CR2_MMS_SHIFT;
324		master_mode_max = MASTER_MODE_MAX;
325	}
326
327	for (i = 0; i <= master_mode_max; i++) {
328		if (!strncmp(master_mode_table[i], buf,
329			     strlen(master_mode_table[i]))) {
330			guard(mutex)(&priv->lock);
331			if (!priv->enabled) {
332				/* Clock should be enabled first */
333				priv->enabled = true;
334				ret = clk_enable(priv->clk);
335				if (ret)
336					return ret;
337			}
338			regmap_update_bits(priv->regmap, TIM_CR2, mask,
339					   i << shift);
340			return len;
341		}
342	}
343
344	return -EINVAL;
345}
346
347static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
348					       struct device_attribute *attr,
349					       char *buf)
350{
351	struct iio_trigger *trig = to_iio_trigger(dev);
352	unsigned int i, master_mode_max;
353	size_t len = 0;
354
355	if (stm32_timer_is_trgo2_name(trig->name))
356		master_mode_max = MASTER_MODE2_MAX;
357	else
358		master_mode_max = MASTER_MODE_MAX;
359
360	for (i = 0; i <= master_mode_max; i++)
361		len += scnprintf(buf + len, PAGE_SIZE - len,
362			"%s ", master_mode_table[i]);
363
364	/* replace trailing space by newline */
365	buf[len - 1] = '\n';
366
367	return len;
368}
369
370static IIO_DEVICE_ATTR(master_mode_available, 0444,
371		       stm32_tt_show_master_mode_avail, NULL, 0);
372
373static IIO_DEVICE_ATTR(master_mode, 0660,
374		       stm32_tt_show_master_mode,
375		       stm32_tt_store_master_mode,
376		       0);
377
378static struct attribute *stm32_trigger_attrs[] = {
379	&iio_dev_attr_sampling_frequency.dev_attr.attr,
380	&iio_dev_attr_master_mode.dev_attr.attr,
381	&iio_dev_attr_master_mode_available.dev_attr.attr,
382	NULL,
383};
384
385static const struct attribute_group stm32_trigger_attr_group = {
386	.attrs = stm32_trigger_attrs,
387};
388
389static const struct attribute_group *stm32_trigger_attr_groups[] = {
390	&stm32_trigger_attr_group,
391	NULL,
392};
393
394static const struct iio_trigger_ops timer_trigger_ops = {
395};
396
397static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
398{
399	struct iio_trigger *tr;
400
401	list_for_each_entry(tr, &priv->tr_list, alloc_list)
402		iio_trigger_unregister(tr);
403}
404
405static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
406{
407	int ret;
408	const char * const *cur = priv->triggers;
409
410	INIT_LIST_HEAD(&priv->tr_list);
411
412	while (cur && *cur) {
413		struct iio_trigger *trig;
414		bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
415		bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
416
417		if (cur_is_trgo2 && !priv->has_trgo2) {
418			cur++;
419			continue;
420		}
421
422		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
423		if  (!trig)
424			return -ENOMEM;
425
426		trig->dev.parent = priv->dev->parent;
427		trig->ops = &timer_trigger_ops;
428
429		/*
430		 * sampling frequency and master mode attributes
431		 * should only be available on trgo/trgo2 triggers
432		 */
433		if (cur_is_trgo || cur_is_trgo2)
434			trig->dev.groups = stm32_trigger_attr_groups;
435
436		iio_trigger_set_drvdata(trig, priv);
437
438		ret = iio_trigger_register(trig);
439		if (ret) {
440			stm32_unregister_iio_triggers(priv);
441			return ret;
442		}
443
444		list_add_tail(&trig->alloc_list, &priv->tr_list);
445		cur++;
446	}
447
448	return 0;
449}
450
451static int stm32_counter_read_raw(struct iio_dev *indio_dev,
452				  struct iio_chan_spec const *chan,
453				  int *val, int *val2, long mask)
454{
455	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
456	u32 dat;
457
458	switch (mask) {
459	case IIO_CHAN_INFO_RAW:
460		regmap_read(priv->regmap, TIM_CNT, &dat);
461		*val = dat;
462		return IIO_VAL_INT;
463
464	case IIO_CHAN_INFO_ENABLE:
465		regmap_read(priv->regmap, TIM_CR1, &dat);
466		*val = (dat & TIM_CR1_CEN) ? 1 : 0;
467		return IIO_VAL_INT;
468
469	case IIO_CHAN_INFO_SCALE:
470		regmap_read(priv->regmap, TIM_SMCR, &dat);
471		dat &= TIM_SMCR_SMS;
472
473		*val = 1;
474		*val2 = 0;
475
476		/* in quadrature case scale = 0.25 */
477		if (dat == 3)
478			*val2 = 2;
479
480		return IIO_VAL_FRACTIONAL_LOG2;
481	}
482
483	return -EINVAL;
484}
485
486static int stm32_counter_write_raw(struct iio_dev *indio_dev,
487				   struct iio_chan_spec const *chan,
488				   int val, int val2, long mask)
489{
490	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
491	int ret;
492
493	switch (mask) {
494	case IIO_CHAN_INFO_RAW:
495		return regmap_write(priv->regmap, TIM_CNT, val);
496
497	case IIO_CHAN_INFO_SCALE:
498		/* fixed scale */
499		return -EINVAL;
500
501	case IIO_CHAN_INFO_ENABLE: {
502		guard(mutex)(&priv->lock);
503		if (val) {
504			if (!priv->enabled) {
505				priv->enabled = true;
506				ret = clk_enable(priv->clk);
507				if (ret)
508					return ret;
509			}
510			regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
511		} else {
512			regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
513			if (priv->enabled) {
514				priv->enabled = false;
515				clk_disable(priv->clk);
516			}
517		}
518
519		return 0;
520	}
521	default:
522		return -EINVAL;
523	}
524}
525
526static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
527					  struct iio_trigger *trig)
528{
529	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
530	const char * const *cur = priv->valids;
531	unsigned int i = 0;
532
533	if (!is_stm32_timer_trigger(trig))
534		return -EINVAL;
535
536	while (cur && *cur) {
537		if (!strncmp(trig->name, *cur, strlen(trig->name))) {
538			regmap_update_bits(priv->regmap,
539					   TIM_SMCR, TIM_SMCR_TS,
540					   i << TIM_SMCR_TS_SHIFT);
541			return 0;
542		}
543		cur++;
544		i++;
545	}
546
547	return -EINVAL;
548}
549
550static const struct iio_info stm32_trigger_info = {
551	.validate_trigger = stm32_counter_validate_trigger,
552	.read_raw = stm32_counter_read_raw,
553	.write_raw = stm32_counter_write_raw
554};
555
556static const char *const stm32_trigger_modes[] = {
557	"trigger",
558};
559
560static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
561				  const struct iio_chan_spec *chan,
562				  unsigned int mode)
563{
564	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
565
566	regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);
567
568	return 0;
569}
570
571static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
572				  const struct iio_chan_spec *chan)
573{
574	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
575	u32 smcr;
576
577	regmap_read(priv->regmap, TIM_SMCR, &smcr);
578
579	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
580}
581
582static const struct iio_enum stm32_trigger_mode_enum = {
583	.items = stm32_trigger_modes,
584	.num_items = ARRAY_SIZE(stm32_trigger_modes),
585	.set = stm32_set_trigger_mode,
586	.get = stm32_get_trigger_mode
587};
588
589static const char *const stm32_enable_modes[] = {
590	"always",
591	"gated",
592	"triggered",
593};
594
595static int stm32_enable_mode2sms(int mode)
596{
597	switch (mode) {
598	case 0:
599		return 0;
600	case 1:
601		return 5;
602	case 2:
603		return 6;
604	}
605
606	return -EINVAL;
607}
608
609static int stm32_set_enable_mode(struct iio_dev *indio_dev,
610				 const struct iio_chan_spec *chan,
611				 unsigned int mode)
612{
613	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
614	int sms = stm32_enable_mode2sms(mode);
615	int ret;
616
617	if (sms < 0)
618		return sms;
619	/*
620	 * Triggered mode sets CEN bit automatically by hardware. So, first
621	 * enable counter clock, so it can use it. Keeps it in sync with CEN.
622	 */
623	scoped_guard(mutex, &priv->lock) {
624		if (sms == 6 && !priv->enabled) {
625			ret = clk_enable(priv->clk);
626			if (ret)
627				return ret;
628
629			priv->enabled = true;
630		}
631	}
632
633	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
634
635	return 0;
636}
637
638static int stm32_sms2enable_mode(int mode)
639{
640	switch (mode) {
641	case 0:
642		return 0;
643	case 5:
644		return 1;
645	case 6:
646		return 2;
647	}
648
649	return -EINVAL;
650}
651
652static int stm32_get_enable_mode(struct iio_dev *indio_dev,
653				 const struct iio_chan_spec *chan)
654{
655	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
656	u32 smcr;
657
658	regmap_read(priv->regmap, TIM_SMCR, &smcr);
659	smcr &= TIM_SMCR_SMS;
660
661	return stm32_sms2enable_mode(smcr);
662}
663
664static const struct iio_enum stm32_enable_mode_enum = {
665	.items = stm32_enable_modes,
666	.num_items = ARRAY_SIZE(stm32_enable_modes),
667	.set = stm32_set_enable_mode,
668	.get = stm32_get_enable_mode
669};
670
671static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
672				      uintptr_t private,
673				      const struct iio_chan_spec *chan,
674				      char *buf)
675{
676	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
677	u32 arr;
678
679	regmap_read(priv->regmap, TIM_ARR, &arr);
680
681	return snprintf(buf, PAGE_SIZE, "%u\n", arr);
682}
683
684static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
685				      uintptr_t private,
686				      const struct iio_chan_spec *chan,
687				      const char *buf, size_t len)
688{
689	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
690	unsigned int preset;
691	int ret;
692
693	ret = kstrtouint(buf, 0, &preset);
694	if (ret)
695		return ret;
696
697	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
698	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
699	regmap_write(priv->regmap, TIM_ARR, preset);
700
701	return len;
702}
703
704static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
705	{
706		.name = "preset",
707		.shared = IIO_SEPARATE,
708		.read = stm32_count_get_preset,
709		.write = stm32_count_set_preset
710	},
711	IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
712	IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum),
713	IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
714	IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum),
715	{ }
716};
717
718static const struct iio_chan_spec stm32_trigger_channel = {
719	.type = IIO_COUNT,
720	.channel = 0,
721	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
722			      BIT(IIO_CHAN_INFO_ENABLE) |
723			      BIT(IIO_CHAN_INFO_SCALE),
724	.ext_info = stm32_trigger_count_info,
725	.indexed = 1
726};
727
728static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
729{
730	struct iio_dev *indio_dev;
731	int ret;
732
733	indio_dev = devm_iio_device_alloc(dev,
734					  sizeof(struct stm32_timer_trigger));
735	if (!indio_dev)
736		return NULL;
737
738	indio_dev->name = dev_name(dev);
739	indio_dev->info = &stm32_trigger_info;
740	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
741	indio_dev->num_channels = 1;
742	indio_dev->channels = &stm32_trigger_channel;
743
744	ret = devm_iio_device_register(dev, indio_dev);
745	if (ret)
746		return NULL;
747
748	return iio_priv(indio_dev);
749}
750
751/**
752 * is_stm32_timer_trigger
753 * @trig: trigger to be checked
754 *
755 * return true if the trigger is a valid stm32 iio timer trigger
756 * either return false
757 */
758bool is_stm32_timer_trigger(struct iio_trigger *trig)
759{
760	return (trig->ops == &timer_trigger_ops);
761}
762EXPORT_SYMBOL(is_stm32_timer_trigger);
763
764static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
765{
766	u32 val;
767
768	/*
769	 * Master mode selection 2 bits can only be written and read back when
770	 * timer supports it.
771	 */
772	regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
773	regmap_read(priv->regmap, TIM_CR2, &val);
774	regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
775	priv->has_trgo2 = !!val;
776}
777
778static int stm32_timer_trigger_probe(struct platform_device *pdev)
779{
780	struct device *dev = &pdev->dev;
781	struct stm32_timer_trigger *priv;
782	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
783	const struct stm32_timer_trigger_cfg *cfg;
784	unsigned int index;
785	int ret;
786
787	ret = device_property_read_u32(dev, "reg", &index);
788	if (ret)
789		return ret;
790
791	cfg = device_get_match_data(dev);
792
793	if (index >= ARRAY_SIZE(triggers_table) ||
794	    index >= cfg->num_valids_table)
795		return -EINVAL;
796
797	/* Create an IIO device only if we have triggers to be validated */
798	if (cfg->valids_table && *cfg->valids_table[index])
799		priv = stm32_setup_counter_device(dev);
800	else
801		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
802
803	if (!priv)
804		return -ENOMEM;
805
806	priv->dev = dev;
807	priv->regmap = ddata->regmap;
808	priv->clk = ddata->clk;
809	priv->max_arr = ddata->max_arr;
810	priv->triggers = triggers_table[index];
811	if (cfg->valids_table && *cfg->valids_table[index])
812		priv->valids = cfg->valids_table[index];
813	stm32_timer_detect_trgo2(priv);
814	mutex_init(&priv->lock);
815
816	ret = stm32_register_iio_triggers(priv);
817	if (ret)
818		return ret;
819
820	platform_set_drvdata(pdev, priv);
821
822	return 0;
823}
824
825static void stm32_timer_trigger_remove(struct platform_device *pdev)
826{
827	struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
828	u32 val;
829
830	/* Unregister triggers before everything can be safely turned off */
831	stm32_unregister_iio_triggers(priv);
832
833	/* Check if nobody else use the timer, then disable it */
834	regmap_read(priv->regmap, TIM_CCER, &val);
835	if (!(val & TIM_CCER_CCXE))
836		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
837
838	if (priv->enabled)
839		clk_disable(priv->clk);
840}
841
842static int stm32_timer_trigger_suspend(struct device *dev)
843{
844	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
845
846	/* Only take care of enabled timer: don't disturb other MFD child */
847	if (priv->enabled) {
848		/* Backup registers that may get lost in low power mode */
849		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
850		regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
851		regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
852		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
853		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
854		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
855
856		/* Disable the timer */
857		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
858		clk_disable(priv->clk);
859	}
860
861	return 0;
862}
863
864static int stm32_timer_trigger_resume(struct device *dev)
865{
866	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
867	int ret;
868
869	if (priv->enabled) {
870		ret = clk_enable(priv->clk);
871		if (ret)
872			return ret;
873
874		/* restore master/slave modes */
875		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
876		regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
877
878		/* restore sampling_frequency (trgo / trgo2 triggers) */
879		regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
880		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
881		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
882
883		/* Also re-enables the timer */
884		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
885	}
886
887	return 0;
888}
889
890static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
891				stm32_timer_trigger_suspend,
892				stm32_timer_trigger_resume);
893
894static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
895	.valids_table = valids_table,
896	.num_valids_table = ARRAY_SIZE(valids_table),
897};
898
899static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
900	.valids_table = stm32h7_valids_table,
901	.num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
902};
903
904static const struct stm32_timer_trigger_cfg stm32mp25_timer_trg_cfg = {
905	/*
906	 * valids_table not used: counter framework is now superseding the deprecated IIO
907	 * counter interface (IIO_COUNT), so don't support it. num_valids_table is only
908	 * kept here to register the IIO HW triggers. valids_table should be moved at some
909	 * point to the stm32-timer-cnt driver instead.
910	 */
911	.num_valids_table = ARRAY_SIZE(triggers_table),
912};
913
914static const struct of_device_id stm32_trig_of_match[] = {
915	{
916		.compatible = "st,stm32-timer-trigger",
917		.data = (void *)&stm32_timer_trg_cfg,
918	}, {
919		.compatible = "st,stm32h7-timer-trigger",
920		.data = (void *)&stm32h7_timer_trg_cfg,
921	}, {
922		.compatible = "st,stm32mp25-timer-trigger",
923		.data = (void *)&stm32mp25_timer_trg_cfg,
924	},
925	{ }
926};
927MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
928
929static struct platform_driver stm32_timer_trigger_driver = {
930	.probe = stm32_timer_trigger_probe,
931	.remove = stm32_timer_trigger_remove,
932	.driver = {
933		.name = "stm32-timer-trigger",
934		.of_match_table = stm32_trig_of_match,
935		.pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops),
936	},
937};
938module_platform_driver(stm32_timer_trigger_driver);
939
940MODULE_ALIAS("platform:stm32-timer-trigger");
941MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
942MODULE_LICENSE("GPL v2");