opt4060.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2024 Axis Communications AB
   4 *
   5 * Datasheet: https://www.ti.com/lit/gpn/opt4060
   6 *
   7 * Device driver for the Texas Instruments OPT4060 RGBW Color Sensor.
   8 */
   9
  10#include <linux/bitfield.h>
  11#include <linux/i2c.h>
  12#include <linux/iio/iio.h>
  13#include <linux/math64.h>
  14#include <linux/units.h>
  15#include <linux/limits.h>
  16#include <linux/module.h>
  17#include <linux/property.h>
  18#include <linux/regmap.h>
  19#include <linux/mutex.h>
  20#include <linux/regulator/consumer.h>
  21#include <linux/iio/events.h>
  22#include <linux/iio/trigger.h>
  23#include <linux/iio/trigger_consumer.h>
  24#include <linux/iio/triggered_buffer.h>
  25
  26/* OPT4060 register set */
  27#define OPT4060_RED_MSB				0x00
  28#define OPT4060_RED_LSB				0x01
  29#define OPT4060_GREEN_MSB			0x02
  30#define OPT4060_GREEN_LSB			0x03
  31#define OPT4060_BLUE_MSB			0x04
  32#define OPT4060_BLUE_LSB			0x05
  33#define OPT4060_CLEAR_MSB			0x06
  34#define OPT4060_CLEAR_LSB			0x07
  35#define OPT4060_THRESHOLD_LOW			0x08
  36#define OPT4060_THRESHOLD_HIGH			0x09
  37#define OPT4060_CTRL				0x0a
  38#define OPT4060_INT_CTRL			0x0b
  39#define OPT4060_RES_CTRL			0x0c
  40#define OPT4060_DEVICE_ID			0x11
  41
  42/* OPT4060 register mask */
  43#define OPT4060_EXPONENT_MASK			GENMASK(15, 12)
  44#define OPT4060_MSB_MASK			GENMASK(11, 0)
  45#define OPT4060_LSB_MASK			GENMASK(15, 8)
  46#define OPT4060_COUNTER_MASK			GENMASK(7, 4)
  47#define OPT4060_CRC_MASK			GENMASK(3, 0)
  48
  49/* OPT4060 device id mask */
  50#define OPT4060_DEVICE_ID_MASK			GENMASK(11, 0)
  51
  52/* OPT4060 control register masks */
  53#define OPT4060_CTRL_QWAKE_MASK			BIT(15)
  54#define OPT4060_CTRL_RANGE_MASK			GENMASK(13, 10)
  55#define OPT4060_CTRL_CONV_TIME_MASK		GENMASK(9, 6)
  56#define OPT4060_CTRL_OPER_MODE_MASK		GENMASK(5, 4)
  57#define OPT4060_CTRL_LATCH_MASK			BIT(3)
  58#define OPT4060_CTRL_INT_POL_MASK		BIT(2)
  59#define OPT4060_CTRL_FAULT_COUNT_MASK		GENMASK(1, 0)
  60
  61/* OPT4060 interrupt control register masks */
  62#define OPT4060_INT_CTRL_THRESH_SEL		GENMASK(6, 5)
  63#define OPT4060_INT_CTRL_OUTPUT			BIT(4)
  64#define OPT4060_INT_CTRL_INT_CFG		GENMASK(3, 2)
  65#define OPT4060_INT_CTRL_THRESHOLD		0x0
  66#define OPT4060_INT_CTRL_NEXT_CH		0x1
  67#define OPT4060_INT_CTRL_ALL_CH			0x3
  68
  69/* OPT4060 result control register masks */
  70#define OPT4060_RES_CTRL_OVERLOAD		BIT(3)
  71#define OPT4060_RES_CTRL_CONV_READY		BIT(2)
  72#define OPT4060_RES_CTRL_FLAG_H			BIT(1)
  73#define OPT4060_RES_CTRL_FLAG_L			BIT(0)
  74
  75/* OPT4060 constants */
  76#define OPT4060_DEVICE_ID_VAL			0x821
  77
  78/* OPT4060 operating modes */
  79#define OPT4060_CTRL_OPER_MODE_OFF		0x0
  80#define OPT4060_CTRL_OPER_MODE_FORCED		0x1
  81#define OPT4060_CTRL_OPER_MODE_ONE_SHOT		0x2
  82#define OPT4060_CTRL_OPER_MODE_CONTINUOUS	0x3
  83
  84/* OPT4060 conversion control register definitions */
  85#define OPT4060_CTRL_CONVERSION_0_6MS		0x0
  86#define OPT4060_CTRL_CONVERSION_1MS		0x1
  87#define OPT4060_CTRL_CONVERSION_1_8MS		0x2
  88#define OPT4060_CTRL_CONVERSION_3_4MS		0x3
  89#define OPT4060_CTRL_CONVERSION_6_5MS		0x4
  90#define OPT4060_CTRL_CONVERSION_12_7MS		0x5
  91#define OPT4060_CTRL_CONVERSION_25MS		0x6
  92#define OPT4060_CTRL_CONVERSION_50MS		0x7
  93#define OPT4060_CTRL_CONVERSION_100MS		0x8
  94#define OPT4060_CTRL_CONVERSION_200MS		0x9
  95#define OPT4060_CTRL_CONVERSION_400MS		0xa
  96#define OPT4060_CTRL_CONVERSION_800MS		0xb
  97
  98/* OPT4060 fault count control register definitions */
  99#define OPT4060_CTRL_FAULT_COUNT_1		0x0
 100#define OPT4060_CTRL_FAULT_COUNT_2		0x1
 101#define OPT4060_CTRL_FAULT_COUNT_4		0x2
 102#define OPT4060_CTRL_FAULT_COUNT_8		0x3
 103
 104/* OPT4060 scale light level range definitions */
 105#define OPT4060_CTRL_LIGHT_SCALE_AUTO		12
 106
 107/* OPT4060 default values */
 108#define OPT4060_DEFAULT_CONVERSION_TIME OPT4060_CTRL_CONVERSION_50MS
 109
 110/*
 111 * enum opt4060_chan_type - OPT4060 channel types
 112 * @OPT4060_RED:	Red channel.
 113 * @OPT4060_GREEN:	Green channel.
 114 * @OPT4060_BLUE:	Blue channel.
 115 * @OPT4060_CLEAR:	Clear (white) channel.
 116 * @OPT4060_ILLUM:	Calculated illuminance channel.
 117 * @OPT4060_NUM_CHANS:	Number of channel types.
 118 */
 119enum opt4060_chan_type {
 120	OPT4060_RED,
 121	OPT4060_GREEN,
 122	OPT4060_BLUE,
 123	OPT4060_CLEAR,
 124	OPT4060_ILLUM,
 125	OPT4060_NUM_CHANS
 126};
 127
 128struct opt4060_chip {
 129	struct regmap *regmap;
 130	struct device *dev;
 131	struct iio_trigger *trig;
 132	u8 int_time;
 133	int irq;
 134	/*
 135	 * Mutex for protecting sensor irq settings. Switching between interrupt
 136	 * on each sample and on thresholds needs to be synchronized.
 137	 */
 138	struct mutex irq_setting_lock;
 139	/*
 140	 * Mutex for protecting event enabling.
 141	 */
 142	struct mutex event_enabling_lock;
 143	struct completion completion;
 144	bool thresh_event_lo_active;
 145	bool thresh_event_hi_active;
 146};
 147
 148struct opt4060_channel_factor {
 149	u32 mul;
 150	u32 div;
 151};
 152
 153static const int opt4060_int_time_available[][2] = {
 154	{ 0,    600 },
 155	{ 0,   1000 },
 156	{ 0,   1800 },
 157	{ 0,   3400 },
 158	{ 0,   6500 },
 159	{ 0,  12700 },
 160	{ 0,  25000 },
 161	{ 0,  50000 },
 162	{ 0, 100000 },
 163	{ 0, 200000 },
 164	{ 0, 400000 },
 165	{ 0, 800000 },
 166};
 167
 168/*
 169 * Conversion time is integration time + time to set register
 170 * this is used as integration time.
 171 */
 172static const int opt4060_int_time_reg[][2] = {
 173	{    600,  OPT4060_CTRL_CONVERSION_0_6MS  },
 174	{   1000,  OPT4060_CTRL_CONVERSION_1MS    },
 175	{   1800,  OPT4060_CTRL_CONVERSION_1_8MS  },
 176	{   3400,  OPT4060_CTRL_CONVERSION_3_4MS  },
 177	{   6500,  OPT4060_CTRL_CONVERSION_6_5MS  },
 178	{  12700,  OPT4060_CTRL_CONVERSION_12_7MS },
 179	{  25000,  OPT4060_CTRL_CONVERSION_25MS   },
 180	{  50000,  OPT4060_CTRL_CONVERSION_50MS   },
 181	{ 100000,  OPT4060_CTRL_CONVERSION_100MS  },
 182	{ 200000,  OPT4060_CTRL_CONVERSION_200MS  },
 183	{ 400000,  OPT4060_CTRL_CONVERSION_400MS  },
 184	{ 800000,  OPT4060_CTRL_CONVERSION_800MS  },
 185};
 186
 187static int opt4060_als_time_to_index(const u32 als_integration_time)
 188{
 189	int i;
 190
 191	for (i = 0; i < ARRAY_SIZE(opt4060_int_time_available); i++) {
 192		if (als_integration_time == opt4060_int_time_available[i][1])
 193			return i;
 194	}
 195
 196	return -EINVAL;
 197}
 198
 199static u8 opt4060_calculate_crc(u8 exp, u32 mantissa, u8 count)
 200{
 201	u8 crc;
 202
 203	/*
 204	 * Calculates a 4-bit CRC from a 20-bit mantissa, 4-bit exponent and a 4-bit counter.
 205	 * crc[0] = XOR(mantissa[19:0], exp[3:0], count[3:0])
 206	 * crc[1] = XOR(mantissa[1,3,5,7,9,11,13,15,17,19], exp[1,3], count[1,3])
 207	 * crc[2] = XOR(mantissa[3,7,11,15,19], exp[3], count[3])
 208	 * crc[3] = XOR(mantissa[3,11,19])
 209	 */
 210	crc = (hweight32(mantissa) + hweight32(exp) + hweight32(count)) % 2;
 211	crc |= ((hweight32(mantissa & 0xAAAAA) + hweight32(exp & 0xA)
 212		 + hweight32(count & 0xA)) % 2) << 1;
 213	crc |= ((hweight32(mantissa & 0x88888) + hweight32(exp & 0x8)
 214		 + hweight32(count & 0x8)) % 2) << 2;
 215	crc |= (hweight32(mantissa & 0x80808) % 2) << 3;
 216
 217	return crc;
 218}
 219
 220static int opt4060_set_int_state(struct opt4060_chip *chip, u32 state)
 221{
 222	int ret;
 223	unsigned int regval;
 224
 225	guard(mutex)(&chip->irq_setting_lock);
 226
 227	regval = FIELD_PREP(OPT4060_INT_CTRL_INT_CFG, state);
 228	ret = regmap_update_bits(chip->regmap, OPT4060_INT_CTRL,
 229				 OPT4060_INT_CTRL_INT_CFG, regval);
 230	if (ret)
 231		dev_err(chip->dev, "Failed to set interrupt config\n");
 232	return ret;
 233}
 234
 235static int opt4060_set_sampling_mode(struct opt4060_chip *chip,
 236				     bool continuous)
 237{
 238	unsigned int reg;
 239	int ret;
 240
 241	ret = regmap_read(chip->regmap, OPT4060_CTRL, &reg);
 242	if (ret < 0) {
 243		dev_err(chip->dev, "Failed to read ctrl register\n");
 244		return ret;
 245	}
 246	reg &= ~OPT4060_CTRL_OPER_MODE_MASK;
 247	if (continuous)
 248		reg |= FIELD_PREP(OPT4060_CTRL_OPER_MODE_MASK,
 249				  OPT4060_CTRL_OPER_MODE_CONTINUOUS);
 250	else
 251		reg |= FIELD_PREP(OPT4060_CTRL_OPER_MODE_MASK,
 252				  OPT4060_CTRL_OPER_MODE_ONE_SHOT);
 253
 254	/*
 255	 * Trigger a new conversions by writing to CRTL register. It is not
 256	 * possible to use regmap_update_bits() since that will only write when
 257	 * data is modified.
 258	 */
 259	ret = regmap_write(chip->regmap, OPT4060_CTRL, reg);
 260	if (ret)
 261		dev_err(chip->dev, "Failed to set ctrl register\n");
 262	return ret;
 263}
 264
 265static bool opt4060_event_active(struct opt4060_chip *chip)
 266{
 267	return chip->thresh_event_lo_active || chip->thresh_event_hi_active;
 268}
 269
 270static int opt4060_set_state_common(struct opt4060_chip *chip,
 271				    bool continuous_sampling,
 272				    bool continuous_irq)
 273{
 274	int ret = 0;
 275
 276	/* It is important to setup irq before sampling to avoid missing samples. */
 277	if (continuous_irq)
 278		ret = opt4060_set_int_state(chip, OPT4060_INT_CTRL_ALL_CH);
 279	else
 280		ret = opt4060_set_int_state(chip, OPT4060_INT_CTRL_THRESHOLD);
 281	if (ret) {
 282		dev_err(chip->dev, "Failed to set irq state.\n");
 283		return ret;
 284	}
 285
 286	if (continuous_sampling || opt4060_event_active(chip))
 287		ret = opt4060_set_sampling_mode(chip, true);
 288	else
 289		ret = opt4060_set_sampling_mode(chip, false);
 290	if (ret)
 291		dev_err(chip->dev, "Failed to set sampling state.\n");
 292	return ret;
 293}
 294
 295/*
 296 * Function for setting the driver state for sampling and irq. Either direct
 297 * mode of buffer mode will be claimed during the transition to prevent races
 298 * between sysfs read, buffer or events.
 299 */
 300static int opt4060_set_driver_state(struct iio_dev *indio_dev,
 301				    bool continuous_sampling,
 302				    bool continuous_irq)
 303{
 304	struct opt4060_chip *chip = iio_priv(indio_dev);
 305	int ret = 0;
 306any_mode_retry:
 307	if (iio_device_claim_buffer_mode(indio_dev)) {
 308		/*
 309		 * This one is a *bit* hacky. If we cannot claim buffer mode,
 310		 * then try direct mode so that we make sure things cannot
 311		 * concurrently change. And we just keep trying until we get one
 312		 * of the modes...
 313		 */
 314		if (!iio_device_claim_direct(indio_dev))
 315			goto any_mode_retry;
 316		/*
 317		 * This path means that we managed to claim direct mode. In
 318		 * this case the buffer isn't enabled and it's okay to leave
 319		 * continuous mode for sampling and/or irq.
 320		 */
 321		ret = opt4060_set_state_common(chip, continuous_sampling,
 322					       continuous_irq);
 323		iio_device_release_direct(indio_dev);
 324		return ret;
 325	} else {
 326		/*
 327		 * This path means that we managed to claim buffer mode. In
 328		 * this case the buffer is enabled and irq and sampling must go
 329		 * to or remain continuous, but only if the trigger is from this
 330		 * device.
 331		 */
 332		if (!iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
 333			ret = opt4060_set_state_common(chip, true, true);
 334		else
 335			ret = opt4060_set_state_common(chip, continuous_sampling,
 336						       continuous_irq);
 337		iio_device_release_buffer_mode(indio_dev);
 338	}
 339	return ret;
 340}
 341
 342/*
 343 * This function is called with framework mutex locked.
 344 */
 345static int opt4060_trigger_set_state(struct iio_trigger *trig, bool state)
 346{
 347	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 348	struct opt4060_chip *chip = iio_priv(indio_dev);
 349
 350	return opt4060_set_state_common(chip, state, state);
 351}
 352
 353static int opt4060_read_raw_value(struct opt4060_chip *chip,
 354				  unsigned long address, u32 *raw)
 355{
 356	int ret;
 357	u16 result[2];
 358	u32 mantissa_raw;
 359	u16 msb, lsb;
 360	u8 exp, count, crc, calc_crc;
 361
 362	ret = regmap_bulk_read(chip->regmap, address, result, 2);
 363	if (ret) {
 364		dev_err(chip->dev, "Reading channel data failed\n");
 365		return ret;
 366	}
 367	exp = FIELD_GET(OPT4060_EXPONENT_MASK, result[0]);
 368	msb = FIELD_GET(OPT4060_MSB_MASK, result[0]);
 369	count = FIELD_GET(OPT4060_COUNTER_MASK, result[1]);
 370	crc = FIELD_GET(OPT4060_CRC_MASK, result[1]);
 371	lsb = FIELD_GET(OPT4060_LSB_MASK, result[1]);
 372	mantissa_raw = (msb << 8) + lsb;
 373	calc_crc = opt4060_calculate_crc(exp, mantissa_raw, count);
 374	if (calc_crc != crc)
 375		return -EIO;
 376	*raw = mantissa_raw << exp;
 377	return 0;
 378}
 379
 380static int opt4060_trigger_new_samples(struct iio_dev *indio_dev)
 381{
 382	struct opt4060_chip *chip = iio_priv(indio_dev);
 383	int ret;
 384
 385	/*
 386	 * The conversion time should be 500us startup time plus the integration time
 387	 * times the number of channels. An exact timeout isn't critical, it's better
 388	 * not to get incorrect errors in the log. Setting the timeout to double the
 389	 * theoretical time plus and extra 100ms margin.
 390	 */
 391	unsigned int timeout_us = (500 + OPT4060_NUM_CHANS *
 392				  opt4060_int_time_reg[chip->int_time][0]) * 2 + 100000;
 393
 394	/* Setting the state in one shot mode with irq on each sample. */
 395	ret = opt4060_set_driver_state(indio_dev, false, true);
 396	if (ret)
 397		return ret;
 398
 399	if (chip->irq) {
 400		guard(mutex)(&chip->irq_setting_lock);
 401		reinit_completion(&chip->completion);
 402		if (wait_for_completion_timeout(&chip->completion,
 403						usecs_to_jiffies(timeout_us)) == 0) {
 404			dev_err(chip->dev, "Completion timed out.\n");
 405			return -ETIME;
 406		}
 407	} else {
 408		unsigned int ready;
 409
 410		ret = regmap_read_poll_timeout(chip->regmap, OPT4060_RES_CTRL,
 411					       ready, (ready & OPT4060_RES_CTRL_CONV_READY),
 412					       1000, timeout_us);
 413		if (ret)
 414			dev_err(chip->dev, "Conversion ready did not finish within timeout.\n");
 415	}
 416	/* Setting the state in one shot mode with irq on thresholds. */
 417	return opt4060_set_driver_state(indio_dev, false, false);
 418}
 419
 420static int opt4060_read_chan_raw(struct iio_dev *indio_dev,
 421				 struct iio_chan_spec const *chan, int *val)
 422{
 423	struct opt4060_chip *chip = iio_priv(indio_dev);
 424	u32 adc_raw;
 425	int ret;
 426
 427	ret = opt4060_trigger_new_samples(indio_dev);
 428	if (ret) {
 429		dev_err(chip->dev, "Failed to trigger new samples.\n");
 430		return ret;
 431	}
 432
 433	ret = opt4060_read_raw_value(chip, chan->address, &adc_raw);
 434	if (ret) {
 435		dev_err(chip->dev, "Reading raw channel data failed.\n");
 436		return ret;
 437	}
 438	*val = adc_raw;
 439	return IIO_VAL_INT;
 440}
 441
 442/*
 443 * Returns the scale values used for red, green and blue. Scales the raw value
 444 * so that for a particular test light source, typically white, the measurement
 445 * intensity is the same across different color channels.
 446 */
 447static int opt4060_get_chan_scale(struct iio_dev *indio_dev,
 448				  struct iio_chan_spec const *chan,
 449				  int *val, int *val2)
 450{
 451	struct opt4060_chip *chip = iio_priv(indio_dev);
 452
 453	switch (chan->scan_index) {
 454	case OPT4060_RED:
 455		/* 2.4 */
 456		*val = 2;
 457		*val2 = 400000;
 458		break;
 459	case OPT4060_GREEN:
 460		/* 1.0 */
 461		*val = 1;
 462		*val2 = 0;
 463		break;
 464	case OPT4060_BLUE:
 465		/* 1.3 */
 466		*val = 1;
 467		*val2 = 300000;
 468		break;
 469	default:
 470		dev_err(chip->dev, "Unexpected channel index.\n");
 471		return -EINVAL;
 472	}
 473	return IIO_VAL_INT_PLUS_MICRO;
 474}
 475
 476static int opt4060_calc_illuminance(struct opt4060_chip *chip, int *val)
 477{
 478	u32 lux_raw;
 479	int ret;
 480
 481	/* The green wide spectral channel is used for illuminance. */
 482	ret = opt4060_read_raw_value(chip, OPT4060_GREEN_MSB, &lux_raw);
 483	if (ret) {
 484		dev_err(chip->dev, "Reading raw channel data failed\n");
 485		return ret;
 486	}
 487
 488	/* Illuminance is calculated by ADC_RAW * 2.15e-3. */
 489	*val = DIV_U64_ROUND_CLOSEST((u64)(lux_raw * 215), 1000);
 490	return ret;
 491}
 492
 493static int opt4060_read_illuminance(struct iio_dev *indio_dev,
 494				    struct iio_chan_spec const *chan,
 495				    int *val)
 496{
 497	struct opt4060_chip *chip = iio_priv(indio_dev);
 498	int ret;
 499
 500	ret = opt4060_trigger_new_samples(indio_dev);
 501	if (ret) {
 502		dev_err(chip->dev, "Failed to trigger new samples.\n");
 503		return ret;
 504	}
 505	ret = opt4060_calc_illuminance(chip, val);
 506	if (ret) {
 507		dev_err(chip->dev, "Failed to calculate illuminance.\n");
 508		return ret;
 509	}
 510
 511	return IIO_VAL_INT;
 512}
 513
 514static int opt4060_set_int_time(struct opt4060_chip *chip)
 515{
 516	unsigned int regval;
 517	int ret;
 518
 519	regval = FIELD_PREP(OPT4060_CTRL_CONV_TIME_MASK, chip->int_time);
 520	ret = regmap_update_bits(chip->regmap, OPT4060_CTRL,
 521				 OPT4060_CTRL_CONV_TIME_MASK, regval);
 522	if (ret)
 523		dev_err(chip->dev, "Failed to set integration time.\n");
 524
 525	return ret;
 526}
 527
 528static int opt4060_power_down(struct opt4060_chip *chip)
 529{
 530	int ret;
 531
 532	ret = regmap_clear_bits(chip->regmap, OPT4060_CTRL, OPT4060_CTRL_OPER_MODE_MASK);
 533	if (ret)
 534		dev_err(chip->dev, "Failed to power down\n");
 535
 536	return ret;
 537}
 538
 539static void opt4060_chip_off_action(void *chip)
 540{
 541	opt4060_power_down(chip);
 542}
 543
 544#define _OPT4060_COLOR_CHANNEL(_color, _mask, _ev_spec, _num_ev_spec)		\
 545{										\
 546	.type = IIO_INTENSITY,							\
 547	.modified = 1,								\
 548	.channel2 = IIO_MOD_LIGHT_##_color,					\
 549	.info_mask_separate = _mask,						\
 550	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),			\
 551	.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),	\
 552	.address = OPT4060_##_color##_MSB,					\
 553	.scan_index = OPT4060_##_color,						\
 554	.scan_type = {								\
 555		.sign = 'u',							\
 556		.realbits = 32,							\
 557		.storagebits = 32,						\
 558		.endianness = IIO_CPU,						\
 559	},									\
 560	.event_spec = _ev_spec,							\
 561	.num_event_specs = _num_ev_spec,					\
 562}
 563
 564#define OPT4060_COLOR_CHANNEL(_color, _mask)					\
 565	_OPT4060_COLOR_CHANNEL(_color, _mask, opt4060_event_spec,		\
 566			       ARRAY_SIZE(opt4060_event_spec))			\
 567
 568#define OPT4060_COLOR_CHANNEL_NO_EVENTS(_color, _mask)				\
 569	_OPT4060_COLOR_CHANNEL(_color, _mask, NULL, 0)				\
 570
 571#define OPT4060_LIGHT_CHANNEL(_channel)						\
 572{										\
 573	.type = IIO_LIGHT,							\
 574	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),			\
 575	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),			\
 576	.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),	\
 577	.scan_index = OPT4060_##_channel,					\
 578	.scan_type = {								\
 579		.sign = 'u',							\
 580		.realbits = 32,							\
 581		.storagebits = 32,						\
 582		.endianness = IIO_CPU,						\
 583	},									\
 584}
 585
 586static const struct iio_event_spec opt4060_event_spec[] = {
 587	{
 588		.type = IIO_EV_TYPE_THRESH,
 589		.dir = IIO_EV_DIR_RISING,
 590		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 591				 BIT(IIO_EV_INFO_ENABLE),
 592	}, {
 593		.type = IIO_EV_TYPE_THRESH,
 594		.dir = IIO_EV_DIR_FALLING,
 595		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 596				 BIT(IIO_EV_INFO_ENABLE),
 597	}, {
 598		.type = IIO_EV_TYPE_THRESH,
 599		.dir = IIO_EV_DIR_EITHER,
 600		.mask_separate = BIT(IIO_EV_INFO_PERIOD),
 601	},
 602};
 603
 604static const struct iio_chan_spec opt4060_channels[] = {
 605	OPT4060_COLOR_CHANNEL(RED, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 606	OPT4060_COLOR_CHANNEL(GREEN, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 607	OPT4060_COLOR_CHANNEL(BLUE, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 608	OPT4060_COLOR_CHANNEL(CLEAR, BIT(IIO_CHAN_INFO_RAW)),
 609	OPT4060_LIGHT_CHANNEL(ILLUM),
 610	IIO_CHAN_SOFT_TIMESTAMP(OPT4060_NUM_CHANS),
 611};
 612
 613static const struct iio_chan_spec opt4060_channels_no_events[] = {
 614	OPT4060_COLOR_CHANNEL_NO_EVENTS(RED, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 615	OPT4060_COLOR_CHANNEL_NO_EVENTS(GREEN, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 616	OPT4060_COLOR_CHANNEL_NO_EVENTS(BLUE, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)),
 617	OPT4060_COLOR_CHANNEL_NO_EVENTS(CLEAR, BIT(IIO_CHAN_INFO_RAW)),
 618	OPT4060_LIGHT_CHANNEL(ILLUM),
 619	IIO_CHAN_SOFT_TIMESTAMP(OPT4060_NUM_CHANS),
 620};
 621
 622static int opt4060_read_raw(struct iio_dev *indio_dev,
 623			    struct iio_chan_spec const *chan,
 624			    int *val, int *val2, long mask)
 625{
 626	struct opt4060_chip *chip = iio_priv(indio_dev);
 627
 628	switch (mask) {
 629	case IIO_CHAN_INFO_RAW:
 630		return opt4060_read_chan_raw(indio_dev, chan, val);
 631	case IIO_CHAN_INFO_SCALE:
 632		return opt4060_get_chan_scale(indio_dev, chan, val, val2);
 633	case IIO_CHAN_INFO_PROCESSED:
 634		return opt4060_read_illuminance(indio_dev, chan, val);
 635	case IIO_CHAN_INFO_INT_TIME:
 636		*val = 0;
 637		*val2 = opt4060_int_time_reg[chip->int_time][0];
 638		return IIO_VAL_INT_PLUS_MICRO;
 639	default:
 640		return -EINVAL;
 641	}
 642}
 643
 644static int opt4060_write_raw(struct iio_dev *indio_dev,
 645			     struct iio_chan_spec const *chan,
 646			     int val, int val2, long mask)
 647{
 648	struct opt4060_chip *chip = iio_priv(indio_dev);
 649	int int_time;
 650
 651	switch (mask) {
 652	case IIO_CHAN_INFO_INT_TIME:
 653		int_time = opt4060_als_time_to_index(val2);
 654		if (int_time < 0)
 655			return int_time;
 656		chip->int_time = int_time;
 657		return opt4060_set_int_time(chip);
 658	default:
 659		return -EINVAL;
 660	}
 661}
 662
 663static int opt4060_write_raw_get_fmt(struct iio_dev *indio_dev,
 664				     struct iio_chan_spec const *chan,
 665				     long mask)
 666{
 667	switch (mask) {
 668	case IIO_CHAN_INFO_INT_TIME:
 669		return IIO_VAL_INT_PLUS_MICRO;
 670	default:
 671		return -EINVAL;
 672	}
 673}
 674
 675static u32 opt4060_calc_th_reg(u32 adc_val)
 676{
 677	u32 th_val, th_exp, bits;
 678	/*
 679	 * The threshold registers take 4 bits of exponent and 12 bits of data
 680	 * ADC = TH_VAL << (8 + TH_EXP)
 681	 */
 682	bits = fls(adc_val);
 683
 684	if (bits > 31)
 685		th_exp = 11; /* Maximum exponent */
 686	else if (bits > 20)
 687		th_exp = bits - 20;
 688	else
 689		th_exp = 0;
 690	th_val = (adc_val >> (8 + th_exp)) & 0xfff;
 691
 692	return (th_exp << 12) + th_val;
 693}
 694
 695static u32 opt4060_calc_val_from_th_reg(u32 th_reg)
 696{
 697	/*
 698	 * The threshold registers take 4 bits of exponent and 12 bits of data
 699	 * ADC = TH_VAL << (8 + TH_EXP)
 700	 */
 701	u32 th_val, th_exp;
 702
 703	th_exp = (th_reg >> 12) & 0xf;
 704	th_val = th_reg & 0xfff;
 705
 706	return th_val << (8 + th_exp);
 707}
 708
 709static int opt4060_read_available(struct iio_dev *indio_dev,
 710				  struct iio_chan_spec const *chan,
 711				  const int **vals, int *type, int *length,
 712				  long mask)
 713{
 714	switch (mask) {
 715	case IIO_CHAN_INFO_INT_TIME:
 716		*length = ARRAY_SIZE(opt4060_int_time_available) * 2;
 717		*vals = (const int *)opt4060_int_time_available;
 718		*type = IIO_VAL_INT_PLUS_MICRO;
 719		return IIO_AVAIL_LIST;
 720
 721	default:
 722		return -EINVAL;
 723	}
 724}
 725
 726static ssize_t opt4060_read_ev_period(struct opt4060_chip *chip, int *val,
 727				      int *val2)
 728{
 729	int ret, pers, fault_count, int_time;
 730	u64 uval;
 731
 732	int_time = opt4060_int_time_reg[chip->int_time][0];
 733
 734	ret = regmap_read(chip->regmap, OPT4060_CTRL, &fault_count);
 735	if (ret < 0)
 736		return ret;
 737
 738	fault_count = fault_count & OPT4060_CTRL_FAULT_COUNT_MASK;
 739	switch (fault_count) {
 740	case OPT4060_CTRL_FAULT_COUNT_2:
 741		pers = 2;
 742		break;
 743	case OPT4060_CTRL_FAULT_COUNT_4:
 744		pers = 4;
 745		break;
 746	case OPT4060_CTRL_FAULT_COUNT_8:
 747		pers = 8;
 748		break;
 749
 750	default:
 751		pers = 1;
 752		break;
 753	}
 754
 755	uval = mul_u32_u32(int_time, pers);
 756	*val = div_u64_rem(uval, MICRO, val2);
 757
 758	return IIO_VAL_INT_PLUS_MICRO;
 759}
 760
 761static ssize_t opt4060_write_ev_period(struct opt4060_chip *chip, int val,
 762				       int val2)
 763{
 764	u64 uval, int_time;
 765	unsigned int regval, fault_count_val;
 766
 767	uval = mul_u32_u32(val, MICRO) + val2;
 768	int_time = opt4060_int_time_reg[chip->int_time][0];
 769
 770	/* Check if the period is closest to 1, 2, 4 or 8 times integration time.*/
 771	if (uval <= int_time)
 772		fault_count_val = OPT4060_CTRL_FAULT_COUNT_1;
 773	else if (uval <= int_time * 2)
 774		fault_count_val = OPT4060_CTRL_FAULT_COUNT_2;
 775	else if (uval <= int_time * 4)
 776		fault_count_val = OPT4060_CTRL_FAULT_COUNT_4;
 777	else
 778		fault_count_val = OPT4060_CTRL_FAULT_COUNT_8;
 779
 780	regval = FIELD_PREP(OPT4060_CTRL_FAULT_COUNT_MASK, fault_count_val);
 781	return regmap_update_bits(chip->regmap, OPT4060_CTRL,
 782				 OPT4060_CTRL_FAULT_COUNT_MASK, regval);
 783}
 784
 785static int opt4060_get_channel_sel(struct opt4060_chip *chip, int *ch_sel)
 786{
 787	int ret;
 788	u32 regval;
 789
 790	ret = regmap_read(chip->regmap, OPT4060_INT_CTRL, &regval);
 791	if (ret) {
 792		dev_err(chip->dev, "Failed to get channel selection.\n");
 793		return ret;
 794	}
 795	*ch_sel = FIELD_GET(OPT4060_INT_CTRL_THRESH_SEL, regval);
 796	return ret;
 797}
 798
 799static int opt4060_set_channel_sel(struct opt4060_chip *chip, int ch_sel)
 800{
 801	int ret;
 802	u32 regval;
 803
 804	regval = FIELD_PREP(OPT4060_INT_CTRL_THRESH_SEL, ch_sel);
 805	ret = regmap_update_bits(chip->regmap, OPT4060_INT_CTRL,
 806				 OPT4060_INT_CTRL_THRESH_SEL, regval);
 807	if (ret)
 808		dev_err(chip->dev, "Failed to set channel selection.\n");
 809	return ret;
 810}
 811
 812static int opt4060_get_thresholds(struct opt4060_chip *chip, u32 *th_lo, u32 *th_hi)
 813{
 814	int ret;
 815	u32 regval;
 816
 817	ret = regmap_read(chip->regmap, OPT4060_THRESHOLD_LOW, &regval);
 818	if (ret) {
 819		dev_err(chip->dev, "Failed to read THRESHOLD_LOW.\n");
 820		return ret;
 821	}
 822	*th_lo = opt4060_calc_val_from_th_reg(regval);
 823
 824	ret = regmap_read(chip->regmap, OPT4060_THRESHOLD_HIGH, &regval);
 825	if (ret) {
 826		dev_err(chip->dev, "Failed to read THRESHOLD_LOW.\n");
 827		return ret;
 828	}
 829	*th_hi = opt4060_calc_val_from_th_reg(regval);
 830
 831	return ret;
 832}
 833
 834static int opt4060_set_thresholds(struct opt4060_chip *chip, u32 th_lo, u32 th_hi)
 835{
 836	int ret;
 837
 838	ret = regmap_write(chip->regmap, OPT4060_THRESHOLD_LOW, opt4060_calc_th_reg(th_lo));
 839	if (ret) {
 840		dev_err(chip->dev, "Failed to write THRESHOLD_LOW.\n");
 841		return ret;
 842	}
 843
 844	ret = regmap_write(chip->regmap, OPT4060_THRESHOLD_HIGH, opt4060_calc_th_reg(th_hi));
 845	if (ret)
 846		dev_err(chip->dev, "Failed to write THRESHOLD_HIGH.\n");
 847
 848	return ret;
 849}
 850
 851static int opt4060_read_event(struct iio_dev *indio_dev,
 852			      const struct iio_chan_spec *chan,
 853			      enum iio_event_type type,
 854			      enum iio_event_direction dir,
 855			      enum iio_event_info info,
 856			      int *val, int *val2)
 857{
 858	struct opt4060_chip *chip = iio_priv(indio_dev);
 859	u32 th_lo, th_hi;
 860	int ret;
 861
 862	if (chan->type != IIO_INTENSITY)
 863		return -EINVAL;
 864	if (type != IIO_EV_TYPE_THRESH)
 865		return -EINVAL;
 866
 867	switch (info) {
 868	case IIO_EV_INFO_VALUE:
 869		ret = opt4060_get_thresholds(chip, &th_lo, &th_hi);
 870		if (ret)
 871			return ret;
 872		if (dir == IIO_EV_DIR_FALLING) {
 873			*val = th_lo;
 874			ret = IIO_VAL_INT;
 875		} else if (dir == IIO_EV_DIR_RISING) {
 876			*val = th_hi;
 877			ret = IIO_VAL_INT;
 878		}
 879		return ret;
 880	case IIO_EV_INFO_PERIOD:
 881		return opt4060_read_ev_period(chip, val, val2);
 882	default:
 883		return -EINVAL;
 884	}
 885}
 886
 887static int opt4060_write_event(struct iio_dev *indio_dev,
 888			       const struct iio_chan_spec *chan,
 889			       enum iio_event_type type,
 890			       enum iio_event_direction dir,
 891			       enum iio_event_info info,
 892			       int val, int val2)
 893{
 894	struct opt4060_chip *chip = iio_priv(indio_dev);
 895	u32 th_lo, th_hi;
 896	int ret;
 897
 898	if (chan->type != IIO_INTENSITY)
 899		return -EINVAL;
 900	if (type != IIO_EV_TYPE_THRESH)
 901		return -EINVAL;
 902
 903	switch (info) {
 904	case IIO_EV_INFO_VALUE:
 905		ret = opt4060_get_thresholds(chip, &th_lo, &th_hi);
 906		if (ret)
 907			return ret;
 908		if (dir == IIO_EV_DIR_FALLING)
 909			th_lo = val;
 910		else if (dir == IIO_EV_DIR_RISING)
 911			th_hi = val;
 912		return opt4060_set_thresholds(chip, th_lo, th_hi);
 913	case IIO_EV_INFO_PERIOD:
 914		return opt4060_write_ev_period(chip, val, val2);
 915	default:
 916		return -EINVAL;
 917	}
 918}
 919
 920static int opt4060_read_event_config(struct iio_dev *indio_dev,
 921				     const struct iio_chan_spec *chan,
 922				     enum iio_event_type type,
 923				     enum iio_event_direction dir)
 924{
 925	int ch_sel, ch_idx = chan->scan_index;
 926	struct opt4060_chip *chip = iio_priv(indio_dev);
 927	int ret;
 928
 929	if (chan->type != IIO_INTENSITY)
 930		return -EINVAL;
 931	if (type != IIO_EV_TYPE_THRESH)
 932		return -EINVAL;
 933
 934	ret = opt4060_get_channel_sel(chip, &ch_sel);
 935	if (ret)
 936		return ret;
 937
 938	if (((dir == IIO_EV_DIR_FALLING) && chip->thresh_event_lo_active) ||
 939	    ((dir == IIO_EV_DIR_RISING) && chip->thresh_event_hi_active))
 940		return ch_sel == ch_idx;
 941
 942	return ret;
 943}
 944
 945static int opt4060_write_event_config(struct iio_dev *indio_dev,
 946				      const struct iio_chan_spec *chan,
 947				      enum iio_event_type type,
 948				      enum iio_event_direction dir, bool state)
 949{
 950	int ch_sel, ch_idx = chan->scan_index;
 951	struct opt4060_chip *chip = iio_priv(indio_dev);
 952	int ret;
 953
 954	guard(mutex)(&chip->event_enabling_lock);
 955
 956	if (chan->type != IIO_INTENSITY)
 957		return -EINVAL;
 958	if (type != IIO_EV_TYPE_THRESH)
 959		return -EINVAL;
 960
 961	ret = opt4060_get_channel_sel(chip, &ch_sel);
 962	if (ret)
 963		return ret;
 964
 965	if (state) {
 966		/* Only one channel can be active at the same time */
 967		if ((chip->thresh_event_lo_active || chip->thresh_event_hi_active) &&
 968		    (ch_idx != ch_sel))
 969			return -EBUSY;
 970		if (dir == IIO_EV_DIR_FALLING)
 971			chip->thresh_event_lo_active = true;
 972		else if (dir == IIO_EV_DIR_RISING)
 973			chip->thresh_event_hi_active = true;
 974		ret = opt4060_set_channel_sel(chip, ch_idx);
 975		if (ret)
 976			return ret;
 977	} else {
 978		if (ch_idx == ch_sel) {
 979			if (dir == IIO_EV_DIR_FALLING)
 980				chip->thresh_event_lo_active = false;
 981			else if (dir == IIO_EV_DIR_RISING)
 982				chip->thresh_event_hi_active = false;
 983		}
 984	}
 985
 986	return opt4060_set_driver_state(indio_dev,
 987					chip->thresh_event_hi_active |
 988					chip->thresh_event_lo_active,
 989					false);
 990}
 991
 992static const struct iio_info opt4060_info = {
 993	.read_raw = opt4060_read_raw,
 994	.write_raw = opt4060_write_raw,
 995	.write_raw_get_fmt = opt4060_write_raw_get_fmt,
 996	.read_avail = opt4060_read_available,
 997	.read_event_value = opt4060_read_event,
 998	.write_event_value = opt4060_write_event,
 999	.read_event_config = opt4060_read_event_config,
1000	.write_event_config = opt4060_write_event_config,
1001};
1002
1003static const struct iio_info opt4060_info_no_irq = {
1004	.read_raw = opt4060_read_raw,
1005	.write_raw = opt4060_write_raw,
1006	.write_raw_get_fmt = opt4060_write_raw_get_fmt,
1007	.read_avail = opt4060_read_available,
1008};
1009
1010static int opt4060_load_defaults(struct opt4060_chip *chip)
1011{
1012	u16 reg;
1013	int ret;
1014
1015	chip->int_time = OPT4060_DEFAULT_CONVERSION_TIME;
1016
1017	/* Set initial MIN/MAX thresholds */
1018	ret = opt4060_set_thresholds(chip, 0, UINT_MAX);
1019	if (ret)
1020		return ret;
1021
1022	/*
1023	 * Setting auto-range, latched window for thresholds, one-shot conversion
1024	 * and quick wake-up mode as default.
1025	 */
1026	reg = FIELD_PREP(OPT4060_CTRL_RANGE_MASK,
1027			 OPT4060_CTRL_LIGHT_SCALE_AUTO);
1028	reg |= FIELD_PREP(OPT4060_CTRL_CONV_TIME_MASK, chip->int_time);
1029	reg |= FIELD_PREP(OPT4060_CTRL_OPER_MODE_MASK,
1030				OPT4060_CTRL_OPER_MODE_ONE_SHOT);
1031	reg |= OPT4060_CTRL_QWAKE_MASK | OPT4060_CTRL_LATCH_MASK;
1032
1033	ret = regmap_write(chip->regmap, OPT4060_CTRL, reg);
1034	if (ret)
1035		dev_err(chip->dev, "Failed to set configuration\n");
1036
1037	return ret;
1038}
1039
1040static bool opt4060_volatile_reg(struct device *dev, unsigned int reg)
1041{
1042	return reg <= OPT4060_CLEAR_LSB || reg == OPT4060_RES_CTRL;
1043}
1044
1045static bool opt4060_writable_reg(struct device *dev, unsigned int reg)
1046{
1047	return reg >= OPT4060_THRESHOLD_LOW || reg >= OPT4060_INT_CTRL;
1048}
1049
1050static bool opt4060_readonly_reg(struct device *dev, unsigned int reg)
1051{
1052	return reg == OPT4060_DEVICE_ID;
1053}
1054
1055static bool opt4060_readable_reg(struct device *dev, unsigned int reg)
1056{
1057	/* Volatile, writable and read-only registers are readable. */
1058	return opt4060_volatile_reg(dev, reg) || opt4060_writable_reg(dev, reg) ||
1059	       opt4060_readonly_reg(dev, reg);
1060}
1061
1062static const struct regmap_config opt4060_regmap_config = {
1063	.name = "opt4060",
1064	.reg_bits = 8,
1065	.val_bits = 16,
1066	.cache_type = REGCACHE_MAPLE,
1067	.max_register = OPT4060_DEVICE_ID,
1068	.readable_reg = opt4060_readable_reg,
1069	.writeable_reg = opt4060_writable_reg,
1070	.volatile_reg = opt4060_volatile_reg,
1071	.val_format_endian = REGMAP_ENDIAN_BIG,
1072};
1073
1074static const struct iio_trigger_ops opt4060_trigger_ops = {
1075	.set_trigger_state = opt4060_trigger_set_state,
1076};
1077
1078static irqreturn_t opt4060_trigger_handler(int irq, void *p)
1079{
1080	struct iio_poll_func *pf = p;
1081	struct iio_dev *idev = pf->indio_dev;
1082	struct opt4060_chip *chip = iio_priv(idev);
1083	struct  {
1084		u32 chan[OPT4060_NUM_CHANS];
1085		aligned_s64 ts;
1086	} raw = { };
1087	int i = 0;
1088	int chan, ret;
1089
1090	/* If the trigger is not from this driver, a new sample is needed.*/
1091	if (iio_trigger_validate_own_device(idev->trig, idev))
1092		opt4060_trigger_new_samples(idev);
1093
1094	iio_for_each_active_channel(idev, chan) {
1095		if (chan == OPT4060_ILLUM)
1096			ret = opt4060_calc_illuminance(chip, &raw.chan[i++]);
1097		else
1098			ret = opt4060_read_raw_value(chip,
1099						     idev->channels[chan].address,
1100						     &raw.chan[i++]);
1101		if (ret) {
1102			dev_err(chip->dev, "Reading channel data failed\n");
1103			goto err_read;
1104		}
1105	}
1106
1107	iio_push_to_buffers_with_ts(idev, &raw, sizeof(raw), pf->timestamp);
1108err_read:
1109	iio_trigger_notify_done(idev->trig);
1110	return IRQ_HANDLED;
1111}
1112
1113static irqreturn_t opt4060_irq_thread(int irq, void *private)
1114{
1115	struct iio_dev *idev = private;
1116	struct opt4060_chip *chip = iio_priv(idev);
1117	int ret, dummy;
1118	unsigned int int_res;
1119
1120	ret = regmap_read(chip->regmap, OPT4060_RES_CTRL, &int_res);
1121	if (ret < 0) {
1122		dev_err(chip->dev, "Failed to read interrupt reasons.\n");
1123		return IRQ_NONE;
1124	}
1125
1126	/* Read OPT4060_CTRL to clear interrupt */
1127	ret = regmap_read(chip->regmap, OPT4060_CTRL, &dummy);
1128	if (ret < 0) {
1129		dev_err(chip->dev, "Failed to clear interrupt\n");
1130		return IRQ_NONE;
1131	}
1132
1133	/* Handle events */
1134	if (int_res & (OPT4060_RES_CTRL_FLAG_H | OPT4060_RES_CTRL_FLAG_L)) {
1135		u64 code;
1136		int chan = 0;
1137
1138		ret = opt4060_get_channel_sel(chip, &chan);
1139		if (ret) {
1140			dev_err(chip->dev, "Failed to read threshold channel.\n");
1141			return IRQ_NONE;
1142		}
1143
1144		/* Check if the interrupt is from the lower threshold */
1145		if (int_res & OPT4060_RES_CTRL_FLAG_L) {
1146			code = IIO_MOD_EVENT_CODE(IIO_INTENSITY,
1147						  chan,
1148						  idev->channels[chan].channel2,
1149						  IIO_EV_TYPE_THRESH,
1150						  IIO_EV_DIR_FALLING);
1151			iio_push_event(idev, code, iio_get_time_ns(idev));
1152		}
1153		/* Check if the interrupt is from the upper threshold */
1154		if (int_res & OPT4060_RES_CTRL_FLAG_H) {
1155			code = IIO_MOD_EVENT_CODE(IIO_INTENSITY,
1156						  chan,
1157						  idev->channels[chan].channel2,
1158						  IIO_EV_TYPE_THRESH,
1159						  IIO_EV_DIR_RISING);
1160			iio_push_event(idev, code, iio_get_time_ns(idev));
1161		}
1162	}
1163
1164	/* Handle conversion ready */
1165	if (int_res & OPT4060_RES_CTRL_CONV_READY) {
1166		/* Signal completion for potentially waiting reads */
1167		complete(&chip->completion);
1168
1169		/* Handle data ready triggers */
1170		if (iio_buffer_enabled(idev))
1171			iio_trigger_poll_nested(chip->trig);
1172	}
1173	return IRQ_HANDLED;
1174}
1175
1176static int opt4060_setup_buffer(struct opt4060_chip *chip, struct iio_dev *idev)
1177{
1178	int ret;
1179
1180	ret = devm_iio_triggered_buffer_setup(chip->dev, idev,
1181					      &iio_pollfunc_store_time,
1182					      opt4060_trigger_handler, NULL);
1183	if (ret)
1184		return dev_err_probe(chip->dev, ret,
1185				     "Buffer setup failed.\n");
1186	return ret;
1187}
1188
1189static int opt4060_setup_trigger(struct opt4060_chip *chip, struct iio_dev *idev)
1190{
1191	struct iio_trigger *data_trigger;
1192	char *name;
1193	int ret;
1194
1195	data_trigger = devm_iio_trigger_alloc(chip->dev, "%s-data-ready-dev%d",
1196					      idev->name, iio_device_id(idev));
1197	if (!data_trigger)
1198		return -ENOMEM;
1199
1200	/*
1201	 * The data trigger allows for sample capture on each new conversion
1202	 * ready interrupt.
1203	 */
1204	chip->trig = data_trigger;
1205	data_trigger->ops = &opt4060_trigger_ops;
1206	iio_trigger_set_drvdata(data_trigger, idev);
1207	ret = devm_iio_trigger_register(chip->dev, data_trigger);
1208	if (ret)
1209		return dev_err_probe(chip->dev, ret,
1210				     "Data ready trigger registration failed\n");
1211
1212	name = devm_kasprintf(chip->dev, GFP_KERNEL, "%s-opt4060",
1213			      dev_name(chip->dev));
1214	if (!name)
1215		return -ENOMEM;
1216
1217	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL, opt4060_irq_thread,
1218					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1219					name, idev);
1220	if (ret)
1221		return dev_err_probe(chip->dev, ret, "Could not request IRQ\n");
1222
1223	init_completion(&chip->completion);
1224
1225	ret = devm_mutex_init(chip->dev, &chip->irq_setting_lock);
1226	if (ret)
1227		return ret;
1228
1229	ret = devm_mutex_init(chip->dev, &chip->event_enabling_lock);
1230	if (ret)
1231		return ret;
1232
1233	ret = regmap_write_bits(chip->regmap, OPT4060_INT_CTRL,
1234				OPT4060_INT_CTRL_OUTPUT,
1235				OPT4060_INT_CTRL_OUTPUT);
1236	if (ret)
1237		return dev_err_probe(chip->dev, ret,
1238				     "Failed to set interrupt as output\n");
1239
1240	return 0;
1241}
1242
1243static int opt4060_probe(struct i2c_client *client)
1244{
1245	struct device *dev = &client->dev;
1246	struct opt4060_chip *chip;
1247	struct iio_dev *indio_dev;
1248	int ret;
1249	unsigned int regval, dev_id;
1250
1251	indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
1252	if (!indio_dev)
1253		return -ENOMEM;
1254
1255	chip = iio_priv(indio_dev);
1256
1257	ret = devm_regulator_get_enable(dev, "vdd");
1258	if (ret)
1259		return dev_err_probe(dev, ret, "Failed to enable vdd supply\n");
1260
1261	chip->regmap = devm_regmap_init_i2c(client, &opt4060_regmap_config);
1262	if (IS_ERR(chip->regmap))
1263		return dev_err_probe(dev, PTR_ERR(chip->regmap),
1264				     "regmap initialization failed\n");
1265
1266	chip->dev = dev;
1267	chip->irq = client->irq;
1268
1269	ret = regmap_reinit_cache(chip->regmap, &opt4060_regmap_config);
1270	if (ret)
1271		return dev_err_probe(dev, ret,
1272				     "failed to reinit regmap cache\n");
1273
1274	ret = regmap_read(chip->regmap, OPT4060_DEVICE_ID, &regval);
1275	if (ret < 0)
1276		return dev_err_probe(dev, ret,
1277			"Failed to read the device ID register\n");
1278
1279	dev_id = FIELD_GET(OPT4060_DEVICE_ID_MASK, regval);
1280	if (dev_id != OPT4060_DEVICE_ID_VAL)
1281		dev_info(dev, "Device ID: %#04x unknown\n", dev_id);
1282
1283	if (chip->irq) {
1284		indio_dev->info = &opt4060_info;
1285		indio_dev->channels = opt4060_channels;
1286		indio_dev->num_channels = ARRAY_SIZE(opt4060_channels);
1287	} else {
1288		indio_dev->info = &opt4060_info_no_irq;
1289		indio_dev->channels = opt4060_channels_no_events;
1290		indio_dev->num_channels = ARRAY_SIZE(opt4060_channels_no_events);
1291	}
1292	indio_dev->modes = INDIO_DIRECT_MODE;
1293	indio_dev->name = "opt4060";
1294
1295	ret = opt4060_load_defaults(chip);
1296	if (ret < 0)
1297		return dev_err_probe(dev, ret,
1298				     "Failed to set sensor defaults\n");
1299
1300	ret = devm_add_action_or_reset(dev, opt4060_chip_off_action, chip);
1301	if (ret < 0)
1302		return ret;
1303
1304	ret = opt4060_setup_buffer(chip, indio_dev);
1305	if (ret)
1306		return ret;
1307
1308	if (chip->irq) {
1309		ret = opt4060_setup_trigger(chip, indio_dev);
1310		if (ret)
1311			return ret;
1312	}
1313
1314	return devm_iio_device_register(dev, indio_dev);
1315}
1316
1317static const struct i2c_device_id opt4060_id[] = {
1318	{ "opt4060", },
1319	{ }
1320};
1321MODULE_DEVICE_TABLE(i2c, opt4060_id);
1322
1323static const struct of_device_id opt4060_of_match[] = {
1324	{ .compatible = "ti,opt4060" },
1325	{ }
1326};
1327MODULE_DEVICE_TABLE(of, opt4060_of_match);
1328
1329static struct i2c_driver opt4060_driver = {
1330	.driver = {
1331		.name = "opt4060",
1332		.of_match_table = opt4060_of_match,
1333	},
1334	.probe = opt4060_probe,
1335	.id_table = opt4060_id,
1336};
1337module_i2c_driver(opt4060_driver);
1338
1339MODULE_AUTHOR("Per-Daniel Olsson <perdaniel.olsson@axis.com>");
1340MODULE_DESCRIPTION("Texas Instruments OPT4060 RGBW color sensor driver");
1341MODULE_LICENSE("GPL");