adux1020.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
  4 *
  5 * Copyright (C) 2019 Linaro Ltd.
  6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7 *
  8 * TODO: Triggered buffer support
  9 */
 10
 11#include <linux/bitfield.h>
 12#include <linux/delay.h>
 13#include <linux/err.h>
 14#include <linux/i2c.h>
 15#include <linux/init.h>
 16#include <linux/interrupt.h>
 17#include <linux/irq.h>
 18#include <linux/module.h>
 19#include <linux/mutex.h>
 20#include <linux/regmap.h>
 21
 22#include <linux/iio/iio.h>
 23#include <linux/iio/sysfs.h>
 24#include <linux/iio/events.h>
 25
 26#define ADUX1020_DRV_NAME		"adux1020"
 27
 28/* System registers */
 29#define ADUX1020_REG_CHIP_ID		0x08
 30#define ADUX1020_REG_SLAVE_ADDRESS	0x09
 31
 32#define ADUX1020_REG_SW_RESET		0x0f
 33#define ADUX1020_REG_INT_ENABLE		0x1c
 34#define ADUX1020_REG_INT_POLARITY	0x1d
 35#define ADUX1020_REG_PROX_TH_ON1	0x2a
 36#define ADUX1020_REG_PROX_TH_OFF1	0x2b
 37#define	ADUX1020_REG_PROX_TYPE		0x2f
 38#define	ADUX1020_REG_TEST_MODES_3	0x32
 39#define	ADUX1020_REG_FORCE_MODE		0x33
 40#define	ADUX1020_REG_FREQUENCY		0x40
 41#define ADUX1020_REG_LED_CURRENT	0x41
 42#define	ADUX1020_REG_OP_MODE		0x45
 43#define	ADUX1020_REG_INT_MASK		0x48
 44#define	ADUX1020_REG_INT_STATUS		0x49
 45#define	ADUX1020_REG_DATA_BUFFER	0x60
 46
 47/* Chip ID bits */
 48#define ADUX1020_CHIP_ID_MASK		GENMASK(11, 0)
 49#define ADUX1020_CHIP_ID		0x03fc
 50
 51#define ADUX1020_SW_RESET		BIT(1)
 52#define ADUX1020_FIFO_FLUSH		BIT(15)
 53#define ADUX1020_OP_MODE_MASK		GENMASK(3, 0)
 54#define ADUX1020_DATA_OUT_MODE_MASK	GENMASK(7, 4)
 55#define ADUX1020_DATA_OUT_PROX_I	FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
 56
 57#define ADUX1020_MODE_INT_MASK		GENMASK(7, 0)
 58#define ADUX1020_INT_ENABLE		0x2094
 59#define ADUX1020_INT_DISABLE		0x2090
 60#define ADUX1020_PROX_INT_ENABLE	0x00f0
 61#define ADUX1020_PROX_ON1_INT		BIT(0)
 62#define ADUX1020_PROX_OFF1_INT		BIT(1)
 63#define ADUX1020_FIFO_INT_ENABLE	0x7f
 64#define ADUX1020_MODE_INT_DISABLE	0xff
 65#define ADUX1020_MODE_INT_STATUS_MASK	GENMASK(7, 0)
 66#define ADUX1020_FIFO_STATUS_MASK	GENMASK(15, 8)
 67#define ADUX1020_INT_CLEAR		0xff
 68#define ADUX1020_PROX_TYPE		BIT(15)
 69
 70#define ADUX1020_INT_PROX_ON1		BIT(0)
 71#define ADUX1020_INT_PROX_OFF1		BIT(1)
 72
 73#define ADUX1020_FORCE_CLOCK_ON		0x0f4f
 74#define ADUX1020_FORCE_CLOCK_RESET	0x0040
 75#define ADUX1020_ACTIVE_4_STATE		0x0008
 76
 77#define ADUX1020_PROX_FREQ_MASK		GENMASK(7, 4)
 78#define ADUX1020_PROX_FREQ(x)		FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
 79
 80#define ADUX1020_LED_CURRENT_MASK	GENMASK(3, 0)
 81#define ADUX1020_LED_PIREF_EN		BIT(12)
 82
 83/* Operating modes */
 84enum adux1020_op_modes {
 85	ADUX1020_MODE_STANDBY,
 86	ADUX1020_MODE_PROX_I,
 87	ADUX1020_MODE_PROX_XY,
 88	ADUX1020_MODE_GEST,
 89	ADUX1020_MODE_SAMPLE,
 90	ADUX1020_MODE_FORCE = 0x0e,
 91	ADUX1020_MODE_IDLE = 0x0f,
 92};
 93
 94struct adux1020_data {
 95	struct i2c_client *client;
 96	struct iio_dev *indio_dev;
 97	struct mutex lock;
 98	struct regmap *regmap;
 99};
100
101struct adux1020_mode_data {
102	u8 bytes;
103	u8 buf_len;
104	u16 int_en;
105};
106
107static const struct adux1020_mode_data adux1020_modes[] = {
108	[ADUX1020_MODE_PROX_I] = {
109		.bytes = 2,
110		.buf_len = 1,
111		.int_en = ADUX1020_PROX_INT_ENABLE,
112	},
113};
114
115static const struct regmap_config adux1020_regmap_config = {
116	.name = "adux1020_regmap",
117	.reg_bits = 8,
118	.val_bits = 16,
119	.max_register = 0x6F,
120};
121
122static const struct reg_sequence adux1020_def_conf[] = {
123	{ 0x000c, 0x000f },
124	{ 0x0010, 0x1010 },
125	{ 0x0011, 0x004c },
126	{ 0x0012, 0x5f0c },
127	{ 0x0013, 0xada5 },
128	{ 0x0014, 0x0080 },
129	{ 0x0015, 0x0000 },
130	{ 0x0016, 0x0600 },
131	{ 0x0017, 0x0000 },
132	{ 0x0018, 0x2693 },
133	{ 0x0019, 0x0004 },
134	{ 0x001a, 0x4280 },
135	{ 0x001b, 0x0060 },
136	{ 0x001c, 0x2094 },
137	{ 0x001d, 0x0020 },
138	{ 0x001e, 0x0001 },
139	{ 0x001f, 0x0100 },
140	{ 0x0020, 0x0320 },
141	{ 0x0021, 0x0A13 },
142	{ 0x0022, 0x0320 },
143	{ 0x0023, 0x0113 },
144	{ 0x0024, 0x0000 },
145	{ 0x0025, 0x2412 },
146	{ 0x0026, 0x2412 },
147	{ 0x0027, 0x0022 },
148	{ 0x0028, 0x0000 },
149	{ 0x0029, 0x0300 },
150	{ 0x002a, 0x0700 },
151	{ 0x002b, 0x0600 },
152	{ 0x002c, 0x6000 },
153	{ 0x002d, 0x4000 },
154	{ 0x002e, 0x0000 },
155	{ 0x002f, 0x0000 },
156	{ 0x0030, 0x0000 },
157	{ 0x0031, 0x0000 },
158	{ 0x0032, 0x0040 },
159	{ 0x0033, 0x0008 },
160	{ 0x0034, 0xE400 },
161	{ 0x0038, 0x8080 },
162	{ 0x0039, 0x8080 },
163	{ 0x003a, 0x2000 },
164	{ 0x003b, 0x1f00 },
165	{ 0x003c, 0x2000 },
166	{ 0x003d, 0x2000 },
167	{ 0x003e, 0x0000 },
168	{ 0x0040, 0x8069 },
169	{ 0x0041, 0x1f2f },
170	{ 0x0042, 0x4000 },
171	{ 0x0043, 0x0000 },
172	{ 0x0044, 0x0008 },
173	{ 0x0046, 0x0000 },
174	{ 0x0048, 0x00ef },
175	{ 0x0049, 0x0000 },
176	{ 0x0045, 0x0000 },
177};
178
179static const int adux1020_rates[][2] = {
180	{ 0, 100000 },
181	{ 0, 200000 },
182	{ 0, 500000 },
183	{ 1, 0 },
184	{ 2, 0 },
185	{ 5, 0 },
186	{ 10, 0 },
187	{ 20, 0 },
188	{ 50, 0 },
189	{ 100, 0 },
190	{ 190, 0 },
191	{ 450, 0 },
192	{ 820, 0 },
193	{ 1400, 0 },
194};
195
196static const int adux1020_led_currents[][2] = {
197	{ 0, 25000 },
198	{ 0, 40000 },
199	{ 0, 55000 },
200	{ 0, 70000 },
201	{ 0, 85000 },
202	{ 0, 100000 },
203	{ 0, 115000 },
204	{ 0, 130000 },
205	{ 0, 145000 },
206	{ 0, 160000 },
207	{ 0, 175000 },
208	{ 0, 190000 },
209	{ 0, 205000 },
210	{ 0, 220000 },
211	{ 0, 235000 },
212	{ 0, 250000 },
213};
214
215static int adux1020_flush_fifo(struct adux1020_data *data)
216{
217	int ret;
218
219	/* Force Idle mode */
220	ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
221			   ADUX1020_ACTIVE_4_STATE);
222	if (ret < 0)
223		return ret;
224
225	ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
226				 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
227	if (ret < 0)
228		return ret;
229
230	ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
231				 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
232	if (ret < 0)
233		return ret;
234
235	/* Flush FIFO */
236	ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
237			   ADUX1020_FORCE_CLOCK_ON);
238	if (ret < 0)
239		return ret;
240
241	ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
242			   ADUX1020_FIFO_FLUSH);
243	if (ret < 0)
244		return ret;
245
246	return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
247			    ADUX1020_FORCE_CLOCK_RESET);
248}
249
250static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
251{
252	unsigned int regval;
253	int i, ret;
254
255	/* Enable 32MHz clock */
256	ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
257			   ADUX1020_FORCE_CLOCK_ON);
258	if (ret < 0)
259		return ret;
260
261	for (i = 0; i < buf_len; i++) {
262		ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
263				  &regval);
264		if (ret < 0)
265			return ret;
266
267		buf[i] = regval;
268	}
269
270	/* Set 32MHz clock to be controlled by internal state machine */
271	return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
272			    ADUX1020_FORCE_CLOCK_RESET);
273}
274
275static int adux1020_set_mode(struct adux1020_data *data,
276			     enum adux1020_op_modes mode)
277{
278	int ret;
279
280	/* Switch to standby mode before changing the mode */
281	ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
282			   ADUX1020_MODE_STANDBY);
283	if (ret < 0)
284		return ret;
285
286	/* Set data out and switch to the desired mode */
287	switch (mode) {
288	case ADUX1020_MODE_PROX_I:
289		ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
290					 ADUX1020_DATA_OUT_MODE_MASK,
291					 ADUX1020_DATA_OUT_PROX_I);
292		if (ret < 0)
293			return ret;
294
295		ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
296					 ADUX1020_OP_MODE_MASK,
297					 ADUX1020_MODE_PROX_I);
298		if (ret < 0)
299			return ret;
300		break;
301	default:
302		return -EINVAL;
303	}
304
305	return 0;
306}
307
308static int adux1020_measure(struct adux1020_data *data,
309			    enum adux1020_op_modes mode,
310			    u16 *val)
311{
312	unsigned int status;
313	int ret, tries = 50;
314
315	/* Disable INT pin as polling is going to be used */
316	ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
317			   ADUX1020_INT_DISABLE);
318	if (ret < 0)
319		return ret;
320
321	/* Enable mode interrupt */
322	ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
323				 ADUX1020_MODE_INT_MASK,
324				 adux1020_modes[mode].int_en);
325	if (ret < 0)
326		return ret;
327
328	while (tries--) {
329		ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
330				  &status);
331		if (ret < 0)
332			return ret;
333
334		status &= ADUX1020_FIFO_STATUS_MASK;
335		if (status >= adux1020_modes[mode].bytes)
336			break;
337		msleep(20);
338	}
339
340	if (tries < 0)
341		return -EIO;
342
343	ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
344	if (ret < 0)
345		return ret;
346
347	/* Clear mode interrupt */
348	ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
349			   (~adux1020_modes[mode].int_en));
350	if (ret < 0)
351		return ret;
352
353	/* Disable mode interrupts */
354	return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
355				  ADUX1020_MODE_INT_MASK,
356				  ADUX1020_MODE_INT_DISABLE);
357}
358
359static int adux1020_read_raw(struct iio_dev *indio_dev,
360			     struct iio_chan_spec const *chan,
361			     int *val, int *val2, long mask)
362{
363	struct adux1020_data *data = iio_priv(indio_dev);
364	u16 buf[3];
365	int ret = -EINVAL;
366	unsigned int regval;
367
368	mutex_lock(&data->lock);
369
370	switch (mask) {
371	case IIO_CHAN_INFO_RAW:
372		switch (chan->type) {
373		case IIO_PROXIMITY:
374			ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
375			if (ret < 0)
376				goto fail;
377
378			ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
379			if (ret < 0)
380				goto fail;
381
382			*val = buf[0];
383			ret = IIO_VAL_INT;
384			break;
385		default:
386			break;
387		}
388		break;
389	case IIO_CHAN_INFO_PROCESSED:
390		switch (chan->type) {
391		case IIO_CURRENT:
392			ret = regmap_read(data->regmap,
393					  ADUX1020_REG_LED_CURRENT, &regval);
394			if (ret < 0)
395				goto fail;
396
397			regval = regval & ADUX1020_LED_CURRENT_MASK;
398
399			*val = adux1020_led_currents[regval][0];
400			*val2 = adux1020_led_currents[regval][1];
401
402			ret = IIO_VAL_INT_PLUS_MICRO;
403			break;
404		default:
405			break;
406		}
407		break;
408	case IIO_CHAN_INFO_SAMP_FREQ:
409		switch (chan->type) {
410		case IIO_PROXIMITY:
411			ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
412					  &regval);
413			if (ret < 0)
414				goto fail;
415
416			regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
417
418			*val = adux1020_rates[regval][0];
419			*val2 = adux1020_rates[regval][1];
420
421			ret = IIO_VAL_INT_PLUS_MICRO;
422			break;
423		default:
424			break;
425		}
426		break;
427	default:
428		break;
429	}
430
431fail:
432	mutex_unlock(&data->lock);
433
434	return ret;
435};
436
437static inline int adux1020_find_index(const int array[][2], int count, int val,
438				      int val2)
439{
440	int i;
441
442	for (i = 0; i < count; i++)
443		if (val == array[i][0] && val2 == array[i][1])
444			return i;
445
446	return -EINVAL;
447}
448
449static int adux1020_write_raw(struct iio_dev *indio_dev,
450			      struct iio_chan_spec const *chan,
451			      int val, int val2, long mask)
452{
453	struct adux1020_data *data = iio_priv(indio_dev);
454	int i, ret = -EINVAL;
455
456	mutex_lock(&data->lock);
457
458	switch (mask) {
459	case IIO_CHAN_INFO_SAMP_FREQ:
460		if (chan->type == IIO_PROXIMITY) {
461			i = adux1020_find_index(adux1020_rates,
462						ARRAY_SIZE(adux1020_rates),
463						val, val2);
464			if (i < 0) {
465				ret = i;
466				goto fail;
467			}
468
469			ret = regmap_update_bits(data->regmap,
470						 ADUX1020_REG_FREQUENCY,
471						 ADUX1020_PROX_FREQ_MASK,
472						 ADUX1020_PROX_FREQ(i));
473		}
474		break;
475	case IIO_CHAN_INFO_PROCESSED:
476		if (chan->type == IIO_CURRENT) {
477			i = adux1020_find_index(adux1020_led_currents,
478					ARRAY_SIZE(adux1020_led_currents),
479					val, val2);
480			if (i < 0) {
481				ret = i;
482				goto fail;
483			}
484
485			ret = regmap_update_bits(data->regmap,
486						 ADUX1020_REG_LED_CURRENT,
487						 ADUX1020_LED_CURRENT_MASK, i);
488		}
489		break;
490	default:
491		break;
492	}
493
494fail:
495	mutex_unlock(&data->lock);
496
497	return ret;
498}
499
500static int adux1020_write_event_config(struct iio_dev *indio_dev,
501				       const struct iio_chan_spec *chan,
502				       enum iio_event_type type,
503				       enum iio_event_direction dir,
504				       bool state)
505{
506	struct adux1020_data *data = iio_priv(indio_dev);
507	int ret, mask;
508
509	mutex_lock(&data->lock);
510
511	ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
512			   ADUX1020_INT_ENABLE);
513	if (ret < 0)
514		goto fail;
515
516	ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
517	if (ret < 0)
518		goto fail;
519
520	switch (chan->type) {
521	case IIO_PROXIMITY:
522		if (dir == IIO_EV_DIR_RISING)
523			mask = ADUX1020_PROX_ON1_INT;
524		else
525			mask = ADUX1020_PROX_OFF1_INT;
526
527		if (state)
528			ret = regmap_clear_bits(data->regmap,
529						ADUX1020_REG_INT_MASK, mask);
530		else
531			ret = regmap_set_bits(data->regmap,
532					      ADUX1020_REG_INT_MASK, mask);
533		if (ret < 0)
534			goto fail;
535
536		/*
537		 * Trigger proximity interrupt when the intensity is above
538		 * or below threshold
539		 */
540		ret = regmap_set_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
541				      ADUX1020_PROX_TYPE);
542		if (ret < 0)
543			goto fail;
544
545		/* Set proximity mode */
546		ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
547		break;
548	default:
549		ret = -EINVAL;
550		break;
551	}
552
553fail:
554	mutex_unlock(&data->lock);
555
556	return ret;
557}
558
559static int adux1020_read_event_config(struct iio_dev *indio_dev,
560				      const struct iio_chan_spec *chan,
561				      enum iio_event_type type,
562				      enum iio_event_direction dir)
563{
564	struct adux1020_data *data = iio_priv(indio_dev);
565	int ret, mask;
566	unsigned int regval;
567
568	switch (chan->type) {
569	case IIO_PROXIMITY:
570		if (dir == IIO_EV_DIR_RISING)
571			mask = ADUX1020_PROX_ON1_INT;
572		else
573			mask = ADUX1020_PROX_OFF1_INT;
574		break;
575	default:
576		return -EINVAL;
577	}
578
579	ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, &regval);
580	if (ret < 0)
581		return ret;
582
583	return !(regval & mask);
584}
585
586static int adux1020_read_thresh(struct iio_dev *indio_dev,
587				const struct iio_chan_spec *chan,
588				enum iio_event_type type,
589				enum iio_event_direction dir,
590				enum iio_event_info info, int *val, int *val2)
591{
592	struct adux1020_data *data = iio_priv(indio_dev);
593	u8 reg;
594	int ret;
595	unsigned int regval;
596
597	switch (chan->type) {
598	case IIO_PROXIMITY:
599		if (dir == IIO_EV_DIR_RISING)
600			reg = ADUX1020_REG_PROX_TH_ON1;
601		else
602			reg = ADUX1020_REG_PROX_TH_OFF1;
603		break;
604	default:
605		return -EINVAL;
606	}
607
608	ret = regmap_read(data->regmap, reg, &regval);
609	if (ret < 0)
610		return ret;
611
612	*val = regval;
613
614	return IIO_VAL_INT;
615}
616
617static int adux1020_write_thresh(struct iio_dev *indio_dev,
618				 const struct iio_chan_spec *chan,
619				 enum iio_event_type type,
620				 enum iio_event_direction dir,
621				 enum iio_event_info info, int val, int val2)
622{
623	struct adux1020_data *data = iio_priv(indio_dev);
624	u8 reg;
625
626	switch (chan->type) {
627	case IIO_PROXIMITY:
628		if (dir == IIO_EV_DIR_RISING)
629			reg = ADUX1020_REG_PROX_TH_ON1;
630		else
631			reg = ADUX1020_REG_PROX_TH_OFF1;
632		break;
633	default:
634		return -EINVAL;
635	}
636
637	/* Full scale threshold value is 0-65535  */
638	if (val < 0 || val > 65535)
639		return -EINVAL;
640
641	return regmap_write(data->regmap, reg, val);
642}
643
644static const struct iio_event_spec adux1020_proximity_event[] = {
645	{
646		.type = IIO_EV_TYPE_THRESH,
647		.dir = IIO_EV_DIR_RISING,
648		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
649			BIT(IIO_EV_INFO_ENABLE),
650	},
651	{
652		.type = IIO_EV_TYPE_THRESH,
653		.dir = IIO_EV_DIR_FALLING,
654		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
655			BIT(IIO_EV_INFO_ENABLE),
656	},
657};
658
659static const struct iio_chan_spec adux1020_channels[] = {
660	{
661		.type = IIO_PROXIMITY,
662		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
663				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
664		.event_spec = adux1020_proximity_event,
665		.num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
666	},
667	{
668		.type = IIO_CURRENT,
669		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
670		.extend_name = "led",
671		.output = 1,
672	},
673};
674
675static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
676		      "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
677
678static struct attribute *adux1020_attributes[] = {
679	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
680	NULL
681};
682
683static const struct attribute_group adux1020_attribute_group = {
684	.attrs = adux1020_attributes,
685};
686
687static const struct iio_info adux1020_info = {
688	.attrs = &adux1020_attribute_group,
689	.read_raw = adux1020_read_raw,
690	.write_raw = adux1020_write_raw,
691	.read_event_config = adux1020_read_event_config,
692	.write_event_config = adux1020_write_event_config,
693	.read_event_value = adux1020_read_thresh,
694	.write_event_value = adux1020_write_thresh,
695};
696
697static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
698{
699	struct iio_dev *indio_dev = private;
700	struct adux1020_data *data = iio_priv(indio_dev);
701	int ret, status;
702
703	ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
704	if (ret < 0)
705		return IRQ_HANDLED;
706
707	status &= ADUX1020_MODE_INT_STATUS_MASK;
708
709	if (status & ADUX1020_INT_PROX_ON1) {
710		iio_push_event(indio_dev,
711			       IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
712						    IIO_EV_TYPE_THRESH,
713						    IIO_EV_DIR_RISING),
714			       iio_get_time_ns(indio_dev));
715	}
716
717	if (status & ADUX1020_INT_PROX_OFF1) {
718		iio_push_event(indio_dev,
719			       IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
720						    IIO_EV_TYPE_THRESH,
721						    IIO_EV_DIR_FALLING),
722			       iio_get_time_ns(indio_dev));
723	}
724
725	regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
726			   ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
727
728	return IRQ_HANDLED;
729}
730
731static int adux1020_chip_init(struct adux1020_data *data)
732{
733	struct i2c_client *client = data->client;
734	int ret;
735	unsigned int val;
736
737	ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
738	if (ret < 0)
739		return ret;
740
741	if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
742		dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
743		return -ENODEV;
744	}
745
746	dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
747
748	ret = regmap_set_bits(data->regmap, ADUX1020_REG_SW_RESET,
749			      ADUX1020_SW_RESET);
750	if (ret < 0)
751		return ret;
752
753	/* Load default configuration */
754	ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
755				     ARRAY_SIZE(adux1020_def_conf));
756	if (ret < 0)
757		return ret;
758
759	ret = adux1020_flush_fifo(data);
760	if (ret < 0)
761		return ret;
762
763	/* Use LED_IREF for proximity mode */
764	ret = regmap_clear_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
765				ADUX1020_LED_PIREF_EN);
766	if (ret < 0)
767		return ret;
768
769	/* Mask all interrupts */
770	return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
771			   ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
772}
773
774static int adux1020_probe(struct i2c_client *client)
775{
776	struct adux1020_data *data;
777	struct iio_dev *indio_dev;
778	int ret;
779
780	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
781	if (!indio_dev)
782		return -ENOMEM;
783
784	indio_dev->info = &adux1020_info;
785	indio_dev->name = ADUX1020_DRV_NAME;
786	indio_dev->channels = adux1020_channels;
787	indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
788	indio_dev->modes = INDIO_DIRECT_MODE;
789
790	data = iio_priv(indio_dev);
791
792	data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
793	if (IS_ERR(data->regmap)) {
794		dev_err(&client->dev, "regmap initialization failed.\n");
795		return PTR_ERR(data->regmap);
796	}
797
798	data->client = client;
799	data->indio_dev = indio_dev;
800	mutex_init(&data->lock);
801
802	ret = adux1020_chip_init(data);
803	if (ret)
804		return ret;
805
806	if (client->irq) {
807		ret = devm_request_threaded_irq(&client->dev, client->irq,
808					NULL, adux1020_interrupt_handler,
809					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
810					ADUX1020_DRV_NAME, indio_dev);
811		if (ret) {
812			dev_err(&client->dev, "irq request error %d\n", -ret);
813			return ret;
814		}
815	}
816
817	return devm_iio_device_register(&client->dev, indio_dev);
818}
819
820static const struct i2c_device_id adux1020_id[] = {
821	{ "adux1020" },
822	{ }
823};
824MODULE_DEVICE_TABLE(i2c, adux1020_id);
825
826static const struct of_device_id adux1020_of_match[] = {
827	{ .compatible = "adi,adux1020" },
828	{ }
829};
830MODULE_DEVICE_TABLE(of, adux1020_of_match);
831
832static struct i2c_driver adux1020_driver = {
833	.driver = {
834		.name	= ADUX1020_DRV_NAME,
835		.of_match_table = adux1020_of_match,
836	},
837	.probe		= adux1020_probe,
838	.id_table	= adux1020_id,
839};
840module_i2c_driver(adux1020_driver);
841
842MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
843MODULE_DESCRIPTION("ADUX1020 photometric sensor");
844MODULE_LICENSE("GPL");