inv_mpu_iio.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3* Copyright (C) 2012 Invensense, Inc.
  4*/
  5
  6#ifndef INV_MPU_IIO_H_
  7#define INV_MPU_IIO_H_
  8
  9#include <linux/i2c.h>
 10#include <linux/i2c-mux.h>
 11#include <linux/mutex.h>
 12#include <linux/platform_data/invensense_mpu6050.h>
 13#include <linux/regmap.h>
 14
 15#include <linux/iio/buffer.h>
 16#include <linux/iio/common/inv_sensors_timestamp.h>
 17#include <linux/iio/iio.h>
 18#include <linux/iio/kfifo_buf.h>
 19#include <linux/iio/trigger.h>
 20#include <linux/iio/triggered_buffer.h>
 21#include <linux/iio/trigger_consumer.h>
 22#include <linux/iio/sysfs.h>
 23
 24/**
 25 *  struct inv_mpu6050_reg_map - Notable registers.
 26 *  @sample_rate_div:	Divider applied to gyro output rate.
 27 *  @lpf:		Configures internal low pass filter.
 28 *  @accel_lpf:		Configures accelerometer low pass filter.
 29 *  @user_ctrl:		Enables/resets the FIFO.
 30 *  @fifo_en:		Determines which data will appear in FIFO.
 31 *  @gyro_config:	gyro config register.
 32 *  @accl_config:	accel config register
 33 *  @fifo_count_h:	Upper byte of FIFO count.
 34 *  @fifo_r_w:		FIFO register.
 35 *  @raw_gyro:		Address of first gyro register.
 36 *  @raw_accl:		Address of first accel register.
 37 *  @temperature:	temperature register
 38 *  @int_enable:	Interrupt enable register.
 39 *  @int_status:	Interrupt status register.
 40 *  @pwr_mgmt_1:	Controls chip's power state and clock source.
 41 *  @pwr_mgmt_2:	Controls power state of individual sensors.
 42 *  @int_pin_cfg;	Controls interrupt pin configuration.
 43 *  @accl_offset:	Controls the accelerometer calibration offset.
 44 *  @gyro_offset:	Controls the gyroscope calibration offset.
 45 *  @i2c_if:		Controls the i2c interface
 46 */
 47struct inv_mpu6050_reg_map {
 48	u8 sample_rate_div;
 49	u8 lpf;
 50	u8 accel_lpf;
 51	u8 user_ctrl;
 52	u8 fifo_en;
 53	u8 gyro_config;
 54	u8 accl_config;
 55	u8 fifo_count_h;
 56	u8 fifo_r_w;
 57	u8 raw_gyro;
 58	u8 raw_accl;
 59	u8 temperature;
 60	u8 int_enable;
 61	u8 int_status;
 62	u8 pwr_mgmt_1;
 63	u8 pwr_mgmt_2;
 64	u8 int_pin_cfg;
 65	u8 accl_offset;
 66	u8 gyro_offset;
 67	u8 i2c_if;
 68};
 69
 70/*device enum */
 71enum inv_devices {
 72	INV_MPU6050,
 73	INV_MPU6500,
 74	INV_MPU6515,
 75	INV_MPU6880,
 76	INV_MPU6000,
 77	INV_MPU9150,
 78	INV_MPU9250,
 79	INV_MPU9255,
 80	INV_ICM20608,
 81	INV_ICM20608D,
 82	INV_ICM20609,
 83	INV_ICM20689,
 84	INV_ICM20600,
 85	INV_ICM20602,
 86	INV_ICM20690,
 87	INV_IAM20380,
 88	INV_IAM20680,
 89	INV_IAM20680HP,
 90	INV_IAM20680HT,
 91	INV_NUM_PARTS
 92};
 93
 94/* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer, WoM */
 95#define INV_MPU6050_SENSOR_ACCL		BIT(0)
 96#define INV_MPU6050_SENSOR_GYRO		BIT(1)
 97#define INV_MPU6050_SENSOR_TEMP		BIT(2)
 98#define INV_MPU6050_SENSOR_MAGN		BIT(3)
 99#define INV_MPU6050_SENSOR_WOM		BIT(4)
100
101/**
102 *  struct inv_mpu6050_chip_config - Cached chip configuration data.
103 *  @clk:		selected chip clock
104 *  @fsr:		Full scale range.
105 *  @lpf:		Digital low pass filter frequency.
106 *  @accl_fs:		accel full scale range.
107 *  @accl_en:		accel engine enabled
108 *  @gyro_en:		gyro engine enabled
109 *  @temp_en:		temperature sensor enabled
110 *  @magn_en:		magn engine (i2c master) enabled
111 *  @wom_en:		Wake-on-Motion enabled
112 *  @accl_fifo_enable:	enable accel data output
113 *  @gyro_fifo_enable:	enable gyro data output
114 *  @temp_fifo_enable:	enable temp data output
115 *  @magn_fifo_enable:	enable magn data output
116 *  @divider:		chip sample rate divider (sample rate divider - 1)
117 *  @roc_threshold:	save ROC threshold (WoM) set value
118 */
119struct inv_mpu6050_chip_config {
120	unsigned int clk:3;
121	unsigned int fsr:2;
122	unsigned int lpf:3;
123	unsigned int accl_fs:2;
124	unsigned int accl_en:1;
125	unsigned int gyro_en:1;
126	unsigned int temp_en:1;
127	unsigned int magn_en:1;
128	unsigned int wom_en:1;
129	unsigned int accl_fifo_enable:1;
130	unsigned int gyro_fifo_enable:1;
131	unsigned int temp_fifo_enable:1;
132	unsigned int magn_fifo_enable:1;
133	u8 divider;
134	u8 user_ctrl;
135	u64 roc_threshold;
136};
137
138/*
139 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
140 * May be less if fewer channels are enabled, as long as the timestamp
141 * remains 8 byte aligned
142 */
143#define INV_MPU6050_OUTPUT_DATA_SIZE         32
144
145/**
146 *  struct inv_mpu6050_hw - Other important hardware information.
147 *  @whoami:	Self identification byte from WHO_AM_I register
148 *  @name:      name of the chip.
149 *  @reg:   register map of the chip.
150 *  @config:    configuration of the chip.
151 *  @fifo_size:	size of the FIFO in bytes.
152 *  @temp:	offset and scale to apply to raw temperature.
153 */
154struct inv_mpu6050_hw {
155	u8 whoami;
156	u8 *name;
157	const struct inv_mpu6050_reg_map *reg;
158	const struct inv_mpu6050_chip_config *config;
159	size_t fifo_size;
160	struct {
161		int offset;
162		int scale;
163	} temp;
164	struct {
165		unsigned int accel;
166		unsigned int gyro;
167	} startup_time;
168};
169
170/*
171 *  struct inv_mpu6050_state - Driver state variables.
172 *  @lock:              Chip access lock.
173 *  @trig:              IIO trigger.
174 *  @chip_config:	Cached attribute information.
175 *  @reg:		Map of important registers.
176 *  @hw:		Other hardware-specific information.
177 *  @chip_type:		chip type.
178 *  @plat_data:		platform data (deprecated in favor of @orientation).
179 *  @orientation:	sensor chip orientation relative to main hardware.
180 *  @map		regmap pointer.
181 *  @irq		interrupt number.
182 *  @irq_mask		the int_pin_cfg mask to configure interrupt type.
183 *  @timestamp:		timestamping module
184 *  @vdd_supply:	VDD voltage regulator for the chip.
185 *  @vddio_supply	I/O voltage regulator for the chip.
186 *  @magn_disabled:     magnetometer disabled for backward compatibility reason.
187 *  @magn_raw_to_gauss:	coefficient to convert mag raw value to Gauss.
188 *  @magn_orient:       magnetometer sensor chip orientation if available.
189 *  @suspended_sensors:	sensors mask of sensors turned off for suspend
190 *  @data:		read buffer used for bulk reads.
191 *  @it_timestamp:	interrupt timestamp.
192 */
193struct inv_mpu6050_state {
194	struct mutex lock;
195	struct iio_trigger  *trig;
196	struct inv_mpu6050_chip_config chip_config;
197	const struct inv_mpu6050_reg_map *reg;
198	const struct inv_mpu6050_hw *hw;
199	enum   inv_devices chip_type;
200	struct i2c_mux_core *muxc;
201	struct i2c_client *mux_client;
202	struct inv_mpu6050_platform_data plat_data;
203	struct iio_mount_matrix orientation;
204	struct regmap *map;
205	int irq;
206	u8 irq_mask;
207	unsigned skip_samples;
208	struct inv_sensors_timestamp timestamp;
209	struct regulator *vdd_supply;
210	struct regulator *vddio_supply;
211	bool magn_disabled;
212	s32 magn_raw_to_gauss[3];
213	struct iio_mount_matrix magn_orient;
214	unsigned int suspended_sensors;
215	bool level_shifter;
216	u8 *data;
217	s64 it_timestamp;
218};
219
220/*register and associated bit definition*/
221#define INV_MPU6050_REG_ACCEL_OFFSET        0x06
222#define INV_MPU6050_REG_GYRO_OFFSET         0x13
223
224#define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
225#define INV_MPU6050_REG_CONFIG              0x1A
226#define INV_MPU6050_REG_GYRO_CONFIG         0x1B
227#define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
228
229#define INV_MPU6050_REG_FIFO_EN             0x23
230#define INV_MPU6050_BIT_SLAVE_0             0x01
231#define INV_MPU6050_BIT_SLAVE_1             0x02
232#define INV_MPU6050_BIT_SLAVE_2             0x04
233#define INV_MPU6050_BIT_ACCEL_OUT           0x08
234#define INV_MPU6050_BITS_GYRO_OUT           0x70
235#define INV_MPU6050_BIT_TEMP_OUT            0x80
236
237#define INV_MPU6050_REG_I2C_MST_CTRL        0x24
238#define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
239#define INV_MPU6050_BIT_I2C_MST_P_NSR       0x10
240#define INV_MPU6050_BIT_SLV3_FIFO_EN        0x20
241#define INV_MPU6050_BIT_WAIT_FOR_ES         0x40
242#define INV_MPU6050_BIT_MULT_MST_EN         0x80
243
244/* control I2C slaves from 0 to 3 */
245#define INV_MPU6050_REG_I2C_SLV_ADDR(_x)    (0x25 + 3 * (_x))
246#define INV_MPU6050_BIT_I2C_SLV_RNW         0x80
247
248#define INV_MPU6050_REG_I2C_SLV_REG(_x)     (0x26 + 3 * (_x))
249
250#define INV_MPU6050_REG_I2C_SLV_CTRL(_x)    (0x27 + 3 * (_x))
251#define INV_MPU6050_BIT_SLV_GRP             0x10
252#define INV_MPU6050_BIT_SLV_REG_DIS         0x20
253#define INV_MPU6050_BIT_SLV_BYTE_SW         0x40
254#define INV_MPU6050_BIT_SLV_EN              0x80
255
256/* I2C master delay register */
257#define INV_MPU6050_REG_I2C_SLV4_CTRL       0x34
258#define INV_MPU6050_BITS_I2C_MST_DLY(_x)    ((_x) & 0x1F)
259
260#define INV_MPU6050_REG_I2C_MST_STATUS      0x36
261#define INV_MPU6050_BIT_I2C_SLV0_NACK       0x01
262#define INV_MPU6050_BIT_I2C_SLV1_NACK       0x02
263#define INV_MPU6050_BIT_I2C_SLV2_NACK       0x04
264#define INV_MPU6050_BIT_I2C_SLV3_NACK       0x08
265
266#define INV_MPU6050_REG_INT_ENABLE          0x38
267#define INV_MPU6050_BIT_DATA_RDY_EN         0x01
268#define INV_MPU6050_BIT_DMP_INT_EN          0x02
269#define INV_MPU6500_BIT_WOM_INT_EN          BIT(6)
270#define INV_ICM20608_BIT_WOM_INT_EN         GENMASK(7, 5)
271
272#define INV_MPU6050_REG_RAW_ACCEL           0x3B
273#define INV_MPU6050_REG_TEMPERATURE         0x41
274#define INV_MPU6050_REG_RAW_GYRO            0x43
275
276#define INV_MPU6050_REG_INT_STATUS          0x3A
277#define INV_MPU6500_BIT_WOM_INT             BIT(6)
278#define INV_ICM20608_BIT_WOM_INT            GENMASK(7, 5)
279#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
280#define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
281
282#define INV_MPU6050_REG_EXT_SENS_DATA       0x49
283
284/* I2C slaves data output from 0 to 3 */
285#define INV_MPU6050_REG_I2C_SLV_DO(_x)      (0x63 + (_x))
286
287#define INV_MPU6050_REG_I2C_MST_DELAY_CTRL  0x67
288#define INV_MPU6050_BIT_I2C_SLV0_DLY_EN     0x01
289#define INV_MPU6050_BIT_I2C_SLV1_DLY_EN     0x02
290#define INV_MPU6050_BIT_I2C_SLV2_DLY_EN     0x04
291#define INV_MPU6050_BIT_I2C_SLV3_DLY_EN     0x08
292#define INV_MPU6050_BIT_DELAY_ES_SHADOW     0x80
293
294#define INV_MPU6050_REG_SIGNAL_PATH_RESET   0x68
295#define INV_MPU6050_BIT_TEMP_RST            BIT(0)
296#define INV_MPU6050_BIT_ACCEL_RST           BIT(1)
297#define INV_MPU6050_BIT_GYRO_RST            BIT(2)
298
299#define INV_MPU6050_REG_USER_CTRL           0x6A
300#define INV_MPU6050_BIT_SIG_COND_RST        0x01
301#define INV_MPU6050_BIT_FIFO_RST            0x04
302#define INV_MPU6050_BIT_DMP_RST             0x08
303#define INV_MPU6050_BIT_I2C_MST_EN          0x20
304#define INV_MPU6050_BIT_FIFO_EN             0x40
305#define INV_MPU6050_BIT_DMP_EN              0x80
306#define INV_MPU6050_BIT_I2C_IF_DIS          0x10
307
308#define INV_MPU6050_REG_PWR_MGMT_1          0x6B
309#define INV_MPU6050_BIT_H_RESET             0x80
310#define INV_MPU6050_BIT_SLEEP               0x40
311#define INV_MPU6050_BIT_CYCLE               0x20
312#define INV_MPU6050_BIT_TEMP_DIS            0x08
313#define INV_MPU6050_BIT_CLK_MASK            0x7
314
315#define INV_MPU6050_REG_PWR_MGMT_2          0x6C
316#define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
317#define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
318
319/* ICM20609 registers */
320#define INV_ICM20609_REG_ACCEL_WOM_X_THR    0x20
321#define INV_ICM20609_REG_ACCEL_WOM_Y_THR    0x21
322#define INV_ICM20609_REG_ACCEL_WOM_Z_THR    0x22
323
324/* ICM20602 register */
325#define INV_ICM20602_REG_I2C_IF             0x70
326#define INV_ICM20602_BIT_I2C_IF_DIS         0x40
327
328#define INV_MPU6050_REG_FIFO_COUNT_H        0x72
329#define INV_MPU6050_REG_FIFO_R_W            0x74
330
331#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
332#define INV_MPU6050_FIFO_COUNT_BYTE          2
333
334/* MPU9X50 9-axis magnetometer */
335#define INV_MPU9X50_BYTES_MAGN               7
336
337/* FIFO temperature sample size */
338#define INV_MPU6050_BYTES_PER_TEMP_SENSOR   2
339
340/* mpu6500 registers */
341#define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
342#define INV_ICM20689_BITS_FIFO_SIZE_MAX     0xC0
343#define INV_MPU6500_REG_LP_ODR              0x1E
344#define INV_MPU6500_REG_WOM_THRESHOLD       0x1F
345#define INV_MPU6500_REG_ACCEL_INTEL_CTRL    0x69
346#define INV_MPU6500_BIT_ACCEL_INTEL_EN      BIT(7)
347#define INV_MPU6500_BIT_ACCEL_INTEL_MODE    BIT(6)
348#define INV_MPU6500_REG_ACCEL_OFFSET        0x77
349
350/* delay time in milliseconds */
351#define INV_MPU6050_POWER_UP_TIME            100
352#define INV_MPU6050_TEMP_UP_TIME             100
353#define INV_MPU6050_ACCEL_STARTUP_TIME       20
354#define INV_MPU6050_GYRO_STARTUP_TIME        60
355#define INV_MPU6050_GYRO_DOWN_TIME           150
356#define INV_MPU6050_SUSPEND_DELAY_MS         2000
357
358#define INV_MPU6500_GYRO_STARTUP_TIME        70
359#define INV_MPU6500_ACCEL_STARTUP_TIME       30
360
361#define INV_ICM20602_GYRO_STARTUP_TIME       100
362#define INV_ICM20602_ACCEL_STARTUP_TIME      20
363
364#define INV_ICM20690_GYRO_STARTUP_TIME       80
365#define INV_ICM20690_ACCEL_STARTUP_TIME      10
366
367
368/* delay time in microseconds */
369#define INV_MPU6050_REG_UP_TIME_MIN          5000
370#define INV_MPU6050_REG_UP_TIME_MAX          10000
371
372#define INV_MPU6050_TEMP_OFFSET	             12420
373#define INV_MPU6050_TEMP_SCALE               2941176
374#define INV_MPU6050_MAX_GYRO_FS_PARAM        3
375#define INV_MPU6050_MAX_ACCL_FS_PARAM        3
376#define INV_MPU6050_THREE_AXIS               3
377#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
378#define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT   2
379#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
380
381#define INV_MPU6500_TEMP_OFFSET              7011
382#define INV_MPU6500_TEMP_SCALE               2995178
383
384#define INV_ICM20608_TEMP_OFFSET	     8170
385#define INV_ICM20608_TEMP_SCALE		     3059976
386
387#define INV_MPU6050_REG_INT_PIN_CFG	0x37
388#define INV_MPU6050_ACTIVE_HIGH		0x00
389#define INV_MPU6050_ACTIVE_LOW		0x80
390/* enable level triggering */
391#define INV_MPU6050_LATCH_INT_EN	0x20
392#define INV_MPU6050_BIT_BYPASS_EN	0x2
393/* allow acking interrupts by any register read */
394#define INV_MPU6050_INT_RD_CLEAR	0x10
395
396/* Allowed timestamp period jitter in percent */
397#define INV_MPU6050_TS_PERIOD_JITTER	4
398
399/* init parameters */
400#define INV_MPU6050_MAX_FIFO_RATE            1000
401#define INV_MPU6050_MIN_FIFO_RATE            4
402
403/* chip internal frequency: 1KHz */
404#define INV_MPU6050_INTERNAL_FREQ_HZ		1000
405/* return the frequency divider (chip sample rate divider + 1) */
406#define INV_MPU6050_FREQ_DIVIDER(st)					\
407	((st)->chip_config.divider + 1)
408/* chip sample rate divider to fifo rate */
409#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)			\
410	((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
411#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)			\
412	(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
413
414#define INV_MPU6050_REG_WHOAMI			117
415
416#define INV_MPU6000_WHOAMI_VALUE		0x68
417#define INV_MPU6050_WHOAMI_VALUE		0x68
418#define INV_MPU6500_WHOAMI_VALUE		0x70
419#define INV_MPU6880_WHOAMI_VALUE		0x78
420#define INV_MPU9150_WHOAMI_VALUE		0x68
421#define INV_MPU9250_WHOAMI_VALUE		0x71
422#define INV_MPU9255_WHOAMI_VALUE		0x73
423#define INV_MPU6515_WHOAMI_VALUE		0x74
424#define INV_ICM20608_WHOAMI_VALUE		0xAF
425#define INV_ICM20608D_WHOAMI_VALUE		0xAE
426#define INV_ICM20609_WHOAMI_VALUE		0xA6
427#define INV_ICM20689_WHOAMI_VALUE		0x98
428#define INV_ICM20600_WHOAMI_VALUE		0x11
429#define INV_ICM20602_WHOAMI_VALUE		0x12
430#define INV_ICM20690_WHOAMI_VALUE		0x20
431#define INV_IAM20380_WHOAMI_VALUE		0xB5
432#define INV_IAM20680_WHOAMI_VALUE		0xA9
433#define INV_IAM20680HP_WHOAMI_VALUE		0xF8
434#define INV_IAM20680HT_WHOAMI_VALUE		0xFA
435
436/* scan element definition for generic MPU6xxx devices */
437enum inv_mpu6050_scan {
438	INV_MPU6050_SCAN_ACCL_X,
439	INV_MPU6050_SCAN_ACCL_Y,
440	INV_MPU6050_SCAN_ACCL_Z,
441	INV_MPU6050_SCAN_TEMP,
442	INV_MPU6050_SCAN_GYRO_X,
443	INV_MPU6050_SCAN_GYRO_Y,
444	INV_MPU6050_SCAN_GYRO_Z,
445	INV_MPU6050_SCAN_TIMESTAMP,
446
447	INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
448	INV_MPU9X50_SCAN_MAGN_Y,
449	INV_MPU9X50_SCAN_MAGN_Z,
450	INV_MPU9X50_SCAN_TIMESTAMP,
451};
452
453enum inv_mpu6050_filter_e {
454	INV_MPU6050_FILTER_NOLPF2 = 0,
455	INV_MPU6050_FILTER_200HZ,
456	INV_MPU6050_FILTER_100HZ,
457	INV_MPU6050_FILTER_45HZ,
458	INV_MPU6050_FILTER_20HZ,
459	INV_MPU6050_FILTER_10HZ,
460	INV_MPU6050_FILTER_5HZ,
461	INV_MPU6050_FILTER_NOLPF,
462	NUM_MPU6050_FILTER
463};
464
465enum inv_mpu6050_lposc_e {
466	INV_MPU6050_LPOSC_4HZ = 4,
467	INV_MPU6050_LPOSC_8HZ,
468	INV_MPU6050_LPOSC_16HZ,
469	INV_MPU6050_LPOSC_31HZ,
470	INV_MPU6050_LPOSC_62HZ,
471	INV_MPU6050_LPOSC_125HZ,
472	INV_MPU6050_LPOSC_250HZ,
473	INV_MPU6050_LPOSC_500HZ,
474	NUM_MPU6050_LPOSC,
475};
476
477/* IIO attribute address */
478enum INV_MPU6050_IIO_ATTR_ADDR {
479	ATTR_GYRO_MATRIX,
480	ATTR_ACCL_MATRIX,
481};
482
483enum inv_mpu6050_accl_fs_e {
484	INV_MPU6050_FS_02G = 0,
485	INV_MPU6050_FS_04G,
486	INV_MPU6050_FS_08G,
487	INV_MPU6050_FS_16G,
488	NUM_ACCL_FSR
489};
490
491enum inv_mpu6050_fsr_e {
492	INV_MPU6050_FSR_250DPS = 0,
493	INV_MPU6050_FSR_500DPS,
494	INV_MPU6050_FSR_1000DPS,
495	INV_MPU6050_FSR_2000DPS,
496	NUM_MPU6050_FSR
497};
498
499enum inv_mpu6050_clock_sel_e {
500	INV_CLK_INTERNAL = 0,
501	INV_CLK_PLL,
502	NUM_CLK
503};
504
505irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
506int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
507int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
508int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
509			      unsigned int mask);
510int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
511void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
512int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
513		int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
514extern const struct dev_pm_ops inv_mpu_pmops;
515
516#endif